xref: /openbmc/linux/sound/soc/fsl/fsl_sai.c (revision 6774def6)
1 /*
2  * Freescale ALSA SoC Digital Audio Interface (SAI) driver.
3  *
4  * Copyright 2012-2013 Freescale Semiconductor, Inc.
5  *
6  * This program is free software, you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License as published by the
8  * Free Software Foundation, either version 2 of the License, or(at your
9  * option) any later version.
10  *
11  */
12 
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <sound/core.h>
21 #include <sound/dmaengine_pcm.h>
22 #include <sound/pcm_params.h>
23 
24 #include "fsl_sai.h"
25 #include "imx-pcm.h"
26 
27 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
28 		       FSL_SAI_CSR_FEIE)
29 
30 static irqreturn_t fsl_sai_isr(int irq, void *devid)
31 {
32 	struct fsl_sai *sai = (struct fsl_sai *)devid;
33 	struct device *dev = &sai->pdev->dev;
34 	u32 flags, xcsr, mask;
35 	bool irq_none = true;
36 
37 	/*
38 	 * Both IRQ status bits and IRQ mask bits are in the xCSR but
39 	 * different shifts. And we here create a mask only for those
40 	 * IRQs that we activated.
41 	 */
42 	mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
43 
44 	/* Tx IRQ */
45 	regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
46 	flags = xcsr & mask;
47 
48 	if (flags)
49 		irq_none = false;
50 	else
51 		goto irq_rx;
52 
53 	if (flags & FSL_SAI_CSR_WSF)
54 		dev_dbg(dev, "isr: Start of Tx word detected\n");
55 
56 	if (flags & FSL_SAI_CSR_SEF)
57 		dev_warn(dev, "isr: Tx Frame sync error detected\n");
58 
59 	if (flags & FSL_SAI_CSR_FEF) {
60 		dev_warn(dev, "isr: Transmit underrun detected\n");
61 		/* FIFO reset for safety */
62 		xcsr |= FSL_SAI_CSR_FR;
63 	}
64 
65 	if (flags & FSL_SAI_CSR_FWF)
66 		dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
67 
68 	if (flags & FSL_SAI_CSR_FRF)
69 		dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
70 
71 	flags &= FSL_SAI_CSR_xF_W_MASK;
72 	xcsr &= ~FSL_SAI_CSR_xF_MASK;
73 
74 	if (flags)
75 		regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
76 
77 irq_rx:
78 	/* Rx IRQ */
79 	regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
80 	flags = xcsr & mask;
81 
82 	if (flags)
83 		irq_none = false;
84 	else
85 		goto out;
86 
87 	if (flags & FSL_SAI_CSR_WSF)
88 		dev_dbg(dev, "isr: Start of Rx word detected\n");
89 
90 	if (flags & FSL_SAI_CSR_SEF)
91 		dev_warn(dev, "isr: Rx Frame sync error detected\n");
92 
93 	if (flags & FSL_SAI_CSR_FEF) {
94 		dev_warn(dev, "isr: Receive overflow detected\n");
95 		/* FIFO reset for safety */
96 		xcsr |= FSL_SAI_CSR_FR;
97 	}
98 
99 	if (flags & FSL_SAI_CSR_FWF)
100 		dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
101 
102 	if (flags & FSL_SAI_CSR_FRF)
103 		dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
104 
105 	flags &= FSL_SAI_CSR_xF_W_MASK;
106 	xcsr &= ~FSL_SAI_CSR_xF_MASK;
107 
108 	if (flags)
109 		regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
110 
111 out:
112 	if (irq_none)
113 		return IRQ_NONE;
114 	else
115 		return IRQ_HANDLED;
116 }
117 
118 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
119 		int clk_id, unsigned int freq, int fsl_dir)
120 {
121 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
122 	bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
123 	u32 val_cr2 = 0;
124 
125 	switch (clk_id) {
126 	case FSL_SAI_CLK_BUS:
127 		val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
128 		break;
129 	case FSL_SAI_CLK_MAST1:
130 		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
131 		break;
132 	case FSL_SAI_CLK_MAST2:
133 		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
134 		break;
135 	case FSL_SAI_CLK_MAST3:
136 		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
137 		break;
138 	default:
139 		return -EINVAL;
140 	}
141 
142 	regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
143 			   FSL_SAI_CR2_MSEL_MASK, val_cr2);
144 
145 	return 0;
146 }
147 
148 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
149 		int clk_id, unsigned int freq, int dir)
150 {
151 	int ret;
152 
153 	if (dir == SND_SOC_CLOCK_IN)
154 		return 0;
155 
156 	ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
157 					FSL_FMT_TRANSMITTER);
158 	if (ret) {
159 		dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
160 		return ret;
161 	}
162 
163 	ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
164 					FSL_FMT_RECEIVER);
165 	if (ret)
166 		dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
167 
168 	return ret;
169 }
170 
171 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
172 				unsigned int fmt, int fsl_dir)
173 {
174 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
175 	bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
176 	u32 val_cr2 = 0, val_cr4 = 0;
177 
178 	if (!sai->is_lsb_first)
179 		val_cr4 |= FSL_SAI_CR4_MF;
180 
181 	/* DAI mode */
182 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
183 	case SND_SOC_DAIFMT_I2S:
184 		/*
185 		 * Frame low, 1clk before data, one word length for frame sync,
186 		 * frame sync starts one serial clock cycle earlier,
187 		 * that is, together with the last bit of the previous
188 		 * data word.
189 		 */
190 		val_cr2 |= FSL_SAI_CR2_BCP;
191 		val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
192 		break;
193 	case SND_SOC_DAIFMT_LEFT_J:
194 		/*
195 		 * Frame high, one word length for frame sync,
196 		 * frame sync asserts with the first bit of the frame.
197 		 */
198 		val_cr2 |= FSL_SAI_CR2_BCP;
199 		break;
200 	case SND_SOC_DAIFMT_DSP_A:
201 		/*
202 		 * Frame high, 1clk before data, one bit for frame sync,
203 		 * frame sync starts one serial clock cycle earlier,
204 		 * that is, together with the last bit of the previous
205 		 * data word.
206 		 */
207 		val_cr2 |= FSL_SAI_CR2_BCP;
208 		val_cr4 |= FSL_SAI_CR4_FSE;
209 		sai->is_dsp_mode = true;
210 		break;
211 	case SND_SOC_DAIFMT_DSP_B:
212 		/*
213 		 * Frame high, one bit for frame sync,
214 		 * frame sync asserts with the first bit of the frame.
215 		 */
216 		val_cr2 |= FSL_SAI_CR2_BCP;
217 		sai->is_dsp_mode = true;
218 		break;
219 	case SND_SOC_DAIFMT_RIGHT_J:
220 		/* To be done */
221 	default:
222 		return -EINVAL;
223 	}
224 
225 	/* DAI clock inversion */
226 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
227 	case SND_SOC_DAIFMT_IB_IF:
228 		/* Invert both clocks */
229 		val_cr2 ^= FSL_SAI_CR2_BCP;
230 		val_cr4 ^= FSL_SAI_CR4_FSP;
231 		break;
232 	case SND_SOC_DAIFMT_IB_NF:
233 		/* Invert bit clock */
234 		val_cr2 ^= FSL_SAI_CR2_BCP;
235 		break;
236 	case SND_SOC_DAIFMT_NB_IF:
237 		/* Invert frame clock */
238 		val_cr4 ^= FSL_SAI_CR4_FSP;
239 		break;
240 	case SND_SOC_DAIFMT_NB_NF:
241 		/* Nothing to do for both normal cases */
242 		break;
243 	default:
244 		return -EINVAL;
245 	}
246 
247 	/* DAI clock master masks */
248 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
249 	case SND_SOC_DAIFMT_CBS_CFS:
250 		val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
251 		val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
252 		break;
253 	case SND_SOC_DAIFMT_CBM_CFM:
254 		break;
255 	case SND_SOC_DAIFMT_CBS_CFM:
256 		val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
257 		break;
258 	case SND_SOC_DAIFMT_CBM_CFS:
259 		val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
260 		break;
261 	default:
262 		return -EINVAL;
263 	}
264 
265 	regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
266 			   FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
267 	regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
268 			   FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
269 			   FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
270 
271 	return 0;
272 }
273 
274 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
275 {
276 	int ret;
277 
278 	ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
279 	if (ret) {
280 		dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
281 		return ret;
282 	}
283 
284 	ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
285 	if (ret)
286 		dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
287 
288 	return ret;
289 }
290 
291 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
292 		struct snd_pcm_hw_params *params,
293 		struct snd_soc_dai *cpu_dai)
294 {
295 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
296 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
297 	unsigned int channels = params_channels(params);
298 	u32 word_width = snd_pcm_format_width(params_format(params));
299 	u32 val_cr4 = 0, val_cr5 = 0;
300 
301 	if (!sai->is_dsp_mode)
302 		val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
303 
304 	val_cr5 |= FSL_SAI_CR5_WNW(word_width);
305 	val_cr5 |= FSL_SAI_CR5_W0W(word_width);
306 
307 	if (sai->is_lsb_first)
308 		val_cr5 |= FSL_SAI_CR5_FBT(0);
309 	else
310 		val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
311 
312 	val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
313 
314 	regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
315 			   FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
316 			   val_cr4);
317 	regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
318 			   FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
319 			   FSL_SAI_CR5_FBT_MASK, val_cr5);
320 	regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
321 
322 	return 0;
323 }
324 
325 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
326 		struct snd_soc_dai *cpu_dai)
327 {
328 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
329 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
330 	u32 xcsr, count = 100;
331 
332 	/*
333 	 * Asynchronous mode: Clear SYNC for both Tx and Rx.
334 	 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
335 	 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
336 	 */
337 	regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, 0);
338 	regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
339 			   sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
340 
341 	/*
342 	 * It is recommended that the transmitter is the last enabled
343 	 * and the first disabled.
344 	 */
345 	switch (cmd) {
346 	case SNDRV_PCM_TRIGGER_START:
347 	case SNDRV_PCM_TRIGGER_RESUME:
348 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
349 		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
350 				   FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
351 
352 		regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
353 				   FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
354 		regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
355 				   FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
356 
357 		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
358 				   FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
359 		break;
360 	case SNDRV_PCM_TRIGGER_STOP:
361 	case SNDRV_PCM_TRIGGER_SUSPEND:
362 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
363 		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
364 				   FSL_SAI_CSR_FRDE, 0);
365 		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
366 				   FSL_SAI_CSR_xIE_MASK, 0);
367 
368 		/* Check if the opposite FRDE is also disabled */
369 		regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
370 		if (!(xcsr & FSL_SAI_CSR_FRDE)) {
371 			/* Disable both directions and reset their FIFOs */
372 			regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
373 					   FSL_SAI_CSR_TERE, 0);
374 			regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
375 					   FSL_SAI_CSR_TERE, 0);
376 
377 			/* TERE will remain set till the end of current frame */
378 			do {
379 				udelay(10);
380 				regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
381 			} while (--count && xcsr & FSL_SAI_CSR_TERE);
382 
383 			regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
384 					   FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
385 			regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
386 					   FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
387 		}
388 		break;
389 	default:
390 		return -EINVAL;
391 	}
392 
393 	return 0;
394 }
395 
396 static int fsl_sai_startup(struct snd_pcm_substream *substream,
397 		struct snd_soc_dai *cpu_dai)
398 {
399 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
400 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
401 	struct device *dev = &sai->pdev->dev;
402 	int ret;
403 
404 	ret = clk_prepare_enable(sai->bus_clk);
405 	if (ret) {
406 		dev_err(dev, "failed to enable bus clock: %d\n", ret);
407 		return ret;
408 	}
409 
410 	regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
411 			   FSL_SAI_CR3_TRCE);
412 
413 	return 0;
414 }
415 
416 static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
417 		struct snd_soc_dai *cpu_dai)
418 {
419 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
420 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
421 
422 	regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
423 
424 	clk_disable_unprepare(sai->bus_clk);
425 }
426 
427 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
428 	.set_sysclk	= fsl_sai_set_dai_sysclk,
429 	.set_fmt	= fsl_sai_set_dai_fmt,
430 	.hw_params	= fsl_sai_hw_params,
431 	.trigger	= fsl_sai_trigger,
432 	.startup	= fsl_sai_startup,
433 	.shutdown	= fsl_sai_shutdown,
434 };
435 
436 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
437 {
438 	struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
439 
440 	/* Software Reset for both Tx and Rx */
441 	regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
442 	regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
443 	/* Clear SR bit to finish the reset */
444 	regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
445 	regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
446 
447 	regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
448 			   FSL_SAI_MAXBURST_TX * 2);
449 	regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
450 			   FSL_SAI_MAXBURST_RX - 1);
451 
452 	snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
453 				&sai->dma_params_rx);
454 
455 	snd_soc_dai_set_drvdata(cpu_dai, sai);
456 
457 	return 0;
458 }
459 
460 static struct snd_soc_dai_driver fsl_sai_dai = {
461 	.probe = fsl_sai_dai_probe,
462 	.playback = {
463 		.stream_name = "CPU-Playback",
464 		.channels_min = 1,
465 		.channels_max = 2,
466 		.rates = SNDRV_PCM_RATE_8000_96000,
467 		.formats = FSL_SAI_FORMATS,
468 	},
469 	.capture = {
470 		.stream_name = "CPU-Capture",
471 		.channels_min = 1,
472 		.channels_max = 2,
473 		.rates = SNDRV_PCM_RATE_8000_96000,
474 		.formats = FSL_SAI_FORMATS,
475 	},
476 	.ops = &fsl_sai_pcm_dai_ops,
477 };
478 
479 static const struct snd_soc_component_driver fsl_component = {
480 	.name           = "fsl-sai",
481 };
482 
483 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
484 {
485 	switch (reg) {
486 	case FSL_SAI_TCSR:
487 	case FSL_SAI_TCR1:
488 	case FSL_SAI_TCR2:
489 	case FSL_SAI_TCR3:
490 	case FSL_SAI_TCR4:
491 	case FSL_SAI_TCR5:
492 	case FSL_SAI_TFR:
493 	case FSL_SAI_TMR:
494 	case FSL_SAI_RCSR:
495 	case FSL_SAI_RCR1:
496 	case FSL_SAI_RCR2:
497 	case FSL_SAI_RCR3:
498 	case FSL_SAI_RCR4:
499 	case FSL_SAI_RCR5:
500 	case FSL_SAI_RDR:
501 	case FSL_SAI_RFR:
502 	case FSL_SAI_RMR:
503 		return true;
504 	default:
505 		return false;
506 	}
507 }
508 
509 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
510 {
511 	switch (reg) {
512 	case FSL_SAI_TFR:
513 	case FSL_SAI_RFR:
514 	case FSL_SAI_TDR:
515 	case FSL_SAI_RDR:
516 		return true;
517 	default:
518 		return false;
519 	}
520 
521 }
522 
523 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
524 {
525 	switch (reg) {
526 	case FSL_SAI_TCSR:
527 	case FSL_SAI_TCR1:
528 	case FSL_SAI_TCR2:
529 	case FSL_SAI_TCR3:
530 	case FSL_SAI_TCR4:
531 	case FSL_SAI_TCR5:
532 	case FSL_SAI_TDR:
533 	case FSL_SAI_TMR:
534 	case FSL_SAI_RCSR:
535 	case FSL_SAI_RCR1:
536 	case FSL_SAI_RCR2:
537 	case FSL_SAI_RCR3:
538 	case FSL_SAI_RCR4:
539 	case FSL_SAI_RCR5:
540 	case FSL_SAI_RMR:
541 		return true;
542 	default:
543 		return false;
544 	}
545 }
546 
547 static const struct regmap_config fsl_sai_regmap_config = {
548 	.reg_bits = 32,
549 	.reg_stride = 4,
550 	.val_bits = 32,
551 
552 	.max_register = FSL_SAI_RMR,
553 	.readable_reg = fsl_sai_readable_reg,
554 	.volatile_reg = fsl_sai_volatile_reg,
555 	.writeable_reg = fsl_sai_writeable_reg,
556 };
557 
558 static int fsl_sai_probe(struct platform_device *pdev)
559 {
560 	struct device_node *np = pdev->dev.of_node;
561 	struct fsl_sai *sai;
562 	struct resource *res;
563 	void __iomem *base;
564 	char tmp[8];
565 	int irq, ret, i;
566 
567 	sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
568 	if (!sai)
569 		return -ENOMEM;
570 
571 	sai->pdev = pdev;
572 
573 	if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
574 		sai->sai_on_imx = true;
575 
576 	sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
577 
578 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
579 	base = devm_ioremap_resource(&pdev->dev, res);
580 	if (IS_ERR(base))
581 		return PTR_ERR(base);
582 
583 	sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
584 			"bus", base, &fsl_sai_regmap_config);
585 
586 	/* Compatible with old DTB cases */
587 	if (IS_ERR(sai->regmap))
588 		sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
589 				"sai", base, &fsl_sai_regmap_config);
590 	if (IS_ERR(sai->regmap)) {
591 		dev_err(&pdev->dev, "regmap init failed\n");
592 		return PTR_ERR(sai->regmap);
593 	}
594 
595 	/* No error out for old DTB cases but only mark the clock NULL */
596 	sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
597 	if (IS_ERR(sai->bus_clk)) {
598 		dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
599 				PTR_ERR(sai->bus_clk));
600 		sai->bus_clk = NULL;
601 	}
602 
603 	for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
604 		sprintf(tmp, "mclk%d", i + 1);
605 		sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
606 		if (IS_ERR(sai->mclk_clk[i])) {
607 			dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
608 					i + 1, PTR_ERR(sai->mclk_clk[i]));
609 			sai->mclk_clk[i] = NULL;
610 		}
611 	}
612 
613 	irq = platform_get_irq(pdev, 0);
614 	if (irq < 0) {
615 		dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
616 		return irq;
617 	}
618 
619 	ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
620 	if (ret) {
621 		dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
622 		return ret;
623 	}
624 
625 	/* Sync Tx with Rx as default by following old DT binding */
626 	sai->synchronous[RX] = true;
627 	sai->synchronous[TX] = false;
628 	fsl_sai_dai.symmetric_rates = 1;
629 	fsl_sai_dai.symmetric_channels = 1;
630 	fsl_sai_dai.symmetric_samplebits = 1;
631 
632 	if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
633 	    of_find_property(np, "fsl,sai-asynchronous", NULL)) {
634 		/* error out if both synchronous and asynchronous are present */
635 		dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
636 		return -EINVAL;
637 	}
638 
639 	if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
640 		/* Sync Rx with Tx */
641 		sai->synchronous[RX] = false;
642 		sai->synchronous[TX] = true;
643 	} else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
644 		/* Discard all settings for asynchronous mode */
645 		sai->synchronous[RX] = false;
646 		sai->synchronous[TX] = false;
647 		fsl_sai_dai.symmetric_rates = 0;
648 		fsl_sai_dai.symmetric_channels = 0;
649 		fsl_sai_dai.symmetric_samplebits = 0;
650 	}
651 
652 	sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
653 	sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
654 	sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
655 	sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
656 
657 	platform_set_drvdata(pdev, sai);
658 
659 	ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
660 			&fsl_sai_dai, 1);
661 	if (ret)
662 		return ret;
663 
664 	if (sai->sai_on_imx)
665 		return imx_pcm_dma_init(pdev);
666 	else
667 		return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
668 				SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
669 }
670 
671 static const struct of_device_id fsl_sai_ids[] = {
672 	{ .compatible = "fsl,vf610-sai", },
673 	{ .compatible = "fsl,imx6sx-sai", },
674 	{ /* sentinel */ }
675 };
676 
677 static struct platform_driver fsl_sai_driver = {
678 	.probe = fsl_sai_probe,
679 	.driver = {
680 		.name = "fsl-sai",
681 		.owner = THIS_MODULE,
682 		.of_match_table = fsl_sai_ids,
683 	},
684 };
685 module_platform_driver(fsl_sai_driver);
686 
687 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
688 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
689 MODULE_ALIAS("platform:fsl-sai");
690 MODULE_LICENSE("GPL");
691