1 /* 2 * Freescale ALSA SoC Digital Audio Interface (SAI) driver. 3 * 4 * Copyright 2012-2013 Freescale Semiconductor, Inc. 5 * 6 * This program is free software, you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation, either version 2 of the License, or(at your 9 * option) any later version. 10 * 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/dmaengine.h> 16 #include <linux/module.h> 17 #include <linux/of_address.h> 18 #include <linux/slab.h> 19 #include <sound/core.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 23 #include "fsl_sai.h" 24 25 static inline u32 sai_readl(struct fsl_sai *sai, 26 const void __iomem *addr) 27 { 28 u32 val; 29 30 val = __raw_readl(addr); 31 32 if (likely(sai->big_endian_regs)) 33 val = be32_to_cpu(val); 34 else 35 val = le32_to_cpu(val); 36 rmb(); 37 38 return val; 39 } 40 41 static inline void sai_writel(struct fsl_sai *sai, 42 u32 val, void __iomem *addr) 43 { 44 wmb(); 45 if (likely(sai->big_endian_regs)) 46 val = cpu_to_be32(val); 47 else 48 val = cpu_to_le32(val); 49 50 __raw_writel(val, addr); 51 } 52 53 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 54 int clk_id, unsigned int freq, int fsl_dir) 55 { 56 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 57 u32 val_cr2, reg_cr2; 58 59 if (fsl_dir == FSL_FMT_TRANSMITTER) 60 reg_cr2 = FSL_SAI_TCR2; 61 else 62 reg_cr2 = FSL_SAI_RCR2; 63 64 val_cr2 = sai_readl(sai, sai->base + reg_cr2); 65 val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK; 66 67 switch (clk_id) { 68 case FSL_SAI_CLK_BUS: 69 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 70 break; 71 case FSL_SAI_CLK_MAST1: 72 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 73 break; 74 case FSL_SAI_CLK_MAST2: 75 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 76 break; 77 case FSL_SAI_CLK_MAST3: 78 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 79 break; 80 default: 81 return -EINVAL; 82 } 83 84 sai_writel(sai, val_cr2, sai->base + reg_cr2); 85 86 return 0; 87 } 88 89 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 90 int clk_id, unsigned int freq, int dir) 91 { 92 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 93 int ret; 94 95 if (dir == SND_SOC_CLOCK_IN) 96 return 0; 97 98 ret = clk_prepare_enable(sai->clk); 99 if (ret) 100 return ret; 101 102 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, 103 FSL_FMT_TRANSMITTER); 104 if (ret) { 105 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 106 goto err_clk; 107 } 108 109 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, 110 FSL_FMT_RECEIVER); 111 if (ret) { 112 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 113 goto err_clk; 114 } 115 116 err_clk: 117 clk_disable_unprepare(sai->clk); 118 119 return ret; 120 } 121 122 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 123 unsigned int fmt, int fsl_dir) 124 { 125 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 126 u32 val_cr2, val_cr4, reg_cr2, reg_cr4; 127 128 if (fsl_dir == FSL_FMT_TRANSMITTER) { 129 reg_cr2 = FSL_SAI_TCR2; 130 reg_cr4 = FSL_SAI_TCR4; 131 } else { 132 reg_cr2 = FSL_SAI_RCR2; 133 reg_cr4 = FSL_SAI_RCR4; 134 } 135 136 val_cr2 = sai_readl(sai, sai->base + reg_cr2); 137 val_cr4 = sai_readl(sai, sai->base + reg_cr4); 138 139 if (sai->big_endian_data) 140 val_cr4 &= ~FSL_SAI_CR4_MF; 141 else 142 val_cr4 |= FSL_SAI_CR4_MF; 143 144 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 145 case SND_SOC_DAIFMT_I2S: 146 val_cr4 |= FSL_SAI_CR4_FSE; 147 break; 148 default: 149 return -EINVAL; 150 } 151 152 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 153 case SND_SOC_DAIFMT_IB_IF: 154 val_cr4 |= FSL_SAI_CR4_FSP; 155 val_cr2 &= ~FSL_SAI_CR2_BCP; 156 break; 157 case SND_SOC_DAIFMT_IB_NF: 158 val_cr4 &= ~FSL_SAI_CR4_FSP; 159 val_cr2 &= ~FSL_SAI_CR2_BCP; 160 break; 161 case SND_SOC_DAIFMT_NB_IF: 162 val_cr4 |= FSL_SAI_CR4_FSP; 163 val_cr2 |= FSL_SAI_CR2_BCP; 164 break; 165 case SND_SOC_DAIFMT_NB_NF: 166 val_cr4 &= ~FSL_SAI_CR4_FSP; 167 val_cr2 |= FSL_SAI_CR2_BCP; 168 break; 169 default: 170 return -EINVAL; 171 } 172 173 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 174 case SND_SOC_DAIFMT_CBS_CFS: 175 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 176 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 177 break; 178 case SND_SOC_DAIFMT_CBM_CFM: 179 val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR; 180 val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR; 181 break; 182 default: 183 return -EINVAL; 184 } 185 186 sai_writel(sai, val_cr2, sai->base + reg_cr2); 187 sai_writel(sai, val_cr4, sai->base + reg_cr4); 188 189 return 0; 190 } 191 192 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 193 { 194 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 195 int ret; 196 197 ret = clk_prepare_enable(sai->clk); 198 if (ret) 199 return ret; 200 201 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER); 202 if (ret) { 203 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 204 goto err_clk; 205 } 206 207 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER); 208 if (ret) { 209 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 210 goto err_clk; 211 } 212 213 err_clk: 214 clk_disable_unprepare(sai->clk); 215 216 return ret; 217 } 218 219 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 220 struct snd_pcm_hw_params *params, 221 struct snd_soc_dai *cpu_dai) 222 { 223 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 224 u32 val_cr4, val_cr5, val_mr, reg_cr4, reg_cr5, reg_mr; 225 unsigned int channels = params_channels(params); 226 u32 word_width = snd_pcm_format_width(params_format(params)); 227 228 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 229 reg_cr4 = FSL_SAI_TCR4; 230 reg_cr5 = FSL_SAI_TCR5; 231 reg_mr = FSL_SAI_TMR; 232 } else { 233 reg_cr4 = FSL_SAI_RCR4; 234 reg_cr5 = FSL_SAI_RCR5; 235 reg_mr = FSL_SAI_RMR; 236 } 237 238 val_cr4 = sai_readl(sai, sai->base + reg_cr4); 239 val_cr4 &= ~FSL_SAI_CR4_SYWD_MASK; 240 val_cr4 &= ~FSL_SAI_CR4_FRSZ_MASK; 241 242 val_cr5 = sai_readl(sai, sai->base + reg_cr5); 243 val_cr5 &= ~FSL_SAI_CR5_WNW_MASK; 244 val_cr5 &= ~FSL_SAI_CR5_W0W_MASK; 245 val_cr5 &= ~FSL_SAI_CR5_FBT_MASK; 246 247 val_cr4 |= FSL_SAI_CR4_SYWD(word_width); 248 val_cr5 |= FSL_SAI_CR5_WNW(word_width); 249 val_cr5 |= FSL_SAI_CR5_W0W(word_width); 250 251 val_cr5 &= ~FSL_SAI_CR5_FBT_MASK; 252 if (sai->big_endian_data) 253 val_cr5 |= FSL_SAI_CR5_FBT(0); 254 else 255 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 256 257 val_cr4 |= FSL_SAI_CR4_FRSZ(channels); 258 val_mr = ~0UL - ((1 << channels) - 1); 259 260 sai_writel(sai, val_cr4, sai->base + reg_cr4); 261 sai_writel(sai, val_cr5, sai->base + reg_cr5); 262 sai_writel(sai, val_mr, sai->base + reg_mr); 263 264 return 0; 265 } 266 267 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 268 struct snd_soc_dai *cpu_dai) 269 { 270 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 271 u32 tcsr, rcsr, val_cr2, val_cr3, reg_cr3; 272 273 val_cr2 = sai_readl(sai, sai->base + FSL_SAI_TCR2); 274 val_cr2 &= ~FSL_SAI_CR2_SYNC; 275 sai_writel(sai, val_cr2, sai->base + FSL_SAI_TCR2); 276 277 val_cr2 = sai_readl(sai, sai->base + FSL_SAI_RCR2); 278 val_cr2 |= FSL_SAI_CR2_SYNC; 279 sai_writel(sai, val_cr2, sai->base + FSL_SAI_RCR2); 280 281 tcsr = sai_readl(sai, sai->base + FSL_SAI_TCSR); 282 rcsr = sai_readl(sai, sai->base + FSL_SAI_RCSR); 283 284 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 285 tcsr |= FSL_SAI_CSR_FRDE; 286 rcsr &= ~FSL_SAI_CSR_FRDE; 287 reg_cr3 = FSL_SAI_TCR3; 288 } else { 289 rcsr |= FSL_SAI_CSR_FRDE; 290 tcsr &= ~FSL_SAI_CSR_FRDE; 291 reg_cr3 = FSL_SAI_RCR3; 292 } 293 294 val_cr3 = sai_readl(sai, sai->base + reg_cr3); 295 296 switch (cmd) { 297 case SNDRV_PCM_TRIGGER_START: 298 case SNDRV_PCM_TRIGGER_RESUME: 299 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 300 tcsr |= FSL_SAI_CSR_TERE; 301 rcsr |= FSL_SAI_CSR_TERE; 302 val_cr3 |= FSL_SAI_CR3_TRCE; 303 304 sai_writel(sai, val_cr3, sai->base + reg_cr3); 305 sai_writel(sai, rcsr, sai->base + FSL_SAI_RCSR); 306 sai_writel(sai, tcsr, sai->base + FSL_SAI_TCSR); 307 break; 308 309 case SNDRV_PCM_TRIGGER_STOP: 310 case SNDRV_PCM_TRIGGER_SUSPEND: 311 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 312 if (!(cpu_dai->playback_active || cpu_dai->capture_active)) { 313 tcsr &= ~FSL_SAI_CSR_TERE; 314 rcsr &= ~FSL_SAI_CSR_TERE; 315 } 316 317 val_cr3 &= ~FSL_SAI_CR3_TRCE; 318 319 sai_writel(sai, tcsr, sai->base + FSL_SAI_TCSR); 320 sai_writel(sai, rcsr, sai->base + FSL_SAI_RCSR); 321 sai_writel(sai, val_cr3, sai->base + reg_cr3); 322 break; 323 default: 324 return -EINVAL; 325 } 326 327 return 0; 328 } 329 330 static int fsl_sai_startup(struct snd_pcm_substream *substream, 331 struct snd_soc_dai *cpu_dai) 332 { 333 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 334 335 return clk_prepare_enable(sai->clk); 336 } 337 338 static void fsl_sai_shutdown(struct snd_pcm_substream *substream, 339 struct snd_soc_dai *cpu_dai) 340 { 341 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 342 343 clk_disable_unprepare(sai->clk); 344 } 345 346 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 347 .set_sysclk = fsl_sai_set_dai_sysclk, 348 .set_fmt = fsl_sai_set_dai_fmt, 349 .hw_params = fsl_sai_hw_params, 350 .trigger = fsl_sai_trigger, 351 .startup = fsl_sai_startup, 352 .shutdown = fsl_sai_shutdown, 353 }; 354 355 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 356 { 357 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 358 int ret; 359 360 ret = clk_prepare_enable(sai->clk); 361 if (ret) 362 return ret; 363 364 sai_writel(sai, 0x0, sai->base + FSL_SAI_RCSR); 365 sai_writel(sai, 0x0, sai->base + FSL_SAI_TCSR); 366 sai_writel(sai, FSL_SAI_MAXBURST_TX * 2, sai->base + FSL_SAI_TCR1); 367 sai_writel(sai, FSL_SAI_MAXBURST_RX - 1, sai->base + FSL_SAI_RCR1); 368 369 clk_disable_unprepare(sai->clk); 370 371 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 372 &sai->dma_params_rx); 373 374 snd_soc_dai_set_drvdata(cpu_dai, sai); 375 376 return 0; 377 } 378 379 static struct snd_soc_dai_driver fsl_sai_dai = { 380 .probe = fsl_sai_dai_probe, 381 .playback = { 382 .channels_min = 1, 383 .channels_max = 2, 384 .rates = SNDRV_PCM_RATE_8000_96000, 385 .formats = FSL_SAI_FORMATS, 386 }, 387 .capture = { 388 .channels_min = 1, 389 .channels_max = 2, 390 .rates = SNDRV_PCM_RATE_8000_96000, 391 .formats = FSL_SAI_FORMATS, 392 }, 393 .ops = &fsl_sai_pcm_dai_ops, 394 }; 395 396 static const struct snd_soc_component_driver fsl_component = { 397 .name = "fsl-sai", 398 }; 399 400 static int fsl_sai_probe(struct platform_device *pdev) 401 { 402 struct device_node *np = pdev->dev.of_node; 403 struct fsl_sai *sai; 404 struct resource *res; 405 int ret; 406 407 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 408 if (!sai) 409 return -ENOMEM; 410 411 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 412 sai->base = devm_ioremap_resource(&pdev->dev, res); 413 if (IS_ERR(sai->base)) 414 return PTR_ERR(sai->base); 415 416 sai->clk = devm_clk_get(&pdev->dev, "sai"); 417 if (IS_ERR(sai->clk)) { 418 dev_err(&pdev->dev, "Cannot get SAI's clock\n"); 419 return PTR_ERR(sai->clk); 420 } 421 422 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR; 423 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR; 424 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; 425 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; 426 427 sai->big_endian_regs = of_property_read_bool(np, "big-endian-regs"); 428 sai->big_endian_data = of_property_read_bool(np, "big-endian-data"); 429 430 platform_set_drvdata(pdev, sai); 431 432 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component, 433 &fsl_sai_dai, 1); 434 if (ret) 435 return ret; 436 437 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 438 SND_DMAENGINE_PCM_FLAG_NO_RESIDUE); 439 } 440 441 static const struct of_device_id fsl_sai_ids[] = { 442 { .compatible = "fsl,vf610-sai", }, 443 { /* sentinel */ } 444 }; 445 446 static struct platform_driver fsl_sai_driver = { 447 .probe = fsl_sai_probe, 448 .driver = { 449 .name = "fsl-sai", 450 .owner = THIS_MODULE, 451 .of_match_table = fsl_sai_ids, 452 }, 453 }; 454 module_platform_driver(fsl_sai_driver); 455 456 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 457 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 458 MODULE_ALIAS("platform:fsl-sai"); 459 MODULE_LICENSE("GPL"); 460