1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/pinctrl/consumer.h> 14 #include <linux/pm_qos.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/time.h> 19 #include <sound/core.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 24 25 #include "fsl_sai.h" 26 #include "fsl_utils.h" 27 #include "imx-pcm.h" 28 29 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 30 FSL_SAI_CSR_FEIE) 31 32 static const unsigned int fsl_sai_rates[] = { 33 8000, 11025, 12000, 16000, 22050, 34 24000, 32000, 44100, 48000, 64000, 35 88200, 96000, 176400, 192000, 352800, 36 384000, 705600, 768000, 1411200, 2822400, 37 }; 38 39 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 40 .count = ARRAY_SIZE(fsl_sai_rates), 41 .list = fsl_sai_rates, 42 }; 43 44 /** 45 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 46 * 47 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 48 * or Receiver's for both streams. This function is used to check if clocks of 49 * the stream's are synced by the opposite stream. 50 * 51 * @sai: SAI context 52 * @dir: stream direction 53 */ 54 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 55 { 56 int adir = (dir == TX) ? RX : TX; 57 58 /* current dir in async mode while opposite dir in sync mode */ 59 return !sai->synchronous[dir] && sai->synchronous[adir]; 60 } 61 62 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk) 63 { 64 struct pinctrl_state *state = NULL; 65 66 if (sai->is_pdm_mode) { 67 /* DSD512@44.1kHz, DSD512@48kHz */ 68 if (bclk >= 22579200) 69 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); 70 71 /* Get default DSD state */ 72 if (IS_ERR_OR_NULL(state)) 73 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); 74 } else { 75 /* 706k32b2c, 768k32b2c, etc */ 76 if (bclk >= 45158400) 77 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); 78 } 79 80 /* Get default state */ 81 if (IS_ERR_OR_NULL(state)) 82 state = pinctrl_lookup_state(sai->pinctrl, "default"); 83 84 return state; 85 } 86 87 static irqreturn_t fsl_sai_isr(int irq, void *devid) 88 { 89 struct fsl_sai *sai = (struct fsl_sai *)devid; 90 unsigned int ofs = sai->soc_data->reg_offset; 91 struct device *dev = &sai->pdev->dev; 92 u32 flags, xcsr, mask; 93 irqreturn_t iret = IRQ_NONE; 94 95 /* 96 * Both IRQ status bits and IRQ mask bits are in the xCSR but 97 * different shifts. And we here create a mask only for those 98 * IRQs that we activated. 99 */ 100 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 101 102 /* Tx IRQ */ 103 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 104 flags = xcsr & mask; 105 106 if (flags) 107 iret = IRQ_HANDLED; 108 else 109 goto irq_rx; 110 111 if (flags & FSL_SAI_CSR_WSF) 112 dev_dbg(dev, "isr: Start of Tx word detected\n"); 113 114 if (flags & FSL_SAI_CSR_SEF) 115 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 116 117 if (flags & FSL_SAI_CSR_FEF) 118 dev_dbg(dev, "isr: Transmit underrun detected\n"); 119 120 if (flags & FSL_SAI_CSR_FWF) 121 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 122 123 if (flags & FSL_SAI_CSR_FRF) 124 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 125 126 flags &= FSL_SAI_CSR_xF_W_MASK; 127 xcsr &= ~FSL_SAI_CSR_xF_MASK; 128 129 if (flags) 130 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 131 132 irq_rx: 133 /* Rx IRQ */ 134 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 135 flags = xcsr & mask; 136 137 if (flags) 138 iret = IRQ_HANDLED; 139 else 140 goto out; 141 142 if (flags & FSL_SAI_CSR_WSF) 143 dev_dbg(dev, "isr: Start of Rx word detected\n"); 144 145 if (flags & FSL_SAI_CSR_SEF) 146 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 147 148 if (flags & FSL_SAI_CSR_FEF) 149 dev_dbg(dev, "isr: Receive overflow detected\n"); 150 151 if (flags & FSL_SAI_CSR_FWF) 152 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 153 154 if (flags & FSL_SAI_CSR_FRF) 155 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 156 157 flags &= FSL_SAI_CSR_xF_W_MASK; 158 xcsr &= ~FSL_SAI_CSR_xF_MASK; 159 160 if (flags) 161 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 162 163 out: 164 return iret; 165 } 166 167 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 168 u32 rx_mask, int slots, int slot_width) 169 { 170 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 171 172 sai->slots = slots; 173 sai->slot_width = slot_width; 174 175 return 0; 176 } 177 178 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 179 unsigned int ratio) 180 { 181 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 182 183 sai->bclk_ratio = ratio; 184 185 return 0; 186 } 187 188 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 189 int clk_id, unsigned int freq, bool tx) 190 { 191 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 192 unsigned int ofs = sai->soc_data->reg_offset; 193 u32 val_cr2 = 0; 194 195 switch (clk_id) { 196 case FSL_SAI_CLK_BUS: 197 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 198 break; 199 case FSL_SAI_CLK_MAST1: 200 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 201 break; 202 case FSL_SAI_CLK_MAST2: 203 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 204 break; 205 case FSL_SAI_CLK_MAST3: 206 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 207 break; 208 default: 209 return -EINVAL; 210 } 211 212 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 213 FSL_SAI_CR2_MSEL_MASK, val_cr2); 214 215 return 0; 216 } 217 218 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq) 219 { 220 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 221 int ret; 222 223 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], 224 sai->pll8k_clk, sai->pll11k_clk, freq); 225 226 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); 227 if (ret < 0) 228 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); 229 230 return ret; 231 } 232 233 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 234 int clk_id, unsigned int freq, int dir) 235 { 236 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 237 int ret; 238 239 if (dir == SND_SOC_CLOCK_IN) 240 return 0; 241 242 if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) { 243 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) { 244 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); 245 return -EINVAL; 246 } 247 248 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { 249 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); 250 return -EINVAL; 251 } 252 253 if (sai->mclk_streams == 0) { 254 ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq); 255 if (ret < 0) 256 return ret; 257 } 258 } 259 260 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); 261 if (ret) { 262 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 263 return ret; 264 } 265 266 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false); 267 if (ret) 268 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 269 270 return ret; 271 } 272 273 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 274 unsigned int fmt, bool tx) 275 { 276 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 277 unsigned int ofs = sai->soc_data->reg_offset; 278 u32 val_cr2 = 0, val_cr4 = 0; 279 280 if (!sai->is_lsb_first) 281 val_cr4 |= FSL_SAI_CR4_MF; 282 283 sai->is_pdm_mode = false; 284 /* DAI mode */ 285 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 286 case SND_SOC_DAIFMT_I2S: 287 /* 288 * Frame low, 1clk before data, one word length for frame sync, 289 * frame sync starts one serial clock cycle earlier, 290 * that is, together with the last bit of the previous 291 * data word. 292 */ 293 val_cr2 |= FSL_SAI_CR2_BCP; 294 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 295 break; 296 case SND_SOC_DAIFMT_LEFT_J: 297 /* 298 * Frame high, one word length for frame sync, 299 * frame sync asserts with the first bit of the frame. 300 */ 301 val_cr2 |= FSL_SAI_CR2_BCP; 302 break; 303 case SND_SOC_DAIFMT_DSP_A: 304 /* 305 * Frame high, 1clk before data, one bit for frame sync, 306 * frame sync starts one serial clock cycle earlier, 307 * that is, together with the last bit of the previous 308 * data word. 309 */ 310 val_cr2 |= FSL_SAI_CR2_BCP; 311 val_cr4 |= FSL_SAI_CR4_FSE; 312 sai->is_dsp_mode = true; 313 break; 314 case SND_SOC_DAIFMT_DSP_B: 315 /* 316 * Frame high, one bit for frame sync, 317 * frame sync asserts with the first bit of the frame. 318 */ 319 val_cr2 |= FSL_SAI_CR2_BCP; 320 sai->is_dsp_mode = true; 321 break; 322 case SND_SOC_DAIFMT_PDM: 323 val_cr2 |= FSL_SAI_CR2_BCP; 324 val_cr4 &= ~FSL_SAI_CR4_MF; 325 sai->is_pdm_mode = true; 326 break; 327 case SND_SOC_DAIFMT_RIGHT_J: 328 /* To be done */ 329 default: 330 return -EINVAL; 331 } 332 333 /* DAI clock inversion */ 334 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 335 case SND_SOC_DAIFMT_IB_IF: 336 /* Invert both clocks */ 337 val_cr2 ^= FSL_SAI_CR2_BCP; 338 val_cr4 ^= FSL_SAI_CR4_FSP; 339 break; 340 case SND_SOC_DAIFMT_IB_NF: 341 /* Invert bit clock */ 342 val_cr2 ^= FSL_SAI_CR2_BCP; 343 break; 344 case SND_SOC_DAIFMT_NB_IF: 345 /* Invert frame clock */ 346 val_cr4 ^= FSL_SAI_CR4_FSP; 347 break; 348 case SND_SOC_DAIFMT_NB_NF: 349 /* Nothing to do for both normal cases */ 350 break; 351 default: 352 return -EINVAL; 353 } 354 355 /* DAI clock provider masks */ 356 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 357 case SND_SOC_DAIFMT_BP_FP: 358 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 359 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 360 sai->is_consumer_mode = false; 361 break; 362 case SND_SOC_DAIFMT_BC_FC: 363 sai->is_consumer_mode = true; 364 break; 365 case SND_SOC_DAIFMT_BP_FC: 366 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 367 sai->is_consumer_mode = false; 368 break; 369 case SND_SOC_DAIFMT_BC_FP: 370 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 371 sai->is_consumer_mode = true; 372 break; 373 default: 374 return -EINVAL; 375 } 376 377 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 378 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 379 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 380 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 381 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 382 383 return 0; 384 } 385 386 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 387 { 388 int ret; 389 390 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 391 if (ret) { 392 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 393 return ret; 394 } 395 396 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 397 if (ret) 398 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 399 400 return ret; 401 } 402 403 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 404 { 405 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 406 unsigned int reg, ofs = sai->soc_data->reg_offset; 407 unsigned long clk_rate; 408 u32 savediv = 0, ratio, bestdiff = freq; 409 int adir = tx ? RX : TX; 410 int dir = tx ? TX : RX; 411 u32 id; 412 bool support_1_1_ratio = sai->verid.version >= 0x0301; 413 414 /* Don't apply to consumer mode */ 415 if (sai->is_consumer_mode) 416 return 0; 417 418 /* 419 * There is no point in polling MCLK0 if it is identical to MCLK1. 420 * And given that MQS use case has to use MCLK1 though two clocks 421 * are the same, we simply skip MCLK0 and start to find from MCLK1. 422 */ 423 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 424 425 for (; id < FSL_SAI_MCLK_MAX; id++) { 426 int diff; 427 428 clk_rate = clk_get_rate(sai->mclk_clk[id]); 429 if (!clk_rate) 430 continue; 431 432 ratio = DIV_ROUND_CLOSEST(clk_rate, freq); 433 if (!ratio || ratio > 512) 434 continue; 435 if (ratio == 1 && !support_1_1_ratio) 436 continue; 437 if ((ratio & 1) && ratio > 1) 438 continue; 439 440 diff = abs((long)clk_rate - ratio * freq); 441 442 /* 443 * Drop the source that can not be 444 * divided into the required rate. 445 */ 446 if (diff != 0 && clk_rate / diff < 1000) 447 continue; 448 449 dev_dbg(dai->dev, 450 "ratio %d for freq %dHz based on clock %ldHz\n", 451 ratio, freq, clk_rate); 452 453 454 if (diff < bestdiff) { 455 savediv = ratio; 456 sai->mclk_id[tx] = id; 457 bestdiff = diff; 458 } 459 460 if (diff == 0) 461 break; 462 } 463 464 if (savediv == 0) { 465 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 466 tx ? 'T' : 'R', freq); 467 return -EINVAL; 468 } 469 470 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 471 sai->mclk_id[tx], savediv, bestdiff); 472 473 /* 474 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 475 * set TCR2 register for playback. 476 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 477 * and capture. 478 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 479 * and capture. 480 * 4) For Tx and Rx are both Synchronous with another SAI, we just 481 * ignore it. 482 */ 483 if (fsl_sai_dir_is_synced(sai, adir)) 484 reg = FSL_SAI_xCR2(!tx, ofs); 485 else if (!sai->synchronous[dir]) 486 reg = FSL_SAI_xCR2(tx, ofs); 487 else 488 return 0; 489 490 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, 491 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 492 493 if (savediv == 1) 494 regmap_update_bits(sai->regmap, reg, 495 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 496 FSL_SAI_CR2_BYP); 497 else 498 regmap_update_bits(sai->regmap, reg, 499 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 500 savediv / 2 - 1); 501 502 if (sai->soc_data->max_register >= FSL_SAI_MCTL) { 503 /* SAI is in master mode at this point, so enable MCLK */ 504 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 505 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 506 } 507 508 return 0; 509 } 510 511 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 512 struct snd_pcm_hw_params *params, 513 struct snd_soc_dai *cpu_dai) 514 { 515 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 516 unsigned int ofs = sai->soc_data->reg_offset; 517 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 518 unsigned int channels = params_channels(params); 519 struct snd_dmaengine_dai_dma_data *dma_params; 520 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; 521 u32 word_width = params_width(params); 522 int trce_mask = 0, dl_cfg_idx = 0; 523 int dl_cfg_cnt = sai->dl_cfg_cnt; 524 u32 dl_type = FSL_SAI_DL_I2S; 525 u32 val_cr4 = 0, val_cr5 = 0; 526 u32 slots = (channels == 1) ? 2 : channels; 527 u32 slot_width = word_width; 528 int adir = tx ? RX : TX; 529 u32 pins, bclk; 530 int ret, i; 531 532 if (sai->slots) 533 slots = sai->slots; 534 535 if (sai->slot_width) 536 slot_width = sai->slot_width; 537 538 pins = DIV_ROUND_UP(channels, slots); 539 540 /* 541 * PDM mode, channels are independent 542 * each channels are on one dataline/FIFO. 543 */ 544 if (sai->is_pdm_mode) { 545 pins = channels; 546 dl_type = FSL_SAI_DL_PDM; 547 } 548 549 for (i = 0; i < dl_cfg_cnt; i++) { 550 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) { 551 dl_cfg_idx = i; 552 break; 553 } 554 } 555 556 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) { 557 dev_err(cpu_dai->dev, "channel not supported\n"); 558 return -EINVAL; 559 } 560 561 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); 562 563 if (!IS_ERR_OR_NULL(sai->pinctrl)) { 564 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); 565 if (!IS_ERR_OR_NULL(sai->pins_state)) { 566 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 567 if (ret) { 568 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); 569 return ret; 570 } 571 } 572 } 573 574 if (!sai->is_consumer_mode) { 575 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk); 576 if (ret) 577 return ret; 578 579 /* Do not enable the clock if it is already enabled */ 580 if (!(sai->mclk_streams & BIT(substream->stream))) { 581 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 582 if (ret) 583 return ret; 584 585 sai->mclk_streams |= BIT(substream->stream); 586 } 587 } 588 589 if (!sai->is_dsp_mode && !sai->is_pdm_mode) 590 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 591 592 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 593 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 594 595 if (sai->is_lsb_first || sai->is_pdm_mode) 596 val_cr5 |= FSL_SAI_CR5_FBT(0); 597 else 598 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 599 600 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 601 602 /* Set to output mode to avoid tri-stated data pins */ 603 if (tx) 604 val_cr4 |= FSL_SAI_CR4_CHMOD; 605 606 /* 607 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 608 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 609 * RCR5(TCR5) for playback(capture), or there will be sync error. 610 */ 611 612 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) { 613 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 614 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 615 FSL_SAI_CR4_CHMOD_MASK, 616 val_cr4); 617 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 618 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 619 FSL_SAI_CR5_FBT_MASK, val_cr5); 620 } 621 622 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1) 623 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 624 FSL_SAI_CR4_FCOMB_MASK, 0); 625 else 626 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 627 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); 628 629 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; 630 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + 631 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4; 632 633 /* Find a proper tcre setting */ 634 for (i = 0; i < sai->soc_data->pins; i++) { 635 trce_mask = (1 << (i + 1)) - 1; 636 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins) 637 break; 638 } 639 640 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 641 FSL_SAI_CR3_TRCE_MASK, 642 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); 643 644 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 645 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 646 FSL_SAI_CR4_CHMOD_MASK, 647 val_cr4); 648 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 649 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 650 FSL_SAI_CR5_FBT_MASK, val_cr5); 651 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 652 ~0UL - ((1 << min(channels, slots)) - 1)); 653 654 return 0; 655 } 656 657 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 658 struct snd_soc_dai *cpu_dai) 659 { 660 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 661 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 662 unsigned int ofs = sai->soc_data->reg_offset; 663 664 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 665 FSL_SAI_CR3_TRCE_MASK, 0); 666 667 if (!sai->is_consumer_mode && 668 sai->mclk_streams & BIT(substream->stream)) { 669 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 670 sai->mclk_streams &= ~BIT(substream->stream); 671 } 672 673 return 0; 674 } 675 676 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 677 { 678 unsigned int ofs = sai->soc_data->reg_offset; 679 bool tx = dir == TX; 680 u32 xcsr, count = 100; 681 682 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 683 FSL_SAI_CSR_TERE, 0); 684 685 /* TERE will remain set till the end of current frame */ 686 do { 687 udelay(10); 688 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 689 } while (--count && xcsr & FSL_SAI_CSR_TERE); 690 691 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 692 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 693 694 /* 695 * For sai master mode, after several open/close sai, 696 * there will be no frame clock, and can't recover 697 * anymore. Add software reset to fix this issue. 698 * This is a hardware bug, and will be fix in the 699 * next sai version. 700 */ 701 if (!sai->is_consumer_mode) { 702 /* Software Reset */ 703 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); 704 /* Clear SR bit to finish the reset */ 705 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); 706 } 707 } 708 709 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 710 struct snd_soc_dai *cpu_dai) 711 { 712 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 713 unsigned int ofs = sai->soc_data->reg_offset; 714 715 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 716 int adir = tx ? RX : TX; 717 int dir = tx ? TX : RX; 718 u32 xcsr; 719 720 /* 721 * Asynchronous mode: Clear SYNC for both Tx and Rx. 722 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 723 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 724 */ 725 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 726 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 727 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 728 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 729 730 /* 731 * It is recommended that the transmitter is the last enabled 732 * and the first disabled. 733 */ 734 switch (cmd) { 735 case SNDRV_PCM_TRIGGER_START: 736 case SNDRV_PCM_TRIGGER_RESUME: 737 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 738 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 739 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 740 741 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 742 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 743 /* 744 * Enable the opposite direction for synchronous mode 745 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 746 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 747 * 748 * RM recommends to enable RE after TE for case 1 and to enable 749 * TE after RE for case 2, but we here may not always guarantee 750 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 751 * TE after RE, which is against what RM recommends but should 752 * be safe to do, judging by years of testing results. 753 */ 754 if (fsl_sai_dir_is_synced(sai, adir)) 755 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 756 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 757 758 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 759 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 760 break; 761 case SNDRV_PCM_TRIGGER_STOP: 762 case SNDRV_PCM_TRIGGER_SUSPEND: 763 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 764 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 765 FSL_SAI_CSR_FRDE, 0); 766 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 767 FSL_SAI_CSR_xIE_MASK, 0); 768 769 /* Check if the opposite FRDE is also disabled */ 770 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 771 772 /* 773 * If opposite stream provides clocks for synchronous mode and 774 * it is inactive, disable it before disabling the current one 775 */ 776 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 777 fsl_sai_config_disable(sai, adir); 778 779 /* 780 * Disable current stream if either of: 781 * 1. current stream doesn't provide clocks for synchronous mode 782 * 2. current stream provides clocks for synchronous mode but no 783 * more stream is active. 784 */ 785 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 786 fsl_sai_config_disable(sai, dir); 787 788 break; 789 default: 790 return -EINVAL; 791 } 792 793 return 0; 794 } 795 796 static int fsl_sai_startup(struct snd_pcm_substream *substream, 797 struct snd_soc_dai *cpu_dai) 798 { 799 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 800 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 801 int ret; 802 803 /* 804 * EDMA controller needs period size to be a multiple of 805 * tx/rx maxburst 806 */ 807 if (sai->soc_data->use_edma) 808 snd_pcm_hw_constraint_step(substream->runtime, 0, 809 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 810 tx ? sai->dma_params_tx.maxburst : 811 sai->dma_params_rx.maxburst); 812 813 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 814 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); 815 816 return ret; 817 } 818 819 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 820 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 821 .set_sysclk = fsl_sai_set_dai_sysclk, 822 .set_fmt = fsl_sai_set_dai_fmt, 823 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 824 .hw_params = fsl_sai_hw_params, 825 .hw_free = fsl_sai_hw_free, 826 .trigger = fsl_sai_trigger, 827 .startup = fsl_sai_startup, 828 }; 829 830 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 831 { 832 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 833 unsigned int ofs = sai->soc_data->reg_offset; 834 835 /* Software Reset for both Tx and Rx */ 836 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 837 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 838 /* Clear SR bit to finish the reset */ 839 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 840 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 841 842 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 843 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 844 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX); 845 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 846 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 847 FSL_SAI_MAXBURST_RX - 1); 848 849 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 850 &sai->dma_params_rx); 851 852 return 0; 853 } 854 855 static int fsl_sai_dai_resume(struct snd_soc_component *component) 856 { 857 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 858 struct device *dev = &sai->pdev->dev; 859 int ret; 860 861 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { 862 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 863 if (ret) { 864 dev_err(dev, "failed to set proper pins state: %d\n", ret); 865 return ret; 866 } 867 } 868 869 return 0; 870 } 871 872 static struct snd_soc_dai_driver fsl_sai_dai_template = { 873 .probe = fsl_sai_dai_probe, 874 .playback = { 875 .stream_name = "CPU-Playback", 876 .channels_min = 1, 877 .channels_max = 32, 878 .rate_min = 8000, 879 .rate_max = 2822400, 880 .rates = SNDRV_PCM_RATE_KNOT, 881 .formats = FSL_SAI_FORMATS, 882 }, 883 .capture = { 884 .stream_name = "CPU-Capture", 885 .channels_min = 1, 886 .channels_max = 32, 887 .rate_min = 8000, 888 .rate_max = 2822400, 889 .rates = SNDRV_PCM_RATE_KNOT, 890 .formats = FSL_SAI_FORMATS, 891 }, 892 .ops = &fsl_sai_pcm_dai_ops, 893 }; 894 895 static const struct snd_soc_component_driver fsl_component = { 896 .name = "fsl-sai", 897 .resume = fsl_sai_dai_resume, 898 .legacy_dai_naming = 1, 899 }; 900 901 static struct reg_default fsl_sai_reg_defaults_ofs0[] = { 902 {FSL_SAI_TCR1(0), 0}, 903 {FSL_SAI_TCR2(0), 0}, 904 {FSL_SAI_TCR3(0), 0}, 905 {FSL_SAI_TCR4(0), 0}, 906 {FSL_SAI_TCR5(0), 0}, 907 {FSL_SAI_TDR0, 0}, 908 {FSL_SAI_TDR1, 0}, 909 {FSL_SAI_TDR2, 0}, 910 {FSL_SAI_TDR3, 0}, 911 {FSL_SAI_TDR4, 0}, 912 {FSL_SAI_TDR5, 0}, 913 {FSL_SAI_TDR6, 0}, 914 {FSL_SAI_TDR7, 0}, 915 {FSL_SAI_TMR, 0}, 916 {FSL_SAI_RCR1(0), 0}, 917 {FSL_SAI_RCR2(0), 0}, 918 {FSL_SAI_RCR3(0), 0}, 919 {FSL_SAI_RCR4(0), 0}, 920 {FSL_SAI_RCR5(0), 0}, 921 {FSL_SAI_RMR, 0}, 922 }; 923 924 static struct reg_default fsl_sai_reg_defaults_ofs8[] = { 925 {FSL_SAI_TCR1(8), 0}, 926 {FSL_SAI_TCR2(8), 0}, 927 {FSL_SAI_TCR3(8), 0}, 928 {FSL_SAI_TCR4(8), 0}, 929 {FSL_SAI_TCR5(8), 0}, 930 {FSL_SAI_TDR0, 0}, 931 {FSL_SAI_TDR1, 0}, 932 {FSL_SAI_TDR2, 0}, 933 {FSL_SAI_TDR3, 0}, 934 {FSL_SAI_TDR4, 0}, 935 {FSL_SAI_TDR5, 0}, 936 {FSL_SAI_TDR6, 0}, 937 {FSL_SAI_TDR7, 0}, 938 {FSL_SAI_TMR, 0}, 939 {FSL_SAI_RCR1(8), 0}, 940 {FSL_SAI_RCR2(8), 0}, 941 {FSL_SAI_RCR3(8), 0}, 942 {FSL_SAI_RCR4(8), 0}, 943 {FSL_SAI_RCR5(8), 0}, 944 {FSL_SAI_RMR, 0}, 945 {FSL_SAI_MCTL, 0}, 946 {FSL_SAI_MDIV, 0}, 947 }; 948 949 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 950 { 951 struct fsl_sai *sai = dev_get_drvdata(dev); 952 unsigned int ofs = sai->soc_data->reg_offset; 953 954 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 955 return true; 956 957 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 958 return true; 959 960 switch (reg) { 961 case FSL_SAI_TFR0: 962 case FSL_SAI_TFR1: 963 case FSL_SAI_TFR2: 964 case FSL_SAI_TFR3: 965 case FSL_SAI_TFR4: 966 case FSL_SAI_TFR5: 967 case FSL_SAI_TFR6: 968 case FSL_SAI_TFR7: 969 case FSL_SAI_TMR: 970 case FSL_SAI_RDR0: 971 case FSL_SAI_RDR1: 972 case FSL_SAI_RDR2: 973 case FSL_SAI_RDR3: 974 case FSL_SAI_RDR4: 975 case FSL_SAI_RDR5: 976 case FSL_SAI_RDR6: 977 case FSL_SAI_RDR7: 978 case FSL_SAI_RFR0: 979 case FSL_SAI_RFR1: 980 case FSL_SAI_RFR2: 981 case FSL_SAI_RFR3: 982 case FSL_SAI_RFR4: 983 case FSL_SAI_RFR5: 984 case FSL_SAI_RFR6: 985 case FSL_SAI_RFR7: 986 case FSL_SAI_RMR: 987 case FSL_SAI_MCTL: 988 case FSL_SAI_MDIV: 989 case FSL_SAI_VERID: 990 case FSL_SAI_PARAM: 991 case FSL_SAI_TTCTN: 992 case FSL_SAI_RTCTN: 993 case FSL_SAI_TTCTL: 994 case FSL_SAI_TBCTN: 995 case FSL_SAI_TTCAP: 996 case FSL_SAI_RTCTL: 997 case FSL_SAI_RBCTN: 998 case FSL_SAI_RTCAP: 999 return true; 1000 default: 1001 return false; 1002 } 1003 } 1004 1005 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 1006 { 1007 struct fsl_sai *sai = dev_get_drvdata(dev); 1008 unsigned int ofs = sai->soc_data->reg_offset; 1009 1010 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 1011 return true; 1012 1013 /* Set VERID and PARAM be volatile for reading value in probe */ 1014 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 1015 return true; 1016 1017 switch (reg) { 1018 case FSL_SAI_TFR0: 1019 case FSL_SAI_TFR1: 1020 case FSL_SAI_TFR2: 1021 case FSL_SAI_TFR3: 1022 case FSL_SAI_TFR4: 1023 case FSL_SAI_TFR5: 1024 case FSL_SAI_TFR6: 1025 case FSL_SAI_TFR7: 1026 case FSL_SAI_RFR0: 1027 case FSL_SAI_RFR1: 1028 case FSL_SAI_RFR2: 1029 case FSL_SAI_RFR3: 1030 case FSL_SAI_RFR4: 1031 case FSL_SAI_RFR5: 1032 case FSL_SAI_RFR6: 1033 case FSL_SAI_RFR7: 1034 case FSL_SAI_RDR0: 1035 case FSL_SAI_RDR1: 1036 case FSL_SAI_RDR2: 1037 case FSL_SAI_RDR3: 1038 case FSL_SAI_RDR4: 1039 case FSL_SAI_RDR5: 1040 case FSL_SAI_RDR6: 1041 case FSL_SAI_RDR7: 1042 return true; 1043 default: 1044 return false; 1045 } 1046 } 1047 1048 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 1049 { 1050 struct fsl_sai *sai = dev_get_drvdata(dev); 1051 unsigned int ofs = sai->soc_data->reg_offset; 1052 1053 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1054 return true; 1055 1056 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1057 return true; 1058 1059 switch (reg) { 1060 case FSL_SAI_TDR0: 1061 case FSL_SAI_TDR1: 1062 case FSL_SAI_TDR2: 1063 case FSL_SAI_TDR3: 1064 case FSL_SAI_TDR4: 1065 case FSL_SAI_TDR5: 1066 case FSL_SAI_TDR6: 1067 case FSL_SAI_TDR7: 1068 case FSL_SAI_TMR: 1069 case FSL_SAI_RMR: 1070 case FSL_SAI_MCTL: 1071 case FSL_SAI_MDIV: 1072 case FSL_SAI_TTCTL: 1073 case FSL_SAI_RTCTL: 1074 return true; 1075 default: 1076 return false; 1077 } 1078 } 1079 1080 static struct regmap_config fsl_sai_regmap_config = { 1081 .reg_bits = 32, 1082 .reg_stride = 4, 1083 .val_bits = 32, 1084 .fast_io = true, 1085 1086 .max_register = FSL_SAI_RMR, 1087 .reg_defaults = fsl_sai_reg_defaults_ofs0, 1088 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 1089 .readable_reg = fsl_sai_readable_reg, 1090 .volatile_reg = fsl_sai_volatile_reg, 1091 .writeable_reg = fsl_sai_writeable_reg, 1092 .cache_type = REGCACHE_FLAT, 1093 }; 1094 1095 static int fsl_sai_check_version(struct device *dev) 1096 { 1097 struct fsl_sai *sai = dev_get_drvdata(dev); 1098 unsigned char ofs = sai->soc_data->reg_offset; 1099 unsigned int val; 1100 int ret; 1101 1102 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 1103 return 0; 1104 1105 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 1106 if (ret < 0) 1107 return ret; 1108 1109 dev_dbg(dev, "VERID: 0x%016X\n", val); 1110 1111 sai->verid.version = val & 1112 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK); 1113 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 1114 1115 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 1116 if (ret < 0) 1117 return ret; 1118 1119 dev_dbg(dev, "PARAM: 0x%016X\n", val); 1120 1121 /* Max slots per frame, power of 2 */ 1122 sai->param.slot_num = 1 << 1123 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 1124 1125 /* Words per fifo, power of 2 */ 1126 sai->param.fifo_depth = 1 << 1127 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 1128 1129 /* Number of datalines implemented */ 1130 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 1131 1132 return 0; 1133 } 1134 1135 /* 1136 * Calculate the offset between first two datalines, don't 1137 * different offset in one case. 1138 */ 1139 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask) 1140 { 1141 int fbidx, nbidx, offset; 1142 1143 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1144 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1); 1145 offset = nbidx - fbidx - 1; 1146 1147 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); 1148 } 1149 1150 /* 1151 * read the fsl,dataline property from dts file. 1152 * It has 3 value for each configuration, first one means the type: 1153 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is 1154 * dataline mask for 'tx'. for example 1155 * 1156 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>, 1157 * 1158 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type 1159 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). 1160 * 1161 */ 1162 static int fsl_sai_read_dlcfg(struct fsl_sai *sai) 1163 { 1164 struct platform_device *pdev = sai->pdev; 1165 struct device_node *np = pdev->dev.of_node; 1166 struct device *dev = &pdev->dev; 1167 int ret, elems, i, index, num_cfg; 1168 char *propname = "fsl,dataline"; 1169 struct fsl_sai_dl_cfg *cfg; 1170 unsigned long dl_mask; 1171 unsigned int soc_dl; 1172 u32 rx, tx, type; 1173 1174 elems = of_property_count_u32_elems(np, propname); 1175 1176 if (elems <= 0) { 1177 elems = 0; 1178 } else if (elems % 3) { 1179 dev_err(dev, "Number of elements must be divisible to 3.\n"); 1180 return -EINVAL; 1181 } 1182 1183 num_cfg = elems / 3; 1184 /* Add one more for default value */ 1185 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL); 1186 if (!cfg) 1187 return -ENOMEM; 1188 1189 /* Consider default value "0 0xFF 0xFF" if property is missing */ 1190 soc_dl = BIT(sai->soc_data->pins) - 1; 1191 cfg[0].type = FSL_SAI_DL_DEFAULT; 1192 cfg[0].pins[0] = sai->soc_data->pins; 1193 cfg[0].mask[0] = soc_dl; 1194 cfg[0].start_off[0] = 0; 1195 cfg[0].next_off[0] = 0; 1196 1197 cfg[0].pins[1] = sai->soc_data->pins; 1198 cfg[0].mask[1] = soc_dl; 1199 cfg[0].start_off[1] = 0; 1200 cfg[0].next_off[1] = 0; 1201 for (i = 1, index = 0; i < num_cfg + 1; i++) { 1202 /* 1203 * type of dataline 1204 * 0 means default mode 1205 * 1 means I2S mode 1206 * 2 means PDM mode 1207 */ 1208 ret = of_property_read_u32_index(np, propname, index++, &type); 1209 if (ret) 1210 return -EINVAL; 1211 1212 ret = of_property_read_u32_index(np, propname, index++, &rx); 1213 if (ret) 1214 return -EINVAL; 1215 1216 ret = of_property_read_u32_index(np, propname, index++, &tx); 1217 if (ret) 1218 return -EINVAL; 1219 1220 if ((rx & ~soc_dl) || (tx & ~soc_dl)) { 1221 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl); 1222 return -EINVAL; 1223 } 1224 1225 rx = rx & soc_dl; 1226 tx = tx & soc_dl; 1227 1228 cfg[i].type = type; 1229 cfg[i].pins[0] = hweight8(rx); 1230 cfg[i].mask[0] = rx; 1231 dl_mask = rx; 1232 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1233 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx); 1234 1235 cfg[i].pins[1] = hweight8(tx); 1236 cfg[i].mask[1] = tx; 1237 dl_mask = tx; 1238 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1239 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx); 1240 } 1241 1242 sai->dl_cfg = cfg; 1243 sai->dl_cfg_cnt = num_cfg + 1; 1244 return 0; 1245 } 1246 1247 static int fsl_sai_runtime_suspend(struct device *dev); 1248 static int fsl_sai_runtime_resume(struct device *dev); 1249 1250 static int fsl_sai_probe(struct platform_device *pdev) 1251 { 1252 struct device_node *np = pdev->dev.of_node; 1253 struct device *dev = &pdev->dev; 1254 struct fsl_sai *sai; 1255 struct regmap *gpr; 1256 void __iomem *base; 1257 char tmp[8]; 1258 int irq, ret, i; 1259 int index; 1260 1261 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); 1262 if (!sai) 1263 return -ENOMEM; 1264 1265 sai->pdev = pdev; 1266 sai->soc_data = of_device_get_match_data(dev); 1267 1268 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1269 1270 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); 1271 if (IS_ERR(base)) 1272 return PTR_ERR(base); 1273 1274 if (sai->soc_data->reg_offset == 8) { 1275 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1276 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1277 fsl_sai_regmap_config.num_reg_defaults = 1278 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1279 } 1280 1281 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); 1282 if (IS_ERR(sai->regmap)) { 1283 dev_err(dev, "regmap init failed\n"); 1284 return PTR_ERR(sai->regmap); 1285 } 1286 1287 sai->bus_clk = devm_clk_get(dev, "bus"); 1288 /* Compatible with old DTB cases */ 1289 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1290 sai->bus_clk = devm_clk_get(dev, "sai"); 1291 if (IS_ERR(sai->bus_clk)) { 1292 dev_err(dev, "failed to get bus clock: %ld\n", 1293 PTR_ERR(sai->bus_clk)); 1294 /* -EPROBE_DEFER */ 1295 return PTR_ERR(sai->bus_clk); 1296 } 1297 1298 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1299 sprintf(tmp, "mclk%d", i); 1300 sai->mclk_clk[i] = devm_clk_get(dev, tmp); 1301 if (IS_ERR(sai->mclk_clk[i])) { 1302 dev_err(dev, "failed to get mclk%d clock: %ld\n", 1303 i, PTR_ERR(sai->mclk_clk[i])); 1304 sai->mclk_clk[i] = NULL; 1305 } 1306 } 1307 1308 if (sai->soc_data->mclk0_is_mclk1) 1309 sai->mclk_clk[0] = sai->mclk_clk[1]; 1310 else 1311 sai->mclk_clk[0] = sai->bus_clk; 1312 1313 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, 1314 &sai->pll11k_clk); 1315 1316 /* read dataline mask for rx and tx*/ 1317 ret = fsl_sai_read_dlcfg(sai); 1318 if (ret < 0) { 1319 dev_err(dev, "failed to read dlcfg %d\n", ret); 1320 return ret; 1321 } 1322 1323 irq = platform_get_irq(pdev, 0); 1324 if (irq < 0) 1325 return irq; 1326 1327 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED, 1328 np->name, sai); 1329 if (ret) { 1330 dev_err(dev, "failed to claim irq %u\n", irq); 1331 return ret; 1332 } 1333 1334 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, 1335 sizeof(fsl_sai_dai_template)); 1336 1337 /* Sync Tx with Rx as default by following old DT binding */ 1338 sai->synchronous[RX] = true; 1339 sai->synchronous[TX] = false; 1340 sai->cpu_dai_drv.symmetric_rate = 1; 1341 sai->cpu_dai_drv.symmetric_channels = 1; 1342 sai->cpu_dai_drv.symmetric_sample_bits = 1; 1343 1344 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && 1345 of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1346 /* error out if both synchronous and asynchronous are present */ 1347 dev_err(dev, "invalid binding for synchronous mode\n"); 1348 return -EINVAL; 1349 } 1350 1351 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { 1352 /* Sync Rx with Tx */ 1353 sai->synchronous[RX] = false; 1354 sai->synchronous[TX] = true; 1355 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1356 /* Discard all settings for asynchronous mode */ 1357 sai->synchronous[RX] = false; 1358 sai->synchronous[TX] = false; 1359 sai->cpu_dai_drv.symmetric_rate = 0; 1360 sai->cpu_dai_drv.symmetric_channels = 0; 1361 sai->cpu_dai_drv.symmetric_sample_bits = 0; 1362 } 1363 1364 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1365 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1366 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1367 if (IS_ERR(gpr)) { 1368 dev_err(dev, "cannot find iomuxc registers\n"); 1369 return PTR_ERR(gpr); 1370 } 1371 1372 index = of_alias_get_id(np, "sai"); 1373 if (index < 0) 1374 return index; 1375 1376 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1377 MCLK_DIR(index)); 1378 } 1379 1380 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; 1381 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; 1382 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; 1383 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; 1384 1385 sai->pinctrl = devm_pinctrl_get(&pdev->dev); 1386 1387 platform_set_drvdata(pdev, sai); 1388 pm_runtime_enable(dev); 1389 if (!pm_runtime_enabled(dev)) { 1390 ret = fsl_sai_runtime_resume(dev); 1391 if (ret) 1392 goto err_pm_disable; 1393 } 1394 1395 ret = pm_runtime_resume_and_get(dev); 1396 if (ret < 0) 1397 goto err_pm_get_sync; 1398 1399 /* Get sai version */ 1400 ret = fsl_sai_check_version(dev); 1401 if (ret < 0) 1402 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1403 1404 /* Select MCLK direction */ 1405 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1406 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1407 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1408 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1409 } 1410 1411 ret = pm_runtime_put_sync(dev); 1412 if (ret < 0) 1413 goto err_pm_get_sync; 1414 1415 /* 1416 * Register platform component before registering cpu dai for there 1417 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1418 */ 1419 if (sai->soc_data->use_imx_pcm) { 1420 ret = imx_pcm_dma_init(pdev); 1421 if (ret) { 1422 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)) 1423 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); 1424 goto err_pm_get_sync; 1425 } 1426 } else { 1427 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1428 if (ret) 1429 goto err_pm_get_sync; 1430 } 1431 1432 ret = devm_snd_soc_register_component(dev, &fsl_component, 1433 &sai->cpu_dai_drv, 1); 1434 if (ret) 1435 goto err_pm_get_sync; 1436 1437 return ret; 1438 1439 err_pm_get_sync: 1440 if (!pm_runtime_status_suspended(dev)) 1441 fsl_sai_runtime_suspend(dev); 1442 err_pm_disable: 1443 pm_runtime_disable(dev); 1444 1445 return ret; 1446 } 1447 1448 static int fsl_sai_remove(struct platform_device *pdev) 1449 { 1450 pm_runtime_disable(&pdev->dev); 1451 if (!pm_runtime_status_suspended(&pdev->dev)) 1452 fsl_sai_runtime_suspend(&pdev->dev); 1453 1454 return 0; 1455 } 1456 1457 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1458 .use_imx_pcm = false, 1459 .use_edma = false, 1460 .fifo_depth = 32, 1461 .pins = 1, 1462 .reg_offset = 0, 1463 .mclk0_is_mclk1 = false, 1464 .flags = 0, 1465 .max_register = FSL_SAI_RMR, 1466 }; 1467 1468 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1469 .use_imx_pcm = true, 1470 .use_edma = false, 1471 .fifo_depth = 32, 1472 .pins = 1, 1473 .reg_offset = 0, 1474 .mclk0_is_mclk1 = true, 1475 .flags = 0, 1476 .max_register = FSL_SAI_RMR, 1477 }; 1478 1479 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1480 .use_imx_pcm = true, 1481 .use_edma = false, 1482 .fifo_depth = 16, 1483 .pins = 2, 1484 .reg_offset = 8, 1485 .mclk0_is_mclk1 = false, 1486 .flags = PMQOS_CPU_LATENCY, 1487 .max_register = FSL_SAI_RMR, 1488 }; 1489 1490 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1491 .use_imx_pcm = true, 1492 .use_edma = false, 1493 .fifo_depth = 128, 1494 .pins = 8, 1495 .reg_offset = 8, 1496 .mclk0_is_mclk1 = false, 1497 .flags = 0, 1498 .max_register = FSL_SAI_RMR, 1499 }; 1500 1501 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1502 .use_imx_pcm = true, 1503 .use_edma = true, 1504 .fifo_depth = 64, 1505 .pins = 1, 1506 .reg_offset = 0, 1507 .mclk0_is_mclk1 = false, 1508 .flags = 0, 1509 .max_register = FSL_SAI_RMR, 1510 }; 1511 1512 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = { 1513 .use_imx_pcm = true, 1514 .use_edma = false, 1515 .fifo_depth = 128, 1516 .reg_offset = 8, 1517 .mclk0_is_mclk1 = false, 1518 .pins = 8, 1519 .flags = 0, 1520 .max_register = FSL_SAI_MCTL, 1521 }; 1522 1523 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1524 .use_imx_pcm = true, 1525 .use_edma = false, 1526 .fifo_depth = 128, 1527 .reg_offset = 8, 1528 .mclk0_is_mclk1 = false, 1529 .pins = 8, 1530 .flags = 0, 1531 .max_register = FSL_SAI_MDIV, 1532 }; 1533 1534 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { 1535 .use_imx_pcm = true, 1536 .use_edma = true, 1537 .fifo_depth = 16, 1538 .reg_offset = 8, 1539 .mclk0_is_mclk1 = false, 1540 .pins = 4, 1541 .flags = PMQOS_CPU_LATENCY, 1542 .max_register = FSL_SAI_RTCAP, 1543 }; 1544 1545 static const struct of_device_id fsl_sai_ids[] = { 1546 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1547 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1548 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1549 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1550 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1551 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1552 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1553 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1554 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1555 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mp_data }, 1556 { /* sentinel */ } 1557 }; 1558 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1559 1560 static int fsl_sai_runtime_suspend(struct device *dev) 1561 { 1562 struct fsl_sai *sai = dev_get_drvdata(dev); 1563 1564 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1565 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1566 1567 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1568 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1569 1570 clk_disable_unprepare(sai->bus_clk); 1571 1572 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1573 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1574 1575 regcache_cache_only(sai->regmap, true); 1576 1577 return 0; 1578 } 1579 1580 static int fsl_sai_runtime_resume(struct device *dev) 1581 { 1582 struct fsl_sai *sai = dev_get_drvdata(dev); 1583 unsigned int ofs = sai->soc_data->reg_offset; 1584 int ret; 1585 1586 ret = clk_prepare_enable(sai->bus_clk); 1587 if (ret) { 1588 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1589 return ret; 1590 } 1591 1592 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1593 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1594 if (ret) 1595 goto disable_bus_clk; 1596 } 1597 1598 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1599 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1600 if (ret) 1601 goto disable_tx_clk; 1602 } 1603 1604 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1605 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1606 1607 regcache_cache_only(sai->regmap, false); 1608 regcache_mark_dirty(sai->regmap); 1609 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 1610 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 1611 usleep_range(1000, 2000); 1612 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1613 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1614 1615 ret = regcache_sync(sai->regmap); 1616 if (ret) 1617 goto disable_rx_clk; 1618 1619 return 0; 1620 1621 disable_rx_clk: 1622 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1623 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1624 disable_tx_clk: 1625 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1626 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1627 disable_bus_clk: 1628 clk_disable_unprepare(sai->bus_clk); 1629 1630 return ret; 1631 } 1632 1633 static const struct dev_pm_ops fsl_sai_pm_ops = { 1634 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, 1635 fsl_sai_runtime_resume, NULL) 1636 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1637 pm_runtime_force_resume) 1638 }; 1639 1640 static struct platform_driver fsl_sai_driver = { 1641 .probe = fsl_sai_probe, 1642 .remove = fsl_sai_remove, 1643 .driver = { 1644 .name = "fsl-sai", 1645 .pm = &fsl_sai_pm_ops, 1646 .of_match_table = fsl_sai_ids, 1647 }, 1648 }; 1649 module_platform_driver(fsl_sai_driver); 1650 1651 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1652 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1653 MODULE_ALIAS("platform:fsl-sai"); 1654 MODULE_LICENSE("GPL"); 1655