1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/pm_qos.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 #include <linux/time.h> 18 #include <sound/core.h> 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 23 24 #include "fsl_sai.h" 25 #include "imx-pcm.h" 26 27 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 28 FSL_SAI_CSR_FEIE) 29 30 static const unsigned int fsl_sai_rates[] = { 31 8000, 11025, 12000, 16000, 22050, 32 24000, 32000, 44100, 48000, 64000, 33 88200, 96000, 176400, 192000 34 }; 35 36 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 37 .count = ARRAY_SIZE(fsl_sai_rates), 38 .list = fsl_sai_rates, 39 }; 40 41 /** 42 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 43 * 44 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 45 * or Receiver's for both streams. This function is used to check if clocks of 46 * the stream's are synced by the opposite stream. 47 * 48 * @sai: SAI context 49 * @dir: stream direction 50 */ 51 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 52 { 53 int adir = (dir == TX) ? RX : TX; 54 55 /* current dir in async mode while opposite dir in sync mode */ 56 return !sai->synchronous[dir] && sai->synchronous[adir]; 57 } 58 59 static irqreturn_t fsl_sai_isr(int irq, void *devid) 60 { 61 struct fsl_sai *sai = (struct fsl_sai *)devid; 62 unsigned int ofs = sai->soc_data->reg_offset; 63 struct device *dev = &sai->pdev->dev; 64 u32 flags, xcsr, mask; 65 bool irq_none = true; 66 67 /* 68 * Both IRQ status bits and IRQ mask bits are in the xCSR but 69 * different shifts. And we here create a mask only for those 70 * IRQs that we activated. 71 */ 72 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 73 74 /* Tx IRQ */ 75 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 76 flags = xcsr & mask; 77 78 if (flags) 79 irq_none = false; 80 else 81 goto irq_rx; 82 83 if (flags & FSL_SAI_CSR_WSF) 84 dev_dbg(dev, "isr: Start of Tx word detected\n"); 85 86 if (flags & FSL_SAI_CSR_SEF) 87 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 88 89 if (flags & FSL_SAI_CSR_FEF) { 90 dev_dbg(dev, "isr: Transmit underrun detected\n"); 91 /* FIFO reset for safety */ 92 xcsr |= FSL_SAI_CSR_FR; 93 } 94 95 if (flags & FSL_SAI_CSR_FWF) 96 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 97 98 if (flags & FSL_SAI_CSR_FRF) 99 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 100 101 flags &= FSL_SAI_CSR_xF_W_MASK; 102 xcsr &= ~FSL_SAI_CSR_xF_MASK; 103 104 if (flags) 105 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 106 107 irq_rx: 108 /* Rx IRQ */ 109 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 110 flags = xcsr & mask; 111 112 if (flags) 113 irq_none = false; 114 else 115 goto out; 116 117 if (flags & FSL_SAI_CSR_WSF) 118 dev_dbg(dev, "isr: Start of Rx word detected\n"); 119 120 if (flags & FSL_SAI_CSR_SEF) 121 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 122 123 if (flags & FSL_SAI_CSR_FEF) { 124 dev_dbg(dev, "isr: Receive overflow detected\n"); 125 /* FIFO reset for safety */ 126 xcsr |= FSL_SAI_CSR_FR; 127 } 128 129 if (flags & FSL_SAI_CSR_FWF) 130 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 131 132 if (flags & FSL_SAI_CSR_FRF) 133 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 134 135 flags &= FSL_SAI_CSR_xF_W_MASK; 136 xcsr &= ~FSL_SAI_CSR_xF_MASK; 137 138 if (flags) 139 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 140 141 out: 142 if (irq_none) 143 return IRQ_NONE; 144 else 145 return IRQ_HANDLED; 146 } 147 148 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 149 u32 rx_mask, int slots, int slot_width) 150 { 151 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 152 153 sai->slots = slots; 154 sai->slot_width = slot_width; 155 156 return 0; 157 } 158 159 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 160 unsigned int ratio) 161 { 162 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 163 164 sai->bclk_ratio = ratio; 165 166 return 0; 167 } 168 169 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 170 int clk_id, unsigned int freq, int fsl_dir) 171 { 172 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 173 unsigned int ofs = sai->soc_data->reg_offset; 174 bool tx = fsl_dir == FSL_FMT_TRANSMITTER; 175 u32 val_cr2 = 0; 176 177 switch (clk_id) { 178 case FSL_SAI_CLK_BUS: 179 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 180 break; 181 case FSL_SAI_CLK_MAST1: 182 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 183 break; 184 case FSL_SAI_CLK_MAST2: 185 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 186 break; 187 case FSL_SAI_CLK_MAST3: 188 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 189 break; 190 default: 191 return -EINVAL; 192 } 193 194 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 195 FSL_SAI_CR2_MSEL_MASK, val_cr2); 196 197 return 0; 198 } 199 200 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 201 int clk_id, unsigned int freq, int dir) 202 { 203 int ret; 204 205 if (dir == SND_SOC_CLOCK_IN) 206 return 0; 207 208 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, 209 FSL_FMT_TRANSMITTER); 210 if (ret) { 211 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 212 return ret; 213 } 214 215 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, 216 FSL_FMT_RECEIVER); 217 if (ret) 218 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 219 220 return ret; 221 } 222 223 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 224 unsigned int fmt, int fsl_dir) 225 { 226 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 227 unsigned int ofs = sai->soc_data->reg_offset; 228 bool tx = fsl_dir == FSL_FMT_TRANSMITTER; 229 u32 val_cr2 = 0, val_cr4 = 0; 230 231 if (!sai->is_lsb_first) 232 val_cr4 |= FSL_SAI_CR4_MF; 233 234 /* DAI mode */ 235 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 236 case SND_SOC_DAIFMT_I2S: 237 /* 238 * Frame low, 1clk before data, one word length for frame sync, 239 * frame sync starts one serial clock cycle earlier, 240 * that is, together with the last bit of the previous 241 * data word. 242 */ 243 val_cr2 |= FSL_SAI_CR2_BCP; 244 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 245 break; 246 case SND_SOC_DAIFMT_LEFT_J: 247 /* 248 * Frame high, one word length for frame sync, 249 * frame sync asserts with the first bit of the frame. 250 */ 251 val_cr2 |= FSL_SAI_CR2_BCP; 252 break; 253 case SND_SOC_DAIFMT_DSP_A: 254 /* 255 * Frame high, 1clk before data, one bit for frame sync, 256 * frame sync starts one serial clock cycle earlier, 257 * that is, together with the last bit of the previous 258 * data word. 259 */ 260 val_cr2 |= FSL_SAI_CR2_BCP; 261 val_cr4 |= FSL_SAI_CR4_FSE; 262 sai->is_dsp_mode = true; 263 break; 264 case SND_SOC_DAIFMT_DSP_B: 265 /* 266 * Frame high, one bit for frame sync, 267 * frame sync asserts with the first bit of the frame. 268 */ 269 val_cr2 |= FSL_SAI_CR2_BCP; 270 sai->is_dsp_mode = true; 271 break; 272 case SND_SOC_DAIFMT_RIGHT_J: 273 /* To be done */ 274 default: 275 return -EINVAL; 276 } 277 278 /* DAI clock inversion */ 279 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 280 case SND_SOC_DAIFMT_IB_IF: 281 /* Invert both clocks */ 282 val_cr2 ^= FSL_SAI_CR2_BCP; 283 val_cr4 ^= FSL_SAI_CR4_FSP; 284 break; 285 case SND_SOC_DAIFMT_IB_NF: 286 /* Invert bit clock */ 287 val_cr2 ^= FSL_SAI_CR2_BCP; 288 break; 289 case SND_SOC_DAIFMT_NB_IF: 290 /* Invert frame clock */ 291 val_cr4 ^= FSL_SAI_CR4_FSP; 292 break; 293 case SND_SOC_DAIFMT_NB_NF: 294 /* Nothing to do for both normal cases */ 295 break; 296 default: 297 return -EINVAL; 298 } 299 300 /* DAI clock master masks */ 301 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 302 case SND_SOC_DAIFMT_CBS_CFS: 303 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 304 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 305 sai->is_slave_mode = false; 306 break; 307 case SND_SOC_DAIFMT_CBM_CFM: 308 sai->is_slave_mode = true; 309 break; 310 case SND_SOC_DAIFMT_CBS_CFM: 311 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 312 sai->is_slave_mode = false; 313 break; 314 case SND_SOC_DAIFMT_CBM_CFS: 315 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 316 sai->is_slave_mode = true; 317 break; 318 default: 319 return -EINVAL; 320 } 321 322 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 323 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 324 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 325 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 326 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 327 328 return 0; 329 } 330 331 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 332 { 333 int ret; 334 335 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER); 336 if (ret) { 337 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 338 return ret; 339 } 340 341 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER); 342 if (ret) 343 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 344 345 return ret; 346 } 347 348 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 349 { 350 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 351 unsigned int ofs = sai->soc_data->reg_offset; 352 unsigned long clk_rate; 353 u32 savediv = 0, ratio, savesub = freq; 354 int adir = tx ? RX : TX; 355 int dir = tx ? TX : RX; 356 u32 id; 357 int ret = 0; 358 359 /* Don't apply to slave mode */ 360 if (sai->is_slave_mode) 361 return 0; 362 363 /* 364 * There is no point in polling MCLK0 if it is identical to MCLK1. 365 * And given that MQS use case has to use MCLK1 though two clocks 366 * are the same, we simply skip MCLK0 and start to find from MCLK1. 367 */ 368 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 369 370 for (; id < FSL_SAI_MCLK_MAX; id++) { 371 clk_rate = clk_get_rate(sai->mclk_clk[id]); 372 if (!clk_rate) 373 continue; 374 375 ratio = clk_rate / freq; 376 377 ret = clk_rate - ratio * freq; 378 379 /* 380 * Drop the source that can not be 381 * divided into the required rate. 382 */ 383 if (ret != 0 && clk_rate / ret < 1000) 384 continue; 385 386 dev_dbg(dai->dev, 387 "ratio %d for freq %dHz based on clock %ldHz\n", 388 ratio, freq, clk_rate); 389 390 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512) 391 ratio /= 2; 392 else 393 continue; 394 395 if (ret < savesub) { 396 savediv = ratio; 397 sai->mclk_id[tx] = id; 398 savesub = ret; 399 } 400 401 if (ret == 0) 402 break; 403 } 404 405 if (savediv == 0) { 406 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 407 tx ? 'T' : 'R', freq); 408 return -EINVAL; 409 } 410 411 /* 412 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 413 * set TCR2 register for playback. 414 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 415 * and capture. 416 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 417 * and capture. 418 * 4) For Tx and Rx are both Synchronous with another SAI, we just 419 * ignore it. 420 */ 421 if (fsl_sai_dir_is_synced(sai, adir)) { 422 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs), 423 FSL_SAI_CR2_MSEL_MASK, 424 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 425 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs), 426 FSL_SAI_CR2_DIV_MASK, savediv - 1); 427 } else if (!sai->synchronous[dir]) { 428 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 429 FSL_SAI_CR2_MSEL_MASK, 430 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 431 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 432 FSL_SAI_CR2_DIV_MASK, savediv - 1); 433 } 434 435 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 436 sai->mclk_id[tx], savediv, savesub); 437 438 return 0; 439 } 440 441 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 442 struct snd_pcm_hw_params *params, 443 struct snd_soc_dai *cpu_dai) 444 { 445 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 446 unsigned int ofs = sai->soc_data->reg_offset; 447 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 448 unsigned int channels = params_channels(params); 449 u32 word_width = params_width(params); 450 u32 val_cr4 = 0, val_cr5 = 0; 451 u32 slots = (channels == 1) ? 2 : channels; 452 u32 slot_width = word_width; 453 int adir = tx ? RX : TX; 454 u32 pins; 455 int ret; 456 457 if (sai->slots) 458 slots = sai->slots; 459 460 if (sai->slot_width) 461 slot_width = sai->slot_width; 462 463 pins = DIV_ROUND_UP(channels, slots); 464 465 if (!sai->is_slave_mode) { 466 if (sai->bclk_ratio) 467 ret = fsl_sai_set_bclk(cpu_dai, tx, 468 sai->bclk_ratio * 469 params_rate(params)); 470 else 471 ret = fsl_sai_set_bclk(cpu_dai, tx, 472 slots * slot_width * 473 params_rate(params)); 474 if (ret) 475 return ret; 476 477 /* Do not enable the clock if it is already enabled */ 478 if (!(sai->mclk_streams & BIT(substream->stream))) { 479 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 480 if (ret) 481 return ret; 482 483 sai->mclk_streams |= BIT(substream->stream); 484 } 485 } 486 487 if (!sai->is_dsp_mode) 488 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 489 490 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 491 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 492 493 if (sai->is_lsb_first) 494 val_cr5 |= FSL_SAI_CR5_FBT(0); 495 else 496 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 497 498 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 499 500 /* Set to output mode to avoid tri-stated data pins */ 501 if (tx) 502 val_cr4 |= FSL_SAI_CR4_CHMOD; 503 504 /* 505 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 506 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 507 * RCR5(TCR5) for playback(capture), or there will be sync error. 508 */ 509 510 if (!sai->is_slave_mode && fsl_sai_dir_is_synced(sai, adir)) { 511 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 512 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 513 FSL_SAI_CR4_CHMOD_MASK, 514 val_cr4); 515 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 516 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 517 FSL_SAI_CR5_FBT_MASK, val_cr5); 518 } 519 520 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 521 FSL_SAI_CR3_TRCE_MASK, 522 FSL_SAI_CR3_TRCE((1 << pins) - 1)); 523 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 524 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 525 FSL_SAI_CR4_CHMOD_MASK, 526 val_cr4); 527 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 528 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 529 FSL_SAI_CR5_FBT_MASK, val_cr5); 530 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 531 ~0UL - ((1 << min(channels, slots)) - 1)); 532 533 return 0; 534 } 535 536 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 537 struct snd_soc_dai *cpu_dai) 538 { 539 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 540 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 541 unsigned int ofs = sai->soc_data->reg_offset; 542 543 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 544 FSL_SAI_CR3_TRCE_MASK, 0); 545 546 if (!sai->is_slave_mode && 547 sai->mclk_streams & BIT(substream->stream)) { 548 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 549 sai->mclk_streams &= ~BIT(substream->stream); 550 } 551 552 return 0; 553 } 554 555 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 556 { 557 unsigned int ofs = sai->soc_data->reg_offset; 558 bool tx = dir == TX; 559 u32 xcsr, count = 100; 560 561 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 562 FSL_SAI_CSR_TERE, 0); 563 564 /* TERE will remain set till the end of current frame */ 565 do { 566 udelay(10); 567 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 568 } while (--count && xcsr & FSL_SAI_CSR_TERE); 569 570 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 571 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 572 573 /* 574 * For sai master mode, after several open/close sai, 575 * there will be no frame clock, and can't recover 576 * anymore. Add software reset to fix this issue. 577 * This is a hardware bug, and will be fix in the 578 * next sai version. 579 */ 580 if (!sai->is_slave_mode) { 581 /* Software Reset */ 582 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); 583 /* Clear SR bit to finish the reset */ 584 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); 585 } 586 } 587 588 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 589 struct snd_soc_dai *cpu_dai) 590 { 591 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 592 unsigned int ofs = sai->soc_data->reg_offset; 593 594 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 595 int adir = tx ? RX : TX; 596 int dir = tx ? TX : RX; 597 u32 xcsr; 598 599 /* 600 * Asynchronous mode: Clear SYNC for both Tx and Rx. 601 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 602 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 603 */ 604 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 605 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 606 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 607 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 608 609 /* 610 * It is recommended that the transmitter is the last enabled 611 * and the first disabled. 612 */ 613 switch (cmd) { 614 case SNDRV_PCM_TRIGGER_START: 615 case SNDRV_PCM_TRIGGER_RESUME: 616 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 617 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 618 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 619 620 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 621 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 622 /* 623 * Enable the opposite direction for synchronous mode 624 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 625 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 626 * 627 * RM recommends to enable RE after TE for case 1 and to enable 628 * TE after RE for case 2, but we here may not always guarantee 629 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 630 * TE after RE, which is against what RM recommends but should 631 * be safe to do, judging by years of testing results. 632 */ 633 if (fsl_sai_dir_is_synced(sai, adir)) 634 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 635 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 636 637 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 638 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 639 break; 640 case SNDRV_PCM_TRIGGER_STOP: 641 case SNDRV_PCM_TRIGGER_SUSPEND: 642 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 643 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 644 FSL_SAI_CSR_FRDE, 0); 645 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 646 FSL_SAI_CSR_xIE_MASK, 0); 647 648 /* Check if the opposite FRDE is also disabled */ 649 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 650 651 /* 652 * If opposite stream provides clocks for synchronous mode and 653 * it is inactive, disable it before disabling the current one 654 */ 655 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 656 fsl_sai_config_disable(sai, adir); 657 658 /* 659 * Disable current stream if either of: 660 * 1. current stream doesn't provide clocks for synchronous mode 661 * 2. current stream provides clocks for synchronous mode but no 662 * more stream is active. 663 */ 664 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 665 fsl_sai_config_disable(sai, dir); 666 667 break; 668 default: 669 return -EINVAL; 670 } 671 672 return 0; 673 } 674 675 static int fsl_sai_startup(struct snd_pcm_substream *substream, 676 struct snd_soc_dai *cpu_dai) 677 { 678 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 679 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 680 int ret; 681 682 /* 683 * EDMA controller needs period size to be a multiple of 684 * tx/rx maxburst 685 */ 686 if (sai->soc_data->use_edma) 687 snd_pcm_hw_constraint_step(substream->runtime, 0, 688 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 689 tx ? sai->dma_params_tx.maxburst : 690 sai->dma_params_rx.maxburst); 691 692 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 693 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); 694 695 return ret; 696 } 697 698 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 699 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 700 .set_sysclk = fsl_sai_set_dai_sysclk, 701 .set_fmt = fsl_sai_set_dai_fmt, 702 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 703 .hw_params = fsl_sai_hw_params, 704 .hw_free = fsl_sai_hw_free, 705 .trigger = fsl_sai_trigger, 706 .startup = fsl_sai_startup, 707 }; 708 709 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 710 { 711 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 712 unsigned int ofs = sai->soc_data->reg_offset; 713 714 /* Software Reset for both Tx and Rx */ 715 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 716 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 717 /* Clear SR bit to finish the reset */ 718 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 719 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 720 721 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 722 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 723 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX); 724 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 725 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 726 FSL_SAI_MAXBURST_RX - 1); 727 728 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 729 &sai->dma_params_rx); 730 731 return 0; 732 } 733 734 static struct snd_soc_dai_driver fsl_sai_dai_template = { 735 .probe = fsl_sai_dai_probe, 736 .playback = { 737 .stream_name = "CPU-Playback", 738 .channels_min = 1, 739 .channels_max = 32, 740 .rate_min = 8000, 741 .rate_max = 192000, 742 .rates = SNDRV_PCM_RATE_KNOT, 743 .formats = FSL_SAI_FORMATS, 744 }, 745 .capture = { 746 .stream_name = "CPU-Capture", 747 .channels_min = 1, 748 .channels_max = 32, 749 .rate_min = 8000, 750 .rate_max = 192000, 751 .rates = SNDRV_PCM_RATE_KNOT, 752 .formats = FSL_SAI_FORMATS, 753 }, 754 .ops = &fsl_sai_pcm_dai_ops, 755 }; 756 757 static const struct snd_soc_component_driver fsl_component = { 758 .name = "fsl-sai", 759 }; 760 761 static struct reg_default fsl_sai_reg_defaults_ofs0[] = { 762 {FSL_SAI_TCR1(0), 0}, 763 {FSL_SAI_TCR2(0), 0}, 764 {FSL_SAI_TCR3(0), 0}, 765 {FSL_SAI_TCR4(0), 0}, 766 {FSL_SAI_TCR5(0), 0}, 767 {FSL_SAI_TDR0, 0}, 768 {FSL_SAI_TDR1, 0}, 769 {FSL_SAI_TDR2, 0}, 770 {FSL_SAI_TDR3, 0}, 771 {FSL_SAI_TDR4, 0}, 772 {FSL_SAI_TDR5, 0}, 773 {FSL_SAI_TDR6, 0}, 774 {FSL_SAI_TDR7, 0}, 775 {FSL_SAI_TMR, 0}, 776 {FSL_SAI_RCR1(0), 0}, 777 {FSL_SAI_RCR2(0), 0}, 778 {FSL_SAI_RCR3(0), 0}, 779 {FSL_SAI_RCR4(0), 0}, 780 {FSL_SAI_RCR5(0), 0}, 781 {FSL_SAI_RMR, 0}, 782 }; 783 784 static struct reg_default fsl_sai_reg_defaults_ofs8[] = { 785 {FSL_SAI_TCR1(8), 0}, 786 {FSL_SAI_TCR2(8), 0}, 787 {FSL_SAI_TCR3(8), 0}, 788 {FSL_SAI_TCR4(8), 0}, 789 {FSL_SAI_TCR5(8), 0}, 790 {FSL_SAI_TDR0, 0}, 791 {FSL_SAI_TDR1, 0}, 792 {FSL_SAI_TDR2, 0}, 793 {FSL_SAI_TDR3, 0}, 794 {FSL_SAI_TDR4, 0}, 795 {FSL_SAI_TDR5, 0}, 796 {FSL_SAI_TDR6, 0}, 797 {FSL_SAI_TDR7, 0}, 798 {FSL_SAI_TMR, 0}, 799 {FSL_SAI_RCR1(8), 0}, 800 {FSL_SAI_RCR2(8), 0}, 801 {FSL_SAI_RCR3(8), 0}, 802 {FSL_SAI_RCR4(8), 0}, 803 {FSL_SAI_RCR5(8), 0}, 804 {FSL_SAI_RMR, 0}, 805 {FSL_SAI_MCTL, 0}, 806 {FSL_SAI_MDIV, 0}, 807 }; 808 809 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 810 { 811 struct fsl_sai *sai = dev_get_drvdata(dev); 812 unsigned int ofs = sai->soc_data->reg_offset; 813 814 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 815 return true; 816 817 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 818 return true; 819 820 switch (reg) { 821 case FSL_SAI_TFR0: 822 case FSL_SAI_TFR1: 823 case FSL_SAI_TFR2: 824 case FSL_SAI_TFR3: 825 case FSL_SAI_TFR4: 826 case FSL_SAI_TFR5: 827 case FSL_SAI_TFR6: 828 case FSL_SAI_TFR7: 829 case FSL_SAI_TMR: 830 case FSL_SAI_RDR0: 831 case FSL_SAI_RDR1: 832 case FSL_SAI_RDR2: 833 case FSL_SAI_RDR3: 834 case FSL_SAI_RDR4: 835 case FSL_SAI_RDR5: 836 case FSL_SAI_RDR6: 837 case FSL_SAI_RDR7: 838 case FSL_SAI_RFR0: 839 case FSL_SAI_RFR1: 840 case FSL_SAI_RFR2: 841 case FSL_SAI_RFR3: 842 case FSL_SAI_RFR4: 843 case FSL_SAI_RFR5: 844 case FSL_SAI_RFR6: 845 case FSL_SAI_RFR7: 846 case FSL_SAI_RMR: 847 case FSL_SAI_MCTL: 848 case FSL_SAI_MDIV: 849 case FSL_SAI_VERID: 850 case FSL_SAI_PARAM: 851 case FSL_SAI_TTCTN: 852 case FSL_SAI_RTCTN: 853 case FSL_SAI_TTCTL: 854 case FSL_SAI_TBCTN: 855 case FSL_SAI_TTCAP: 856 case FSL_SAI_RTCTL: 857 case FSL_SAI_RBCTN: 858 case FSL_SAI_RTCAP: 859 return true; 860 default: 861 return false; 862 } 863 } 864 865 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 866 { 867 struct fsl_sai *sai = dev_get_drvdata(dev); 868 unsigned int ofs = sai->soc_data->reg_offset; 869 870 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 871 return true; 872 873 /* Set VERID and PARAM be volatile for reading value in probe */ 874 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 875 return true; 876 877 switch (reg) { 878 case FSL_SAI_TFR0: 879 case FSL_SAI_TFR1: 880 case FSL_SAI_TFR2: 881 case FSL_SAI_TFR3: 882 case FSL_SAI_TFR4: 883 case FSL_SAI_TFR5: 884 case FSL_SAI_TFR6: 885 case FSL_SAI_TFR7: 886 case FSL_SAI_RFR0: 887 case FSL_SAI_RFR1: 888 case FSL_SAI_RFR2: 889 case FSL_SAI_RFR3: 890 case FSL_SAI_RFR4: 891 case FSL_SAI_RFR5: 892 case FSL_SAI_RFR6: 893 case FSL_SAI_RFR7: 894 case FSL_SAI_RDR0: 895 case FSL_SAI_RDR1: 896 case FSL_SAI_RDR2: 897 case FSL_SAI_RDR3: 898 case FSL_SAI_RDR4: 899 case FSL_SAI_RDR5: 900 case FSL_SAI_RDR6: 901 case FSL_SAI_RDR7: 902 return true; 903 default: 904 return false; 905 } 906 } 907 908 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 909 { 910 struct fsl_sai *sai = dev_get_drvdata(dev); 911 unsigned int ofs = sai->soc_data->reg_offset; 912 913 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 914 return true; 915 916 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 917 return true; 918 919 switch (reg) { 920 case FSL_SAI_TDR0: 921 case FSL_SAI_TDR1: 922 case FSL_SAI_TDR2: 923 case FSL_SAI_TDR3: 924 case FSL_SAI_TDR4: 925 case FSL_SAI_TDR5: 926 case FSL_SAI_TDR6: 927 case FSL_SAI_TDR7: 928 case FSL_SAI_TMR: 929 case FSL_SAI_RMR: 930 case FSL_SAI_MCTL: 931 case FSL_SAI_MDIV: 932 case FSL_SAI_TTCTL: 933 case FSL_SAI_RTCTL: 934 return true; 935 default: 936 return false; 937 } 938 } 939 940 static struct regmap_config fsl_sai_regmap_config = { 941 .reg_bits = 32, 942 .reg_stride = 4, 943 .val_bits = 32, 944 .fast_io = true, 945 946 .max_register = FSL_SAI_RMR, 947 .reg_defaults = fsl_sai_reg_defaults_ofs0, 948 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 949 .readable_reg = fsl_sai_readable_reg, 950 .volatile_reg = fsl_sai_volatile_reg, 951 .writeable_reg = fsl_sai_writeable_reg, 952 .cache_type = REGCACHE_FLAT, 953 }; 954 955 static int fsl_sai_check_version(struct device *dev) 956 { 957 struct fsl_sai *sai = dev_get_drvdata(dev); 958 unsigned char ofs = sai->soc_data->reg_offset; 959 unsigned int val; 960 int ret; 961 962 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 963 return 0; 964 965 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 966 if (ret < 0) 967 return ret; 968 969 dev_dbg(dev, "VERID: 0x%016X\n", val); 970 971 sai->verid.major = (val & FSL_SAI_VERID_MAJOR_MASK) >> 972 FSL_SAI_VERID_MAJOR_SHIFT; 973 sai->verid.minor = (val & FSL_SAI_VERID_MINOR_MASK) >> 974 FSL_SAI_VERID_MINOR_SHIFT; 975 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 976 977 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 978 if (ret < 0) 979 return ret; 980 981 dev_dbg(dev, "PARAM: 0x%016X\n", val); 982 983 /* Max slots per frame, power of 2 */ 984 sai->param.slot_num = 1 << 985 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 986 987 /* Words per fifo, power of 2 */ 988 sai->param.fifo_depth = 1 << 989 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 990 991 /* Number of datalines implemented */ 992 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 993 994 return 0; 995 } 996 997 static int fsl_sai_runtime_suspend(struct device *dev); 998 static int fsl_sai_runtime_resume(struct device *dev); 999 1000 static int fsl_sai_probe(struct platform_device *pdev) 1001 { 1002 struct device_node *np = pdev->dev.of_node; 1003 struct fsl_sai *sai; 1004 struct regmap *gpr; 1005 struct resource *res; 1006 void __iomem *base; 1007 char tmp[8]; 1008 int irq, ret, i; 1009 int index; 1010 1011 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1012 if (!sai) 1013 return -ENOMEM; 1014 1015 sai->pdev = pdev; 1016 sai->soc_data = of_device_get_match_data(&pdev->dev); 1017 1018 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1019 1020 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1021 base = devm_ioremap_resource(&pdev->dev, res); 1022 if (IS_ERR(base)) 1023 return PTR_ERR(base); 1024 1025 if (sai->soc_data->reg_offset == 8) { 1026 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1027 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1028 fsl_sai_regmap_config.num_reg_defaults = 1029 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1030 } 1031 1032 sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, &fsl_sai_regmap_config); 1033 if (IS_ERR(sai->regmap)) { 1034 dev_err(&pdev->dev, "regmap init failed\n"); 1035 return PTR_ERR(sai->regmap); 1036 } 1037 1038 sai->bus_clk = devm_clk_get(&pdev->dev, "bus"); 1039 /* Compatible with old DTB cases */ 1040 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1041 sai->bus_clk = devm_clk_get(&pdev->dev, "sai"); 1042 if (IS_ERR(sai->bus_clk)) { 1043 dev_err(&pdev->dev, "failed to get bus clock: %ld\n", 1044 PTR_ERR(sai->bus_clk)); 1045 /* -EPROBE_DEFER */ 1046 return PTR_ERR(sai->bus_clk); 1047 } 1048 1049 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1050 sprintf(tmp, "mclk%d", i); 1051 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp); 1052 if (IS_ERR(sai->mclk_clk[i])) { 1053 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n", 1054 i + 1, PTR_ERR(sai->mclk_clk[i])); 1055 sai->mclk_clk[i] = NULL; 1056 } 1057 } 1058 1059 if (sai->soc_data->mclk0_is_mclk1) 1060 sai->mclk_clk[0] = sai->mclk_clk[1]; 1061 else 1062 sai->mclk_clk[0] = sai->bus_clk; 1063 1064 irq = platform_get_irq(pdev, 0); 1065 if (irq < 0) 1066 return irq; 1067 1068 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, IRQF_SHARED, 1069 np->name, sai); 1070 if (ret) { 1071 dev_err(&pdev->dev, "failed to claim irq %u\n", irq); 1072 return ret; 1073 } 1074 1075 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, 1076 sizeof(fsl_sai_dai_template)); 1077 1078 /* Sync Tx with Rx as default by following old DT binding */ 1079 sai->synchronous[RX] = true; 1080 sai->synchronous[TX] = false; 1081 sai->cpu_dai_drv.symmetric_rate = 1; 1082 sai->cpu_dai_drv.symmetric_channels = 1; 1083 sai->cpu_dai_drv.symmetric_sample_bits = 1; 1084 1085 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && 1086 of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1087 /* error out if both synchronous and asynchronous are present */ 1088 dev_err(&pdev->dev, "invalid binding for synchronous mode\n"); 1089 return -EINVAL; 1090 } 1091 1092 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { 1093 /* Sync Rx with Tx */ 1094 sai->synchronous[RX] = false; 1095 sai->synchronous[TX] = true; 1096 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1097 /* Discard all settings for asynchronous mode */ 1098 sai->synchronous[RX] = false; 1099 sai->synchronous[TX] = false; 1100 sai->cpu_dai_drv.symmetric_rate = 0; 1101 sai->cpu_dai_drv.symmetric_channels = 0; 1102 sai->cpu_dai_drv.symmetric_sample_bits = 0; 1103 } 1104 1105 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1106 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1107 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1108 if (IS_ERR(gpr)) { 1109 dev_err(&pdev->dev, "cannot find iomuxc registers\n"); 1110 return PTR_ERR(gpr); 1111 } 1112 1113 index = of_alias_get_id(np, "sai"); 1114 if (index < 0) 1115 return index; 1116 1117 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1118 MCLK_DIR(index)); 1119 } 1120 1121 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0; 1122 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0; 1123 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; 1124 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; 1125 1126 platform_set_drvdata(pdev, sai); 1127 pm_runtime_enable(&pdev->dev); 1128 if (!pm_runtime_enabled(&pdev->dev)) { 1129 ret = fsl_sai_runtime_resume(&pdev->dev); 1130 if (ret) 1131 goto err_pm_disable; 1132 } 1133 1134 ret = pm_runtime_get_sync(&pdev->dev); 1135 if (ret < 0) { 1136 pm_runtime_put_noidle(&pdev->dev); 1137 goto err_pm_get_sync; 1138 } 1139 1140 /* Get sai version */ 1141 ret = fsl_sai_check_version(&pdev->dev); 1142 if (ret < 0) 1143 dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret); 1144 1145 /* Select MCLK direction */ 1146 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1147 sai->verid.major >= 3 && sai->verid.minor >= 1) { 1148 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1149 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1150 } 1151 1152 ret = pm_runtime_put_sync(&pdev->dev); 1153 if (ret < 0) 1154 goto err_pm_get_sync; 1155 1156 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component, 1157 &sai->cpu_dai_drv, 1); 1158 if (ret) 1159 goto err_pm_get_sync; 1160 1161 if (sai->soc_data->use_imx_pcm) { 1162 ret = imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE); 1163 if (ret) 1164 goto err_pm_get_sync; 1165 } else { 1166 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1167 if (ret) 1168 goto err_pm_get_sync; 1169 } 1170 1171 return ret; 1172 1173 err_pm_get_sync: 1174 if (!pm_runtime_status_suspended(&pdev->dev)) 1175 fsl_sai_runtime_suspend(&pdev->dev); 1176 err_pm_disable: 1177 pm_runtime_disable(&pdev->dev); 1178 1179 return ret; 1180 } 1181 1182 static int fsl_sai_remove(struct platform_device *pdev) 1183 { 1184 pm_runtime_disable(&pdev->dev); 1185 if (!pm_runtime_status_suspended(&pdev->dev)) 1186 fsl_sai_runtime_suspend(&pdev->dev); 1187 1188 return 0; 1189 } 1190 1191 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1192 .use_imx_pcm = false, 1193 .use_edma = false, 1194 .fifo_depth = 32, 1195 .reg_offset = 0, 1196 .mclk0_is_mclk1 = false, 1197 .flags = 0, 1198 }; 1199 1200 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1201 .use_imx_pcm = true, 1202 .use_edma = false, 1203 .fifo_depth = 32, 1204 .reg_offset = 0, 1205 .mclk0_is_mclk1 = true, 1206 .flags = 0, 1207 }; 1208 1209 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1210 .use_imx_pcm = true, 1211 .use_edma = false, 1212 .fifo_depth = 16, 1213 .reg_offset = 8, 1214 .mclk0_is_mclk1 = false, 1215 .flags = PMQOS_CPU_LATENCY, 1216 }; 1217 1218 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1219 .use_imx_pcm = true, 1220 .use_edma = false, 1221 .fifo_depth = 128, 1222 .reg_offset = 8, 1223 .mclk0_is_mclk1 = false, 1224 .flags = 0, 1225 }; 1226 1227 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1228 .use_imx_pcm = true, 1229 .use_edma = true, 1230 .fifo_depth = 64, 1231 .reg_offset = 0, 1232 .mclk0_is_mclk1 = false, 1233 .flags = 0, 1234 }; 1235 1236 static const struct of_device_id fsl_sai_ids[] = { 1237 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1238 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1239 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1240 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1241 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1242 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1243 { /* sentinel */ } 1244 }; 1245 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1246 1247 static int fsl_sai_runtime_suspend(struct device *dev) 1248 { 1249 struct fsl_sai *sai = dev_get_drvdata(dev); 1250 1251 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1252 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1253 1254 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1255 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1256 1257 clk_disable_unprepare(sai->bus_clk); 1258 1259 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1260 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1261 1262 regcache_cache_only(sai->regmap, true); 1263 1264 return 0; 1265 } 1266 1267 static int fsl_sai_runtime_resume(struct device *dev) 1268 { 1269 struct fsl_sai *sai = dev_get_drvdata(dev); 1270 unsigned int ofs = sai->soc_data->reg_offset; 1271 int ret; 1272 1273 ret = clk_prepare_enable(sai->bus_clk); 1274 if (ret) { 1275 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1276 return ret; 1277 } 1278 1279 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1280 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1281 if (ret) 1282 goto disable_bus_clk; 1283 } 1284 1285 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1286 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1287 if (ret) 1288 goto disable_tx_clk; 1289 } 1290 1291 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1292 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1293 1294 regcache_cache_only(sai->regmap, false); 1295 regcache_mark_dirty(sai->regmap); 1296 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 1297 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 1298 usleep_range(1000, 2000); 1299 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1300 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1301 1302 ret = regcache_sync(sai->regmap); 1303 if (ret) 1304 goto disable_rx_clk; 1305 1306 return 0; 1307 1308 disable_rx_clk: 1309 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1310 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1311 disable_tx_clk: 1312 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1313 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1314 disable_bus_clk: 1315 clk_disable_unprepare(sai->bus_clk); 1316 1317 return ret; 1318 } 1319 1320 static const struct dev_pm_ops fsl_sai_pm_ops = { 1321 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, 1322 fsl_sai_runtime_resume, NULL) 1323 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1324 pm_runtime_force_resume) 1325 }; 1326 1327 static struct platform_driver fsl_sai_driver = { 1328 .probe = fsl_sai_probe, 1329 .remove = fsl_sai_remove, 1330 .driver = { 1331 .name = "fsl-sai", 1332 .pm = &fsl_sai_pm_ops, 1333 .of_match_table = fsl_sai_ids, 1334 }, 1335 }; 1336 module_platform_driver(fsl_sai_driver); 1337 1338 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1339 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1340 MODULE_ALIAS("platform:fsl-sai"); 1341 MODULE_LICENSE("GPL"); 1342