1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/pinctrl/consumer.h> 14 #include <linux/pm_qos.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/time.h> 19 #include <sound/core.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 24 25 #include "fsl_sai.h" 26 #include "fsl_utils.h" 27 #include "imx-pcm.h" 28 29 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 30 FSL_SAI_CSR_FEIE) 31 32 static const unsigned int fsl_sai_rates[] = { 33 8000, 11025, 12000, 16000, 22050, 34 24000, 32000, 44100, 48000, 64000, 35 88200, 96000, 176400, 192000, 352800, 36 384000, 705600, 768000, 1411200, 2822400, 37 }; 38 39 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 40 .count = ARRAY_SIZE(fsl_sai_rates), 41 .list = fsl_sai_rates, 42 }; 43 44 /** 45 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 46 * 47 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 48 * or Receiver's for both streams. This function is used to check if clocks of 49 * the stream's are synced by the opposite stream. 50 * 51 * @sai: SAI context 52 * @dir: stream direction 53 */ 54 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 55 { 56 int adir = (dir == TX) ? RX : TX; 57 58 /* current dir in async mode while opposite dir in sync mode */ 59 return !sai->synchronous[dir] && sai->synchronous[adir]; 60 } 61 62 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk) 63 { 64 struct pinctrl_state *state = NULL; 65 66 if (sai->is_pdm_mode) { 67 /* DSD512@44.1kHz, DSD512@48kHz */ 68 if (bclk >= 22579200) 69 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); 70 71 /* Get default DSD state */ 72 if (IS_ERR_OR_NULL(state)) 73 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); 74 } else { 75 /* 706k32b2c, 768k32b2c, etc */ 76 if (bclk >= 45158400) 77 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); 78 } 79 80 /* Get default state */ 81 if (IS_ERR_OR_NULL(state)) 82 state = pinctrl_lookup_state(sai->pinctrl, "default"); 83 84 return state; 85 } 86 87 static irqreturn_t fsl_sai_isr(int irq, void *devid) 88 { 89 struct fsl_sai *sai = (struct fsl_sai *)devid; 90 unsigned int ofs = sai->soc_data->reg_offset; 91 struct device *dev = &sai->pdev->dev; 92 u32 flags, xcsr, mask; 93 irqreturn_t iret = IRQ_NONE; 94 95 /* 96 * Both IRQ status bits and IRQ mask bits are in the xCSR but 97 * different shifts. And we here create a mask only for those 98 * IRQs that we activated. 99 */ 100 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 101 102 /* Tx IRQ */ 103 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 104 flags = xcsr & mask; 105 106 if (flags) 107 iret = IRQ_HANDLED; 108 else 109 goto irq_rx; 110 111 if (flags & FSL_SAI_CSR_WSF) 112 dev_dbg(dev, "isr: Start of Tx word detected\n"); 113 114 if (flags & FSL_SAI_CSR_SEF) 115 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 116 117 if (flags & FSL_SAI_CSR_FEF) 118 dev_dbg(dev, "isr: Transmit underrun detected\n"); 119 120 if (flags & FSL_SAI_CSR_FWF) 121 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 122 123 if (flags & FSL_SAI_CSR_FRF) 124 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 125 126 flags &= FSL_SAI_CSR_xF_W_MASK; 127 xcsr &= ~FSL_SAI_CSR_xF_MASK; 128 129 if (flags) 130 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 131 132 irq_rx: 133 /* Rx IRQ */ 134 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 135 flags = xcsr & mask; 136 137 if (flags) 138 iret = IRQ_HANDLED; 139 else 140 goto out; 141 142 if (flags & FSL_SAI_CSR_WSF) 143 dev_dbg(dev, "isr: Start of Rx word detected\n"); 144 145 if (flags & FSL_SAI_CSR_SEF) 146 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 147 148 if (flags & FSL_SAI_CSR_FEF) 149 dev_dbg(dev, "isr: Receive overflow detected\n"); 150 151 if (flags & FSL_SAI_CSR_FWF) 152 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 153 154 if (flags & FSL_SAI_CSR_FRF) 155 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 156 157 flags &= FSL_SAI_CSR_xF_W_MASK; 158 xcsr &= ~FSL_SAI_CSR_xF_MASK; 159 160 if (flags) 161 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 162 163 out: 164 return iret; 165 } 166 167 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 168 u32 rx_mask, int slots, int slot_width) 169 { 170 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 171 172 sai->slots = slots; 173 sai->slot_width = slot_width; 174 175 return 0; 176 } 177 178 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 179 unsigned int ratio) 180 { 181 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 182 183 sai->bclk_ratio = ratio; 184 185 return 0; 186 } 187 188 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 189 int clk_id, unsigned int freq, bool tx) 190 { 191 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 192 unsigned int ofs = sai->soc_data->reg_offset; 193 u32 val_cr2 = 0; 194 195 switch (clk_id) { 196 case FSL_SAI_CLK_BUS: 197 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 198 break; 199 case FSL_SAI_CLK_MAST1: 200 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 201 break; 202 case FSL_SAI_CLK_MAST2: 203 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 204 break; 205 case FSL_SAI_CLK_MAST3: 206 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 207 break; 208 default: 209 return -EINVAL; 210 } 211 212 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 213 FSL_SAI_CR2_MSEL_MASK, val_cr2); 214 215 return 0; 216 } 217 218 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq) 219 { 220 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 221 int ret; 222 223 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], 224 sai->pll8k_clk, sai->pll11k_clk, freq); 225 226 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); 227 if (ret < 0) 228 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); 229 230 return ret; 231 } 232 233 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 234 int clk_id, unsigned int freq, int dir) 235 { 236 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 237 int ret; 238 239 if (dir == SND_SOC_CLOCK_IN) 240 return 0; 241 242 if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) { 243 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) { 244 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); 245 return -EINVAL; 246 } 247 248 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { 249 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); 250 return -EINVAL; 251 } 252 253 if (sai->mclk_streams == 0) { 254 ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq); 255 if (ret < 0) 256 return ret; 257 } 258 } 259 260 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); 261 if (ret) { 262 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 263 return ret; 264 } 265 266 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false); 267 if (ret) 268 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 269 270 return ret; 271 } 272 273 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 274 unsigned int fmt, bool tx) 275 { 276 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 277 unsigned int ofs = sai->soc_data->reg_offset; 278 u32 val_cr2 = 0, val_cr4 = 0; 279 280 if (!sai->is_lsb_first) 281 val_cr4 |= FSL_SAI_CR4_MF; 282 283 sai->is_pdm_mode = false; 284 sai->is_dsp_mode = false; 285 /* DAI mode */ 286 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 287 case SND_SOC_DAIFMT_I2S: 288 /* 289 * Frame low, 1clk before data, one word length for frame sync, 290 * frame sync starts one serial clock cycle earlier, 291 * that is, together with the last bit of the previous 292 * data word. 293 */ 294 val_cr2 |= FSL_SAI_CR2_BCP; 295 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 296 break; 297 case SND_SOC_DAIFMT_LEFT_J: 298 /* 299 * Frame high, one word length for frame sync, 300 * frame sync asserts with the first bit of the frame. 301 */ 302 val_cr2 |= FSL_SAI_CR2_BCP; 303 break; 304 case SND_SOC_DAIFMT_DSP_A: 305 /* 306 * Frame high, 1clk before data, one bit for frame sync, 307 * frame sync starts one serial clock cycle earlier, 308 * that is, together with the last bit of the previous 309 * data word. 310 */ 311 val_cr2 |= FSL_SAI_CR2_BCP; 312 val_cr4 |= FSL_SAI_CR4_FSE; 313 sai->is_dsp_mode = true; 314 break; 315 case SND_SOC_DAIFMT_DSP_B: 316 /* 317 * Frame high, one bit for frame sync, 318 * frame sync asserts with the first bit of the frame. 319 */ 320 val_cr2 |= FSL_SAI_CR2_BCP; 321 sai->is_dsp_mode = true; 322 break; 323 case SND_SOC_DAIFMT_PDM: 324 val_cr2 |= FSL_SAI_CR2_BCP; 325 val_cr4 &= ~FSL_SAI_CR4_MF; 326 sai->is_pdm_mode = true; 327 break; 328 case SND_SOC_DAIFMT_RIGHT_J: 329 /* To be done */ 330 default: 331 return -EINVAL; 332 } 333 334 /* DAI clock inversion */ 335 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 336 case SND_SOC_DAIFMT_IB_IF: 337 /* Invert both clocks */ 338 val_cr2 ^= FSL_SAI_CR2_BCP; 339 val_cr4 ^= FSL_SAI_CR4_FSP; 340 break; 341 case SND_SOC_DAIFMT_IB_NF: 342 /* Invert bit clock */ 343 val_cr2 ^= FSL_SAI_CR2_BCP; 344 break; 345 case SND_SOC_DAIFMT_NB_IF: 346 /* Invert frame clock */ 347 val_cr4 ^= FSL_SAI_CR4_FSP; 348 break; 349 case SND_SOC_DAIFMT_NB_NF: 350 /* Nothing to do for both normal cases */ 351 break; 352 default: 353 return -EINVAL; 354 } 355 356 /* DAI clock provider masks */ 357 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 358 case SND_SOC_DAIFMT_BP_FP: 359 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 360 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 361 sai->is_consumer_mode = false; 362 break; 363 case SND_SOC_DAIFMT_BC_FC: 364 sai->is_consumer_mode = true; 365 break; 366 case SND_SOC_DAIFMT_BP_FC: 367 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 368 sai->is_consumer_mode = false; 369 break; 370 case SND_SOC_DAIFMT_BC_FP: 371 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 372 sai->is_consumer_mode = true; 373 break; 374 default: 375 return -EINVAL; 376 } 377 378 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 379 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 380 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 381 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 382 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 383 384 return 0; 385 } 386 387 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 388 { 389 int ret; 390 391 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 392 if (ret) { 393 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 394 return ret; 395 } 396 397 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 398 if (ret) 399 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 400 401 return ret; 402 } 403 404 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 405 { 406 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 407 unsigned int reg, ofs = sai->soc_data->reg_offset; 408 unsigned long clk_rate; 409 u32 savediv = 0, ratio, bestdiff = freq; 410 int adir = tx ? RX : TX; 411 int dir = tx ? TX : RX; 412 u32 id; 413 bool support_1_1_ratio = sai->verid.version >= 0x0301; 414 415 /* Don't apply to consumer mode */ 416 if (sai->is_consumer_mode) 417 return 0; 418 419 /* 420 * There is no point in polling MCLK0 if it is identical to MCLK1. 421 * And given that MQS use case has to use MCLK1 though two clocks 422 * are the same, we simply skip MCLK0 and start to find from MCLK1. 423 */ 424 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 425 426 for (; id < FSL_SAI_MCLK_MAX; id++) { 427 int diff; 428 429 clk_rate = clk_get_rate(sai->mclk_clk[id]); 430 if (!clk_rate) 431 continue; 432 433 ratio = DIV_ROUND_CLOSEST(clk_rate, freq); 434 if (!ratio || ratio > 512) 435 continue; 436 if (ratio == 1 && !support_1_1_ratio) 437 continue; 438 if ((ratio & 1) && ratio > 1) 439 continue; 440 441 diff = abs((long)clk_rate - ratio * freq); 442 443 /* 444 * Drop the source that can not be 445 * divided into the required rate. 446 */ 447 if (diff != 0 && clk_rate / diff < 1000) 448 continue; 449 450 dev_dbg(dai->dev, 451 "ratio %d for freq %dHz based on clock %ldHz\n", 452 ratio, freq, clk_rate); 453 454 455 if (diff < bestdiff) { 456 savediv = ratio; 457 sai->mclk_id[tx] = id; 458 bestdiff = diff; 459 } 460 461 if (diff == 0) 462 break; 463 } 464 465 if (savediv == 0) { 466 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 467 tx ? 'T' : 'R', freq); 468 return -EINVAL; 469 } 470 471 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 472 sai->mclk_id[tx], savediv, bestdiff); 473 474 /* 475 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 476 * set TCR2 register for playback. 477 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 478 * and capture. 479 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 480 * and capture. 481 * 4) For Tx and Rx are both Synchronous with another SAI, we just 482 * ignore it. 483 */ 484 if (fsl_sai_dir_is_synced(sai, adir)) 485 reg = FSL_SAI_xCR2(!tx, ofs); 486 else if (!sai->synchronous[dir]) 487 reg = FSL_SAI_xCR2(tx, ofs); 488 else 489 return 0; 490 491 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, 492 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 493 494 if (savediv == 1) { 495 regmap_update_bits(sai->regmap, reg, 496 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 497 FSL_SAI_CR2_BYP); 498 if (fsl_sai_dir_is_synced(sai, adir)) 499 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 500 FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI); 501 else 502 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 503 FSL_SAI_CR2_BCI, 0); 504 } else { 505 regmap_update_bits(sai->regmap, reg, 506 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 507 savediv / 2 - 1); 508 } 509 510 return 0; 511 } 512 513 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 514 struct snd_pcm_hw_params *params, 515 struct snd_soc_dai *cpu_dai) 516 { 517 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 518 unsigned int ofs = sai->soc_data->reg_offset; 519 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 520 unsigned int channels = params_channels(params); 521 struct snd_dmaengine_dai_dma_data *dma_params; 522 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; 523 u32 word_width = params_width(params); 524 int trce_mask = 0, dl_cfg_idx = 0; 525 int dl_cfg_cnt = sai->dl_cfg_cnt; 526 u32 dl_type = FSL_SAI_DL_I2S; 527 u32 val_cr4 = 0, val_cr5 = 0; 528 u32 slots = (channels == 1) ? 2 : channels; 529 u32 slot_width = word_width; 530 int adir = tx ? RX : TX; 531 u32 pins, bclk; 532 u32 watermark; 533 int ret, i; 534 535 if (sai->slot_width) 536 slot_width = sai->slot_width; 537 538 if (sai->slots) 539 slots = sai->slots; 540 else if (sai->bclk_ratio) 541 slots = sai->bclk_ratio / slot_width; 542 543 pins = DIV_ROUND_UP(channels, slots); 544 545 /* 546 * PDM mode, channels are independent 547 * each channels are on one dataline/FIFO. 548 */ 549 if (sai->is_pdm_mode) { 550 pins = channels; 551 dl_type = FSL_SAI_DL_PDM; 552 } 553 554 for (i = 0; i < dl_cfg_cnt; i++) { 555 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) { 556 dl_cfg_idx = i; 557 break; 558 } 559 } 560 561 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) { 562 dev_err(cpu_dai->dev, "channel not supported\n"); 563 return -EINVAL; 564 } 565 566 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); 567 568 if (!IS_ERR_OR_NULL(sai->pinctrl)) { 569 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); 570 if (!IS_ERR_OR_NULL(sai->pins_state)) { 571 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 572 if (ret) { 573 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); 574 return ret; 575 } 576 } 577 } 578 579 if (!sai->is_consumer_mode) { 580 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk); 581 if (ret) 582 return ret; 583 584 /* Do not enable the clock if it is already enabled */ 585 if (!(sai->mclk_streams & BIT(substream->stream))) { 586 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 587 if (ret) 588 return ret; 589 590 sai->mclk_streams |= BIT(substream->stream); 591 } 592 } 593 594 if (!sai->is_dsp_mode && !sai->is_pdm_mode) 595 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 596 597 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 598 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 599 600 if (sai->is_lsb_first || sai->is_pdm_mode) 601 val_cr5 |= FSL_SAI_CR5_FBT(0); 602 else 603 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 604 605 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 606 607 /* Set to output mode to avoid tri-stated data pins */ 608 if (tx) 609 val_cr4 |= FSL_SAI_CR4_CHMOD; 610 611 /* 612 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 613 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 614 * RCR5(TCR5) for playback(capture), or there will be sync error. 615 */ 616 617 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) { 618 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 619 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 620 FSL_SAI_CR4_CHMOD_MASK, 621 val_cr4); 622 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 623 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 624 FSL_SAI_CR5_FBT_MASK, val_cr5); 625 } 626 627 /* 628 * Combine mode has limation: 629 * - Can't used for singel dataline/FIFO case except the FIFO0 630 * - Can't used for multi dataline/FIFO case except the enabled FIFOs 631 * are successive and start from FIFO0 632 * 633 * So for common usage, all multi fifo case disable the combine mode. 634 */ 635 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma) 636 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 637 FSL_SAI_CR4_FCOMB_MASK, 0); 638 else 639 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 640 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); 641 642 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; 643 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + 644 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4; 645 646 if (sai->is_multi_fifo_dma) { 647 sai->audio_config[tx].words_per_fifo = min(slots, channels); 648 if (tx) { 649 sai->audio_config[tx].n_fifos_dst = pins; 650 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx]; 651 } else { 652 sai->audio_config[tx].n_fifos_src = pins; 653 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx]; 654 } 655 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins; 656 dma_params->peripheral_config = &sai->audio_config[tx]; 657 dma_params->peripheral_size = sizeof(sai->audio_config[tx]); 658 659 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) : 660 (dma_params->maxburst - 1); 661 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs), 662 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 663 watermark); 664 } 665 666 /* Find a proper tcre setting */ 667 for (i = 0; i < sai->soc_data->pins; i++) { 668 trce_mask = (1 << (i + 1)) - 1; 669 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins) 670 break; 671 } 672 673 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 674 FSL_SAI_CR3_TRCE_MASK, 675 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); 676 677 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 678 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 679 FSL_SAI_CR4_CHMOD_MASK, 680 val_cr4); 681 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 682 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 683 FSL_SAI_CR5_FBT_MASK, val_cr5); 684 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 685 ~0UL - ((1 << min(channels, slots)) - 1)); 686 687 return 0; 688 } 689 690 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 691 struct snd_soc_dai *cpu_dai) 692 { 693 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 694 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 695 unsigned int ofs = sai->soc_data->reg_offset; 696 697 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 698 FSL_SAI_CR3_TRCE_MASK, 0); 699 700 if (!sai->is_consumer_mode && 701 sai->mclk_streams & BIT(substream->stream)) { 702 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 703 sai->mclk_streams &= ~BIT(substream->stream); 704 } 705 706 return 0; 707 } 708 709 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 710 { 711 unsigned int ofs = sai->soc_data->reg_offset; 712 bool tx = dir == TX; 713 u32 xcsr, count = 100, mask; 714 715 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 716 mask = FSL_SAI_CSR_TERE; 717 else 718 mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE; 719 720 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 721 mask, 0); 722 723 /* TERE will remain set till the end of current frame */ 724 do { 725 udelay(10); 726 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 727 } while (--count && xcsr & FSL_SAI_CSR_TERE); 728 729 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 730 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 731 732 /* 733 * For sai master mode, after several open/close sai, 734 * there will be no frame clock, and can't recover 735 * anymore. Add software reset to fix this issue. 736 * This is a hardware bug, and will be fix in the 737 * next sai version. 738 */ 739 if (!sai->is_consumer_mode) { 740 /* Software Reset */ 741 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); 742 /* Clear SR bit to finish the reset */ 743 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); 744 } 745 } 746 747 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 748 struct snd_soc_dai *cpu_dai) 749 { 750 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 751 unsigned int ofs = sai->soc_data->reg_offset; 752 753 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 754 int adir = tx ? RX : TX; 755 int dir = tx ? TX : RX; 756 u32 xcsr; 757 758 /* 759 * Asynchronous mode: Clear SYNC for both Tx and Rx. 760 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 761 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 762 */ 763 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 764 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 765 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 766 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 767 768 /* 769 * It is recommended that the transmitter is the last enabled 770 * and the first disabled. 771 */ 772 switch (cmd) { 773 case SNDRV_PCM_TRIGGER_START: 774 case SNDRV_PCM_TRIGGER_RESUME: 775 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 776 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 777 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 778 779 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 780 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 781 /* 782 * Enable the opposite direction for synchronous mode 783 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 784 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 785 * 786 * RM recommends to enable RE after TE for case 1 and to enable 787 * TE after RE for case 2, but we here may not always guarantee 788 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 789 * TE after RE, which is against what RM recommends but should 790 * be safe to do, judging by years of testing results. 791 */ 792 if (fsl_sai_dir_is_synced(sai, adir)) 793 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 794 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 795 796 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 797 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 798 break; 799 case SNDRV_PCM_TRIGGER_STOP: 800 case SNDRV_PCM_TRIGGER_SUSPEND: 801 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 802 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 803 FSL_SAI_CSR_FRDE, 0); 804 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 805 FSL_SAI_CSR_xIE_MASK, 0); 806 807 /* Check if the opposite FRDE is also disabled */ 808 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 809 810 /* 811 * If opposite stream provides clocks for synchronous mode and 812 * it is inactive, disable it before disabling the current one 813 */ 814 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 815 fsl_sai_config_disable(sai, adir); 816 817 /* 818 * Disable current stream if either of: 819 * 1. current stream doesn't provide clocks for synchronous mode 820 * 2. current stream provides clocks for synchronous mode but no 821 * more stream is active. 822 */ 823 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 824 fsl_sai_config_disable(sai, dir); 825 826 break; 827 default: 828 return -EINVAL; 829 } 830 831 return 0; 832 } 833 834 static int fsl_sai_startup(struct snd_pcm_substream *substream, 835 struct snd_soc_dai *cpu_dai) 836 { 837 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 838 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 839 int ret; 840 841 /* 842 * EDMA controller needs period size to be a multiple of 843 * tx/rx maxburst 844 */ 845 if (sai->soc_data->use_edma) 846 snd_pcm_hw_constraint_step(substream->runtime, 0, 847 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 848 tx ? sai->dma_params_tx.maxburst : 849 sai->dma_params_rx.maxburst); 850 851 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 852 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); 853 854 return ret; 855 } 856 857 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 858 { 859 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 860 unsigned int ofs = sai->soc_data->reg_offset; 861 862 /* Software Reset for both Tx and Rx */ 863 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 864 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 865 /* Clear SR bit to finish the reset */ 866 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 867 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 868 869 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 870 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 871 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst); 872 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 873 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 874 sai->dma_params_rx.maxburst - 1); 875 876 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 877 &sai->dma_params_rx); 878 879 return 0; 880 } 881 882 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 883 .probe = fsl_sai_dai_probe, 884 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 885 .set_sysclk = fsl_sai_set_dai_sysclk, 886 .set_fmt = fsl_sai_set_dai_fmt, 887 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 888 .hw_params = fsl_sai_hw_params, 889 .hw_free = fsl_sai_hw_free, 890 .trigger = fsl_sai_trigger, 891 .startup = fsl_sai_startup, 892 }; 893 894 static int fsl_sai_dai_resume(struct snd_soc_component *component) 895 { 896 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 897 struct device *dev = &sai->pdev->dev; 898 int ret; 899 900 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { 901 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 902 if (ret) { 903 dev_err(dev, "failed to set proper pins state: %d\n", ret); 904 return ret; 905 } 906 } 907 908 return 0; 909 } 910 911 static struct snd_soc_dai_driver fsl_sai_dai_template = { 912 .playback = { 913 .stream_name = "CPU-Playback", 914 .channels_min = 1, 915 .channels_max = 32, 916 .rate_min = 8000, 917 .rate_max = 2822400, 918 .rates = SNDRV_PCM_RATE_KNOT, 919 .formats = FSL_SAI_FORMATS, 920 }, 921 .capture = { 922 .stream_name = "CPU-Capture", 923 .channels_min = 1, 924 .channels_max = 32, 925 .rate_min = 8000, 926 .rate_max = 2822400, 927 .rates = SNDRV_PCM_RATE_KNOT, 928 .formats = FSL_SAI_FORMATS, 929 }, 930 .ops = &fsl_sai_pcm_dai_ops, 931 }; 932 933 static const struct snd_soc_component_driver fsl_component = { 934 .name = "fsl-sai", 935 .resume = fsl_sai_dai_resume, 936 .legacy_dai_naming = 1, 937 }; 938 939 static struct reg_default fsl_sai_reg_defaults_ofs0[] = { 940 {FSL_SAI_TCR1(0), 0}, 941 {FSL_SAI_TCR2(0), 0}, 942 {FSL_SAI_TCR3(0), 0}, 943 {FSL_SAI_TCR4(0), 0}, 944 {FSL_SAI_TCR5(0), 0}, 945 {FSL_SAI_TDR0, 0}, 946 {FSL_SAI_TDR1, 0}, 947 {FSL_SAI_TDR2, 0}, 948 {FSL_SAI_TDR3, 0}, 949 {FSL_SAI_TDR4, 0}, 950 {FSL_SAI_TDR5, 0}, 951 {FSL_SAI_TDR6, 0}, 952 {FSL_SAI_TDR7, 0}, 953 {FSL_SAI_TMR, 0}, 954 {FSL_SAI_RCR1(0), 0}, 955 {FSL_SAI_RCR2(0), 0}, 956 {FSL_SAI_RCR3(0), 0}, 957 {FSL_SAI_RCR4(0), 0}, 958 {FSL_SAI_RCR5(0), 0}, 959 {FSL_SAI_RMR, 0}, 960 }; 961 962 static struct reg_default fsl_sai_reg_defaults_ofs8[] = { 963 {FSL_SAI_TCR1(8), 0}, 964 {FSL_SAI_TCR2(8), 0}, 965 {FSL_SAI_TCR3(8), 0}, 966 {FSL_SAI_TCR4(8), 0}, 967 {FSL_SAI_TCR5(8), 0}, 968 {FSL_SAI_TDR0, 0}, 969 {FSL_SAI_TDR1, 0}, 970 {FSL_SAI_TDR2, 0}, 971 {FSL_SAI_TDR3, 0}, 972 {FSL_SAI_TDR4, 0}, 973 {FSL_SAI_TDR5, 0}, 974 {FSL_SAI_TDR6, 0}, 975 {FSL_SAI_TDR7, 0}, 976 {FSL_SAI_TMR, 0}, 977 {FSL_SAI_RCR1(8), 0}, 978 {FSL_SAI_RCR2(8), 0}, 979 {FSL_SAI_RCR3(8), 0}, 980 {FSL_SAI_RCR4(8), 0}, 981 {FSL_SAI_RCR5(8), 0}, 982 {FSL_SAI_RMR, 0}, 983 {FSL_SAI_MCTL, 0}, 984 {FSL_SAI_MDIV, 0}, 985 }; 986 987 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 988 { 989 struct fsl_sai *sai = dev_get_drvdata(dev); 990 unsigned int ofs = sai->soc_data->reg_offset; 991 992 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 993 return true; 994 995 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 996 return true; 997 998 switch (reg) { 999 case FSL_SAI_TFR0: 1000 case FSL_SAI_TFR1: 1001 case FSL_SAI_TFR2: 1002 case FSL_SAI_TFR3: 1003 case FSL_SAI_TFR4: 1004 case FSL_SAI_TFR5: 1005 case FSL_SAI_TFR6: 1006 case FSL_SAI_TFR7: 1007 case FSL_SAI_TMR: 1008 case FSL_SAI_RDR0: 1009 case FSL_SAI_RDR1: 1010 case FSL_SAI_RDR2: 1011 case FSL_SAI_RDR3: 1012 case FSL_SAI_RDR4: 1013 case FSL_SAI_RDR5: 1014 case FSL_SAI_RDR6: 1015 case FSL_SAI_RDR7: 1016 case FSL_SAI_RFR0: 1017 case FSL_SAI_RFR1: 1018 case FSL_SAI_RFR2: 1019 case FSL_SAI_RFR3: 1020 case FSL_SAI_RFR4: 1021 case FSL_SAI_RFR5: 1022 case FSL_SAI_RFR6: 1023 case FSL_SAI_RFR7: 1024 case FSL_SAI_RMR: 1025 case FSL_SAI_MCTL: 1026 case FSL_SAI_MDIV: 1027 case FSL_SAI_VERID: 1028 case FSL_SAI_PARAM: 1029 case FSL_SAI_TTCTN: 1030 case FSL_SAI_RTCTN: 1031 case FSL_SAI_TTCTL: 1032 case FSL_SAI_TBCTN: 1033 case FSL_SAI_TTCAP: 1034 case FSL_SAI_RTCTL: 1035 case FSL_SAI_RBCTN: 1036 case FSL_SAI_RTCAP: 1037 return true; 1038 default: 1039 return false; 1040 } 1041 } 1042 1043 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 1044 { 1045 struct fsl_sai *sai = dev_get_drvdata(dev); 1046 unsigned int ofs = sai->soc_data->reg_offset; 1047 1048 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 1049 return true; 1050 1051 /* Set VERID and PARAM be volatile for reading value in probe */ 1052 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 1053 return true; 1054 1055 switch (reg) { 1056 case FSL_SAI_TFR0: 1057 case FSL_SAI_TFR1: 1058 case FSL_SAI_TFR2: 1059 case FSL_SAI_TFR3: 1060 case FSL_SAI_TFR4: 1061 case FSL_SAI_TFR5: 1062 case FSL_SAI_TFR6: 1063 case FSL_SAI_TFR7: 1064 case FSL_SAI_RFR0: 1065 case FSL_SAI_RFR1: 1066 case FSL_SAI_RFR2: 1067 case FSL_SAI_RFR3: 1068 case FSL_SAI_RFR4: 1069 case FSL_SAI_RFR5: 1070 case FSL_SAI_RFR6: 1071 case FSL_SAI_RFR7: 1072 case FSL_SAI_RDR0: 1073 case FSL_SAI_RDR1: 1074 case FSL_SAI_RDR2: 1075 case FSL_SAI_RDR3: 1076 case FSL_SAI_RDR4: 1077 case FSL_SAI_RDR5: 1078 case FSL_SAI_RDR6: 1079 case FSL_SAI_RDR7: 1080 return true; 1081 default: 1082 return false; 1083 } 1084 } 1085 1086 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 1087 { 1088 struct fsl_sai *sai = dev_get_drvdata(dev); 1089 unsigned int ofs = sai->soc_data->reg_offset; 1090 1091 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1092 return true; 1093 1094 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1095 return true; 1096 1097 switch (reg) { 1098 case FSL_SAI_TDR0: 1099 case FSL_SAI_TDR1: 1100 case FSL_SAI_TDR2: 1101 case FSL_SAI_TDR3: 1102 case FSL_SAI_TDR4: 1103 case FSL_SAI_TDR5: 1104 case FSL_SAI_TDR6: 1105 case FSL_SAI_TDR7: 1106 case FSL_SAI_TMR: 1107 case FSL_SAI_RMR: 1108 case FSL_SAI_MCTL: 1109 case FSL_SAI_MDIV: 1110 case FSL_SAI_TTCTL: 1111 case FSL_SAI_RTCTL: 1112 return true; 1113 default: 1114 return false; 1115 } 1116 } 1117 1118 static struct regmap_config fsl_sai_regmap_config = { 1119 .reg_bits = 32, 1120 .reg_stride = 4, 1121 .val_bits = 32, 1122 .fast_io = true, 1123 1124 .max_register = FSL_SAI_RMR, 1125 .reg_defaults = fsl_sai_reg_defaults_ofs0, 1126 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 1127 .readable_reg = fsl_sai_readable_reg, 1128 .volatile_reg = fsl_sai_volatile_reg, 1129 .writeable_reg = fsl_sai_writeable_reg, 1130 .cache_type = REGCACHE_FLAT, 1131 }; 1132 1133 static int fsl_sai_check_version(struct device *dev) 1134 { 1135 struct fsl_sai *sai = dev_get_drvdata(dev); 1136 unsigned char ofs = sai->soc_data->reg_offset; 1137 unsigned int val; 1138 int ret; 1139 1140 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 1141 return 0; 1142 1143 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 1144 if (ret < 0) 1145 return ret; 1146 1147 dev_dbg(dev, "VERID: 0x%016X\n", val); 1148 1149 sai->verid.version = val & 1150 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK); 1151 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT; 1152 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 1153 1154 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 1155 if (ret < 0) 1156 return ret; 1157 1158 dev_dbg(dev, "PARAM: 0x%016X\n", val); 1159 1160 /* Max slots per frame, power of 2 */ 1161 sai->param.slot_num = 1 << 1162 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 1163 1164 /* Words per fifo, power of 2 */ 1165 sai->param.fifo_depth = 1 << 1166 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 1167 1168 /* Number of datalines implemented */ 1169 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 1170 1171 return 0; 1172 } 1173 1174 /* 1175 * Calculate the offset between first two datalines, don't 1176 * different offset in one case. 1177 */ 1178 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask) 1179 { 1180 int fbidx, nbidx, offset; 1181 1182 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1183 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1); 1184 offset = nbidx - fbidx - 1; 1185 1186 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); 1187 } 1188 1189 /* 1190 * read the fsl,dataline property from dts file. 1191 * It has 3 value for each configuration, first one means the type: 1192 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is 1193 * dataline mask for 'tx'. for example 1194 * 1195 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>, 1196 * 1197 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type 1198 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). 1199 * 1200 */ 1201 static int fsl_sai_read_dlcfg(struct fsl_sai *sai) 1202 { 1203 struct platform_device *pdev = sai->pdev; 1204 struct device_node *np = pdev->dev.of_node; 1205 struct device *dev = &pdev->dev; 1206 int ret, elems, i, index, num_cfg; 1207 char *propname = "fsl,dataline"; 1208 struct fsl_sai_dl_cfg *cfg; 1209 unsigned long dl_mask; 1210 unsigned int soc_dl; 1211 u32 rx, tx, type; 1212 1213 elems = of_property_count_u32_elems(np, propname); 1214 1215 if (elems <= 0) { 1216 elems = 0; 1217 } else if (elems % 3) { 1218 dev_err(dev, "Number of elements must be divisible to 3.\n"); 1219 return -EINVAL; 1220 } 1221 1222 num_cfg = elems / 3; 1223 /* Add one more for default value */ 1224 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL); 1225 if (!cfg) 1226 return -ENOMEM; 1227 1228 /* Consider default value "0 0xFF 0xFF" if property is missing */ 1229 soc_dl = BIT(sai->soc_data->pins) - 1; 1230 cfg[0].type = FSL_SAI_DL_DEFAULT; 1231 cfg[0].pins[0] = sai->soc_data->pins; 1232 cfg[0].mask[0] = soc_dl; 1233 cfg[0].start_off[0] = 0; 1234 cfg[0].next_off[0] = 0; 1235 1236 cfg[0].pins[1] = sai->soc_data->pins; 1237 cfg[0].mask[1] = soc_dl; 1238 cfg[0].start_off[1] = 0; 1239 cfg[0].next_off[1] = 0; 1240 for (i = 1, index = 0; i < num_cfg + 1; i++) { 1241 /* 1242 * type of dataline 1243 * 0 means default mode 1244 * 1 means I2S mode 1245 * 2 means PDM mode 1246 */ 1247 ret = of_property_read_u32_index(np, propname, index++, &type); 1248 if (ret) 1249 return -EINVAL; 1250 1251 ret = of_property_read_u32_index(np, propname, index++, &rx); 1252 if (ret) 1253 return -EINVAL; 1254 1255 ret = of_property_read_u32_index(np, propname, index++, &tx); 1256 if (ret) 1257 return -EINVAL; 1258 1259 if ((rx & ~soc_dl) || (tx & ~soc_dl)) { 1260 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl); 1261 return -EINVAL; 1262 } 1263 1264 rx = rx & soc_dl; 1265 tx = tx & soc_dl; 1266 1267 cfg[i].type = type; 1268 cfg[i].pins[0] = hweight8(rx); 1269 cfg[i].mask[0] = rx; 1270 dl_mask = rx; 1271 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1272 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx); 1273 1274 cfg[i].pins[1] = hweight8(tx); 1275 cfg[i].mask[1] = tx; 1276 dl_mask = tx; 1277 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1278 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx); 1279 } 1280 1281 sai->dl_cfg = cfg; 1282 sai->dl_cfg_cnt = num_cfg + 1; 1283 return 0; 1284 } 1285 1286 static int fsl_sai_runtime_suspend(struct device *dev); 1287 static int fsl_sai_runtime_resume(struct device *dev); 1288 1289 static int fsl_sai_probe(struct platform_device *pdev) 1290 { 1291 struct device_node *np = pdev->dev.of_node; 1292 struct device *dev = &pdev->dev; 1293 struct fsl_sai *sai; 1294 struct regmap *gpr; 1295 void __iomem *base; 1296 char tmp[8]; 1297 int irq, ret, i; 1298 int index; 1299 u32 dmas[4]; 1300 1301 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); 1302 if (!sai) 1303 return -ENOMEM; 1304 1305 sai->pdev = pdev; 1306 sai->soc_data = of_device_get_match_data(dev); 1307 1308 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1309 1310 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); 1311 if (IS_ERR(base)) 1312 return PTR_ERR(base); 1313 1314 if (sai->soc_data->reg_offset == 8) { 1315 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1316 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1317 fsl_sai_regmap_config.num_reg_defaults = 1318 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1319 } 1320 1321 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); 1322 if (IS_ERR(sai->regmap)) { 1323 dev_err(dev, "regmap init failed\n"); 1324 return PTR_ERR(sai->regmap); 1325 } 1326 1327 sai->bus_clk = devm_clk_get(dev, "bus"); 1328 /* Compatible with old DTB cases */ 1329 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1330 sai->bus_clk = devm_clk_get(dev, "sai"); 1331 if (IS_ERR(sai->bus_clk)) { 1332 dev_err(dev, "failed to get bus clock: %ld\n", 1333 PTR_ERR(sai->bus_clk)); 1334 /* -EPROBE_DEFER */ 1335 return PTR_ERR(sai->bus_clk); 1336 } 1337 1338 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1339 sprintf(tmp, "mclk%d", i); 1340 sai->mclk_clk[i] = devm_clk_get(dev, tmp); 1341 if (IS_ERR(sai->mclk_clk[i])) { 1342 dev_err(dev, "failed to get mclk%d clock: %ld\n", 1343 i, PTR_ERR(sai->mclk_clk[i])); 1344 sai->mclk_clk[i] = NULL; 1345 } 1346 } 1347 1348 if (sai->soc_data->mclk0_is_mclk1) 1349 sai->mclk_clk[0] = sai->mclk_clk[1]; 1350 else 1351 sai->mclk_clk[0] = sai->bus_clk; 1352 1353 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, 1354 &sai->pll11k_clk); 1355 1356 /* Use Multi FIFO mode depending on the support from SDMA script */ 1357 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1358 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) 1359 sai->is_multi_fifo_dma = true; 1360 1361 /* read dataline mask for rx and tx*/ 1362 ret = fsl_sai_read_dlcfg(sai); 1363 if (ret < 0) { 1364 dev_err(dev, "failed to read dlcfg %d\n", ret); 1365 return ret; 1366 } 1367 1368 irq = platform_get_irq(pdev, 0); 1369 if (irq < 0) 1370 return irq; 1371 1372 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED, 1373 np->name, sai); 1374 if (ret) { 1375 dev_err(dev, "failed to claim irq %u\n", irq); 1376 return ret; 1377 } 1378 1379 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, 1380 sizeof(fsl_sai_dai_template)); 1381 1382 /* Sync Tx with Rx as default by following old DT binding */ 1383 sai->synchronous[RX] = true; 1384 sai->synchronous[TX] = false; 1385 sai->cpu_dai_drv.symmetric_rate = 1; 1386 sai->cpu_dai_drv.symmetric_channels = 1; 1387 sai->cpu_dai_drv.symmetric_sample_bits = 1; 1388 1389 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") && 1390 of_property_read_bool(np, "fsl,sai-asynchronous")) { 1391 /* error out if both synchronous and asynchronous are present */ 1392 dev_err(dev, "invalid binding for synchronous mode\n"); 1393 return -EINVAL; 1394 } 1395 1396 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) { 1397 /* Sync Rx with Tx */ 1398 sai->synchronous[RX] = false; 1399 sai->synchronous[TX] = true; 1400 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) { 1401 /* Discard all settings for asynchronous mode */ 1402 sai->synchronous[RX] = false; 1403 sai->synchronous[TX] = false; 1404 sai->cpu_dai_drv.symmetric_rate = 0; 1405 sai->cpu_dai_drv.symmetric_channels = 0; 1406 sai->cpu_dai_drv.symmetric_sample_bits = 0; 1407 } 1408 1409 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output"); 1410 1411 if (sai->mclk_direction_output && 1412 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1413 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1414 if (IS_ERR(gpr)) { 1415 dev_err(dev, "cannot find iomuxc registers\n"); 1416 return PTR_ERR(gpr); 1417 } 1418 1419 index = of_alias_get_id(np, "sai"); 1420 if (index < 0) 1421 return index; 1422 1423 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1424 MCLK_DIR(index)); 1425 } 1426 1427 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; 1428 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; 1429 sai->dma_params_rx.maxburst = 1430 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX; 1431 sai->dma_params_tx.maxburst = 1432 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX; 1433 1434 sai->pinctrl = devm_pinctrl_get(&pdev->dev); 1435 1436 platform_set_drvdata(pdev, sai); 1437 pm_runtime_enable(dev); 1438 if (!pm_runtime_enabled(dev)) { 1439 ret = fsl_sai_runtime_resume(dev); 1440 if (ret) 1441 goto err_pm_disable; 1442 } 1443 1444 ret = pm_runtime_resume_and_get(dev); 1445 if (ret < 0) 1446 goto err_pm_get_sync; 1447 1448 /* Get sai version */ 1449 ret = fsl_sai_check_version(dev); 1450 if (ret < 0) 1451 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1452 1453 /* Select MCLK direction */ 1454 if (sai->mclk_direction_output && 1455 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1456 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1457 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1458 } 1459 1460 ret = pm_runtime_put_sync(dev); 1461 if (ret < 0 && ret != -ENOSYS) 1462 goto err_pm_get_sync; 1463 1464 /* 1465 * Register platform component before registering cpu dai for there 1466 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1467 */ 1468 if (sai->soc_data->use_imx_pcm) { 1469 ret = imx_pcm_dma_init(pdev); 1470 if (ret) { 1471 dev_err_probe(dev, ret, "PCM DMA init failed\n"); 1472 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)) 1473 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); 1474 goto err_pm_get_sync; 1475 } 1476 } else { 1477 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1478 if (ret) { 1479 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n"); 1480 goto err_pm_get_sync; 1481 } 1482 } 1483 1484 ret = devm_snd_soc_register_component(dev, &fsl_component, 1485 &sai->cpu_dai_drv, 1); 1486 if (ret) 1487 goto err_pm_get_sync; 1488 1489 return ret; 1490 1491 err_pm_get_sync: 1492 if (!pm_runtime_status_suspended(dev)) 1493 fsl_sai_runtime_suspend(dev); 1494 err_pm_disable: 1495 pm_runtime_disable(dev); 1496 1497 return ret; 1498 } 1499 1500 static void fsl_sai_remove(struct platform_device *pdev) 1501 { 1502 pm_runtime_disable(&pdev->dev); 1503 if (!pm_runtime_status_suspended(&pdev->dev)) 1504 fsl_sai_runtime_suspend(&pdev->dev); 1505 } 1506 1507 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1508 .use_imx_pcm = false, 1509 .use_edma = false, 1510 .fifo_depth = 32, 1511 .pins = 1, 1512 .reg_offset = 0, 1513 .mclk0_is_mclk1 = false, 1514 .flags = 0, 1515 .max_register = FSL_SAI_RMR, 1516 }; 1517 1518 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1519 .use_imx_pcm = true, 1520 .use_edma = false, 1521 .fifo_depth = 32, 1522 .pins = 1, 1523 .reg_offset = 0, 1524 .mclk0_is_mclk1 = true, 1525 .flags = 0, 1526 .max_register = FSL_SAI_RMR, 1527 }; 1528 1529 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1530 .use_imx_pcm = true, 1531 .use_edma = false, 1532 .fifo_depth = 16, 1533 .pins = 2, 1534 .reg_offset = 8, 1535 .mclk0_is_mclk1 = false, 1536 .flags = PMQOS_CPU_LATENCY, 1537 .max_register = FSL_SAI_RMR, 1538 }; 1539 1540 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1541 .use_imx_pcm = true, 1542 .use_edma = false, 1543 .fifo_depth = 128, 1544 .pins = 8, 1545 .reg_offset = 8, 1546 .mclk0_is_mclk1 = false, 1547 .flags = 0, 1548 .max_register = FSL_SAI_RMR, 1549 }; 1550 1551 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1552 .use_imx_pcm = true, 1553 .use_edma = true, 1554 .fifo_depth = 64, 1555 .pins = 4, 1556 .reg_offset = 0, 1557 .mclk0_is_mclk1 = false, 1558 .flags = 0, 1559 .max_register = FSL_SAI_RMR, 1560 }; 1561 1562 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = { 1563 .use_imx_pcm = true, 1564 .use_edma = false, 1565 .fifo_depth = 128, 1566 .reg_offset = 8, 1567 .mclk0_is_mclk1 = false, 1568 .pins = 8, 1569 .flags = 0, 1570 .max_register = FSL_SAI_MCTL, 1571 }; 1572 1573 static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = { 1574 .use_imx_pcm = true, 1575 .use_edma = false, 1576 .fifo_depth = 128, 1577 .reg_offset = 8, 1578 .mclk0_is_mclk1 = false, 1579 .pins = 8, 1580 .flags = 0, 1581 .max_register = FSL_SAI_MDIV, 1582 }; 1583 1584 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1585 .use_imx_pcm = true, 1586 .use_edma = false, 1587 .fifo_depth = 128, 1588 .reg_offset = 8, 1589 .mclk0_is_mclk1 = false, 1590 .pins = 8, 1591 .flags = 0, 1592 .max_register = FSL_SAI_MDIV, 1593 .mclk_with_tere = true, 1594 }; 1595 1596 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { 1597 .use_imx_pcm = true, 1598 .use_edma = true, 1599 .fifo_depth = 16, 1600 .reg_offset = 8, 1601 .mclk0_is_mclk1 = false, 1602 .pins = 4, 1603 .flags = PMQOS_CPU_LATENCY, 1604 .max_register = FSL_SAI_RTCAP, 1605 }; 1606 1607 static const struct fsl_sai_soc_data fsl_sai_imx93_data = { 1608 .use_imx_pcm = true, 1609 .use_edma = true, 1610 .fifo_depth = 128, 1611 .reg_offset = 8, 1612 .mclk0_is_mclk1 = false, 1613 .pins = 4, 1614 .flags = 0, 1615 .max_register = FSL_SAI_MCTL, 1616 .max_burst = {8, 8}, 1617 }; 1618 1619 static const struct of_device_id fsl_sai_ids[] = { 1620 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1621 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1622 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1623 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1624 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1625 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1626 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1627 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1628 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1629 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data }, 1630 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data }, 1631 { /* sentinel */ } 1632 }; 1633 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1634 1635 static int fsl_sai_runtime_suspend(struct device *dev) 1636 { 1637 struct fsl_sai *sai = dev_get_drvdata(dev); 1638 1639 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1640 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1641 1642 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1643 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1644 1645 clk_disable_unprepare(sai->bus_clk); 1646 1647 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1648 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1649 1650 regcache_cache_only(sai->regmap, true); 1651 1652 return 0; 1653 } 1654 1655 static int fsl_sai_runtime_resume(struct device *dev) 1656 { 1657 struct fsl_sai *sai = dev_get_drvdata(dev); 1658 unsigned int ofs = sai->soc_data->reg_offset; 1659 int ret; 1660 1661 ret = clk_prepare_enable(sai->bus_clk); 1662 if (ret) { 1663 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1664 return ret; 1665 } 1666 1667 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1668 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1669 if (ret) 1670 goto disable_bus_clk; 1671 } 1672 1673 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1674 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1675 if (ret) 1676 goto disable_tx_clk; 1677 } 1678 1679 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1680 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1681 1682 regcache_cache_only(sai->regmap, false); 1683 regcache_mark_dirty(sai->regmap); 1684 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 1685 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 1686 usleep_range(1000, 2000); 1687 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1688 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1689 1690 ret = regcache_sync(sai->regmap); 1691 if (ret) 1692 goto disable_rx_clk; 1693 1694 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 1695 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), 1696 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 1697 1698 return 0; 1699 1700 disable_rx_clk: 1701 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1702 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1703 disable_tx_clk: 1704 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1705 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1706 disable_bus_clk: 1707 clk_disable_unprepare(sai->bus_clk); 1708 1709 return ret; 1710 } 1711 1712 static const struct dev_pm_ops fsl_sai_pm_ops = { 1713 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, 1714 fsl_sai_runtime_resume, NULL) 1715 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1716 pm_runtime_force_resume) 1717 }; 1718 1719 static struct platform_driver fsl_sai_driver = { 1720 .probe = fsl_sai_probe, 1721 .remove_new = fsl_sai_remove, 1722 .driver = { 1723 .name = "fsl-sai", 1724 .pm = &fsl_sai_pm_ops, 1725 .of_match_table = fsl_sai_ids, 1726 }, 1727 }; 1728 module_platform_driver(fsl_sai_driver); 1729 1730 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1731 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1732 MODULE_ALIAS("platform:fsl-sai"); 1733 MODULE_LICENSE("GPL"); 1734