1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/pinctrl/consumer.h> 14 #include <linux/pm_qos.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/time.h> 19 #include <sound/core.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 24 25 #include "fsl_sai.h" 26 #include "fsl_utils.h" 27 #include "imx-pcm.h" 28 29 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 30 FSL_SAI_CSR_FEIE) 31 32 static const unsigned int fsl_sai_rates[] = { 33 8000, 11025, 12000, 16000, 22050, 34 24000, 32000, 44100, 48000, 64000, 35 88200, 96000, 176400, 192000, 352800, 36 384000, 705600, 768000, 1411200, 2822400, 37 }; 38 39 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 40 .count = ARRAY_SIZE(fsl_sai_rates), 41 .list = fsl_sai_rates, 42 }; 43 44 /** 45 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 46 * 47 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 48 * or Receiver's for both streams. This function is used to check if clocks of 49 * the stream's are synced by the opposite stream. 50 * 51 * @sai: SAI context 52 * @dir: stream direction 53 */ 54 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 55 { 56 int adir = (dir == TX) ? RX : TX; 57 58 /* current dir in async mode while opposite dir in sync mode */ 59 return !sai->synchronous[dir] && sai->synchronous[adir]; 60 } 61 62 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk) 63 { 64 struct pinctrl_state *state = NULL; 65 66 if (sai->is_pdm_mode) { 67 /* DSD512@44.1kHz, DSD512@48kHz */ 68 if (bclk >= 22579200) 69 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); 70 71 /* Get default DSD state */ 72 if (IS_ERR_OR_NULL(state)) 73 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); 74 } else { 75 /* 706k32b2c, 768k32b2c, etc */ 76 if (bclk >= 45158400) 77 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); 78 } 79 80 /* Get default state */ 81 if (IS_ERR_OR_NULL(state)) 82 state = pinctrl_lookup_state(sai->pinctrl, "default"); 83 84 return state; 85 } 86 87 static irqreturn_t fsl_sai_isr(int irq, void *devid) 88 { 89 struct fsl_sai *sai = (struct fsl_sai *)devid; 90 unsigned int ofs = sai->soc_data->reg_offset; 91 struct device *dev = &sai->pdev->dev; 92 u32 flags, xcsr, mask; 93 irqreturn_t iret = IRQ_NONE; 94 95 /* 96 * Both IRQ status bits and IRQ mask bits are in the xCSR but 97 * different shifts. And we here create a mask only for those 98 * IRQs that we activated. 99 */ 100 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 101 102 /* Tx IRQ */ 103 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 104 flags = xcsr & mask; 105 106 if (flags) 107 iret = IRQ_HANDLED; 108 else 109 goto irq_rx; 110 111 if (flags & FSL_SAI_CSR_WSF) 112 dev_dbg(dev, "isr: Start of Tx word detected\n"); 113 114 if (flags & FSL_SAI_CSR_SEF) 115 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 116 117 if (flags & FSL_SAI_CSR_FEF) 118 dev_dbg(dev, "isr: Transmit underrun detected\n"); 119 120 if (flags & FSL_SAI_CSR_FWF) 121 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 122 123 if (flags & FSL_SAI_CSR_FRF) 124 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 125 126 flags &= FSL_SAI_CSR_xF_W_MASK; 127 xcsr &= ~FSL_SAI_CSR_xF_MASK; 128 129 if (flags) 130 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 131 132 irq_rx: 133 /* Rx IRQ */ 134 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 135 flags = xcsr & mask; 136 137 if (flags) 138 iret = IRQ_HANDLED; 139 else 140 goto out; 141 142 if (flags & FSL_SAI_CSR_WSF) 143 dev_dbg(dev, "isr: Start of Rx word detected\n"); 144 145 if (flags & FSL_SAI_CSR_SEF) 146 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 147 148 if (flags & FSL_SAI_CSR_FEF) 149 dev_dbg(dev, "isr: Receive overflow detected\n"); 150 151 if (flags & FSL_SAI_CSR_FWF) 152 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 153 154 if (flags & FSL_SAI_CSR_FRF) 155 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 156 157 flags &= FSL_SAI_CSR_xF_W_MASK; 158 xcsr &= ~FSL_SAI_CSR_xF_MASK; 159 160 if (flags) 161 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 162 163 out: 164 return iret; 165 } 166 167 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 168 u32 rx_mask, int slots, int slot_width) 169 { 170 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 171 172 sai->slots = slots; 173 sai->slot_width = slot_width; 174 175 return 0; 176 } 177 178 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 179 unsigned int ratio) 180 { 181 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 182 183 sai->bclk_ratio = ratio; 184 185 return 0; 186 } 187 188 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 189 int clk_id, unsigned int freq, bool tx) 190 { 191 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 192 unsigned int ofs = sai->soc_data->reg_offset; 193 u32 val_cr2 = 0; 194 195 switch (clk_id) { 196 case FSL_SAI_CLK_BUS: 197 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 198 break; 199 case FSL_SAI_CLK_MAST1: 200 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 201 break; 202 case FSL_SAI_CLK_MAST2: 203 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 204 break; 205 case FSL_SAI_CLK_MAST3: 206 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 207 break; 208 default: 209 return -EINVAL; 210 } 211 212 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 213 FSL_SAI_CR2_MSEL_MASK, val_cr2); 214 215 return 0; 216 } 217 218 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq) 219 { 220 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 221 int ret; 222 223 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], 224 sai->pll8k_clk, sai->pll11k_clk, freq); 225 226 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); 227 if (ret < 0) 228 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); 229 230 return ret; 231 } 232 233 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 234 int clk_id, unsigned int freq, int dir) 235 { 236 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 237 int ret; 238 239 if (dir == SND_SOC_CLOCK_IN) 240 return 0; 241 242 if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) { 243 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) { 244 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); 245 return -EINVAL; 246 } 247 248 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { 249 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); 250 return -EINVAL; 251 } 252 253 if (sai->mclk_streams == 0) { 254 ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq); 255 if (ret < 0) 256 return ret; 257 } 258 } 259 260 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); 261 if (ret) { 262 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 263 return ret; 264 } 265 266 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false); 267 if (ret) 268 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 269 270 return ret; 271 } 272 273 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 274 unsigned int fmt, bool tx) 275 { 276 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 277 unsigned int ofs = sai->soc_data->reg_offset; 278 u32 val_cr2 = 0, val_cr4 = 0; 279 280 if (!sai->is_lsb_first) 281 val_cr4 |= FSL_SAI_CR4_MF; 282 283 sai->is_pdm_mode = false; 284 /* DAI mode */ 285 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 286 case SND_SOC_DAIFMT_I2S: 287 /* 288 * Frame low, 1clk before data, one word length for frame sync, 289 * frame sync starts one serial clock cycle earlier, 290 * that is, together with the last bit of the previous 291 * data word. 292 */ 293 val_cr2 |= FSL_SAI_CR2_BCP; 294 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 295 break; 296 case SND_SOC_DAIFMT_LEFT_J: 297 /* 298 * Frame high, one word length for frame sync, 299 * frame sync asserts with the first bit of the frame. 300 */ 301 val_cr2 |= FSL_SAI_CR2_BCP; 302 break; 303 case SND_SOC_DAIFMT_DSP_A: 304 /* 305 * Frame high, 1clk before data, one bit for frame sync, 306 * frame sync starts one serial clock cycle earlier, 307 * that is, together with the last bit of the previous 308 * data word. 309 */ 310 val_cr2 |= FSL_SAI_CR2_BCP; 311 val_cr4 |= FSL_SAI_CR4_FSE; 312 sai->is_dsp_mode = true; 313 break; 314 case SND_SOC_DAIFMT_DSP_B: 315 /* 316 * Frame high, one bit for frame sync, 317 * frame sync asserts with the first bit of the frame. 318 */ 319 val_cr2 |= FSL_SAI_CR2_BCP; 320 sai->is_dsp_mode = true; 321 break; 322 case SND_SOC_DAIFMT_PDM: 323 val_cr2 |= FSL_SAI_CR2_BCP; 324 val_cr4 &= ~FSL_SAI_CR4_MF; 325 sai->is_pdm_mode = true; 326 break; 327 case SND_SOC_DAIFMT_RIGHT_J: 328 /* To be done */ 329 default: 330 return -EINVAL; 331 } 332 333 /* DAI clock inversion */ 334 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 335 case SND_SOC_DAIFMT_IB_IF: 336 /* Invert both clocks */ 337 val_cr2 ^= FSL_SAI_CR2_BCP; 338 val_cr4 ^= FSL_SAI_CR4_FSP; 339 break; 340 case SND_SOC_DAIFMT_IB_NF: 341 /* Invert bit clock */ 342 val_cr2 ^= FSL_SAI_CR2_BCP; 343 break; 344 case SND_SOC_DAIFMT_NB_IF: 345 /* Invert frame clock */ 346 val_cr4 ^= FSL_SAI_CR4_FSP; 347 break; 348 case SND_SOC_DAIFMT_NB_NF: 349 /* Nothing to do for both normal cases */ 350 break; 351 default: 352 return -EINVAL; 353 } 354 355 /* DAI clock provider masks */ 356 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 357 case SND_SOC_DAIFMT_BP_FP: 358 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 359 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 360 sai->is_consumer_mode = false; 361 break; 362 case SND_SOC_DAIFMT_BC_FC: 363 sai->is_consumer_mode = true; 364 break; 365 case SND_SOC_DAIFMT_BP_FC: 366 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 367 sai->is_consumer_mode = false; 368 break; 369 case SND_SOC_DAIFMT_BC_FP: 370 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 371 sai->is_consumer_mode = true; 372 break; 373 default: 374 return -EINVAL; 375 } 376 377 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 378 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 379 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 380 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 381 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 382 383 return 0; 384 } 385 386 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 387 { 388 int ret; 389 390 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 391 if (ret) { 392 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 393 return ret; 394 } 395 396 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 397 if (ret) 398 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 399 400 return ret; 401 } 402 403 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 404 { 405 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 406 unsigned int reg, ofs = sai->soc_data->reg_offset; 407 unsigned long clk_rate; 408 u32 savediv = 0, ratio, bestdiff = freq; 409 int adir = tx ? RX : TX; 410 int dir = tx ? TX : RX; 411 u32 id; 412 bool support_1_1_ratio = sai->verid.version >= 0x0301; 413 414 /* Don't apply to consumer mode */ 415 if (sai->is_consumer_mode) 416 return 0; 417 418 /* 419 * There is no point in polling MCLK0 if it is identical to MCLK1. 420 * And given that MQS use case has to use MCLK1 though two clocks 421 * are the same, we simply skip MCLK0 and start to find from MCLK1. 422 */ 423 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 424 425 for (; id < FSL_SAI_MCLK_MAX; id++) { 426 int diff; 427 428 clk_rate = clk_get_rate(sai->mclk_clk[id]); 429 if (!clk_rate) 430 continue; 431 432 ratio = DIV_ROUND_CLOSEST(clk_rate, freq); 433 if (!ratio || ratio > 512) 434 continue; 435 if (ratio == 1 && !support_1_1_ratio) 436 continue; 437 if ((ratio & 1) && ratio > 1) 438 continue; 439 440 diff = abs((long)clk_rate - ratio * freq); 441 442 /* 443 * Drop the source that can not be 444 * divided into the required rate. 445 */ 446 if (diff != 0 && clk_rate / diff < 1000) 447 continue; 448 449 dev_dbg(dai->dev, 450 "ratio %d for freq %dHz based on clock %ldHz\n", 451 ratio, freq, clk_rate); 452 453 454 if (diff < bestdiff) { 455 savediv = ratio; 456 sai->mclk_id[tx] = id; 457 bestdiff = diff; 458 } 459 460 if (diff == 0) 461 break; 462 } 463 464 if (savediv == 0) { 465 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 466 tx ? 'T' : 'R', freq); 467 return -EINVAL; 468 } 469 470 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 471 sai->mclk_id[tx], savediv, bestdiff); 472 473 /* 474 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 475 * set TCR2 register for playback. 476 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 477 * and capture. 478 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 479 * and capture. 480 * 4) For Tx and Rx are both Synchronous with another SAI, we just 481 * ignore it. 482 */ 483 if (fsl_sai_dir_is_synced(sai, adir)) 484 reg = FSL_SAI_xCR2(!tx, ofs); 485 else if (!sai->synchronous[dir]) 486 reg = FSL_SAI_xCR2(tx, ofs); 487 else 488 return 0; 489 490 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, 491 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 492 493 if (savediv == 1) 494 regmap_update_bits(sai->regmap, reg, 495 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 496 FSL_SAI_CR2_BYP); 497 else 498 regmap_update_bits(sai->regmap, reg, 499 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 500 savediv / 2 - 1); 501 502 if (sai->soc_data->max_register >= FSL_SAI_MCTL) { 503 /* SAI is in master mode at this point, so enable MCLK */ 504 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 505 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 506 } 507 508 return 0; 509 } 510 511 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 512 struct snd_pcm_hw_params *params, 513 struct snd_soc_dai *cpu_dai) 514 { 515 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 516 unsigned int ofs = sai->soc_data->reg_offset; 517 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 518 unsigned int channels = params_channels(params); 519 struct snd_dmaengine_dai_dma_data *dma_params; 520 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; 521 u32 word_width = params_width(params); 522 int trce_mask = 0, dl_cfg_idx = 0; 523 int dl_cfg_cnt = sai->dl_cfg_cnt; 524 u32 dl_type = FSL_SAI_DL_I2S; 525 u32 val_cr4 = 0, val_cr5 = 0; 526 u32 slots = (channels == 1) ? 2 : channels; 527 u32 slot_width = word_width; 528 int adir = tx ? RX : TX; 529 u32 pins, bclk; 530 u32 watermark; 531 int ret, i; 532 533 if (sai->slot_width) 534 slot_width = sai->slot_width; 535 536 if (sai->slots) 537 slots = sai->slots; 538 else if (sai->bclk_ratio) 539 slots = sai->bclk_ratio / slot_width; 540 541 pins = DIV_ROUND_UP(channels, slots); 542 543 /* 544 * PDM mode, channels are independent 545 * each channels are on one dataline/FIFO. 546 */ 547 if (sai->is_pdm_mode) { 548 pins = channels; 549 dl_type = FSL_SAI_DL_PDM; 550 } 551 552 for (i = 0; i < dl_cfg_cnt; i++) { 553 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) { 554 dl_cfg_idx = i; 555 break; 556 } 557 } 558 559 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) { 560 dev_err(cpu_dai->dev, "channel not supported\n"); 561 return -EINVAL; 562 } 563 564 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); 565 566 if (!IS_ERR_OR_NULL(sai->pinctrl)) { 567 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); 568 if (!IS_ERR_OR_NULL(sai->pins_state)) { 569 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 570 if (ret) { 571 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); 572 return ret; 573 } 574 } 575 } 576 577 if (!sai->is_consumer_mode) { 578 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk); 579 if (ret) 580 return ret; 581 582 /* Do not enable the clock if it is already enabled */ 583 if (!(sai->mclk_streams & BIT(substream->stream))) { 584 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 585 if (ret) 586 return ret; 587 588 sai->mclk_streams |= BIT(substream->stream); 589 } 590 } 591 592 if (!sai->is_dsp_mode && !sai->is_pdm_mode) 593 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 594 595 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 596 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 597 598 if (sai->is_lsb_first || sai->is_pdm_mode) 599 val_cr5 |= FSL_SAI_CR5_FBT(0); 600 else 601 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 602 603 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 604 605 /* Set to output mode to avoid tri-stated data pins */ 606 if (tx) 607 val_cr4 |= FSL_SAI_CR4_CHMOD; 608 609 /* 610 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 611 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 612 * RCR5(TCR5) for playback(capture), or there will be sync error. 613 */ 614 615 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) { 616 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 617 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 618 FSL_SAI_CR4_CHMOD_MASK, 619 val_cr4); 620 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 621 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 622 FSL_SAI_CR5_FBT_MASK, val_cr5); 623 } 624 625 /* 626 * Combine mode has limation: 627 * - Can't used for singel dataline/FIFO case except the FIFO0 628 * - Can't used for multi dataline/FIFO case except the enabled FIFOs 629 * are successive and start from FIFO0 630 * 631 * So for common usage, all multi fifo case disable the combine mode. 632 */ 633 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma) 634 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 635 FSL_SAI_CR4_FCOMB_MASK, 0); 636 else 637 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 638 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); 639 640 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; 641 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + 642 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4; 643 644 if (sai->is_multi_fifo_dma) { 645 sai->audio_config[tx].words_per_fifo = min(slots, channels); 646 if (tx) { 647 sai->audio_config[tx].n_fifos_dst = pins; 648 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx]; 649 } else { 650 sai->audio_config[tx].n_fifos_src = pins; 651 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx]; 652 } 653 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins; 654 dma_params->peripheral_config = &sai->audio_config[tx]; 655 dma_params->peripheral_size = sizeof(sai->audio_config[tx]); 656 657 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) : 658 (dma_params->maxburst - 1); 659 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs), 660 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 661 watermark); 662 } 663 664 /* Find a proper tcre setting */ 665 for (i = 0; i < sai->soc_data->pins; i++) { 666 trce_mask = (1 << (i + 1)) - 1; 667 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins) 668 break; 669 } 670 671 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 672 FSL_SAI_CR3_TRCE_MASK, 673 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); 674 675 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 676 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 677 FSL_SAI_CR4_CHMOD_MASK, 678 val_cr4); 679 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 680 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 681 FSL_SAI_CR5_FBT_MASK, val_cr5); 682 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 683 ~0UL - ((1 << min(channels, slots)) - 1)); 684 685 return 0; 686 } 687 688 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 689 struct snd_soc_dai *cpu_dai) 690 { 691 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 692 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 693 unsigned int ofs = sai->soc_data->reg_offset; 694 695 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 696 FSL_SAI_CR3_TRCE_MASK, 0); 697 698 if (!sai->is_consumer_mode && 699 sai->mclk_streams & BIT(substream->stream)) { 700 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 701 sai->mclk_streams &= ~BIT(substream->stream); 702 } 703 704 return 0; 705 } 706 707 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 708 { 709 unsigned int ofs = sai->soc_data->reg_offset; 710 bool tx = dir == TX; 711 u32 xcsr, count = 100; 712 713 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 714 FSL_SAI_CSR_TERE, 0); 715 716 /* TERE will remain set till the end of current frame */ 717 do { 718 udelay(10); 719 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 720 } while (--count && xcsr & FSL_SAI_CSR_TERE); 721 722 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 723 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 724 725 /* 726 * For sai master mode, after several open/close sai, 727 * there will be no frame clock, and can't recover 728 * anymore. Add software reset to fix this issue. 729 * This is a hardware bug, and will be fix in the 730 * next sai version. 731 */ 732 if (!sai->is_consumer_mode) { 733 /* Software Reset */ 734 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); 735 /* Clear SR bit to finish the reset */ 736 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); 737 } 738 } 739 740 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 741 struct snd_soc_dai *cpu_dai) 742 { 743 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 744 unsigned int ofs = sai->soc_data->reg_offset; 745 746 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 747 int adir = tx ? RX : TX; 748 int dir = tx ? TX : RX; 749 u32 xcsr; 750 751 /* 752 * Asynchronous mode: Clear SYNC for both Tx and Rx. 753 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 754 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 755 */ 756 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 757 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 758 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 759 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 760 761 /* 762 * It is recommended that the transmitter is the last enabled 763 * and the first disabled. 764 */ 765 switch (cmd) { 766 case SNDRV_PCM_TRIGGER_START: 767 case SNDRV_PCM_TRIGGER_RESUME: 768 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 769 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 770 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 771 772 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 773 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 774 /* 775 * Enable the opposite direction for synchronous mode 776 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 777 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 778 * 779 * RM recommends to enable RE after TE for case 1 and to enable 780 * TE after RE for case 2, but we here may not always guarantee 781 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 782 * TE after RE, which is against what RM recommends but should 783 * be safe to do, judging by years of testing results. 784 */ 785 if (fsl_sai_dir_is_synced(sai, adir)) 786 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 787 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 788 789 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 790 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 791 break; 792 case SNDRV_PCM_TRIGGER_STOP: 793 case SNDRV_PCM_TRIGGER_SUSPEND: 794 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 795 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 796 FSL_SAI_CSR_FRDE, 0); 797 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 798 FSL_SAI_CSR_xIE_MASK, 0); 799 800 /* Check if the opposite FRDE is also disabled */ 801 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 802 803 /* 804 * If opposite stream provides clocks for synchronous mode and 805 * it is inactive, disable it before disabling the current one 806 */ 807 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 808 fsl_sai_config_disable(sai, adir); 809 810 /* 811 * Disable current stream if either of: 812 * 1. current stream doesn't provide clocks for synchronous mode 813 * 2. current stream provides clocks for synchronous mode but no 814 * more stream is active. 815 */ 816 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 817 fsl_sai_config_disable(sai, dir); 818 819 break; 820 default: 821 return -EINVAL; 822 } 823 824 return 0; 825 } 826 827 static int fsl_sai_startup(struct snd_pcm_substream *substream, 828 struct snd_soc_dai *cpu_dai) 829 { 830 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 831 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 832 int ret; 833 834 /* 835 * EDMA controller needs period size to be a multiple of 836 * tx/rx maxburst 837 */ 838 if (sai->soc_data->use_edma) 839 snd_pcm_hw_constraint_step(substream->runtime, 0, 840 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 841 tx ? sai->dma_params_tx.maxburst : 842 sai->dma_params_rx.maxburst); 843 844 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 845 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); 846 847 return ret; 848 } 849 850 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 851 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 852 .set_sysclk = fsl_sai_set_dai_sysclk, 853 .set_fmt = fsl_sai_set_dai_fmt, 854 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 855 .hw_params = fsl_sai_hw_params, 856 .hw_free = fsl_sai_hw_free, 857 .trigger = fsl_sai_trigger, 858 .startup = fsl_sai_startup, 859 }; 860 861 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 862 { 863 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 864 unsigned int ofs = sai->soc_data->reg_offset; 865 866 /* Software Reset for both Tx and Rx */ 867 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 868 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 869 /* Clear SR bit to finish the reset */ 870 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 871 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 872 873 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 874 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 875 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX); 876 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 877 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 878 FSL_SAI_MAXBURST_RX - 1); 879 880 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 881 &sai->dma_params_rx); 882 883 return 0; 884 } 885 886 static int fsl_sai_dai_resume(struct snd_soc_component *component) 887 { 888 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 889 struct device *dev = &sai->pdev->dev; 890 int ret; 891 892 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { 893 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 894 if (ret) { 895 dev_err(dev, "failed to set proper pins state: %d\n", ret); 896 return ret; 897 } 898 } 899 900 return 0; 901 } 902 903 static struct snd_soc_dai_driver fsl_sai_dai_template = { 904 .probe = fsl_sai_dai_probe, 905 .playback = { 906 .stream_name = "CPU-Playback", 907 .channels_min = 1, 908 .channels_max = 32, 909 .rate_min = 8000, 910 .rate_max = 2822400, 911 .rates = SNDRV_PCM_RATE_KNOT, 912 .formats = FSL_SAI_FORMATS, 913 }, 914 .capture = { 915 .stream_name = "CPU-Capture", 916 .channels_min = 1, 917 .channels_max = 32, 918 .rate_min = 8000, 919 .rate_max = 2822400, 920 .rates = SNDRV_PCM_RATE_KNOT, 921 .formats = FSL_SAI_FORMATS, 922 }, 923 .ops = &fsl_sai_pcm_dai_ops, 924 }; 925 926 static const struct snd_soc_component_driver fsl_component = { 927 .name = "fsl-sai", 928 .resume = fsl_sai_dai_resume, 929 .legacy_dai_naming = 1, 930 }; 931 932 static struct reg_default fsl_sai_reg_defaults_ofs0[] = { 933 {FSL_SAI_TCR1(0), 0}, 934 {FSL_SAI_TCR2(0), 0}, 935 {FSL_SAI_TCR3(0), 0}, 936 {FSL_SAI_TCR4(0), 0}, 937 {FSL_SAI_TCR5(0), 0}, 938 {FSL_SAI_TDR0, 0}, 939 {FSL_SAI_TDR1, 0}, 940 {FSL_SAI_TDR2, 0}, 941 {FSL_SAI_TDR3, 0}, 942 {FSL_SAI_TDR4, 0}, 943 {FSL_SAI_TDR5, 0}, 944 {FSL_SAI_TDR6, 0}, 945 {FSL_SAI_TDR7, 0}, 946 {FSL_SAI_TMR, 0}, 947 {FSL_SAI_RCR1(0), 0}, 948 {FSL_SAI_RCR2(0), 0}, 949 {FSL_SAI_RCR3(0), 0}, 950 {FSL_SAI_RCR4(0), 0}, 951 {FSL_SAI_RCR5(0), 0}, 952 {FSL_SAI_RMR, 0}, 953 }; 954 955 static struct reg_default fsl_sai_reg_defaults_ofs8[] = { 956 {FSL_SAI_TCR1(8), 0}, 957 {FSL_SAI_TCR2(8), 0}, 958 {FSL_SAI_TCR3(8), 0}, 959 {FSL_SAI_TCR4(8), 0}, 960 {FSL_SAI_TCR5(8), 0}, 961 {FSL_SAI_TDR0, 0}, 962 {FSL_SAI_TDR1, 0}, 963 {FSL_SAI_TDR2, 0}, 964 {FSL_SAI_TDR3, 0}, 965 {FSL_SAI_TDR4, 0}, 966 {FSL_SAI_TDR5, 0}, 967 {FSL_SAI_TDR6, 0}, 968 {FSL_SAI_TDR7, 0}, 969 {FSL_SAI_TMR, 0}, 970 {FSL_SAI_RCR1(8), 0}, 971 {FSL_SAI_RCR2(8), 0}, 972 {FSL_SAI_RCR3(8), 0}, 973 {FSL_SAI_RCR4(8), 0}, 974 {FSL_SAI_RCR5(8), 0}, 975 {FSL_SAI_RMR, 0}, 976 {FSL_SAI_MCTL, 0}, 977 {FSL_SAI_MDIV, 0}, 978 }; 979 980 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 981 { 982 struct fsl_sai *sai = dev_get_drvdata(dev); 983 unsigned int ofs = sai->soc_data->reg_offset; 984 985 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 986 return true; 987 988 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 989 return true; 990 991 switch (reg) { 992 case FSL_SAI_TFR0: 993 case FSL_SAI_TFR1: 994 case FSL_SAI_TFR2: 995 case FSL_SAI_TFR3: 996 case FSL_SAI_TFR4: 997 case FSL_SAI_TFR5: 998 case FSL_SAI_TFR6: 999 case FSL_SAI_TFR7: 1000 case FSL_SAI_TMR: 1001 case FSL_SAI_RDR0: 1002 case FSL_SAI_RDR1: 1003 case FSL_SAI_RDR2: 1004 case FSL_SAI_RDR3: 1005 case FSL_SAI_RDR4: 1006 case FSL_SAI_RDR5: 1007 case FSL_SAI_RDR6: 1008 case FSL_SAI_RDR7: 1009 case FSL_SAI_RFR0: 1010 case FSL_SAI_RFR1: 1011 case FSL_SAI_RFR2: 1012 case FSL_SAI_RFR3: 1013 case FSL_SAI_RFR4: 1014 case FSL_SAI_RFR5: 1015 case FSL_SAI_RFR6: 1016 case FSL_SAI_RFR7: 1017 case FSL_SAI_RMR: 1018 case FSL_SAI_MCTL: 1019 case FSL_SAI_MDIV: 1020 case FSL_SAI_VERID: 1021 case FSL_SAI_PARAM: 1022 case FSL_SAI_TTCTN: 1023 case FSL_SAI_RTCTN: 1024 case FSL_SAI_TTCTL: 1025 case FSL_SAI_TBCTN: 1026 case FSL_SAI_TTCAP: 1027 case FSL_SAI_RTCTL: 1028 case FSL_SAI_RBCTN: 1029 case FSL_SAI_RTCAP: 1030 return true; 1031 default: 1032 return false; 1033 } 1034 } 1035 1036 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 1037 { 1038 struct fsl_sai *sai = dev_get_drvdata(dev); 1039 unsigned int ofs = sai->soc_data->reg_offset; 1040 1041 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 1042 return true; 1043 1044 /* Set VERID and PARAM be volatile for reading value in probe */ 1045 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 1046 return true; 1047 1048 switch (reg) { 1049 case FSL_SAI_TFR0: 1050 case FSL_SAI_TFR1: 1051 case FSL_SAI_TFR2: 1052 case FSL_SAI_TFR3: 1053 case FSL_SAI_TFR4: 1054 case FSL_SAI_TFR5: 1055 case FSL_SAI_TFR6: 1056 case FSL_SAI_TFR7: 1057 case FSL_SAI_RFR0: 1058 case FSL_SAI_RFR1: 1059 case FSL_SAI_RFR2: 1060 case FSL_SAI_RFR3: 1061 case FSL_SAI_RFR4: 1062 case FSL_SAI_RFR5: 1063 case FSL_SAI_RFR6: 1064 case FSL_SAI_RFR7: 1065 case FSL_SAI_RDR0: 1066 case FSL_SAI_RDR1: 1067 case FSL_SAI_RDR2: 1068 case FSL_SAI_RDR3: 1069 case FSL_SAI_RDR4: 1070 case FSL_SAI_RDR5: 1071 case FSL_SAI_RDR6: 1072 case FSL_SAI_RDR7: 1073 return true; 1074 default: 1075 return false; 1076 } 1077 } 1078 1079 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 1080 { 1081 struct fsl_sai *sai = dev_get_drvdata(dev); 1082 unsigned int ofs = sai->soc_data->reg_offset; 1083 1084 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1085 return true; 1086 1087 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1088 return true; 1089 1090 switch (reg) { 1091 case FSL_SAI_TDR0: 1092 case FSL_SAI_TDR1: 1093 case FSL_SAI_TDR2: 1094 case FSL_SAI_TDR3: 1095 case FSL_SAI_TDR4: 1096 case FSL_SAI_TDR5: 1097 case FSL_SAI_TDR6: 1098 case FSL_SAI_TDR7: 1099 case FSL_SAI_TMR: 1100 case FSL_SAI_RMR: 1101 case FSL_SAI_MCTL: 1102 case FSL_SAI_MDIV: 1103 case FSL_SAI_TTCTL: 1104 case FSL_SAI_RTCTL: 1105 return true; 1106 default: 1107 return false; 1108 } 1109 } 1110 1111 static struct regmap_config fsl_sai_regmap_config = { 1112 .reg_bits = 32, 1113 .reg_stride = 4, 1114 .val_bits = 32, 1115 .fast_io = true, 1116 1117 .max_register = FSL_SAI_RMR, 1118 .reg_defaults = fsl_sai_reg_defaults_ofs0, 1119 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 1120 .readable_reg = fsl_sai_readable_reg, 1121 .volatile_reg = fsl_sai_volatile_reg, 1122 .writeable_reg = fsl_sai_writeable_reg, 1123 .cache_type = REGCACHE_FLAT, 1124 }; 1125 1126 static int fsl_sai_check_version(struct device *dev) 1127 { 1128 struct fsl_sai *sai = dev_get_drvdata(dev); 1129 unsigned char ofs = sai->soc_data->reg_offset; 1130 unsigned int val; 1131 int ret; 1132 1133 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 1134 return 0; 1135 1136 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 1137 if (ret < 0) 1138 return ret; 1139 1140 dev_dbg(dev, "VERID: 0x%016X\n", val); 1141 1142 sai->verid.version = val & 1143 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK); 1144 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 1145 1146 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 1147 if (ret < 0) 1148 return ret; 1149 1150 dev_dbg(dev, "PARAM: 0x%016X\n", val); 1151 1152 /* Max slots per frame, power of 2 */ 1153 sai->param.slot_num = 1 << 1154 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 1155 1156 /* Words per fifo, power of 2 */ 1157 sai->param.fifo_depth = 1 << 1158 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 1159 1160 /* Number of datalines implemented */ 1161 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 1162 1163 return 0; 1164 } 1165 1166 /* 1167 * Calculate the offset between first two datalines, don't 1168 * different offset in one case. 1169 */ 1170 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask) 1171 { 1172 int fbidx, nbidx, offset; 1173 1174 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1175 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1); 1176 offset = nbidx - fbidx - 1; 1177 1178 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); 1179 } 1180 1181 /* 1182 * read the fsl,dataline property from dts file. 1183 * It has 3 value for each configuration, first one means the type: 1184 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is 1185 * dataline mask for 'tx'. for example 1186 * 1187 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>, 1188 * 1189 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type 1190 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). 1191 * 1192 */ 1193 static int fsl_sai_read_dlcfg(struct fsl_sai *sai) 1194 { 1195 struct platform_device *pdev = sai->pdev; 1196 struct device_node *np = pdev->dev.of_node; 1197 struct device *dev = &pdev->dev; 1198 int ret, elems, i, index, num_cfg; 1199 char *propname = "fsl,dataline"; 1200 struct fsl_sai_dl_cfg *cfg; 1201 unsigned long dl_mask; 1202 unsigned int soc_dl; 1203 u32 rx, tx, type; 1204 1205 elems = of_property_count_u32_elems(np, propname); 1206 1207 if (elems <= 0) { 1208 elems = 0; 1209 } else if (elems % 3) { 1210 dev_err(dev, "Number of elements must be divisible to 3.\n"); 1211 return -EINVAL; 1212 } 1213 1214 num_cfg = elems / 3; 1215 /* Add one more for default value */ 1216 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL); 1217 if (!cfg) 1218 return -ENOMEM; 1219 1220 /* Consider default value "0 0xFF 0xFF" if property is missing */ 1221 soc_dl = BIT(sai->soc_data->pins) - 1; 1222 cfg[0].type = FSL_SAI_DL_DEFAULT; 1223 cfg[0].pins[0] = sai->soc_data->pins; 1224 cfg[0].mask[0] = soc_dl; 1225 cfg[0].start_off[0] = 0; 1226 cfg[0].next_off[0] = 0; 1227 1228 cfg[0].pins[1] = sai->soc_data->pins; 1229 cfg[0].mask[1] = soc_dl; 1230 cfg[0].start_off[1] = 0; 1231 cfg[0].next_off[1] = 0; 1232 for (i = 1, index = 0; i < num_cfg + 1; i++) { 1233 /* 1234 * type of dataline 1235 * 0 means default mode 1236 * 1 means I2S mode 1237 * 2 means PDM mode 1238 */ 1239 ret = of_property_read_u32_index(np, propname, index++, &type); 1240 if (ret) 1241 return -EINVAL; 1242 1243 ret = of_property_read_u32_index(np, propname, index++, &rx); 1244 if (ret) 1245 return -EINVAL; 1246 1247 ret = of_property_read_u32_index(np, propname, index++, &tx); 1248 if (ret) 1249 return -EINVAL; 1250 1251 if ((rx & ~soc_dl) || (tx & ~soc_dl)) { 1252 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl); 1253 return -EINVAL; 1254 } 1255 1256 rx = rx & soc_dl; 1257 tx = tx & soc_dl; 1258 1259 cfg[i].type = type; 1260 cfg[i].pins[0] = hweight8(rx); 1261 cfg[i].mask[0] = rx; 1262 dl_mask = rx; 1263 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1264 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx); 1265 1266 cfg[i].pins[1] = hweight8(tx); 1267 cfg[i].mask[1] = tx; 1268 dl_mask = tx; 1269 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1270 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx); 1271 } 1272 1273 sai->dl_cfg = cfg; 1274 sai->dl_cfg_cnt = num_cfg + 1; 1275 return 0; 1276 } 1277 1278 static int fsl_sai_runtime_suspend(struct device *dev); 1279 static int fsl_sai_runtime_resume(struct device *dev); 1280 1281 static int fsl_sai_probe(struct platform_device *pdev) 1282 { 1283 struct device_node *np = pdev->dev.of_node; 1284 struct device *dev = &pdev->dev; 1285 struct fsl_sai *sai; 1286 struct regmap *gpr; 1287 void __iomem *base; 1288 char tmp[8]; 1289 int irq, ret, i; 1290 int index; 1291 u32 dmas[4]; 1292 1293 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); 1294 if (!sai) 1295 return -ENOMEM; 1296 1297 sai->pdev = pdev; 1298 sai->soc_data = of_device_get_match_data(dev); 1299 1300 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1301 1302 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); 1303 if (IS_ERR(base)) 1304 return PTR_ERR(base); 1305 1306 if (sai->soc_data->reg_offset == 8) { 1307 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1308 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1309 fsl_sai_regmap_config.num_reg_defaults = 1310 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1311 } 1312 1313 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); 1314 if (IS_ERR(sai->regmap)) { 1315 dev_err(dev, "regmap init failed\n"); 1316 return PTR_ERR(sai->regmap); 1317 } 1318 1319 sai->bus_clk = devm_clk_get(dev, "bus"); 1320 /* Compatible with old DTB cases */ 1321 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1322 sai->bus_clk = devm_clk_get(dev, "sai"); 1323 if (IS_ERR(sai->bus_clk)) { 1324 dev_err(dev, "failed to get bus clock: %ld\n", 1325 PTR_ERR(sai->bus_clk)); 1326 /* -EPROBE_DEFER */ 1327 return PTR_ERR(sai->bus_clk); 1328 } 1329 1330 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1331 sprintf(tmp, "mclk%d", i); 1332 sai->mclk_clk[i] = devm_clk_get(dev, tmp); 1333 if (IS_ERR(sai->mclk_clk[i])) { 1334 dev_err(dev, "failed to get mclk%d clock: %ld\n", 1335 i, PTR_ERR(sai->mclk_clk[i])); 1336 sai->mclk_clk[i] = NULL; 1337 } 1338 } 1339 1340 if (sai->soc_data->mclk0_is_mclk1) 1341 sai->mclk_clk[0] = sai->mclk_clk[1]; 1342 else 1343 sai->mclk_clk[0] = sai->bus_clk; 1344 1345 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, 1346 &sai->pll11k_clk); 1347 1348 /* Use Multi FIFO mode depending on the support from SDMA script */ 1349 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1350 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) 1351 sai->is_multi_fifo_dma = true; 1352 1353 /* read dataline mask for rx and tx*/ 1354 ret = fsl_sai_read_dlcfg(sai); 1355 if (ret < 0) { 1356 dev_err(dev, "failed to read dlcfg %d\n", ret); 1357 return ret; 1358 } 1359 1360 irq = platform_get_irq(pdev, 0); 1361 if (irq < 0) 1362 return irq; 1363 1364 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED, 1365 np->name, sai); 1366 if (ret) { 1367 dev_err(dev, "failed to claim irq %u\n", irq); 1368 return ret; 1369 } 1370 1371 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, 1372 sizeof(fsl_sai_dai_template)); 1373 1374 /* Sync Tx with Rx as default by following old DT binding */ 1375 sai->synchronous[RX] = true; 1376 sai->synchronous[TX] = false; 1377 sai->cpu_dai_drv.symmetric_rate = 1; 1378 sai->cpu_dai_drv.symmetric_channels = 1; 1379 sai->cpu_dai_drv.symmetric_sample_bits = 1; 1380 1381 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && 1382 of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1383 /* error out if both synchronous and asynchronous are present */ 1384 dev_err(dev, "invalid binding for synchronous mode\n"); 1385 return -EINVAL; 1386 } 1387 1388 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { 1389 /* Sync Rx with Tx */ 1390 sai->synchronous[RX] = false; 1391 sai->synchronous[TX] = true; 1392 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1393 /* Discard all settings for asynchronous mode */ 1394 sai->synchronous[RX] = false; 1395 sai->synchronous[TX] = false; 1396 sai->cpu_dai_drv.symmetric_rate = 0; 1397 sai->cpu_dai_drv.symmetric_channels = 0; 1398 sai->cpu_dai_drv.symmetric_sample_bits = 0; 1399 } 1400 1401 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1402 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1403 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1404 if (IS_ERR(gpr)) { 1405 dev_err(dev, "cannot find iomuxc registers\n"); 1406 return PTR_ERR(gpr); 1407 } 1408 1409 index = of_alias_get_id(np, "sai"); 1410 if (index < 0) 1411 return index; 1412 1413 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1414 MCLK_DIR(index)); 1415 } 1416 1417 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; 1418 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; 1419 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; 1420 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; 1421 1422 sai->pinctrl = devm_pinctrl_get(&pdev->dev); 1423 1424 platform_set_drvdata(pdev, sai); 1425 pm_runtime_enable(dev); 1426 if (!pm_runtime_enabled(dev)) { 1427 ret = fsl_sai_runtime_resume(dev); 1428 if (ret) 1429 goto err_pm_disable; 1430 } 1431 1432 ret = pm_runtime_resume_and_get(dev); 1433 if (ret < 0) 1434 goto err_pm_get_sync; 1435 1436 /* Get sai version */ 1437 ret = fsl_sai_check_version(dev); 1438 if (ret < 0) 1439 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1440 1441 /* Select MCLK direction */ 1442 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1443 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1444 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1445 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1446 } 1447 1448 ret = pm_runtime_put_sync(dev); 1449 if (ret < 0) 1450 goto err_pm_get_sync; 1451 1452 /* 1453 * Register platform component before registering cpu dai for there 1454 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1455 */ 1456 if (sai->soc_data->use_imx_pcm) { 1457 ret = imx_pcm_dma_init(pdev); 1458 if (ret) { 1459 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)) 1460 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); 1461 goto err_pm_get_sync; 1462 } 1463 } else { 1464 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1465 if (ret) 1466 goto err_pm_get_sync; 1467 } 1468 1469 ret = devm_snd_soc_register_component(dev, &fsl_component, 1470 &sai->cpu_dai_drv, 1); 1471 if (ret) 1472 goto err_pm_get_sync; 1473 1474 return ret; 1475 1476 err_pm_get_sync: 1477 if (!pm_runtime_status_suspended(dev)) 1478 fsl_sai_runtime_suspend(dev); 1479 err_pm_disable: 1480 pm_runtime_disable(dev); 1481 1482 return ret; 1483 } 1484 1485 static int fsl_sai_remove(struct platform_device *pdev) 1486 { 1487 pm_runtime_disable(&pdev->dev); 1488 if (!pm_runtime_status_suspended(&pdev->dev)) 1489 fsl_sai_runtime_suspend(&pdev->dev); 1490 1491 return 0; 1492 } 1493 1494 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1495 .use_imx_pcm = false, 1496 .use_edma = false, 1497 .fifo_depth = 32, 1498 .pins = 1, 1499 .reg_offset = 0, 1500 .mclk0_is_mclk1 = false, 1501 .flags = 0, 1502 .max_register = FSL_SAI_RMR, 1503 }; 1504 1505 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1506 .use_imx_pcm = true, 1507 .use_edma = false, 1508 .fifo_depth = 32, 1509 .pins = 1, 1510 .reg_offset = 0, 1511 .mclk0_is_mclk1 = true, 1512 .flags = 0, 1513 .max_register = FSL_SAI_RMR, 1514 }; 1515 1516 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1517 .use_imx_pcm = true, 1518 .use_edma = false, 1519 .fifo_depth = 16, 1520 .pins = 2, 1521 .reg_offset = 8, 1522 .mclk0_is_mclk1 = false, 1523 .flags = PMQOS_CPU_LATENCY, 1524 .max_register = FSL_SAI_RMR, 1525 }; 1526 1527 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1528 .use_imx_pcm = true, 1529 .use_edma = false, 1530 .fifo_depth = 128, 1531 .pins = 8, 1532 .reg_offset = 8, 1533 .mclk0_is_mclk1 = false, 1534 .flags = 0, 1535 .max_register = FSL_SAI_RMR, 1536 }; 1537 1538 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1539 .use_imx_pcm = true, 1540 .use_edma = true, 1541 .fifo_depth = 64, 1542 .pins = 1, 1543 .reg_offset = 0, 1544 .mclk0_is_mclk1 = false, 1545 .flags = 0, 1546 .max_register = FSL_SAI_RMR, 1547 }; 1548 1549 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = { 1550 .use_imx_pcm = true, 1551 .use_edma = false, 1552 .fifo_depth = 128, 1553 .reg_offset = 8, 1554 .mclk0_is_mclk1 = false, 1555 .pins = 8, 1556 .flags = 0, 1557 .max_register = FSL_SAI_MCTL, 1558 }; 1559 1560 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1561 .use_imx_pcm = true, 1562 .use_edma = false, 1563 .fifo_depth = 128, 1564 .reg_offset = 8, 1565 .mclk0_is_mclk1 = false, 1566 .pins = 8, 1567 .flags = 0, 1568 .max_register = FSL_SAI_MDIV, 1569 }; 1570 1571 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { 1572 .use_imx_pcm = true, 1573 .use_edma = true, 1574 .fifo_depth = 16, 1575 .reg_offset = 8, 1576 .mclk0_is_mclk1 = false, 1577 .pins = 4, 1578 .flags = PMQOS_CPU_LATENCY, 1579 .max_register = FSL_SAI_RTCAP, 1580 }; 1581 1582 static const struct of_device_id fsl_sai_ids[] = { 1583 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1584 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1585 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1586 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1587 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1588 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1589 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1590 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1591 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1592 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mp_data }, 1593 { /* sentinel */ } 1594 }; 1595 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1596 1597 static int fsl_sai_runtime_suspend(struct device *dev) 1598 { 1599 struct fsl_sai *sai = dev_get_drvdata(dev); 1600 1601 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1602 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1603 1604 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1605 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1606 1607 clk_disable_unprepare(sai->bus_clk); 1608 1609 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1610 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1611 1612 regcache_cache_only(sai->regmap, true); 1613 1614 return 0; 1615 } 1616 1617 static int fsl_sai_runtime_resume(struct device *dev) 1618 { 1619 struct fsl_sai *sai = dev_get_drvdata(dev); 1620 unsigned int ofs = sai->soc_data->reg_offset; 1621 int ret; 1622 1623 ret = clk_prepare_enable(sai->bus_clk); 1624 if (ret) { 1625 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1626 return ret; 1627 } 1628 1629 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1630 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1631 if (ret) 1632 goto disable_bus_clk; 1633 } 1634 1635 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1636 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1637 if (ret) 1638 goto disable_tx_clk; 1639 } 1640 1641 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1642 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1643 1644 regcache_cache_only(sai->regmap, false); 1645 regcache_mark_dirty(sai->regmap); 1646 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 1647 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 1648 usleep_range(1000, 2000); 1649 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1650 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1651 1652 ret = regcache_sync(sai->regmap); 1653 if (ret) 1654 goto disable_rx_clk; 1655 1656 return 0; 1657 1658 disable_rx_clk: 1659 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1660 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1661 disable_tx_clk: 1662 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1663 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1664 disable_bus_clk: 1665 clk_disable_unprepare(sai->bus_clk); 1666 1667 return ret; 1668 } 1669 1670 static const struct dev_pm_ops fsl_sai_pm_ops = { 1671 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, 1672 fsl_sai_runtime_resume, NULL) 1673 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1674 pm_runtime_force_resume) 1675 }; 1676 1677 static struct platform_driver fsl_sai_driver = { 1678 .probe = fsl_sai_probe, 1679 .remove = fsl_sai_remove, 1680 .driver = { 1681 .name = "fsl-sai", 1682 .pm = &fsl_sai_pm_ops, 1683 .of_match_table = fsl_sai_ids, 1684 }, 1685 }; 1686 module_platform_driver(fsl_sai_driver); 1687 1688 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1689 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1690 MODULE_ALIAS("platform:fsl-sai"); 1691 MODULE_LICENSE("GPL"); 1692