1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale DMA ALSA SoC PCM driver 4 // 5 // Author: Timur Tabi <timur@freescale.com> 6 // 7 // Copyright 2007-2010 Freescale Semiconductor, Inc. 8 // 9 // This driver implements ASoC support for the Elo DMA controller, which is 10 // the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 11 // the PCM driver is what handles the DMA buffer. 12 13 #include <linux/module.h> 14 #include <linux/init.h> 15 #include <linux/platform_device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/interrupt.h> 18 #include <linux/delay.h> 19 #include <linux/gfp.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_platform.h> 23 #include <linux/list.h> 24 #include <linux/slab.h> 25 26 #include <sound/core.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 31 #include <asm/io.h> 32 33 #include "fsl_dma.h" 34 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */ 35 36 #define DRV_NAME "fsl_dma" 37 38 /* 39 * The formats that the DMA controller supports, which is anything 40 * that is 8, 16, or 32 bits. 41 */ 42 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 43 SNDRV_PCM_FMTBIT_U8 | \ 44 SNDRV_PCM_FMTBIT_S16_LE | \ 45 SNDRV_PCM_FMTBIT_S16_BE | \ 46 SNDRV_PCM_FMTBIT_U16_LE | \ 47 SNDRV_PCM_FMTBIT_U16_BE | \ 48 SNDRV_PCM_FMTBIT_S24_LE | \ 49 SNDRV_PCM_FMTBIT_S24_BE | \ 50 SNDRV_PCM_FMTBIT_U24_LE | \ 51 SNDRV_PCM_FMTBIT_U24_BE | \ 52 SNDRV_PCM_FMTBIT_S32_LE | \ 53 SNDRV_PCM_FMTBIT_S32_BE | \ 54 SNDRV_PCM_FMTBIT_U32_LE | \ 55 SNDRV_PCM_FMTBIT_U32_BE) 56 struct dma_object { 57 struct snd_soc_component_driver dai; 58 dma_addr_t ssi_stx_phys; 59 dma_addr_t ssi_srx_phys; 60 unsigned int ssi_fifo_depth; 61 struct ccsr_dma_channel __iomem *channel; 62 unsigned int irq; 63 bool assigned; 64 }; 65 66 /* 67 * The number of DMA links to use. Two is the bare minimum, but if you 68 * have really small links you might need more. 69 */ 70 #define NUM_DMA_LINKS 2 71 72 /** fsl_dma_private: p-substream DMA data 73 * 74 * Each substream has a 1-to-1 association with a DMA channel. 75 * 76 * The link[] array is first because it needs to be aligned on a 32-byte 77 * boundary, so putting it first will ensure alignment without padding the 78 * structure. 79 * 80 * @link[]: array of link descriptors 81 * @dma_channel: pointer to the DMA channel's registers 82 * @irq: IRQ for this DMA channel 83 * @substream: pointer to the substream object, needed by the ISR 84 * @ssi_sxx_phys: bus address of the STX or SRX register to use 85 * @ld_buf_phys: physical address of the LD buffer 86 * @current_link: index into link[] of the link currently being processed 87 * @dma_buf_phys: physical address of the DMA buffer 88 * @dma_buf_next: physical address of the next period to process 89 * @dma_buf_end: physical address of the byte after the end of the DMA 90 * @buffer period_size: the size of a single period 91 * @num_periods: the number of periods in the DMA buffer 92 */ 93 struct fsl_dma_private { 94 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 95 struct ccsr_dma_channel __iomem *dma_channel; 96 unsigned int irq; 97 struct snd_pcm_substream *substream; 98 dma_addr_t ssi_sxx_phys; 99 unsigned int ssi_fifo_depth; 100 dma_addr_t ld_buf_phys; 101 unsigned int current_link; 102 dma_addr_t dma_buf_phys; 103 dma_addr_t dma_buf_next; 104 dma_addr_t dma_buf_end; 105 size_t period_size; 106 unsigned int num_periods; 107 }; 108 109 /** 110 * fsl_dma_hardare: define characteristics of the PCM hardware. 111 * 112 * The PCM hardware is the Freescale DMA controller. This structure defines 113 * the capabilities of that hardware. 114 * 115 * Since the sampling rate and data format are not controlled by the DMA 116 * controller, we specify no limits for those values. The only exception is 117 * period_bytes_min, which is set to a reasonably low value to prevent the 118 * DMA controller from generating too many interrupts per second. 119 * 120 * Since each link descriptor has a 32-bit byte count field, we set 121 * period_bytes_max to the largest 32-bit number. We also have no maximum 122 * number of periods. 123 * 124 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a 125 * limitation in the SSI driver requires the sample rates for playback and 126 * capture to be the same. 127 */ 128 static const struct snd_pcm_hardware fsl_dma_hardware = { 129 130 .info = SNDRV_PCM_INFO_INTERLEAVED | 131 SNDRV_PCM_INFO_MMAP | 132 SNDRV_PCM_INFO_MMAP_VALID | 133 SNDRV_PCM_INFO_JOINT_DUPLEX | 134 SNDRV_PCM_INFO_PAUSE, 135 .formats = FSLDMA_PCM_FORMATS, 136 .period_bytes_min = 512, /* A reasonable limit */ 137 .period_bytes_max = (u32) -1, 138 .periods_min = NUM_DMA_LINKS, 139 .periods_max = (unsigned int) -1, 140 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 141 }; 142 143 /** 144 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 145 * 146 * This function should be called by the ISR whenever the DMA controller 147 * halts data transfer. 148 */ 149 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 150 { 151 snd_pcm_stop_xrun(substream); 152 } 153 154 /** 155 * fsl_dma_update_pointers - update LD pointers to point to the next period 156 * 157 * As each period is completed, this function changes the the link 158 * descriptor pointers for that period to point to the next period. 159 */ 160 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 161 { 162 struct fsl_dma_link_descriptor *link = 163 &dma_private->link[dma_private->current_link]; 164 165 /* Update our link descriptors to point to the next period. On a 36-bit 166 * system, we also need to update the ESAD bits. We also set (keep) the 167 * snoop bits. See the comments in fsl_dma_hw_params() about snooping. 168 */ 169 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 170 link->source_addr = cpu_to_be32(dma_private->dma_buf_next); 171 #ifdef CONFIG_PHYS_64BIT 172 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 173 upper_32_bits(dma_private->dma_buf_next)); 174 #endif 175 } else { 176 link->dest_addr = cpu_to_be32(dma_private->dma_buf_next); 177 #ifdef CONFIG_PHYS_64BIT 178 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 179 upper_32_bits(dma_private->dma_buf_next)); 180 #endif 181 } 182 183 /* Update our variables for next time */ 184 dma_private->dma_buf_next += dma_private->period_size; 185 186 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 187 dma_private->dma_buf_next = dma_private->dma_buf_phys; 188 189 if (++dma_private->current_link >= NUM_DMA_LINKS) 190 dma_private->current_link = 0; 191 } 192 193 /** 194 * fsl_dma_isr: interrupt handler for the DMA controller 195 * 196 * @irq: IRQ of the DMA channel 197 * @dev_id: pointer to the dma_private structure for this DMA channel 198 */ 199 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 200 { 201 struct fsl_dma_private *dma_private = dev_id; 202 struct snd_pcm_substream *substream = dma_private->substream; 203 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 204 struct device *dev = rtd->dev; 205 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 206 irqreturn_t ret = IRQ_NONE; 207 u32 sr, sr2 = 0; 208 209 /* We got an interrupt, so read the status register to see what we 210 were interrupted for. 211 */ 212 sr = in_be32(&dma_channel->sr); 213 214 if (sr & CCSR_DMA_SR_TE) { 215 dev_err(dev, "dma transmit error\n"); 216 fsl_dma_abort_stream(substream); 217 sr2 |= CCSR_DMA_SR_TE; 218 ret = IRQ_HANDLED; 219 } 220 221 if (sr & CCSR_DMA_SR_CH) 222 ret = IRQ_HANDLED; 223 224 if (sr & CCSR_DMA_SR_PE) { 225 dev_err(dev, "dma programming error\n"); 226 fsl_dma_abort_stream(substream); 227 sr2 |= CCSR_DMA_SR_PE; 228 ret = IRQ_HANDLED; 229 } 230 231 if (sr & CCSR_DMA_SR_EOLNI) { 232 sr2 |= CCSR_DMA_SR_EOLNI; 233 ret = IRQ_HANDLED; 234 } 235 236 if (sr & CCSR_DMA_SR_CB) 237 ret = IRQ_HANDLED; 238 239 if (sr & CCSR_DMA_SR_EOSI) { 240 /* Tell ALSA we completed a period. */ 241 snd_pcm_period_elapsed(substream); 242 243 /* 244 * Update our link descriptors to point to the next period. We 245 * only need to do this if the number of periods is not equal to 246 * the number of links. 247 */ 248 if (dma_private->num_periods != NUM_DMA_LINKS) 249 fsl_dma_update_pointers(dma_private); 250 251 sr2 |= CCSR_DMA_SR_EOSI; 252 ret = IRQ_HANDLED; 253 } 254 255 if (sr & CCSR_DMA_SR_EOLSI) { 256 sr2 |= CCSR_DMA_SR_EOLSI; 257 ret = IRQ_HANDLED; 258 } 259 260 /* Clear the bits that we set */ 261 if (sr2) 262 out_be32(&dma_channel->sr, sr2); 263 264 return ret; 265 } 266 267 /** 268 * fsl_dma_new: initialize this PCM driver. 269 * 270 * This function is called when the codec driver calls snd_soc_new_pcms(), 271 * once for each .dai_link in the machine driver's snd_soc_card 272 * structure. 273 * 274 * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which 275 * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM 276 * is specified. Therefore, any DMA buffers we allocate will always be in low 277 * memory, but we support for 36-bit physical addresses anyway. 278 * 279 * Regardless of where the memory is actually allocated, since the device can 280 * technically DMA to any 36-bit address, we do need to set the DMA mask to 36. 281 */ 282 static int fsl_dma_new(struct snd_soc_component *component, 283 struct snd_soc_pcm_runtime *rtd) 284 { 285 struct snd_card *card = rtd->card->snd_card; 286 struct snd_pcm *pcm = rtd->pcm; 287 int ret; 288 289 ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(36)); 290 if (ret) 291 return ret; 292 293 /* Some codecs have separate DAIs for playback and capture, so we 294 * should allocate a DMA buffer only for the streams that are valid. 295 */ 296 297 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) { 298 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 299 fsl_dma_hardware.buffer_bytes_max, 300 &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer); 301 if (ret) { 302 dev_err(card->dev, "can't alloc playback dma buffer\n"); 303 return ret; 304 } 305 } 306 307 if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) { 308 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 309 fsl_dma_hardware.buffer_bytes_max, 310 &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer); 311 if (ret) { 312 dev_err(card->dev, "can't alloc capture dma buffer\n"); 313 snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer); 314 return ret; 315 } 316 } 317 318 return 0; 319 } 320 321 /** 322 * fsl_dma_open: open a new substream. 323 * 324 * Each substream has its own DMA buffer. 325 * 326 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 327 * descriptors that ping-pong from one period to the next. For example, if 328 * there are six periods and two link descriptors, this is how they look 329 * before playback starts: 330 * 331 * The last link descriptor 332 * ____________ points back to the first 333 * | | 334 * V | 335 * ___ ___ | 336 * | |->| |->| 337 * |___| |___| 338 * | | 339 * | | 340 * V V 341 * _________________________________________ 342 * | | | | | | | The DMA buffer is 343 * | | | | | | | divided into 6 parts 344 * |______|______|______|______|______|______| 345 * 346 * and here's how they look after the first period is finished playing: 347 * 348 * ____________ 349 * | | 350 * V | 351 * ___ ___ | 352 * | |->| |->| 353 * |___| |___| 354 * | | 355 * |______________ 356 * | | 357 * V V 358 * _________________________________________ 359 * | | | | | | | 360 * | | | | | | | 361 * |______|______|______|______|______|______| 362 * 363 * The first link descriptor now points to the third period. The DMA 364 * controller is currently playing the second period. When it finishes, it 365 * will jump back to the first descriptor and play the third period. 366 * 367 * There are four reasons we do this: 368 * 369 * 1. The only way to get the DMA controller to automatically restart the 370 * transfer when it gets to the end of the buffer is to use chaining 371 * mode. Basic direct mode doesn't offer that feature. 372 * 2. We need to receive an interrupt at the end of every period. The DMA 373 * controller can generate an interrupt at the end of every link transfer 374 * (aka segment). Making each period into a DMA segment will give us the 375 * interrupts we need. 376 * 3. By creating only two link descriptors, regardless of the number of 377 * periods, we do not need to reallocate the link descriptors if the 378 * number of periods changes. 379 * 4. All of the audio data is still stored in a single, contiguous DMA 380 * buffer, which is what ALSA expects. We're just dividing it into 381 * contiguous parts, and creating a link descriptor for each one. 382 */ 383 static int fsl_dma_open(struct snd_soc_component *component, 384 struct snd_pcm_substream *substream) 385 { 386 struct snd_pcm_runtime *runtime = substream->runtime; 387 struct device *dev = component->dev; 388 struct dma_object *dma = 389 container_of(component->driver, struct dma_object, dai); 390 struct fsl_dma_private *dma_private; 391 struct ccsr_dma_channel __iomem *dma_channel; 392 dma_addr_t ld_buf_phys; 393 u64 temp_link; /* Pointer to next link descriptor */ 394 u32 mr; 395 unsigned int channel; 396 int ret = 0; 397 unsigned int i; 398 399 /* 400 * Reject any DMA buffer whose size is not a multiple of the period 401 * size. We need to make sure that the DMA buffer can be evenly divided 402 * into periods. 403 */ 404 ret = snd_pcm_hw_constraint_integer(runtime, 405 SNDRV_PCM_HW_PARAM_PERIODS); 406 if (ret < 0) { 407 dev_err(dev, "invalid buffer size\n"); 408 return ret; 409 } 410 411 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 412 413 if (dma->assigned) { 414 dev_err(dev, "dma channel already assigned\n"); 415 return -EBUSY; 416 } 417 418 dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private), 419 &ld_buf_phys, GFP_KERNEL); 420 if (!dma_private) { 421 dev_err(dev, "can't allocate dma private data\n"); 422 return -ENOMEM; 423 } 424 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 425 dma_private->ssi_sxx_phys = dma->ssi_stx_phys; 426 else 427 dma_private->ssi_sxx_phys = dma->ssi_srx_phys; 428 429 dma_private->ssi_fifo_depth = dma->ssi_fifo_depth; 430 dma_private->dma_channel = dma->channel; 431 dma_private->irq = dma->irq; 432 dma_private->substream = substream; 433 dma_private->ld_buf_phys = ld_buf_phys; 434 dma_private->dma_buf_phys = substream->dma_buffer.addr; 435 436 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio", 437 dma_private); 438 if (ret) { 439 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 440 dma_private->irq, ret); 441 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 442 dma_private, dma_private->ld_buf_phys); 443 return ret; 444 } 445 446 dma->assigned = true; 447 448 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 449 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 450 runtime->private_data = dma_private; 451 452 /* Program the fixed DMA controller parameters */ 453 454 dma_channel = dma_private->dma_channel; 455 456 temp_link = dma_private->ld_buf_phys + 457 sizeof(struct fsl_dma_link_descriptor); 458 459 for (i = 0; i < NUM_DMA_LINKS; i++) { 460 dma_private->link[i].next = cpu_to_be64(temp_link); 461 462 temp_link += sizeof(struct fsl_dma_link_descriptor); 463 } 464 /* The last link descriptor points to the first */ 465 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 466 467 /* Tell the DMA controller where the first link descriptor is */ 468 out_be32(&dma_channel->clndar, 469 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 470 out_be32(&dma_channel->eclndar, 471 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 472 473 /* The manual says the BCR must be clear before enabling EMP */ 474 out_be32(&dma_channel->bcr, 0); 475 476 /* 477 * Program the mode register for interrupts, external master control, 478 * and source/destination hold. Also clear the Channel Abort bit. 479 */ 480 mr = in_be32(&dma_channel->mr) & 481 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 482 483 /* 484 * We want External Master Start and External Master Pause enabled, 485 * because the SSI is controlling the DMA controller. We want the DMA 486 * controller to be set up in advance, and then we signal only the SSI 487 * to start transferring. 488 * 489 * We want End-Of-Segment Interrupts enabled, because this will generate 490 * an interrupt at the end of each segment (each link descriptor 491 * represents one segment). Each DMA segment is the same thing as an 492 * ALSA period, so this is how we get an interrupt at the end of every 493 * period. 494 * 495 * We want Error Interrupt enabled, so that we can get an error if 496 * the DMA controller is mis-programmed somehow. 497 */ 498 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 499 CCSR_DMA_MR_EMS_EN; 500 501 /* For playback, we want the destination address to be held. For 502 capture, set the source address to be held. */ 503 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 504 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 505 506 out_be32(&dma_channel->mr, mr); 507 508 return 0; 509 } 510 511 /** 512 * fsl_dma_hw_params: continue initializing the DMA links 513 * 514 * This function obtains hardware parameters about the opened stream and 515 * programs the DMA controller accordingly. 516 * 517 * One drawback of big-endian is that when copying integers of different 518 * sizes to a fixed-sized register, the address to which the integer must be 519 * copied is dependent on the size of the integer. 520 * 521 * For example, if P is the address of a 32-bit register, and X is a 32-bit 522 * integer, then X should be copied to address P. However, if X is a 16-bit 523 * integer, then it should be copied to P+2. If X is an 8-bit register, 524 * then it should be copied to P+3. 525 * 526 * So for playback of 8-bit samples, the DMA controller must transfer single 527 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 528 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 529 * 530 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 531 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 532 * and 8 bytes at a time). So we do not support packed 24-bit samples. 533 * 24-bit data must be padded to 32 bits. 534 */ 535 static int fsl_dma_hw_params(struct snd_soc_component *component, 536 struct snd_pcm_substream *substream, 537 struct snd_pcm_hw_params *hw_params) 538 { 539 struct snd_pcm_runtime *runtime = substream->runtime; 540 struct fsl_dma_private *dma_private = runtime->private_data; 541 struct device *dev = component->dev; 542 543 /* Number of bits per sample */ 544 unsigned int sample_bits = 545 snd_pcm_format_physical_width(params_format(hw_params)); 546 547 /* Number of bytes per frame */ 548 unsigned int sample_bytes = sample_bits / 8; 549 550 /* Bus address of SSI STX register */ 551 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; 552 553 /* Size of the DMA buffer, in bytes */ 554 size_t buffer_size = params_buffer_bytes(hw_params); 555 556 /* Number of bytes per period */ 557 size_t period_size = params_period_bytes(hw_params); 558 559 /* Pointer to next period */ 560 dma_addr_t temp_addr = substream->dma_buffer.addr; 561 562 /* Pointer to DMA controller */ 563 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 564 565 u32 mr; /* DMA Mode Register */ 566 567 unsigned int i; 568 569 /* Initialize our DMA tracking variables */ 570 dma_private->period_size = period_size; 571 dma_private->num_periods = params_periods(hw_params); 572 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 573 dma_private->dma_buf_next = dma_private->dma_buf_phys + 574 (NUM_DMA_LINKS * period_size); 575 576 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 577 /* This happens if the number of periods == NUM_DMA_LINKS */ 578 dma_private->dma_buf_next = dma_private->dma_buf_phys; 579 580 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 581 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 582 583 /* Due to a quirk of the SSI's STX register, the target address 584 * for the DMA operations depends on the sample size. So we calculate 585 * that offset here. While we're at it, also tell the DMA controller 586 * how much data to transfer per sample. 587 */ 588 switch (sample_bits) { 589 case 8: 590 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 591 ssi_sxx_phys += 3; 592 break; 593 case 16: 594 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 595 ssi_sxx_phys += 2; 596 break; 597 case 32: 598 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 599 break; 600 default: 601 /* We should never get here */ 602 dev_err(dev, "unsupported sample size %u\n", sample_bits); 603 return -EINVAL; 604 } 605 606 /* 607 * BWC determines how many bytes are sent/received before the DMA 608 * controller checks the SSI to see if it needs to stop. BWC should 609 * always be a multiple of the frame size, so that we always transmit 610 * whole frames. Each frame occupies two slots in the FIFO. The 611 * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two 612 * (MR[BWC] can only represent even powers of two). 613 * 614 * To simplify the process, we set BWC to the largest value that is 615 * less than or equal to the FIFO watermark. For playback, this ensures 616 * that we transfer the maximum amount without overrunning the FIFO. 617 * For capture, this ensures that we transfer the maximum amount without 618 * underrunning the FIFO. 619 * 620 * f = SSI FIFO depth 621 * w = SSI watermark value (which equals f - 2) 622 * b = DMA bandwidth count (in bytes) 623 * s = sample size (in bytes, which equals frame_size * 2) 624 * 625 * For playback, we never transmit more than the transmit FIFO 626 * watermark, otherwise we might write more data than the FIFO can hold. 627 * The watermark is equal to the FIFO depth minus two. 628 * 629 * For capture, two equations must hold: 630 * w > f - (b / s) 631 * w >= b / s 632 * 633 * So, b > 2 * s, but b must also be <= s * w. To simplify, we set 634 * b = s * w, which is equal to 635 * (dma_private->ssi_fifo_depth - 2) * sample_bytes. 636 */ 637 mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes); 638 639 out_be32(&dma_channel->mr, mr); 640 641 for (i = 0; i < NUM_DMA_LINKS; i++) { 642 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 643 644 link->count = cpu_to_be32(period_size); 645 646 /* The snoop bit tells the DMA controller whether it should tell 647 * the ECM to snoop during a read or write to an address. For 648 * audio, we use DMA to transfer data between memory and an I/O 649 * device (the SSI's STX0 or SRX0 register). Snooping is only 650 * needed if there is a cache, so we need to snoop memory 651 * addresses only. For playback, that means we snoop the source 652 * but not the destination. For capture, we snoop the 653 * destination but not the source. 654 * 655 * Note that failing to snoop properly is unlikely to cause 656 * cache incoherency if the period size is larger than the 657 * size of L1 cache. This is because filling in one period will 658 * flush out the data for the previous period. So if you 659 * increased period_bytes_min to a large enough size, you might 660 * get more performance by not snooping, and you'll still be 661 * okay. You'll need to update fsl_dma_update_pointers() also. 662 */ 663 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 664 link->source_addr = cpu_to_be32(temp_addr); 665 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 666 upper_32_bits(temp_addr)); 667 668 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 669 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 670 upper_32_bits(ssi_sxx_phys)); 671 } else { 672 link->source_addr = cpu_to_be32(ssi_sxx_phys); 673 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 674 upper_32_bits(ssi_sxx_phys)); 675 676 link->dest_addr = cpu_to_be32(temp_addr); 677 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 678 upper_32_bits(temp_addr)); 679 } 680 681 temp_addr += period_size; 682 } 683 684 return 0; 685 } 686 687 /** 688 * fsl_dma_pointer: determine the current position of the DMA transfer 689 * 690 * This function is called by ALSA when ALSA wants to know where in the 691 * stream buffer the hardware currently is. 692 * 693 * For playback, the SAR register contains the physical address of the most 694 * recent DMA transfer. For capture, the value is in the DAR register. 695 * 696 * The base address of the buffer is stored in the source_addr field of the 697 * first link descriptor. 698 */ 699 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_soc_component *component, 700 struct snd_pcm_substream *substream) 701 { 702 struct snd_pcm_runtime *runtime = substream->runtime; 703 struct fsl_dma_private *dma_private = runtime->private_data; 704 struct device *dev = component->dev; 705 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 706 dma_addr_t position; 707 snd_pcm_uframes_t frames; 708 709 /* Obtain the current DMA pointer, but don't read the ESAD bits if we 710 * only have 32-bit DMA addresses. This function is typically called 711 * in interrupt context, so we need to optimize it. 712 */ 713 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 714 position = in_be32(&dma_channel->sar); 715 #ifdef CONFIG_PHYS_64BIT 716 position |= (u64)(in_be32(&dma_channel->satr) & 717 CCSR_DMA_ATR_ESAD_MASK) << 32; 718 #endif 719 } else { 720 position = in_be32(&dma_channel->dar); 721 #ifdef CONFIG_PHYS_64BIT 722 position |= (u64)(in_be32(&dma_channel->datr) & 723 CCSR_DMA_ATR_ESAD_MASK) << 32; 724 #endif 725 } 726 727 /* 728 * When capture is started, the SSI immediately starts to fill its FIFO. 729 * This means that the DMA controller is not started until the FIFO is 730 * full. However, ALSA calls this function before that happens, when 731 * MR.DAR is still zero. In this case, just return zero to indicate 732 * that nothing has been received yet. 733 */ 734 if (!position) 735 return 0; 736 737 if ((position < dma_private->dma_buf_phys) || 738 (position > dma_private->dma_buf_end)) { 739 dev_err(dev, "dma pointer is out of range, halting stream\n"); 740 return SNDRV_PCM_POS_XRUN; 741 } 742 743 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 744 745 /* 746 * If the current address is just past the end of the buffer, wrap it 747 * around. 748 */ 749 if (frames == runtime->buffer_size) 750 frames = 0; 751 752 return frames; 753 } 754 755 /** 756 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 757 * 758 * Release the resources allocated in fsl_dma_hw_params() and de-program the 759 * registers. 760 * 761 * This function can be called multiple times. 762 */ 763 static int fsl_dma_hw_free(struct snd_soc_component *component, 764 struct snd_pcm_substream *substream) 765 { 766 struct snd_pcm_runtime *runtime = substream->runtime; 767 struct fsl_dma_private *dma_private = runtime->private_data; 768 769 if (dma_private) { 770 struct ccsr_dma_channel __iomem *dma_channel; 771 772 dma_channel = dma_private->dma_channel; 773 774 /* Stop the DMA */ 775 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 776 out_be32(&dma_channel->mr, 0); 777 778 /* Reset all the other registers */ 779 out_be32(&dma_channel->sr, -1); 780 out_be32(&dma_channel->clndar, 0); 781 out_be32(&dma_channel->eclndar, 0); 782 out_be32(&dma_channel->satr, 0); 783 out_be32(&dma_channel->sar, 0); 784 out_be32(&dma_channel->datr, 0); 785 out_be32(&dma_channel->dar, 0); 786 out_be32(&dma_channel->bcr, 0); 787 out_be32(&dma_channel->nlndar, 0); 788 out_be32(&dma_channel->enlndar, 0); 789 } 790 791 return 0; 792 } 793 794 /** 795 * fsl_dma_close: close the stream. 796 */ 797 static int fsl_dma_close(struct snd_soc_component *component, 798 struct snd_pcm_substream *substream) 799 { 800 struct snd_pcm_runtime *runtime = substream->runtime; 801 struct fsl_dma_private *dma_private = runtime->private_data; 802 struct device *dev = component->dev; 803 struct dma_object *dma = 804 container_of(component->driver, struct dma_object, dai); 805 806 if (dma_private) { 807 if (dma_private->irq) 808 free_irq(dma_private->irq, dma_private); 809 810 /* Deallocate the fsl_dma_private structure */ 811 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 812 dma_private, dma_private->ld_buf_phys); 813 substream->runtime->private_data = NULL; 814 } 815 816 dma->assigned = false; 817 818 return 0; 819 } 820 821 /* 822 * Remove this PCM driver. 823 */ 824 static void fsl_dma_free_dma_buffers(struct snd_soc_component *component, 825 struct snd_pcm *pcm) 826 { 827 struct snd_pcm_substream *substream; 828 unsigned int i; 829 830 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 831 substream = pcm->streams[i].substream; 832 if (substream) { 833 snd_dma_free_pages(&substream->dma_buffer); 834 substream->dma_buffer.area = NULL; 835 substream->dma_buffer.addr = 0; 836 } 837 } 838 } 839 840 /** 841 * find_ssi_node -- returns the SSI node that points to its DMA channel node 842 * 843 * Although this DMA driver attempts to operate independently of the other 844 * devices, it still needs to determine some information about the SSI device 845 * that it's working with. Unfortunately, the device tree does not contain 846 * a pointer from the DMA channel node to the SSI node -- the pointer goes the 847 * other way. So we need to scan the device tree for SSI nodes until we find 848 * the one that points to the given DMA channel node. It's ugly, but at least 849 * it's contained in this one function. 850 */ 851 static struct device_node *find_ssi_node(struct device_node *dma_channel_np) 852 { 853 struct device_node *ssi_np, *np; 854 855 for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") { 856 /* Check each DMA phandle to see if it points to us. We 857 * assume that device_node pointers are a valid comparison. 858 */ 859 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0); 860 of_node_put(np); 861 if (np == dma_channel_np) 862 return ssi_np; 863 864 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0); 865 of_node_put(np); 866 if (np == dma_channel_np) 867 return ssi_np; 868 } 869 870 return NULL; 871 } 872 873 static int fsl_soc_dma_probe(struct platform_device *pdev) 874 { 875 struct dma_object *dma; 876 struct device_node *np = pdev->dev.of_node; 877 struct device_node *ssi_np; 878 struct resource res; 879 const uint32_t *iprop; 880 int ret; 881 882 /* Find the SSI node that points to us. */ 883 ssi_np = find_ssi_node(np); 884 if (!ssi_np) { 885 dev_err(&pdev->dev, "cannot find parent SSI node\n"); 886 return -ENODEV; 887 } 888 889 ret = of_address_to_resource(ssi_np, 0, &res); 890 if (ret) { 891 dev_err(&pdev->dev, "could not determine resources for %pOF\n", 892 ssi_np); 893 of_node_put(ssi_np); 894 return ret; 895 } 896 897 dma = kzalloc(sizeof(*dma), GFP_KERNEL); 898 if (!dma) { 899 of_node_put(ssi_np); 900 return -ENOMEM; 901 } 902 903 dma->dai.name = DRV_NAME; 904 dma->dai.open = fsl_dma_open; 905 dma->dai.close = fsl_dma_close; 906 dma->dai.hw_params = fsl_dma_hw_params; 907 dma->dai.hw_free = fsl_dma_hw_free; 908 dma->dai.pointer = fsl_dma_pointer; 909 dma->dai.pcm_construct = fsl_dma_new; 910 dma->dai.pcm_destruct = fsl_dma_free_dma_buffers; 911 912 /* Store the SSI-specific information that we need */ 913 dma->ssi_stx_phys = res.start + REG_SSI_STX0; 914 dma->ssi_srx_phys = res.start + REG_SSI_SRX0; 915 916 iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL); 917 if (iprop) 918 dma->ssi_fifo_depth = be32_to_cpup(iprop); 919 else 920 /* Older 8610 DTs didn't have the fifo-depth property */ 921 dma->ssi_fifo_depth = 8; 922 923 of_node_put(ssi_np); 924 925 ret = devm_snd_soc_register_component(&pdev->dev, &dma->dai, NULL, 0); 926 if (ret) { 927 dev_err(&pdev->dev, "could not register platform\n"); 928 kfree(dma); 929 return ret; 930 } 931 932 dma->channel = of_iomap(np, 0); 933 dma->irq = irq_of_parse_and_map(np, 0); 934 935 dev_set_drvdata(&pdev->dev, dma); 936 937 return 0; 938 } 939 940 static int fsl_soc_dma_remove(struct platform_device *pdev) 941 { 942 struct dma_object *dma = dev_get_drvdata(&pdev->dev); 943 944 iounmap(dma->channel); 945 irq_dispose_mapping(dma->irq); 946 kfree(dma); 947 948 return 0; 949 } 950 951 static const struct of_device_id fsl_soc_dma_ids[] = { 952 { .compatible = "fsl,ssi-dma-channel", }, 953 {} 954 }; 955 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids); 956 957 static struct platform_driver fsl_soc_dma_driver = { 958 .driver = { 959 .name = "fsl-pcm-audio", 960 .of_match_table = fsl_soc_dma_ids, 961 }, 962 .probe = fsl_soc_dma_probe, 963 .remove = fsl_soc_dma_remove, 964 }; 965 966 module_platform_driver(fsl_soc_dma_driver); 967 968 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 969 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver"); 970 MODULE_LICENSE("GPL v2"); 971