1 /* 2 * Freescale DMA ALSA SoC PCM driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed 7 * under the terms of the GNU General Public License version 2. This 8 * program is licensed "as is" without any warranty of any kind, whether 9 * express or implied. 10 * 11 * This driver implements ASoC support for the Elo DMA controller, which is 12 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 13 * the PCM driver is what handles the DMA buffer. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/interrupt.h> 21 #include <linux/delay.h> 22 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 28 #include <asm/io.h> 29 30 #include "fsl_dma.h" 31 32 /* 33 * The formats that the DMA controller supports, which is anything 34 * that is 8, 16, or 32 bits. 35 */ 36 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 37 SNDRV_PCM_FMTBIT_U8 | \ 38 SNDRV_PCM_FMTBIT_S16_LE | \ 39 SNDRV_PCM_FMTBIT_S16_BE | \ 40 SNDRV_PCM_FMTBIT_U16_LE | \ 41 SNDRV_PCM_FMTBIT_U16_BE | \ 42 SNDRV_PCM_FMTBIT_S24_LE | \ 43 SNDRV_PCM_FMTBIT_S24_BE | \ 44 SNDRV_PCM_FMTBIT_U24_LE | \ 45 SNDRV_PCM_FMTBIT_U24_BE | \ 46 SNDRV_PCM_FMTBIT_S32_LE | \ 47 SNDRV_PCM_FMTBIT_S32_BE | \ 48 SNDRV_PCM_FMTBIT_U32_LE | \ 49 SNDRV_PCM_FMTBIT_U32_BE) 50 51 #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ 52 SNDRV_PCM_RATE_CONTINUOUS) 53 54 /* DMA global data. This structure is used by fsl_dma_open() to determine 55 * which DMA channels to assign to a substream. Unfortunately, ASoC V1 does 56 * not allow the machine driver to provide this information to the PCM 57 * driver in advance, and there's no way to differentiate between the two 58 * DMA controllers. So for now, this driver only supports one SSI device 59 * using two DMA channels. We cannot support multiple DMA devices. 60 * 61 * ssi_stx_phys: bus address of SSI STX register 62 * ssi_srx_phys: bus address of SSI SRX register 63 * dma_channel: pointer to the DMA channel's registers 64 * irq: IRQ for this DMA channel 65 * assigned: set to 1 if that DMA channel is assigned to a substream 66 */ 67 static struct { 68 dma_addr_t ssi_stx_phys; 69 dma_addr_t ssi_srx_phys; 70 struct ccsr_dma_channel __iomem *dma_channel[2]; 71 unsigned int irq[2]; 72 unsigned int assigned[2]; 73 } dma_global_data; 74 75 /* 76 * The number of DMA links to use. Two is the bare minimum, but if you 77 * have really small links you might need more. 78 */ 79 #define NUM_DMA_LINKS 2 80 81 /** fsl_dma_private: p-substream DMA data 82 * 83 * Each substream has a 1-to-1 association with a DMA channel. 84 * 85 * The link[] array is first because it needs to be aligned on a 32-byte 86 * boundary, so putting it first will ensure alignment without padding the 87 * structure. 88 * 89 * @link[]: array of link descriptors 90 * @controller_id: which DMA controller (0, 1, ...) 91 * @channel_id: which DMA channel on the controller (0, 1, 2, ...) 92 * @dma_channel: pointer to the DMA channel's registers 93 * @irq: IRQ for this DMA channel 94 * @substream: pointer to the substream object, needed by the ISR 95 * @ssi_sxx_phys: bus address of the STX or SRX register to use 96 * @ld_buf_phys: physical address of the LD buffer 97 * @current_link: index into link[] of the link currently being processed 98 * @dma_buf_phys: physical address of the DMA buffer 99 * @dma_buf_next: physical address of the next period to process 100 * @dma_buf_end: physical address of the byte after the end of the DMA 101 * @buffer period_size: the size of a single period 102 * @num_periods: the number of periods in the DMA buffer 103 */ 104 struct fsl_dma_private { 105 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 106 unsigned int controller_id; 107 unsigned int channel_id; 108 struct ccsr_dma_channel __iomem *dma_channel; 109 unsigned int irq; 110 struct snd_pcm_substream *substream; 111 dma_addr_t ssi_sxx_phys; 112 dma_addr_t ld_buf_phys; 113 unsigned int current_link; 114 dma_addr_t dma_buf_phys; 115 dma_addr_t dma_buf_next; 116 dma_addr_t dma_buf_end; 117 size_t period_size; 118 unsigned int num_periods; 119 }; 120 121 /** 122 * fsl_dma_hardare: define characteristics of the PCM hardware. 123 * 124 * The PCM hardware is the Freescale DMA controller. This structure defines 125 * the capabilities of that hardware. 126 * 127 * Since the sampling rate and data format are not controlled by the DMA 128 * controller, we specify no limits for those values. The only exception is 129 * period_bytes_min, which is set to a reasonably low value to prevent the 130 * DMA controller from generating too many interrupts per second. 131 * 132 * Since each link descriptor has a 32-bit byte count field, we set 133 * period_bytes_max to the largest 32-bit number. We also have no maximum 134 * number of periods. 135 * 136 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a 137 * limitation in the SSI driver requires the sample rates for playback and 138 * capture to be the same. 139 */ 140 static const struct snd_pcm_hardware fsl_dma_hardware = { 141 142 .info = SNDRV_PCM_INFO_INTERLEAVED | 143 SNDRV_PCM_INFO_MMAP | 144 SNDRV_PCM_INFO_MMAP_VALID | 145 SNDRV_PCM_INFO_JOINT_DUPLEX, 146 .formats = FSLDMA_PCM_FORMATS, 147 .rates = FSLDMA_PCM_RATES, 148 .rate_min = 5512, 149 .rate_max = 192000, 150 .period_bytes_min = 512, /* A reasonable limit */ 151 .period_bytes_max = (u32) -1, 152 .periods_min = NUM_DMA_LINKS, 153 .periods_max = (unsigned int) -1, 154 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 155 }; 156 157 /** 158 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 159 * 160 * This function should be called by the ISR whenever the DMA controller 161 * halts data transfer. 162 */ 163 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 164 { 165 unsigned long flags; 166 167 snd_pcm_stream_lock_irqsave(substream, flags); 168 169 if (snd_pcm_running(substream)) 170 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); 171 172 snd_pcm_stream_unlock_irqrestore(substream, flags); 173 } 174 175 /** 176 * fsl_dma_update_pointers - update LD pointers to point to the next period 177 * 178 * As each period is completed, this function changes the the link 179 * descriptor pointers for that period to point to the next period. 180 */ 181 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 182 { 183 struct fsl_dma_link_descriptor *link = 184 &dma_private->link[dma_private->current_link]; 185 186 /* Update our link descriptors to point to the next period */ 187 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 188 link->source_addr = 189 cpu_to_be32(dma_private->dma_buf_next); 190 else 191 link->dest_addr = 192 cpu_to_be32(dma_private->dma_buf_next); 193 194 /* Update our variables for next time */ 195 dma_private->dma_buf_next += dma_private->period_size; 196 197 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 198 dma_private->dma_buf_next = dma_private->dma_buf_phys; 199 200 if (++dma_private->current_link >= NUM_DMA_LINKS) 201 dma_private->current_link = 0; 202 } 203 204 /** 205 * fsl_dma_isr: interrupt handler for the DMA controller 206 * 207 * @irq: IRQ of the DMA channel 208 * @dev_id: pointer to the dma_private structure for this DMA channel 209 */ 210 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 211 { 212 struct fsl_dma_private *dma_private = dev_id; 213 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 214 irqreturn_t ret = IRQ_NONE; 215 u32 sr, sr2 = 0; 216 217 /* We got an interrupt, so read the status register to see what we 218 were interrupted for. 219 */ 220 sr = in_be32(&dma_channel->sr); 221 222 if (sr & CCSR_DMA_SR_TE) { 223 dev_err(dma_private->substream->pcm->card->dev, 224 "DMA transmit error (controller=%u channel=%u irq=%u\n", 225 dma_private->controller_id, 226 dma_private->channel_id, irq); 227 fsl_dma_abort_stream(dma_private->substream); 228 sr2 |= CCSR_DMA_SR_TE; 229 ret = IRQ_HANDLED; 230 } 231 232 if (sr & CCSR_DMA_SR_CH) 233 ret = IRQ_HANDLED; 234 235 if (sr & CCSR_DMA_SR_PE) { 236 dev_err(dma_private->substream->pcm->card->dev, 237 "DMA%u programming error (channel=%u irq=%u)\n", 238 dma_private->controller_id, 239 dma_private->channel_id, irq); 240 fsl_dma_abort_stream(dma_private->substream); 241 sr2 |= CCSR_DMA_SR_PE; 242 ret = IRQ_HANDLED; 243 } 244 245 if (sr & CCSR_DMA_SR_EOLNI) { 246 sr2 |= CCSR_DMA_SR_EOLNI; 247 ret = IRQ_HANDLED; 248 } 249 250 if (sr & CCSR_DMA_SR_CB) 251 ret = IRQ_HANDLED; 252 253 if (sr & CCSR_DMA_SR_EOSI) { 254 struct snd_pcm_substream *substream = dma_private->substream; 255 256 /* Tell ALSA we completed a period. */ 257 snd_pcm_period_elapsed(substream); 258 259 /* 260 * Update our link descriptors to point to the next period. We 261 * only need to do this if the number of periods is not equal to 262 * the number of links. 263 */ 264 if (dma_private->num_periods != NUM_DMA_LINKS) 265 fsl_dma_update_pointers(dma_private); 266 267 sr2 |= CCSR_DMA_SR_EOSI; 268 ret = IRQ_HANDLED; 269 } 270 271 if (sr & CCSR_DMA_SR_EOLSI) { 272 sr2 |= CCSR_DMA_SR_EOLSI; 273 ret = IRQ_HANDLED; 274 } 275 276 /* Clear the bits that we set */ 277 if (sr2) 278 out_be32(&dma_channel->sr, sr2); 279 280 return ret; 281 } 282 283 /** 284 * fsl_dma_new: initialize this PCM driver. 285 * 286 * This function is called when the codec driver calls snd_soc_new_pcms(), 287 * once for each .dai_link in the machine driver's snd_soc_machine 288 * structure. 289 */ 290 static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai, 291 struct snd_pcm *pcm) 292 { 293 static u64 fsl_dma_dmamask = DMA_BIT_MASK(32); 294 int ret; 295 296 if (!card->dev->dma_mask) 297 card->dev->dma_mask = &fsl_dma_dmamask; 298 299 if (!card->dev->coherent_dma_mask) 300 card->dev->coherent_dma_mask = fsl_dma_dmamask; 301 302 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->dev, 303 fsl_dma_hardware.buffer_bytes_max, 304 &pcm->streams[0].substream->dma_buffer); 305 if (ret) { 306 dev_err(card->dev, 307 "Can't allocate playback DMA buffer (size=%u)\n", 308 fsl_dma_hardware.buffer_bytes_max); 309 return -ENOMEM; 310 } 311 312 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->dev, 313 fsl_dma_hardware.buffer_bytes_max, 314 &pcm->streams[1].substream->dma_buffer); 315 if (ret) { 316 snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer); 317 dev_err(card->dev, 318 "Can't allocate capture DMA buffer (size=%u)\n", 319 fsl_dma_hardware.buffer_bytes_max); 320 return -ENOMEM; 321 } 322 323 return 0; 324 } 325 326 /** 327 * fsl_dma_open: open a new substream. 328 * 329 * Each substream has its own DMA buffer. 330 */ 331 static int fsl_dma_open(struct snd_pcm_substream *substream) 332 { 333 struct snd_pcm_runtime *runtime = substream->runtime; 334 struct fsl_dma_private *dma_private; 335 dma_addr_t ld_buf_phys; 336 unsigned int channel; 337 int ret = 0; 338 339 /* 340 * Reject any DMA buffer whose size is not a multiple of the period 341 * size. We need to make sure that the DMA buffer can be evenly divided 342 * into periods. 343 */ 344 ret = snd_pcm_hw_constraint_integer(runtime, 345 SNDRV_PCM_HW_PARAM_PERIODS); 346 if (ret < 0) { 347 dev_err(substream->pcm->card->dev, "invalid buffer size\n"); 348 return ret; 349 } 350 351 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 352 353 if (dma_global_data.assigned[channel]) { 354 dev_err(substream->pcm->card->dev, 355 "DMA channel already assigned\n"); 356 return -EBUSY; 357 } 358 359 dma_private = dma_alloc_coherent(substream->pcm->dev, 360 sizeof(struct fsl_dma_private), &ld_buf_phys, GFP_KERNEL); 361 if (!dma_private) { 362 dev_err(substream->pcm->card->dev, 363 "can't allocate DMA private data\n"); 364 return -ENOMEM; 365 } 366 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 367 dma_private->ssi_sxx_phys = dma_global_data.ssi_stx_phys; 368 else 369 dma_private->ssi_sxx_phys = dma_global_data.ssi_srx_phys; 370 371 dma_private->dma_channel = dma_global_data.dma_channel[channel]; 372 dma_private->irq = dma_global_data.irq[channel]; 373 dma_private->substream = substream; 374 dma_private->ld_buf_phys = ld_buf_phys; 375 dma_private->dma_buf_phys = substream->dma_buffer.addr; 376 377 /* We only support one DMA controller for now */ 378 dma_private->controller_id = 0; 379 dma_private->channel_id = channel; 380 381 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private); 382 if (ret) { 383 dev_err(substream->pcm->card->dev, 384 "can't register ISR for IRQ %u (ret=%i)\n", 385 dma_private->irq, ret); 386 dma_free_coherent(substream->pcm->dev, 387 sizeof(struct fsl_dma_private), 388 dma_private, dma_private->ld_buf_phys); 389 return ret; 390 } 391 392 dma_global_data.assigned[channel] = 1; 393 394 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 395 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 396 runtime->private_data = dma_private; 397 398 return 0; 399 } 400 401 /** 402 * fsl_dma_hw_params: allocate the DMA buffer and the DMA link descriptors. 403 * 404 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 405 * descriptors that ping-pong from one period to the next. For example, if 406 * there are six periods and two link descriptors, this is how they look 407 * before playback starts: 408 * 409 * The last link descriptor 410 * ____________ points back to the first 411 * | | 412 * V | 413 * ___ ___ | 414 * | |->| |->| 415 * |___| |___| 416 * | | 417 * | | 418 * V V 419 * _________________________________________ 420 * | | | | | | | The DMA buffer is 421 * | | | | | | | divided into 6 parts 422 * |______|______|______|______|______|______| 423 * 424 * and here's how they look after the first period is finished playing: 425 * 426 * ____________ 427 * | | 428 * V | 429 * ___ ___ | 430 * | |->| |->| 431 * |___| |___| 432 * | | 433 * |______________ 434 * | | 435 * V V 436 * _________________________________________ 437 * | | | | | | | 438 * | | | | | | | 439 * |______|______|______|______|______|______| 440 * 441 * The first link descriptor now points to the third period. The DMA 442 * controller is currently playing the second period. When it finishes, it 443 * will jump back to the first descriptor and play the third period. 444 * 445 * There are four reasons we do this: 446 * 447 * 1. The only way to get the DMA controller to automatically restart the 448 * transfer when it gets to the end of the buffer is to use chaining 449 * mode. Basic direct mode doesn't offer that feature. 450 * 2. We need to receive an interrupt at the end of every period. The DMA 451 * controller can generate an interrupt at the end of every link transfer 452 * (aka segment). Making each period into a DMA segment will give us the 453 * interrupts we need. 454 * 3. By creating only two link descriptors, regardless of the number of 455 * periods, we do not need to reallocate the link descriptors if the 456 * number of periods changes. 457 * 4. All of the audio data is still stored in a single, contiguous DMA 458 * buffer, which is what ALSA expects. We're just dividing it into 459 * contiguous parts, and creating a link descriptor for each one. 460 * 461 * Note that due to a quirk of the SSI's STX register, the target address 462 * for the DMA operations depends on the sample size. So we don't program 463 * the dest_addr (for playback -- source_addr for capture) fields in the 464 * link descriptors here. We do that in fsl_dma_prepare() 465 */ 466 static int fsl_dma_hw_params(struct snd_pcm_substream *substream, 467 struct snd_pcm_hw_params *hw_params) 468 { 469 struct snd_pcm_runtime *runtime = substream->runtime; 470 struct fsl_dma_private *dma_private = runtime->private_data; 471 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 472 473 dma_addr_t temp_addr; /* Pointer to next period */ 474 u64 temp_link; /* Pointer to next link descriptor */ 475 u32 mr; /* Temporary variable for MR register */ 476 477 unsigned int i; 478 479 /* Get all the parameters we need */ 480 size_t buffer_size = params_buffer_bytes(hw_params); 481 size_t period_size = params_period_bytes(hw_params); 482 483 /* Initialize our DMA tracking variables */ 484 dma_private->period_size = period_size; 485 dma_private->num_periods = params_periods(hw_params); 486 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 487 dma_private->dma_buf_next = dma_private->dma_buf_phys + 488 (NUM_DMA_LINKS * period_size); 489 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 490 dma_private->dma_buf_next = dma_private->dma_buf_phys; 491 492 /* 493 * Initialize each link descriptor. 494 * 495 * The actual address in STX0 (destination for playback, source for 496 * capture) is based on the sample size, but we don't know the sample 497 * size in this function, so we'll have to adjust that later. See 498 * comments in fsl_dma_prepare(). 499 * 500 * The DMA controller does not have a cache, so the CPU does not 501 * need to tell it to flush its cache. However, the DMA 502 * controller does need to tell the CPU to flush its cache. 503 * That's what the SNOOP bit does. 504 * 505 * Also, even though the DMA controller supports 36-bit addressing, for 506 * simplicity we currently support only 32-bit addresses for the audio 507 * buffer itself. 508 */ 509 temp_addr = substream->dma_buffer.addr; 510 temp_link = dma_private->ld_buf_phys + 511 sizeof(struct fsl_dma_link_descriptor); 512 513 for (i = 0; i < NUM_DMA_LINKS; i++) { 514 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 515 516 link->count = cpu_to_be32(period_size); 517 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); 518 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); 519 link->next = cpu_to_be64(temp_link); 520 521 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 522 link->source_addr = cpu_to_be32(temp_addr); 523 else 524 link->dest_addr = cpu_to_be32(temp_addr); 525 526 temp_addr += period_size; 527 temp_link += sizeof(struct fsl_dma_link_descriptor); 528 } 529 /* The last link descriptor points to the first */ 530 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 531 532 /* Tell the DMA controller where the first link descriptor is */ 533 out_be32(&dma_channel->clndar, 534 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 535 out_be32(&dma_channel->eclndar, 536 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 537 538 /* The manual says the BCR must be clear before enabling EMP */ 539 out_be32(&dma_channel->bcr, 0); 540 541 /* 542 * Program the mode register for interrupts, external master control, 543 * and source/destination hold. Also clear the Channel Abort bit. 544 */ 545 mr = in_be32(&dma_channel->mr) & 546 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 547 548 /* 549 * We want External Master Start and External Master Pause enabled, 550 * because the SSI is controlling the DMA controller. We want the DMA 551 * controller to be set up in advance, and then we signal only the SSI 552 * to start transfering. 553 * 554 * We want End-Of-Segment Interrupts enabled, because this will generate 555 * an interrupt at the end of each segment (each link descriptor 556 * represents one segment). Each DMA segment is the same thing as an 557 * ALSA period, so this is how we get an interrupt at the end of every 558 * period. 559 * 560 * We want Error Interrupt enabled, so that we can get an error if 561 * the DMA controller is mis-programmed somehow. 562 */ 563 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 564 CCSR_DMA_MR_EMS_EN; 565 566 /* For playback, we want the destination address to be held. For 567 capture, set the source address to be held. */ 568 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 569 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 570 571 out_be32(&dma_channel->mr, mr); 572 573 return 0; 574 } 575 576 /** 577 * fsl_dma_prepare - prepare the DMA registers for playback. 578 * 579 * This function is called after the specifics of the audio data are known, 580 * i.e. snd_pcm_runtime is initialized. 581 * 582 * In this function, we finish programming the registers of the DMA 583 * controller that are dependent on the sample size. 584 * 585 * One of the drawbacks with big-endian is that when copying integers of 586 * different sizes to a fixed-sized register, the address to which the 587 * integer must be copied is dependent on the size of the integer. 588 * 589 * For example, if P is the address of a 32-bit register, and X is a 32-bit 590 * integer, then X should be copied to address P. However, if X is a 16-bit 591 * integer, then it should be copied to P+2. If X is an 8-bit register, 592 * then it should be copied to P+3. 593 * 594 * So for playback of 8-bit samples, the DMA controller must transfer single 595 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 596 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 597 * 598 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 599 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 600 * and 8 bytes at a time). So we do not support packed 24-bit samples. 601 * 24-bit data must be padded to 32 bits. 602 */ 603 static int fsl_dma_prepare(struct snd_pcm_substream *substream) 604 { 605 struct snd_pcm_runtime *runtime = substream->runtime; 606 struct fsl_dma_private *dma_private = runtime->private_data; 607 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 608 u32 mr; 609 unsigned int i; 610 dma_addr_t ssi_sxx_phys; /* Bus address of SSI STX register */ 611 unsigned int frame_size; /* Number of bytes per frame */ 612 613 ssi_sxx_phys = dma_private->ssi_sxx_phys; 614 615 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 616 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 617 618 switch (runtime->sample_bits) { 619 case 8: 620 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 621 ssi_sxx_phys += 3; 622 break; 623 case 16: 624 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 625 ssi_sxx_phys += 2; 626 break; 627 case 32: 628 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 629 break; 630 default: 631 dev_err(substream->pcm->card->dev, 632 "unsupported sample size %u\n", runtime->sample_bits); 633 return -EINVAL; 634 } 635 636 frame_size = runtime->frame_bits / 8; 637 /* 638 * BWC should always be a multiple of the frame size. BWC determines 639 * how many bytes are sent/received before the DMA controller checks the 640 * SSI to see if it needs to stop. For playback, the transmit FIFO can 641 * hold three frames, so we want to send two frames at a time. For 642 * capture, the receive FIFO is triggered when it contains one frame, so 643 * we want to receive one frame at a time. 644 */ 645 646 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 647 mr |= CCSR_DMA_MR_BWC(2 * frame_size); 648 else 649 mr |= CCSR_DMA_MR_BWC(frame_size); 650 651 out_be32(&dma_channel->mr, mr); 652 653 /* 654 * Program the address of the DMA transfer to/from the SSI. 655 */ 656 for (i = 0; i < NUM_DMA_LINKS; i++) { 657 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 658 659 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 660 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 661 else 662 link->source_addr = cpu_to_be32(ssi_sxx_phys); 663 } 664 665 return 0; 666 } 667 668 /** 669 * fsl_dma_pointer: determine the current position of the DMA transfer 670 * 671 * This function is called by ALSA when ALSA wants to know where in the 672 * stream buffer the hardware currently is. 673 * 674 * For playback, the SAR register contains the physical address of the most 675 * recent DMA transfer. For capture, the value is in the DAR register. 676 * 677 * The base address of the buffer is stored in the source_addr field of the 678 * first link descriptor. 679 */ 680 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream) 681 { 682 struct snd_pcm_runtime *runtime = substream->runtime; 683 struct fsl_dma_private *dma_private = runtime->private_data; 684 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 685 dma_addr_t position; 686 snd_pcm_uframes_t frames; 687 688 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 689 position = in_be32(&dma_channel->sar); 690 else 691 position = in_be32(&dma_channel->dar); 692 693 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 694 695 /* 696 * If the current address is just past the end of the buffer, wrap it 697 * around. 698 */ 699 if (frames == runtime->buffer_size) 700 frames = 0; 701 702 return frames; 703 } 704 705 /** 706 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 707 * 708 * Release the resources allocated in fsl_dma_hw_params() and de-program the 709 * registers. 710 * 711 * This function can be called multiple times. 712 */ 713 static int fsl_dma_hw_free(struct snd_pcm_substream *substream) 714 { 715 struct snd_pcm_runtime *runtime = substream->runtime; 716 struct fsl_dma_private *dma_private = runtime->private_data; 717 718 if (dma_private) { 719 struct ccsr_dma_channel __iomem *dma_channel; 720 721 dma_channel = dma_private->dma_channel; 722 723 /* Stop the DMA */ 724 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 725 out_be32(&dma_channel->mr, 0); 726 727 /* Reset all the other registers */ 728 out_be32(&dma_channel->sr, -1); 729 out_be32(&dma_channel->clndar, 0); 730 out_be32(&dma_channel->eclndar, 0); 731 out_be32(&dma_channel->satr, 0); 732 out_be32(&dma_channel->sar, 0); 733 out_be32(&dma_channel->datr, 0); 734 out_be32(&dma_channel->dar, 0); 735 out_be32(&dma_channel->bcr, 0); 736 out_be32(&dma_channel->nlndar, 0); 737 out_be32(&dma_channel->enlndar, 0); 738 } 739 740 return 0; 741 } 742 743 /** 744 * fsl_dma_close: close the stream. 745 */ 746 static int fsl_dma_close(struct snd_pcm_substream *substream) 747 { 748 struct snd_pcm_runtime *runtime = substream->runtime; 749 struct fsl_dma_private *dma_private = runtime->private_data; 750 int dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 751 752 if (dma_private) { 753 if (dma_private->irq) 754 free_irq(dma_private->irq, dma_private); 755 756 if (dma_private->ld_buf_phys) { 757 dma_unmap_single(substream->pcm->dev, 758 dma_private->ld_buf_phys, 759 sizeof(dma_private->link), DMA_TO_DEVICE); 760 } 761 762 /* Deallocate the fsl_dma_private structure */ 763 dma_free_coherent(substream->pcm->dev, 764 sizeof(struct fsl_dma_private), 765 dma_private, dma_private->ld_buf_phys); 766 substream->runtime->private_data = NULL; 767 } 768 769 dma_global_data.assigned[dir] = 0; 770 771 return 0; 772 } 773 774 /* 775 * Remove this PCM driver. 776 */ 777 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm) 778 { 779 struct snd_pcm_substream *substream; 780 unsigned int i; 781 782 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 783 substream = pcm->streams[i].substream; 784 if (substream) { 785 snd_dma_free_pages(&substream->dma_buffer); 786 substream->dma_buffer.area = NULL; 787 substream->dma_buffer.addr = 0; 788 } 789 } 790 } 791 792 static struct snd_pcm_ops fsl_dma_ops = { 793 .open = fsl_dma_open, 794 .close = fsl_dma_close, 795 .ioctl = snd_pcm_lib_ioctl, 796 .hw_params = fsl_dma_hw_params, 797 .hw_free = fsl_dma_hw_free, 798 .prepare = fsl_dma_prepare, 799 .pointer = fsl_dma_pointer, 800 }; 801 802 struct snd_soc_platform fsl_soc_platform = { 803 .name = "fsl-dma", 804 .pcm_ops = &fsl_dma_ops, 805 .pcm_new = fsl_dma_new, 806 .pcm_free = fsl_dma_free_dma_buffers, 807 }; 808 EXPORT_SYMBOL_GPL(fsl_soc_platform); 809 810 /** 811 * fsl_dma_configure: store the DMA parameters from the fabric driver. 812 * 813 * This function is called by the ASoC fabric driver to give us the DMA and 814 * SSI channel information. 815 * 816 * Unfortunately, ASoC V1 does make it possible to determine the DMA/SSI 817 * data when a substream is created, so for now we need to store this data 818 * into a global variable. This means that we can only support one DMA 819 * controller, and hence only one SSI. 820 */ 821 int fsl_dma_configure(struct fsl_dma_info *dma_info) 822 { 823 static int initialized; 824 825 /* We only support one DMA controller for now */ 826 if (initialized) 827 return 0; 828 829 dma_global_data.ssi_stx_phys = dma_info->ssi_stx_phys; 830 dma_global_data.ssi_srx_phys = dma_info->ssi_srx_phys; 831 dma_global_data.dma_channel[0] = dma_info->dma_channel[0]; 832 dma_global_data.dma_channel[1] = dma_info->dma_channel[1]; 833 dma_global_data.irq[0] = dma_info->dma_irq[0]; 834 dma_global_data.irq[1] = dma_info->dma_irq[1]; 835 dma_global_data.assigned[0] = 0; 836 dma_global_data.assigned[1] = 0; 837 838 initialized = 1; 839 return 1; 840 } 841 EXPORT_SYMBOL_GPL(fsl_dma_configure); 842 843 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 844 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM module"); 845 MODULE_LICENSE("GPL"); 846