1 /* 2 * Freescale DMA ALSA SoC PCM driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed 7 * under the terms of the GNU General Public License version 2. This 8 * program is licensed "as is" without any warranty of any kind, whether 9 * express or implied. 10 * 11 * This driver implements ASoC support for the Elo DMA controller, which is 12 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 13 * the PCM driver is what handles the DMA buffer. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/interrupt.h> 21 #include <linux/delay.h> 22 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 28 #include <asm/io.h> 29 30 #include "fsl_dma.h" 31 32 /* 33 * The formats that the DMA controller supports, which is anything 34 * that is 8, 16, or 32 bits. 35 */ 36 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 37 SNDRV_PCM_FMTBIT_U8 | \ 38 SNDRV_PCM_FMTBIT_S16_LE | \ 39 SNDRV_PCM_FMTBIT_S16_BE | \ 40 SNDRV_PCM_FMTBIT_U16_LE | \ 41 SNDRV_PCM_FMTBIT_U16_BE | \ 42 SNDRV_PCM_FMTBIT_S24_LE | \ 43 SNDRV_PCM_FMTBIT_S24_BE | \ 44 SNDRV_PCM_FMTBIT_U24_LE | \ 45 SNDRV_PCM_FMTBIT_U24_BE | \ 46 SNDRV_PCM_FMTBIT_S32_LE | \ 47 SNDRV_PCM_FMTBIT_S32_BE | \ 48 SNDRV_PCM_FMTBIT_U32_LE | \ 49 SNDRV_PCM_FMTBIT_U32_BE) 50 51 #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ 52 SNDRV_PCM_RATE_CONTINUOUS) 53 54 /* DMA global data. This structure is used by fsl_dma_open() to determine 55 * which DMA channels to assign to a substream. Unfortunately, ASoC V1 does 56 * not allow the machine driver to provide this information to the PCM 57 * driver in advance, and there's no way to differentiate between the two 58 * DMA controllers. So for now, this driver only supports one SSI device 59 * using two DMA channels. We cannot support multiple DMA devices. 60 * 61 * ssi_stx_phys: bus address of SSI STX register 62 * ssi_srx_phys: bus address of SSI SRX register 63 * dma_channel: pointer to the DMA channel's registers 64 * irq: IRQ for this DMA channel 65 * assigned: set to 1 if that DMA channel is assigned to a substream 66 */ 67 static struct { 68 dma_addr_t ssi_stx_phys; 69 dma_addr_t ssi_srx_phys; 70 struct ccsr_dma_channel __iomem *dma_channel[2]; 71 unsigned int irq[2]; 72 unsigned int assigned[2]; 73 } dma_global_data; 74 75 /* 76 * The number of DMA links to use. Two is the bare minimum, but if you 77 * have really small links you might need more. 78 */ 79 #define NUM_DMA_LINKS 2 80 81 /** fsl_dma_private: p-substream DMA data 82 * 83 * Each substream has a 1-to-1 association with a DMA channel. 84 * 85 * The link[] array is first because it needs to be aligned on a 32-byte 86 * boundary, so putting it first will ensure alignment without padding the 87 * structure. 88 * 89 * @link[]: array of link descriptors 90 * @controller_id: which DMA controller (0, 1, ...) 91 * @channel_id: which DMA channel on the controller (0, 1, 2, ...) 92 * @dma_channel: pointer to the DMA channel's registers 93 * @irq: IRQ for this DMA channel 94 * @substream: pointer to the substream object, needed by the ISR 95 * @ssi_sxx_phys: bus address of the STX or SRX register to use 96 * @ld_buf_phys: physical address of the LD buffer 97 * @current_link: index into link[] of the link currently being processed 98 * @dma_buf_phys: physical address of the DMA buffer 99 * @dma_buf_next: physical address of the next period to process 100 * @dma_buf_end: physical address of the byte after the end of the DMA 101 * @buffer period_size: the size of a single period 102 * @num_periods: the number of periods in the DMA buffer 103 */ 104 struct fsl_dma_private { 105 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 106 unsigned int controller_id; 107 unsigned int channel_id; 108 struct ccsr_dma_channel __iomem *dma_channel; 109 unsigned int irq; 110 struct snd_pcm_substream *substream; 111 dma_addr_t ssi_sxx_phys; 112 dma_addr_t ld_buf_phys; 113 unsigned int current_link; 114 dma_addr_t dma_buf_phys; 115 dma_addr_t dma_buf_next; 116 dma_addr_t dma_buf_end; 117 size_t period_size; 118 unsigned int num_periods; 119 }; 120 121 /** 122 * fsl_dma_hardare: define characteristics of the PCM hardware. 123 * 124 * The PCM hardware is the Freescale DMA controller. This structure defines 125 * the capabilities of that hardware. 126 * 127 * Since the sampling rate and data format are not controlled by the DMA 128 * controller, we specify no limits for those values. The only exception is 129 * period_bytes_min, which is set to a reasonably low value to prevent the 130 * DMA controller from generating too many interrupts per second. 131 * 132 * Since each link descriptor has a 32-bit byte count field, we set 133 * period_bytes_max to the largest 32-bit number. We also have no maximum 134 * number of periods. 135 */ 136 static const struct snd_pcm_hardware fsl_dma_hardware = { 137 138 .info = SNDRV_PCM_INFO_INTERLEAVED | 139 SNDRV_PCM_INFO_MMAP | 140 SNDRV_PCM_INFO_MMAP_VALID, 141 .formats = FSLDMA_PCM_FORMATS, 142 .rates = FSLDMA_PCM_RATES, 143 .rate_min = 5512, 144 .rate_max = 192000, 145 .period_bytes_min = 512, /* A reasonable limit */ 146 .period_bytes_max = (u32) -1, 147 .periods_min = NUM_DMA_LINKS, 148 .periods_max = (unsigned int) -1, 149 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 150 }; 151 152 /** 153 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 154 * 155 * This function should be called by the ISR whenever the DMA controller 156 * halts data transfer. 157 */ 158 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 159 { 160 unsigned long flags; 161 162 snd_pcm_stream_lock_irqsave(substream, flags); 163 164 if (snd_pcm_running(substream)) 165 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); 166 167 snd_pcm_stream_unlock_irqrestore(substream, flags); 168 } 169 170 /** 171 * fsl_dma_update_pointers - update LD pointers to point to the next period 172 * 173 * As each period is completed, this function changes the the link 174 * descriptor pointers for that period to point to the next period. 175 */ 176 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 177 { 178 struct fsl_dma_link_descriptor *link = 179 &dma_private->link[dma_private->current_link]; 180 181 /* Update our link descriptors to point to the next period */ 182 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 183 link->source_addr = 184 cpu_to_be32(dma_private->dma_buf_next); 185 else 186 link->dest_addr = 187 cpu_to_be32(dma_private->dma_buf_next); 188 189 /* Update our variables for next time */ 190 dma_private->dma_buf_next += dma_private->period_size; 191 192 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 193 dma_private->dma_buf_next = dma_private->dma_buf_phys; 194 195 if (++dma_private->current_link >= NUM_DMA_LINKS) 196 dma_private->current_link = 0; 197 } 198 199 /** 200 * fsl_dma_isr: interrupt handler for the DMA controller 201 * 202 * @irq: IRQ of the DMA channel 203 * @dev_id: pointer to the dma_private structure for this DMA channel 204 */ 205 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 206 { 207 struct fsl_dma_private *dma_private = dev_id; 208 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 209 irqreturn_t ret = IRQ_NONE; 210 u32 sr, sr2 = 0; 211 212 /* We got an interrupt, so read the status register to see what we 213 were interrupted for. 214 */ 215 sr = in_be32(&dma_channel->sr); 216 217 if (sr & CCSR_DMA_SR_TE) { 218 dev_err(dma_private->substream->pcm->card->dev, 219 "DMA transmit error (controller=%u channel=%u irq=%u\n", 220 dma_private->controller_id, 221 dma_private->channel_id, irq); 222 fsl_dma_abort_stream(dma_private->substream); 223 sr2 |= CCSR_DMA_SR_TE; 224 ret = IRQ_HANDLED; 225 } 226 227 if (sr & CCSR_DMA_SR_CH) 228 ret = IRQ_HANDLED; 229 230 if (sr & CCSR_DMA_SR_PE) { 231 dev_err(dma_private->substream->pcm->card->dev, 232 "DMA%u programming error (channel=%u irq=%u)\n", 233 dma_private->controller_id, 234 dma_private->channel_id, irq); 235 fsl_dma_abort_stream(dma_private->substream); 236 sr2 |= CCSR_DMA_SR_PE; 237 ret = IRQ_HANDLED; 238 } 239 240 if (sr & CCSR_DMA_SR_EOLNI) { 241 sr2 |= CCSR_DMA_SR_EOLNI; 242 ret = IRQ_HANDLED; 243 } 244 245 if (sr & CCSR_DMA_SR_CB) 246 ret = IRQ_HANDLED; 247 248 if (sr & CCSR_DMA_SR_EOSI) { 249 struct snd_pcm_substream *substream = dma_private->substream; 250 251 /* Tell ALSA we completed a period. */ 252 snd_pcm_period_elapsed(substream); 253 254 /* 255 * Update our link descriptors to point to the next period. We 256 * only need to do this if the number of periods is not equal to 257 * the number of links. 258 */ 259 if (dma_private->num_periods != NUM_DMA_LINKS) 260 fsl_dma_update_pointers(dma_private); 261 262 sr2 |= CCSR_DMA_SR_EOSI; 263 ret = IRQ_HANDLED; 264 } 265 266 if (sr & CCSR_DMA_SR_EOLSI) { 267 sr2 |= CCSR_DMA_SR_EOLSI; 268 ret = IRQ_HANDLED; 269 } 270 271 /* Clear the bits that we set */ 272 if (sr2) 273 out_be32(&dma_channel->sr, sr2); 274 275 return ret; 276 } 277 278 /** 279 * fsl_dma_new: initialize this PCM driver. 280 * 281 * This function is called when the codec driver calls snd_soc_new_pcms(), 282 * once for each .dai_link in the machine driver's snd_soc_machine 283 * structure. 284 */ 285 static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai, 286 struct snd_pcm *pcm) 287 { 288 static u64 fsl_dma_dmamask = DMA_BIT_MASK(32); 289 int ret; 290 291 if (!card->dev->dma_mask) 292 card->dev->dma_mask = &fsl_dma_dmamask; 293 294 if (!card->dev->coherent_dma_mask) 295 card->dev->coherent_dma_mask = fsl_dma_dmamask; 296 297 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->dev, 298 fsl_dma_hardware.buffer_bytes_max, 299 &pcm->streams[0].substream->dma_buffer); 300 if (ret) { 301 dev_err(card->dev, 302 "Can't allocate playback DMA buffer (size=%u)\n", 303 fsl_dma_hardware.buffer_bytes_max); 304 return -ENOMEM; 305 } 306 307 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->dev, 308 fsl_dma_hardware.buffer_bytes_max, 309 &pcm->streams[1].substream->dma_buffer); 310 if (ret) { 311 snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer); 312 dev_err(card->dev, 313 "Can't allocate capture DMA buffer (size=%u)\n", 314 fsl_dma_hardware.buffer_bytes_max); 315 return -ENOMEM; 316 } 317 318 return 0; 319 } 320 321 /** 322 * fsl_dma_open: open a new substream. 323 * 324 * Each substream has its own DMA buffer. 325 */ 326 static int fsl_dma_open(struct snd_pcm_substream *substream) 327 { 328 struct snd_pcm_runtime *runtime = substream->runtime; 329 struct fsl_dma_private *dma_private; 330 dma_addr_t ld_buf_phys; 331 unsigned int channel; 332 int ret = 0; 333 334 /* 335 * Reject any DMA buffer whose size is not a multiple of the period 336 * size. We need to make sure that the DMA buffer can be evenly divided 337 * into periods. 338 */ 339 ret = snd_pcm_hw_constraint_integer(runtime, 340 SNDRV_PCM_HW_PARAM_PERIODS); 341 if (ret < 0) { 342 dev_err(substream->pcm->card->dev, "invalid buffer size\n"); 343 return ret; 344 } 345 346 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 347 348 if (dma_global_data.assigned[channel]) { 349 dev_err(substream->pcm->card->dev, 350 "DMA channel already assigned\n"); 351 return -EBUSY; 352 } 353 354 dma_private = dma_alloc_coherent(substream->pcm->dev, 355 sizeof(struct fsl_dma_private), &ld_buf_phys, GFP_KERNEL); 356 if (!dma_private) { 357 dev_err(substream->pcm->card->dev, 358 "can't allocate DMA private data\n"); 359 return -ENOMEM; 360 } 361 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 362 dma_private->ssi_sxx_phys = dma_global_data.ssi_stx_phys; 363 else 364 dma_private->ssi_sxx_phys = dma_global_data.ssi_srx_phys; 365 366 dma_private->dma_channel = dma_global_data.dma_channel[channel]; 367 dma_private->irq = dma_global_data.irq[channel]; 368 dma_private->substream = substream; 369 dma_private->ld_buf_phys = ld_buf_phys; 370 dma_private->dma_buf_phys = substream->dma_buffer.addr; 371 372 /* We only support one DMA controller for now */ 373 dma_private->controller_id = 0; 374 dma_private->channel_id = channel; 375 376 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private); 377 if (ret) { 378 dev_err(substream->pcm->card->dev, 379 "can't register ISR for IRQ %u (ret=%i)\n", 380 dma_private->irq, ret); 381 dma_free_coherent(substream->pcm->dev, 382 sizeof(struct fsl_dma_private), 383 dma_private, dma_private->ld_buf_phys); 384 return ret; 385 } 386 387 dma_global_data.assigned[channel] = 1; 388 389 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 390 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 391 runtime->private_data = dma_private; 392 393 return 0; 394 } 395 396 /** 397 * fsl_dma_hw_params: allocate the DMA buffer and the DMA link descriptors. 398 * 399 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 400 * descriptors that ping-pong from one period to the next. For example, if 401 * there are six periods and two link descriptors, this is how they look 402 * before playback starts: 403 * 404 * The last link descriptor 405 * ____________ points back to the first 406 * | | 407 * V | 408 * ___ ___ | 409 * | |->| |->| 410 * |___| |___| 411 * | | 412 * | | 413 * V V 414 * _________________________________________ 415 * | | | | | | | The DMA buffer is 416 * | | | | | | | divided into 6 parts 417 * |______|______|______|______|______|______| 418 * 419 * and here's how they look after the first period is finished playing: 420 * 421 * ____________ 422 * | | 423 * V | 424 * ___ ___ | 425 * | |->| |->| 426 * |___| |___| 427 * | | 428 * |______________ 429 * | | 430 * V V 431 * _________________________________________ 432 * | | | | | | | 433 * | | | | | | | 434 * |______|______|______|______|______|______| 435 * 436 * The first link descriptor now points to the third period. The DMA 437 * controller is currently playing the second period. When it finishes, it 438 * will jump back to the first descriptor and play the third period. 439 * 440 * There are four reasons we do this: 441 * 442 * 1. The only way to get the DMA controller to automatically restart the 443 * transfer when it gets to the end of the buffer is to use chaining 444 * mode. Basic direct mode doesn't offer that feature. 445 * 2. We need to receive an interrupt at the end of every period. The DMA 446 * controller can generate an interrupt at the end of every link transfer 447 * (aka segment). Making each period into a DMA segment will give us the 448 * interrupts we need. 449 * 3. By creating only two link descriptors, regardless of the number of 450 * periods, we do not need to reallocate the link descriptors if the 451 * number of periods changes. 452 * 4. All of the audio data is still stored in a single, contiguous DMA 453 * buffer, which is what ALSA expects. We're just dividing it into 454 * contiguous parts, and creating a link descriptor for each one. 455 * 456 * Note that due to a quirk of the SSI's STX register, the target address 457 * for the DMA operations depends on the sample size. So we don't program 458 * the dest_addr (for playback -- source_addr for capture) fields in the 459 * link descriptors here. We do that in fsl_dma_prepare() 460 */ 461 static int fsl_dma_hw_params(struct snd_pcm_substream *substream, 462 struct snd_pcm_hw_params *hw_params) 463 { 464 struct snd_pcm_runtime *runtime = substream->runtime; 465 struct fsl_dma_private *dma_private = runtime->private_data; 466 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 467 468 dma_addr_t temp_addr; /* Pointer to next period */ 469 u64 temp_link; /* Pointer to next link descriptor */ 470 u32 mr; /* Temporary variable for MR register */ 471 472 unsigned int i; 473 474 /* Get all the parameters we need */ 475 size_t buffer_size = params_buffer_bytes(hw_params); 476 size_t period_size = params_period_bytes(hw_params); 477 478 /* Initialize our DMA tracking variables */ 479 dma_private->period_size = period_size; 480 dma_private->num_periods = params_periods(hw_params); 481 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 482 dma_private->dma_buf_next = dma_private->dma_buf_phys + 483 (NUM_DMA_LINKS * period_size); 484 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 485 dma_private->dma_buf_next = dma_private->dma_buf_phys; 486 487 /* 488 * Initialize each link descriptor. 489 * 490 * The actual address in STX0 (destination for playback, source for 491 * capture) is based on the sample size, but we don't know the sample 492 * size in this function, so we'll have to adjust that later. See 493 * comments in fsl_dma_prepare(). 494 * 495 * The DMA controller does not have a cache, so the CPU does not 496 * need to tell it to flush its cache. However, the DMA 497 * controller does need to tell the CPU to flush its cache. 498 * That's what the SNOOP bit does. 499 * 500 * Also, even though the DMA controller supports 36-bit addressing, for 501 * simplicity we currently support only 32-bit addresses for the audio 502 * buffer itself. 503 */ 504 temp_addr = substream->dma_buffer.addr; 505 temp_link = dma_private->ld_buf_phys + 506 sizeof(struct fsl_dma_link_descriptor); 507 508 for (i = 0; i < NUM_DMA_LINKS; i++) { 509 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 510 511 link->count = cpu_to_be32(period_size); 512 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); 513 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); 514 link->next = cpu_to_be64(temp_link); 515 516 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 517 link->source_addr = cpu_to_be32(temp_addr); 518 else 519 link->dest_addr = cpu_to_be32(temp_addr); 520 521 temp_addr += period_size; 522 temp_link += sizeof(struct fsl_dma_link_descriptor); 523 } 524 /* The last link descriptor points to the first */ 525 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 526 527 /* Tell the DMA controller where the first link descriptor is */ 528 out_be32(&dma_channel->clndar, 529 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 530 out_be32(&dma_channel->eclndar, 531 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 532 533 /* The manual says the BCR must be clear before enabling EMP */ 534 out_be32(&dma_channel->bcr, 0); 535 536 /* 537 * Program the mode register for interrupts, external master control, 538 * and source/destination hold. Also clear the Channel Abort bit. 539 */ 540 mr = in_be32(&dma_channel->mr) & 541 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 542 543 /* 544 * We want External Master Start and External Master Pause enabled, 545 * because the SSI is controlling the DMA controller. We want the DMA 546 * controller to be set up in advance, and then we signal only the SSI 547 * to start transfering. 548 * 549 * We want End-Of-Segment Interrupts enabled, because this will generate 550 * an interrupt at the end of each segment (each link descriptor 551 * represents one segment). Each DMA segment is the same thing as an 552 * ALSA period, so this is how we get an interrupt at the end of every 553 * period. 554 * 555 * We want Error Interrupt enabled, so that we can get an error if 556 * the DMA controller is mis-programmed somehow. 557 */ 558 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 559 CCSR_DMA_MR_EMS_EN; 560 561 /* For playback, we want the destination address to be held. For 562 capture, set the source address to be held. */ 563 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 564 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 565 566 out_be32(&dma_channel->mr, mr); 567 568 return 0; 569 } 570 571 /** 572 * fsl_dma_prepare - prepare the DMA registers for playback. 573 * 574 * This function is called after the specifics of the audio data are known, 575 * i.e. snd_pcm_runtime is initialized. 576 * 577 * In this function, we finish programming the registers of the DMA 578 * controller that are dependent on the sample size. 579 * 580 * One of the drawbacks with big-endian is that when copying integers of 581 * different sizes to a fixed-sized register, the address to which the 582 * integer must be copied is dependent on the size of the integer. 583 * 584 * For example, if P is the address of a 32-bit register, and X is a 32-bit 585 * integer, then X should be copied to address P. However, if X is a 16-bit 586 * integer, then it should be copied to P+2. If X is an 8-bit register, 587 * then it should be copied to P+3. 588 * 589 * So for playback of 8-bit samples, the DMA controller must transfer single 590 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 591 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 592 * 593 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 594 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 595 * and 8 bytes at a time). So we do not support packed 24-bit samples. 596 * 24-bit data must be padded to 32 bits. 597 */ 598 static int fsl_dma_prepare(struct snd_pcm_substream *substream) 599 { 600 struct snd_pcm_runtime *runtime = substream->runtime; 601 struct fsl_dma_private *dma_private = runtime->private_data; 602 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 603 u32 mr; 604 unsigned int i; 605 dma_addr_t ssi_sxx_phys; /* Bus address of SSI STX register */ 606 unsigned int frame_size; /* Number of bytes per frame */ 607 608 ssi_sxx_phys = dma_private->ssi_sxx_phys; 609 610 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 611 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 612 613 switch (runtime->sample_bits) { 614 case 8: 615 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 616 ssi_sxx_phys += 3; 617 break; 618 case 16: 619 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 620 ssi_sxx_phys += 2; 621 break; 622 case 32: 623 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 624 break; 625 default: 626 dev_err(substream->pcm->card->dev, 627 "unsupported sample size %u\n", runtime->sample_bits); 628 return -EINVAL; 629 } 630 631 frame_size = runtime->frame_bits / 8; 632 /* 633 * BWC should always be a multiple of the frame size. BWC determines 634 * how many bytes are sent/received before the DMA controller checks the 635 * SSI to see if it needs to stop. For playback, the transmit FIFO can 636 * hold three frames, so we want to send two frames at a time. For 637 * capture, the receive FIFO is triggered when it contains one frame, so 638 * we want to receive one frame at a time. 639 */ 640 641 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 642 mr |= CCSR_DMA_MR_BWC(2 * frame_size); 643 else 644 mr |= CCSR_DMA_MR_BWC(frame_size); 645 646 out_be32(&dma_channel->mr, mr); 647 648 /* 649 * Program the address of the DMA transfer to/from the SSI. 650 */ 651 for (i = 0; i < NUM_DMA_LINKS; i++) { 652 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 653 654 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 655 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 656 else 657 link->source_addr = cpu_to_be32(ssi_sxx_phys); 658 } 659 660 return 0; 661 } 662 663 /** 664 * fsl_dma_pointer: determine the current position of the DMA transfer 665 * 666 * This function is called by ALSA when ALSA wants to know where in the 667 * stream buffer the hardware currently is. 668 * 669 * For playback, the SAR register contains the physical address of the most 670 * recent DMA transfer. For capture, the value is in the DAR register. 671 * 672 * The base address of the buffer is stored in the source_addr field of the 673 * first link descriptor. 674 */ 675 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream) 676 { 677 struct snd_pcm_runtime *runtime = substream->runtime; 678 struct fsl_dma_private *dma_private = runtime->private_data; 679 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 680 dma_addr_t position; 681 snd_pcm_uframes_t frames; 682 683 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 684 position = in_be32(&dma_channel->sar); 685 else 686 position = in_be32(&dma_channel->dar); 687 688 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 689 690 /* 691 * If the current address is just past the end of the buffer, wrap it 692 * around. 693 */ 694 if (frames == runtime->buffer_size) 695 frames = 0; 696 697 return frames; 698 } 699 700 /** 701 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 702 * 703 * Release the resources allocated in fsl_dma_hw_params() and de-program the 704 * registers. 705 * 706 * This function can be called multiple times. 707 */ 708 static int fsl_dma_hw_free(struct snd_pcm_substream *substream) 709 { 710 struct snd_pcm_runtime *runtime = substream->runtime; 711 struct fsl_dma_private *dma_private = runtime->private_data; 712 713 if (dma_private) { 714 struct ccsr_dma_channel __iomem *dma_channel; 715 716 dma_channel = dma_private->dma_channel; 717 718 /* Stop the DMA */ 719 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 720 out_be32(&dma_channel->mr, 0); 721 722 /* Reset all the other registers */ 723 out_be32(&dma_channel->sr, -1); 724 out_be32(&dma_channel->clndar, 0); 725 out_be32(&dma_channel->eclndar, 0); 726 out_be32(&dma_channel->satr, 0); 727 out_be32(&dma_channel->sar, 0); 728 out_be32(&dma_channel->datr, 0); 729 out_be32(&dma_channel->dar, 0); 730 out_be32(&dma_channel->bcr, 0); 731 out_be32(&dma_channel->nlndar, 0); 732 out_be32(&dma_channel->enlndar, 0); 733 } 734 735 return 0; 736 } 737 738 /** 739 * fsl_dma_close: close the stream. 740 */ 741 static int fsl_dma_close(struct snd_pcm_substream *substream) 742 { 743 struct snd_pcm_runtime *runtime = substream->runtime; 744 struct fsl_dma_private *dma_private = runtime->private_data; 745 int dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 746 747 if (dma_private) { 748 if (dma_private->irq) 749 free_irq(dma_private->irq, dma_private); 750 751 if (dma_private->ld_buf_phys) { 752 dma_unmap_single(substream->pcm->dev, 753 dma_private->ld_buf_phys, 754 sizeof(dma_private->link), DMA_TO_DEVICE); 755 } 756 757 /* Deallocate the fsl_dma_private structure */ 758 dma_free_coherent(substream->pcm->dev, 759 sizeof(struct fsl_dma_private), 760 dma_private, dma_private->ld_buf_phys); 761 substream->runtime->private_data = NULL; 762 } 763 764 dma_global_data.assigned[dir] = 0; 765 766 return 0; 767 } 768 769 /* 770 * Remove this PCM driver. 771 */ 772 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm) 773 { 774 struct snd_pcm_substream *substream; 775 unsigned int i; 776 777 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 778 substream = pcm->streams[i].substream; 779 if (substream) { 780 snd_dma_free_pages(&substream->dma_buffer); 781 substream->dma_buffer.area = NULL; 782 substream->dma_buffer.addr = 0; 783 } 784 } 785 } 786 787 static struct snd_pcm_ops fsl_dma_ops = { 788 .open = fsl_dma_open, 789 .close = fsl_dma_close, 790 .ioctl = snd_pcm_lib_ioctl, 791 .hw_params = fsl_dma_hw_params, 792 .hw_free = fsl_dma_hw_free, 793 .prepare = fsl_dma_prepare, 794 .pointer = fsl_dma_pointer, 795 }; 796 797 struct snd_soc_platform fsl_soc_platform = { 798 .name = "fsl-dma", 799 .pcm_ops = &fsl_dma_ops, 800 .pcm_new = fsl_dma_new, 801 .pcm_free = fsl_dma_free_dma_buffers, 802 }; 803 EXPORT_SYMBOL_GPL(fsl_soc_platform); 804 805 /** 806 * fsl_dma_configure: store the DMA parameters from the fabric driver. 807 * 808 * This function is called by the ASoC fabric driver to give us the DMA and 809 * SSI channel information. 810 * 811 * Unfortunately, ASoC V1 does make it possible to determine the DMA/SSI 812 * data when a substream is created, so for now we need to store this data 813 * into a global variable. This means that we can only support one DMA 814 * controller, and hence only one SSI. 815 */ 816 int fsl_dma_configure(struct fsl_dma_info *dma_info) 817 { 818 static int initialized; 819 820 /* We only support one DMA controller for now */ 821 if (initialized) 822 return 0; 823 824 dma_global_data.ssi_stx_phys = dma_info->ssi_stx_phys; 825 dma_global_data.ssi_srx_phys = dma_info->ssi_srx_phys; 826 dma_global_data.dma_channel[0] = dma_info->dma_channel[0]; 827 dma_global_data.dma_channel[1] = dma_info->dma_channel[1]; 828 dma_global_data.irq[0] = dma_info->dma_irq[0]; 829 dma_global_data.irq[1] = dma_info->dma_irq[1]; 830 dma_global_data.assigned[0] = 0; 831 dma_global_data.assigned[1] = 0; 832 833 initialized = 1; 834 return 1; 835 } 836 EXPORT_SYMBOL_GPL(fsl_dma_configure); 837 838 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 839 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM module"); 840 MODULE_LICENSE("GPL"); 841