1 /* 2 * Freescale DMA ALSA SoC PCM driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed 7 * under the terms of the GNU General Public License version 2. This 8 * program is licensed "as is" without any warranty of any kind, whether 9 * express or implied. 10 * 11 * This driver implements ASoC support for the Elo DMA controller, which is 12 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 13 * the PCM driver is what handles the DMA buffer. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/interrupt.h> 21 #include <linux/delay.h> 22 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 28 #include <asm/io.h> 29 30 #include "fsl_dma.h" 31 32 /* 33 * The formats that the DMA controller supports, which is anything 34 * that is 8, 16, or 32 bits. 35 */ 36 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 37 SNDRV_PCM_FMTBIT_U8 | \ 38 SNDRV_PCM_FMTBIT_S16_LE | \ 39 SNDRV_PCM_FMTBIT_S16_BE | \ 40 SNDRV_PCM_FMTBIT_U16_LE | \ 41 SNDRV_PCM_FMTBIT_U16_BE | \ 42 SNDRV_PCM_FMTBIT_S24_LE | \ 43 SNDRV_PCM_FMTBIT_S24_BE | \ 44 SNDRV_PCM_FMTBIT_U24_LE | \ 45 SNDRV_PCM_FMTBIT_U24_BE | \ 46 SNDRV_PCM_FMTBIT_S32_LE | \ 47 SNDRV_PCM_FMTBIT_S32_BE | \ 48 SNDRV_PCM_FMTBIT_U32_LE | \ 49 SNDRV_PCM_FMTBIT_U32_BE) 50 51 #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ 52 SNDRV_PCM_RATE_CONTINUOUS) 53 54 /* DMA global data. This structure is used by fsl_dma_open() to determine 55 * which DMA channels to assign to a substream. Unfortunately, ASoC V1 does 56 * not allow the machine driver to provide this information to the PCM 57 * driver in advance, and there's no way to differentiate between the two 58 * DMA controllers. So for now, this driver only supports one SSI device 59 * using two DMA channels. We cannot support multiple DMA devices. 60 * 61 * ssi_stx_phys: bus address of SSI STX register 62 * ssi_srx_phys: bus address of SSI SRX register 63 * dma_channel: pointer to the DMA channel's registers 64 * irq: IRQ for this DMA channel 65 * assigned: set to 1 if that DMA channel is assigned to a substream 66 */ 67 static struct { 68 dma_addr_t ssi_stx_phys; 69 dma_addr_t ssi_srx_phys; 70 struct ccsr_dma_channel __iomem *dma_channel[2]; 71 unsigned int irq[2]; 72 unsigned int assigned[2]; 73 } dma_global_data; 74 75 /* 76 * The number of DMA links to use. Two is the bare minimum, but if you 77 * have really small links you might need more. 78 */ 79 #define NUM_DMA_LINKS 2 80 81 /** fsl_dma_private: p-substream DMA data 82 * 83 * Each substream has a 1-to-1 association with a DMA channel. 84 * 85 * The link[] array is first because it needs to be aligned on a 32-byte 86 * boundary, so putting it first will ensure alignment without padding the 87 * structure. 88 * 89 * @link[]: array of link descriptors 90 * @controller_id: which DMA controller (0, 1, ...) 91 * @channel_id: which DMA channel on the controller (0, 1, 2, ...) 92 * @dma_channel: pointer to the DMA channel's registers 93 * @irq: IRQ for this DMA channel 94 * @substream: pointer to the substream object, needed by the ISR 95 * @ssi_sxx_phys: bus address of the STX or SRX register to use 96 * @ld_buf_phys: physical address of the LD buffer 97 * @current_link: index into link[] of the link currently being processed 98 * @dma_buf_phys: physical address of the DMA buffer 99 * @dma_buf_next: physical address of the next period to process 100 * @dma_buf_end: physical address of the byte after the end of the DMA 101 * @buffer period_size: the size of a single period 102 * @num_periods: the number of periods in the DMA buffer 103 */ 104 struct fsl_dma_private { 105 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 106 unsigned int controller_id; 107 unsigned int channel_id; 108 struct ccsr_dma_channel __iomem *dma_channel; 109 unsigned int irq; 110 struct snd_pcm_substream *substream; 111 dma_addr_t ssi_sxx_phys; 112 dma_addr_t ld_buf_phys; 113 unsigned int current_link; 114 dma_addr_t dma_buf_phys; 115 dma_addr_t dma_buf_next; 116 dma_addr_t dma_buf_end; 117 size_t period_size; 118 unsigned int num_periods; 119 }; 120 121 /** 122 * fsl_dma_hardare: define characteristics of the PCM hardware. 123 * 124 * The PCM hardware is the Freescale DMA controller. This structure defines 125 * the capabilities of that hardware. 126 * 127 * Since the sampling rate and data format are not controlled by the DMA 128 * controller, we specify no limits for those values. The only exception is 129 * period_bytes_min, which is set to a reasonably low value to prevent the 130 * DMA controller from generating too many interrupts per second. 131 * 132 * Since each link descriptor has a 32-bit byte count field, we set 133 * period_bytes_max to the largest 32-bit number. We also have no maximum 134 * number of periods. 135 * 136 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a 137 * limitation in the SSI driver requires the sample rates for playback and 138 * capture to be the same. 139 */ 140 static const struct snd_pcm_hardware fsl_dma_hardware = { 141 142 .info = SNDRV_PCM_INFO_INTERLEAVED | 143 SNDRV_PCM_INFO_MMAP | 144 SNDRV_PCM_INFO_MMAP_VALID | 145 SNDRV_PCM_INFO_JOINT_DUPLEX, 146 .formats = FSLDMA_PCM_FORMATS, 147 .rates = FSLDMA_PCM_RATES, 148 .rate_min = 5512, 149 .rate_max = 192000, 150 .period_bytes_min = 512, /* A reasonable limit */ 151 .period_bytes_max = (u32) -1, 152 .periods_min = NUM_DMA_LINKS, 153 .periods_max = (unsigned int) -1, 154 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 155 }; 156 157 /** 158 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 159 * 160 * This function should be called by the ISR whenever the DMA controller 161 * halts data transfer. 162 */ 163 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 164 { 165 unsigned long flags; 166 167 snd_pcm_stream_lock_irqsave(substream, flags); 168 169 if (snd_pcm_running(substream)) 170 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); 171 172 snd_pcm_stream_unlock_irqrestore(substream, flags); 173 } 174 175 /** 176 * fsl_dma_update_pointers - update LD pointers to point to the next period 177 * 178 * As each period is completed, this function changes the the link 179 * descriptor pointers for that period to point to the next period. 180 */ 181 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 182 { 183 struct fsl_dma_link_descriptor *link = 184 &dma_private->link[dma_private->current_link]; 185 186 /* Update our link descriptors to point to the next period */ 187 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 188 link->source_addr = 189 cpu_to_be32(dma_private->dma_buf_next); 190 else 191 link->dest_addr = 192 cpu_to_be32(dma_private->dma_buf_next); 193 194 /* Update our variables for next time */ 195 dma_private->dma_buf_next += dma_private->period_size; 196 197 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 198 dma_private->dma_buf_next = dma_private->dma_buf_phys; 199 200 if (++dma_private->current_link >= NUM_DMA_LINKS) 201 dma_private->current_link = 0; 202 } 203 204 /** 205 * fsl_dma_isr: interrupt handler for the DMA controller 206 * 207 * @irq: IRQ of the DMA channel 208 * @dev_id: pointer to the dma_private structure for this DMA channel 209 */ 210 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 211 { 212 struct fsl_dma_private *dma_private = dev_id; 213 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 214 irqreturn_t ret = IRQ_NONE; 215 u32 sr, sr2 = 0; 216 217 /* We got an interrupt, so read the status register to see what we 218 were interrupted for. 219 */ 220 sr = in_be32(&dma_channel->sr); 221 222 if (sr & CCSR_DMA_SR_TE) { 223 dev_err(dma_private->substream->pcm->card->dev, 224 "DMA transmit error (controller=%u channel=%u irq=%u\n", 225 dma_private->controller_id, 226 dma_private->channel_id, irq); 227 fsl_dma_abort_stream(dma_private->substream); 228 sr2 |= CCSR_DMA_SR_TE; 229 ret = IRQ_HANDLED; 230 } 231 232 if (sr & CCSR_DMA_SR_CH) 233 ret = IRQ_HANDLED; 234 235 if (sr & CCSR_DMA_SR_PE) { 236 dev_err(dma_private->substream->pcm->card->dev, 237 "DMA%u programming error (channel=%u irq=%u)\n", 238 dma_private->controller_id, 239 dma_private->channel_id, irq); 240 fsl_dma_abort_stream(dma_private->substream); 241 sr2 |= CCSR_DMA_SR_PE; 242 ret = IRQ_HANDLED; 243 } 244 245 if (sr & CCSR_DMA_SR_EOLNI) { 246 sr2 |= CCSR_DMA_SR_EOLNI; 247 ret = IRQ_HANDLED; 248 } 249 250 if (sr & CCSR_DMA_SR_CB) 251 ret = IRQ_HANDLED; 252 253 if (sr & CCSR_DMA_SR_EOSI) { 254 struct snd_pcm_substream *substream = dma_private->substream; 255 256 /* Tell ALSA we completed a period. */ 257 snd_pcm_period_elapsed(substream); 258 259 /* 260 * Update our link descriptors to point to the next period. We 261 * only need to do this if the number of periods is not equal to 262 * the number of links. 263 */ 264 if (dma_private->num_periods != NUM_DMA_LINKS) 265 fsl_dma_update_pointers(dma_private); 266 267 sr2 |= CCSR_DMA_SR_EOSI; 268 ret = IRQ_HANDLED; 269 } 270 271 if (sr & CCSR_DMA_SR_EOLSI) { 272 sr2 |= CCSR_DMA_SR_EOLSI; 273 ret = IRQ_HANDLED; 274 } 275 276 /* Clear the bits that we set */ 277 if (sr2) 278 out_be32(&dma_channel->sr, sr2); 279 280 return ret; 281 } 282 283 /** 284 * fsl_dma_new: initialize this PCM driver. 285 * 286 * This function is called when the codec driver calls snd_soc_new_pcms(), 287 * once for each .dai_link in the machine driver's snd_soc_card 288 * structure. 289 */ 290 static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai, 291 struct snd_pcm *pcm) 292 { 293 static u64 fsl_dma_dmamask = DMA_BIT_MASK(32); 294 int ret; 295 296 if (!card->dev->dma_mask) 297 card->dev->dma_mask = &fsl_dma_dmamask; 298 299 if (!card->dev->coherent_dma_mask) 300 card->dev->coherent_dma_mask = fsl_dma_dmamask; 301 302 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->dev, 303 fsl_dma_hardware.buffer_bytes_max, 304 &pcm->streams[0].substream->dma_buffer); 305 if (ret) { 306 dev_err(card->dev, 307 "Can't allocate playback DMA buffer (size=%u)\n", 308 fsl_dma_hardware.buffer_bytes_max); 309 return -ENOMEM; 310 } 311 312 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->dev, 313 fsl_dma_hardware.buffer_bytes_max, 314 &pcm->streams[1].substream->dma_buffer); 315 if (ret) { 316 snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer); 317 dev_err(card->dev, 318 "Can't allocate capture DMA buffer (size=%u)\n", 319 fsl_dma_hardware.buffer_bytes_max); 320 return -ENOMEM; 321 } 322 323 return 0; 324 } 325 326 /** 327 * fsl_dma_open: open a new substream. 328 * 329 * Each substream has its own DMA buffer. 330 * 331 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 332 * descriptors that ping-pong from one period to the next. For example, if 333 * there are six periods and two link descriptors, this is how they look 334 * before playback starts: 335 * 336 * The last link descriptor 337 * ____________ points back to the first 338 * | | 339 * V | 340 * ___ ___ | 341 * | |->| |->| 342 * |___| |___| 343 * | | 344 * | | 345 * V V 346 * _________________________________________ 347 * | | | | | | | The DMA buffer is 348 * | | | | | | | divided into 6 parts 349 * |______|______|______|______|______|______| 350 * 351 * and here's how they look after the first period is finished playing: 352 * 353 * ____________ 354 * | | 355 * V | 356 * ___ ___ | 357 * | |->| |->| 358 * |___| |___| 359 * | | 360 * |______________ 361 * | | 362 * V V 363 * _________________________________________ 364 * | | | | | | | 365 * | | | | | | | 366 * |______|______|______|______|______|______| 367 * 368 * The first link descriptor now points to the third period. The DMA 369 * controller is currently playing the second period. When it finishes, it 370 * will jump back to the first descriptor and play the third period. 371 * 372 * There are four reasons we do this: 373 * 374 * 1. The only way to get the DMA controller to automatically restart the 375 * transfer when it gets to the end of the buffer is to use chaining 376 * mode. Basic direct mode doesn't offer that feature. 377 * 2. We need to receive an interrupt at the end of every period. The DMA 378 * controller can generate an interrupt at the end of every link transfer 379 * (aka segment). Making each period into a DMA segment will give us the 380 * interrupts we need. 381 * 3. By creating only two link descriptors, regardless of the number of 382 * periods, we do not need to reallocate the link descriptors if the 383 * number of periods changes. 384 * 4. All of the audio data is still stored in a single, contiguous DMA 385 * buffer, which is what ALSA expects. We're just dividing it into 386 * contiguous parts, and creating a link descriptor for each one. 387 */ 388 static int fsl_dma_open(struct snd_pcm_substream *substream) 389 { 390 struct snd_pcm_runtime *runtime = substream->runtime; 391 struct fsl_dma_private *dma_private; 392 struct ccsr_dma_channel __iomem *dma_channel; 393 dma_addr_t ld_buf_phys; 394 u64 temp_link; /* Pointer to next link descriptor */ 395 u32 mr; 396 unsigned int channel; 397 int ret = 0; 398 unsigned int i; 399 400 /* 401 * Reject any DMA buffer whose size is not a multiple of the period 402 * size. We need to make sure that the DMA buffer can be evenly divided 403 * into periods. 404 */ 405 ret = snd_pcm_hw_constraint_integer(runtime, 406 SNDRV_PCM_HW_PARAM_PERIODS); 407 if (ret < 0) { 408 dev_err(substream->pcm->card->dev, "invalid buffer size\n"); 409 return ret; 410 } 411 412 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 413 414 if (dma_global_data.assigned[channel]) { 415 dev_err(substream->pcm->card->dev, 416 "DMA channel already assigned\n"); 417 return -EBUSY; 418 } 419 420 dma_private = dma_alloc_coherent(substream->pcm->dev, 421 sizeof(struct fsl_dma_private), &ld_buf_phys, GFP_KERNEL); 422 if (!dma_private) { 423 dev_err(substream->pcm->card->dev, 424 "can't allocate DMA private data\n"); 425 return -ENOMEM; 426 } 427 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 428 dma_private->ssi_sxx_phys = dma_global_data.ssi_stx_phys; 429 else 430 dma_private->ssi_sxx_phys = dma_global_data.ssi_srx_phys; 431 432 dma_private->dma_channel = dma_global_data.dma_channel[channel]; 433 dma_private->irq = dma_global_data.irq[channel]; 434 dma_private->substream = substream; 435 dma_private->ld_buf_phys = ld_buf_phys; 436 dma_private->dma_buf_phys = substream->dma_buffer.addr; 437 438 /* We only support one DMA controller for now */ 439 dma_private->controller_id = 0; 440 dma_private->channel_id = channel; 441 442 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private); 443 if (ret) { 444 dev_err(substream->pcm->card->dev, 445 "can't register ISR for IRQ %u (ret=%i)\n", 446 dma_private->irq, ret); 447 dma_free_coherent(substream->pcm->dev, 448 sizeof(struct fsl_dma_private), 449 dma_private, dma_private->ld_buf_phys); 450 return ret; 451 } 452 453 dma_global_data.assigned[channel] = 1; 454 455 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 456 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 457 runtime->private_data = dma_private; 458 459 /* Program the fixed DMA controller parameters */ 460 461 dma_channel = dma_private->dma_channel; 462 463 temp_link = dma_private->ld_buf_phys + 464 sizeof(struct fsl_dma_link_descriptor); 465 466 for (i = 0; i < NUM_DMA_LINKS; i++) { 467 dma_private->link[i].next = cpu_to_be64(temp_link); 468 469 temp_link += sizeof(struct fsl_dma_link_descriptor); 470 } 471 /* The last link descriptor points to the first */ 472 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 473 474 /* Tell the DMA controller where the first link descriptor is */ 475 out_be32(&dma_channel->clndar, 476 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 477 out_be32(&dma_channel->eclndar, 478 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 479 480 /* The manual says the BCR must be clear before enabling EMP */ 481 out_be32(&dma_channel->bcr, 0); 482 483 /* 484 * Program the mode register for interrupts, external master control, 485 * and source/destination hold. Also clear the Channel Abort bit. 486 */ 487 mr = in_be32(&dma_channel->mr) & 488 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 489 490 /* 491 * We want External Master Start and External Master Pause enabled, 492 * because the SSI is controlling the DMA controller. We want the DMA 493 * controller to be set up in advance, and then we signal only the SSI 494 * to start transferring. 495 * 496 * We want End-Of-Segment Interrupts enabled, because this will generate 497 * an interrupt at the end of each segment (each link descriptor 498 * represents one segment). Each DMA segment is the same thing as an 499 * ALSA period, so this is how we get an interrupt at the end of every 500 * period. 501 * 502 * We want Error Interrupt enabled, so that we can get an error if 503 * the DMA controller is mis-programmed somehow. 504 */ 505 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 506 CCSR_DMA_MR_EMS_EN; 507 508 /* For playback, we want the destination address to be held. For 509 capture, set the source address to be held. */ 510 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 511 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 512 513 out_be32(&dma_channel->mr, mr); 514 515 return 0; 516 } 517 518 /** 519 * fsl_dma_hw_params: continue initializing the DMA links 520 * 521 * This function obtains hardware parameters about the opened stream and 522 * programs the DMA controller accordingly. 523 * 524 * One drawback of big-endian is that when copying integers of different 525 * sizes to a fixed-sized register, the address to which the integer must be 526 * copied is dependent on the size of the integer. 527 * 528 * For example, if P is the address of a 32-bit register, and X is a 32-bit 529 * integer, then X should be copied to address P. However, if X is a 16-bit 530 * integer, then it should be copied to P+2. If X is an 8-bit register, 531 * then it should be copied to P+3. 532 * 533 * So for playback of 8-bit samples, the DMA controller must transfer single 534 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 535 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 536 * 537 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 538 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 539 * and 8 bytes at a time). So we do not support packed 24-bit samples. 540 * 24-bit data must be padded to 32 bits. 541 */ 542 static int fsl_dma_hw_params(struct snd_pcm_substream *substream, 543 struct snd_pcm_hw_params *hw_params) 544 { 545 struct snd_pcm_runtime *runtime = substream->runtime; 546 struct fsl_dma_private *dma_private = runtime->private_data; 547 548 /* Number of bits per sample */ 549 unsigned int sample_size = 550 snd_pcm_format_physical_width(params_format(hw_params)); 551 552 /* Number of bytes per frame */ 553 unsigned int frame_size = 2 * (sample_size / 8); 554 555 /* Bus address of SSI STX register */ 556 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; 557 558 /* Size of the DMA buffer, in bytes */ 559 size_t buffer_size = params_buffer_bytes(hw_params); 560 561 /* Number of bytes per period */ 562 size_t period_size = params_period_bytes(hw_params); 563 564 /* Pointer to next period */ 565 dma_addr_t temp_addr = substream->dma_buffer.addr; 566 567 /* Pointer to DMA controller */ 568 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 569 570 u32 mr; /* DMA Mode Register */ 571 572 unsigned int i; 573 574 /* Initialize our DMA tracking variables */ 575 dma_private->period_size = period_size; 576 dma_private->num_periods = params_periods(hw_params); 577 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 578 dma_private->dma_buf_next = dma_private->dma_buf_phys + 579 (NUM_DMA_LINKS * period_size); 580 581 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 582 /* This happens if the number of periods == NUM_DMA_LINKS */ 583 dma_private->dma_buf_next = dma_private->dma_buf_phys; 584 585 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 586 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 587 588 /* Due to a quirk of the SSI's STX register, the target address 589 * for the DMA operations depends on the sample size. So we calculate 590 * that offset here. While we're at it, also tell the DMA controller 591 * how much data to transfer per sample. 592 */ 593 switch (sample_size) { 594 case 8: 595 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 596 ssi_sxx_phys += 3; 597 break; 598 case 16: 599 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 600 ssi_sxx_phys += 2; 601 break; 602 case 32: 603 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 604 break; 605 default: 606 /* We should never get here */ 607 dev_err(substream->pcm->card->dev, 608 "unsupported sample size %u\n", sample_size); 609 return -EINVAL; 610 } 611 612 /* 613 * BWC should always be a multiple of the frame size. BWC determines 614 * how many bytes are sent/received before the DMA controller checks the 615 * SSI to see if it needs to stop. For playback, the transmit FIFO can 616 * hold three frames, so we want to send two frames at a time. For 617 * capture, the receive FIFO is triggered when it contains one frame, so 618 * we want to receive one frame at a time. 619 */ 620 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 621 mr |= CCSR_DMA_MR_BWC(2 * frame_size); 622 else 623 mr |= CCSR_DMA_MR_BWC(frame_size); 624 625 out_be32(&dma_channel->mr, mr); 626 627 for (i = 0; i < NUM_DMA_LINKS; i++) { 628 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 629 630 link->count = cpu_to_be32(period_size); 631 632 /* Even though the DMA controller supports 36-bit addressing, 633 * for simplicity we allow only 32-bit addresses for the audio 634 * buffer itself. This was enforced in fsl_dma_new() with the 635 * DMA mask. 636 * 637 * The snoop bit tells the DMA controller whether it should tell 638 * the ECM to snoop during a read or write to an address. For 639 * audio, we use DMA to transfer data between memory and an I/O 640 * device (the SSI's STX0 or SRX0 register). Snooping is only 641 * needed if there is a cache, so we need to snoop memory 642 * addresses only. For playback, that means we snoop the source 643 * but not the destination. For capture, we snoop the 644 * destination but not the source. 645 * 646 * Note that failing to snoop properly is unlikely to cause 647 * cache incoherency if the period size is larger than the 648 * size of L1 cache. This is because filling in one period will 649 * flush out the data for the previous period. So if you 650 * increased period_bytes_min to a large enough size, you might 651 * get more performance by not snooping, and you'll still be 652 * okay. 653 */ 654 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 655 link->source_addr = cpu_to_be32(temp_addr); 656 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); 657 658 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 659 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP); 660 } else { 661 link->source_addr = cpu_to_be32(ssi_sxx_phys); 662 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP); 663 664 link->dest_addr = cpu_to_be32(temp_addr); 665 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); 666 } 667 668 temp_addr += period_size; 669 } 670 671 return 0; 672 } 673 674 /** 675 * fsl_dma_pointer: determine the current position of the DMA transfer 676 * 677 * This function is called by ALSA when ALSA wants to know where in the 678 * stream buffer the hardware currently is. 679 * 680 * For playback, the SAR register contains the physical address of the most 681 * recent DMA transfer. For capture, the value is in the DAR register. 682 * 683 * The base address of the buffer is stored in the source_addr field of the 684 * first link descriptor. 685 */ 686 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream) 687 { 688 struct snd_pcm_runtime *runtime = substream->runtime; 689 struct fsl_dma_private *dma_private = runtime->private_data; 690 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 691 dma_addr_t position; 692 snd_pcm_uframes_t frames; 693 694 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 695 position = in_be32(&dma_channel->sar); 696 else 697 position = in_be32(&dma_channel->dar); 698 699 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 700 701 /* 702 * If the current address is just past the end of the buffer, wrap it 703 * around. 704 */ 705 if (frames == runtime->buffer_size) 706 frames = 0; 707 708 return frames; 709 } 710 711 /** 712 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 713 * 714 * Release the resources allocated in fsl_dma_hw_params() and de-program the 715 * registers. 716 * 717 * This function can be called multiple times. 718 */ 719 static int fsl_dma_hw_free(struct snd_pcm_substream *substream) 720 { 721 struct snd_pcm_runtime *runtime = substream->runtime; 722 struct fsl_dma_private *dma_private = runtime->private_data; 723 724 if (dma_private) { 725 struct ccsr_dma_channel __iomem *dma_channel; 726 727 dma_channel = dma_private->dma_channel; 728 729 /* Stop the DMA */ 730 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 731 out_be32(&dma_channel->mr, 0); 732 733 /* Reset all the other registers */ 734 out_be32(&dma_channel->sr, -1); 735 out_be32(&dma_channel->clndar, 0); 736 out_be32(&dma_channel->eclndar, 0); 737 out_be32(&dma_channel->satr, 0); 738 out_be32(&dma_channel->sar, 0); 739 out_be32(&dma_channel->datr, 0); 740 out_be32(&dma_channel->dar, 0); 741 out_be32(&dma_channel->bcr, 0); 742 out_be32(&dma_channel->nlndar, 0); 743 out_be32(&dma_channel->enlndar, 0); 744 } 745 746 return 0; 747 } 748 749 /** 750 * fsl_dma_close: close the stream. 751 */ 752 static int fsl_dma_close(struct snd_pcm_substream *substream) 753 { 754 struct snd_pcm_runtime *runtime = substream->runtime; 755 struct fsl_dma_private *dma_private = runtime->private_data; 756 int dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 757 758 if (dma_private) { 759 if (dma_private->irq) 760 free_irq(dma_private->irq, dma_private); 761 762 if (dma_private->ld_buf_phys) { 763 dma_unmap_single(substream->pcm->dev, 764 dma_private->ld_buf_phys, 765 sizeof(dma_private->link), DMA_TO_DEVICE); 766 } 767 768 /* Deallocate the fsl_dma_private structure */ 769 dma_free_coherent(substream->pcm->dev, 770 sizeof(struct fsl_dma_private), 771 dma_private, dma_private->ld_buf_phys); 772 substream->runtime->private_data = NULL; 773 } 774 775 dma_global_data.assigned[dir] = 0; 776 777 return 0; 778 } 779 780 /* 781 * Remove this PCM driver. 782 */ 783 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm) 784 { 785 struct snd_pcm_substream *substream; 786 unsigned int i; 787 788 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 789 substream = pcm->streams[i].substream; 790 if (substream) { 791 snd_dma_free_pages(&substream->dma_buffer); 792 substream->dma_buffer.area = NULL; 793 substream->dma_buffer.addr = 0; 794 } 795 } 796 } 797 798 static struct snd_pcm_ops fsl_dma_ops = { 799 .open = fsl_dma_open, 800 .close = fsl_dma_close, 801 .ioctl = snd_pcm_lib_ioctl, 802 .hw_params = fsl_dma_hw_params, 803 .hw_free = fsl_dma_hw_free, 804 .pointer = fsl_dma_pointer, 805 }; 806 807 struct snd_soc_platform fsl_soc_platform = { 808 .name = "fsl-dma", 809 .pcm_ops = &fsl_dma_ops, 810 .pcm_new = fsl_dma_new, 811 .pcm_free = fsl_dma_free_dma_buffers, 812 }; 813 EXPORT_SYMBOL_GPL(fsl_soc_platform); 814 815 /** 816 * fsl_dma_configure: store the DMA parameters from the fabric driver. 817 * 818 * This function is called by the ASoC fabric driver to give us the DMA and 819 * SSI channel information. 820 * 821 * Unfortunately, ASoC V1 does make it possible to determine the DMA/SSI 822 * data when a substream is created, so for now we need to store this data 823 * into a global variable. This means that we can only support one DMA 824 * controller, and hence only one SSI. 825 */ 826 int fsl_dma_configure(struct fsl_dma_info *dma_info) 827 { 828 static int initialized; 829 830 /* We only support one DMA controller for now */ 831 if (initialized) 832 return 0; 833 834 dma_global_data.ssi_stx_phys = dma_info->ssi_stx_phys; 835 dma_global_data.ssi_srx_phys = dma_info->ssi_srx_phys; 836 dma_global_data.dma_channel[0] = dma_info->dma_channel[0]; 837 dma_global_data.dma_channel[1] = dma_info->dma_channel[1]; 838 dma_global_data.irq[0] = dma_info->dma_irq[0]; 839 dma_global_data.irq[1] = dma_info->dma_irq[1]; 840 dma_global_data.assigned[0] = 0; 841 dma_global_data.assigned[1] = 0; 842 843 initialized = 1; 844 return 1; 845 } 846 EXPORT_SYMBOL_GPL(fsl_dma_configure); 847 848 static int __init fsl_soc_platform_init(void) 849 { 850 return snd_soc_register_platform(&fsl_soc_platform); 851 } 852 module_init(fsl_soc_platform_init); 853 854 static void __exit fsl_soc_platform_exit(void) 855 { 856 snd_soc_unregister_platform(&fsl_soc_platform); 857 } 858 module_exit(fsl_soc_platform_exit); 859 860 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 861 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM module"); 862 MODULE_LICENSE("GPL"); 863