1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale DMA ALSA SoC PCM driver 4 // 5 // Author: Timur Tabi <timur@freescale.com> 6 // 7 // Copyright 2007-2010 Freescale Semiconductor, Inc. 8 // 9 // This driver implements ASoC support for the Elo DMA controller, which is 10 // the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 11 // the PCM driver is what handles the DMA buffer. 12 13 #include <linux/module.h> 14 #include <linux/init.h> 15 #include <linux/platform_device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/interrupt.h> 18 #include <linux/delay.h> 19 #include <linux/gfp.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_platform.h> 23 #include <linux/list.h> 24 #include <linux/slab.h> 25 26 #include <sound/core.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 31 #include <asm/io.h> 32 33 #include "fsl_dma.h" 34 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */ 35 36 #define DRV_NAME "fsl_dma" 37 38 /* 39 * The formats that the DMA controller supports, which is anything 40 * that is 8, 16, or 32 bits. 41 */ 42 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 43 SNDRV_PCM_FMTBIT_U8 | \ 44 SNDRV_PCM_FMTBIT_S16_LE | \ 45 SNDRV_PCM_FMTBIT_S16_BE | \ 46 SNDRV_PCM_FMTBIT_U16_LE | \ 47 SNDRV_PCM_FMTBIT_U16_BE | \ 48 SNDRV_PCM_FMTBIT_S24_LE | \ 49 SNDRV_PCM_FMTBIT_S24_BE | \ 50 SNDRV_PCM_FMTBIT_U24_LE | \ 51 SNDRV_PCM_FMTBIT_U24_BE | \ 52 SNDRV_PCM_FMTBIT_S32_LE | \ 53 SNDRV_PCM_FMTBIT_S32_BE | \ 54 SNDRV_PCM_FMTBIT_U32_LE | \ 55 SNDRV_PCM_FMTBIT_U32_BE) 56 struct dma_object { 57 struct snd_soc_component_driver dai; 58 dma_addr_t ssi_stx_phys; 59 dma_addr_t ssi_srx_phys; 60 unsigned int ssi_fifo_depth; 61 struct ccsr_dma_channel __iomem *channel; 62 unsigned int irq; 63 bool assigned; 64 }; 65 66 /* 67 * The number of DMA links to use. Two is the bare minimum, but if you 68 * have really small links you might need more. 69 */ 70 #define NUM_DMA_LINKS 2 71 72 /** fsl_dma_private: p-substream DMA data 73 * 74 * Each substream has a 1-to-1 association with a DMA channel. 75 * 76 * The link[] array is first because it needs to be aligned on a 32-byte 77 * boundary, so putting it first will ensure alignment without padding the 78 * structure. 79 * 80 * @link[]: array of link descriptors 81 * @dma_channel: pointer to the DMA channel's registers 82 * @irq: IRQ for this DMA channel 83 * @substream: pointer to the substream object, needed by the ISR 84 * @ssi_sxx_phys: bus address of the STX or SRX register to use 85 * @ld_buf_phys: physical address of the LD buffer 86 * @current_link: index into link[] of the link currently being processed 87 * @dma_buf_phys: physical address of the DMA buffer 88 * @dma_buf_next: physical address of the next period to process 89 * @dma_buf_end: physical address of the byte after the end of the DMA 90 * @buffer period_size: the size of a single period 91 * @num_periods: the number of periods in the DMA buffer 92 */ 93 struct fsl_dma_private { 94 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 95 struct ccsr_dma_channel __iomem *dma_channel; 96 unsigned int irq; 97 struct snd_pcm_substream *substream; 98 dma_addr_t ssi_sxx_phys; 99 unsigned int ssi_fifo_depth; 100 dma_addr_t ld_buf_phys; 101 unsigned int current_link; 102 dma_addr_t dma_buf_phys; 103 dma_addr_t dma_buf_next; 104 dma_addr_t dma_buf_end; 105 size_t period_size; 106 unsigned int num_periods; 107 }; 108 109 /** 110 * fsl_dma_hardare: define characteristics of the PCM hardware. 111 * 112 * The PCM hardware is the Freescale DMA controller. This structure defines 113 * the capabilities of that hardware. 114 * 115 * Since the sampling rate and data format are not controlled by the DMA 116 * controller, we specify no limits for those values. The only exception is 117 * period_bytes_min, which is set to a reasonably low value to prevent the 118 * DMA controller from generating too many interrupts per second. 119 * 120 * Since each link descriptor has a 32-bit byte count field, we set 121 * period_bytes_max to the largest 32-bit number. We also have no maximum 122 * number of periods. 123 * 124 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a 125 * limitation in the SSI driver requires the sample rates for playback and 126 * capture to be the same. 127 */ 128 static const struct snd_pcm_hardware fsl_dma_hardware = { 129 130 .info = SNDRV_PCM_INFO_INTERLEAVED | 131 SNDRV_PCM_INFO_MMAP | 132 SNDRV_PCM_INFO_MMAP_VALID | 133 SNDRV_PCM_INFO_JOINT_DUPLEX | 134 SNDRV_PCM_INFO_PAUSE, 135 .formats = FSLDMA_PCM_FORMATS, 136 .period_bytes_min = 512, /* A reasonable limit */ 137 .period_bytes_max = (u32) -1, 138 .periods_min = NUM_DMA_LINKS, 139 .periods_max = (unsigned int) -1, 140 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 141 }; 142 143 /** 144 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 145 * 146 * This function should be called by the ISR whenever the DMA controller 147 * halts data transfer. 148 */ 149 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 150 { 151 snd_pcm_stop_xrun(substream); 152 } 153 154 /** 155 * fsl_dma_update_pointers - update LD pointers to point to the next period 156 * 157 * As each period is completed, this function changes the link 158 * descriptor pointers for that period to point to the next period. 159 */ 160 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 161 { 162 struct fsl_dma_link_descriptor *link = 163 &dma_private->link[dma_private->current_link]; 164 165 /* Update our link descriptors to point to the next period. On a 36-bit 166 * system, we also need to update the ESAD bits. We also set (keep) the 167 * snoop bits. See the comments in fsl_dma_hw_params() about snooping. 168 */ 169 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 170 link->source_addr = cpu_to_be32(dma_private->dma_buf_next); 171 #ifdef CONFIG_PHYS_64BIT 172 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 173 upper_32_bits(dma_private->dma_buf_next)); 174 #endif 175 } else { 176 link->dest_addr = cpu_to_be32(dma_private->dma_buf_next); 177 #ifdef CONFIG_PHYS_64BIT 178 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 179 upper_32_bits(dma_private->dma_buf_next)); 180 #endif 181 } 182 183 /* Update our variables for next time */ 184 dma_private->dma_buf_next += dma_private->period_size; 185 186 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 187 dma_private->dma_buf_next = dma_private->dma_buf_phys; 188 189 if (++dma_private->current_link >= NUM_DMA_LINKS) 190 dma_private->current_link = 0; 191 } 192 193 /** 194 * fsl_dma_isr: interrupt handler for the DMA controller 195 * 196 * @irq: IRQ of the DMA channel 197 * @dev_id: pointer to the dma_private structure for this DMA channel 198 */ 199 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 200 { 201 struct fsl_dma_private *dma_private = dev_id; 202 struct snd_pcm_substream *substream = dma_private->substream; 203 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 204 struct device *dev = rtd->dev; 205 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 206 irqreturn_t ret = IRQ_NONE; 207 u32 sr, sr2 = 0; 208 209 /* We got an interrupt, so read the status register to see what we 210 were interrupted for. 211 */ 212 sr = in_be32(&dma_channel->sr); 213 214 if (sr & CCSR_DMA_SR_TE) { 215 dev_err(dev, "dma transmit error\n"); 216 fsl_dma_abort_stream(substream); 217 sr2 |= CCSR_DMA_SR_TE; 218 ret = IRQ_HANDLED; 219 } 220 221 if (sr & CCSR_DMA_SR_CH) 222 ret = IRQ_HANDLED; 223 224 if (sr & CCSR_DMA_SR_PE) { 225 dev_err(dev, "dma programming error\n"); 226 fsl_dma_abort_stream(substream); 227 sr2 |= CCSR_DMA_SR_PE; 228 ret = IRQ_HANDLED; 229 } 230 231 if (sr & CCSR_DMA_SR_EOLNI) { 232 sr2 |= CCSR_DMA_SR_EOLNI; 233 ret = IRQ_HANDLED; 234 } 235 236 if (sr & CCSR_DMA_SR_CB) 237 ret = IRQ_HANDLED; 238 239 if (sr & CCSR_DMA_SR_EOSI) { 240 /* Tell ALSA we completed a period. */ 241 snd_pcm_period_elapsed(substream); 242 243 /* 244 * Update our link descriptors to point to the next period. We 245 * only need to do this if the number of periods is not equal to 246 * the number of links. 247 */ 248 if (dma_private->num_periods != NUM_DMA_LINKS) 249 fsl_dma_update_pointers(dma_private); 250 251 sr2 |= CCSR_DMA_SR_EOSI; 252 ret = IRQ_HANDLED; 253 } 254 255 if (sr & CCSR_DMA_SR_EOLSI) { 256 sr2 |= CCSR_DMA_SR_EOLSI; 257 ret = IRQ_HANDLED; 258 } 259 260 /* Clear the bits that we set */ 261 if (sr2) 262 out_be32(&dma_channel->sr, sr2); 263 264 return ret; 265 } 266 267 /** 268 * fsl_dma_new: initialize this PCM driver. 269 * 270 * This function is called when the codec driver calls snd_soc_new_pcms(), 271 * once for each .dai_link in the machine driver's snd_soc_card 272 * structure. 273 * 274 * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which 275 * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM 276 * is specified. Therefore, any DMA buffers we allocate will always be in low 277 * memory, but we support for 36-bit physical addresses anyway. 278 * 279 * Regardless of where the memory is actually allocated, since the device can 280 * technically DMA to any 36-bit address, we do need to set the DMA mask to 36. 281 */ 282 static int fsl_dma_new(struct snd_soc_component *component, 283 struct snd_soc_pcm_runtime *rtd) 284 { 285 struct snd_card *card = rtd->card->snd_card; 286 struct snd_pcm *pcm = rtd->pcm; 287 int ret; 288 289 ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(36)); 290 if (ret) 291 return ret; 292 293 /* Some codecs have separate DAIs for playback and capture, so we 294 * should allocate a DMA buffer only for the streams that are valid. 295 */ 296 297 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) { 298 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 299 fsl_dma_hardware.buffer_bytes_max, 300 &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer); 301 if (ret) { 302 dev_err(card->dev, "can't alloc playback dma buffer\n"); 303 return ret; 304 } 305 } 306 307 if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) { 308 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 309 fsl_dma_hardware.buffer_bytes_max, 310 &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer); 311 if (ret) { 312 dev_err(card->dev, "can't alloc capture dma buffer\n"); 313 snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer); 314 return ret; 315 } 316 } 317 318 return 0; 319 } 320 321 /** 322 * fsl_dma_open: open a new substream. 323 * 324 * Each substream has its own DMA buffer. 325 * 326 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 327 * descriptors that ping-pong from one period to the next. For example, if 328 * there are six periods and two link descriptors, this is how they look 329 * before playback starts: 330 * 331 * The last link descriptor 332 * ____________ points back to the first 333 * | | 334 * V | 335 * ___ ___ | 336 * | |->| |->| 337 * |___| |___| 338 * | | 339 * | | 340 * V V 341 * _________________________________________ 342 * | | | | | | | The DMA buffer is 343 * | | | | | | | divided into 6 parts 344 * |______|______|______|______|______|______| 345 * 346 * and here's how they look after the first period is finished playing: 347 * 348 * ____________ 349 * | | 350 * V | 351 * ___ ___ | 352 * | |->| |->| 353 * |___| |___| 354 * | | 355 * |______________ 356 * | | 357 * V V 358 * _________________________________________ 359 * | | | | | | | 360 * | | | | | | | 361 * |______|______|______|______|______|______| 362 * 363 * The first link descriptor now points to the third period. The DMA 364 * controller is currently playing the second period. When it finishes, it 365 * will jump back to the first descriptor and play the third period. 366 * 367 * There are four reasons we do this: 368 * 369 * 1. The only way to get the DMA controller to automatically restart the 370 * transfer when it gets to the end of the buffer is to use chaining 371 * mode. Basic direct mode doesn't offer that feature. 372 * 2. We need to receive an interrupt at the end of every period. The DMA 373 * controller can generate an interrupt at the end of every link transfer 374 * (aka segment). Making each period into a DMA segment will give us the 375 * interrupts we need. 376 * 3. By creating only two link descriptors, regardless of the number of 377 * periods, we do not need to reallocate the link descriptors if the 378 * number of periods changes. 379 * 4. All of the audio data is still stored in a single, contiguous DMA 380 * buffer, which is what ALSA expects. We're just dividing it into 381 * contiguous parts, and creating a link descriptor for each one. 382 */ 383 static int fsl_dma_open(struct snd_soc_component *component, 384 struct snd_pcm_substream *substream) 385 { 386 struct snd_pcm_runtime *runtime = substream->runtime; 387 struct device *dev = component->dev; 388 struct dma_object *dma = 389 container_of(component->driver, struct dma_object, dai); 390 struct fsl_dma_private *dma_private; 391 struct ccsr_dma_channel __iomem *dma_channel; 392 dma_addr_t ld_buf_phys; 393 u64 temp_link; /* Pointer to next link descriptor */ 394 u32 mr; 395 int ret = 0; 396 unsigned int i; 397 398 /* 399 * Reject any DMA buffer whose size is not a multiple of the period 400 * size. We need to make sure that the DMA buffer can be evenly divided 401 * into periods. 402 */ 403 ret = snd_pcm_hw_constraint_integer(runtime, 404 SNDRV_PCM_HW_PARAM_PERIODS); 405 if (ret < 0) { 406 dev_err(dev, "invalid buffer size\n"); 407 return ret; 408 } 409 410 if (dma->assigned) { 411 dev_err(dev, "dma channel already assigned\n"); 412 return -EBUSY; 413 } 414 415 dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private), 416 &ld_buf_phys, GFP_KERNEL); 417 if (!dma_private) { 418 dev_err(dev, "can't allocate dma private data\n"); 419 return -ENOMEM; 420 } 421 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 422 dma_private->ssi_sxx_phys = dma->ssi_stx_phys; 423 else 424 dma_private->ssi_sxx_phys = dma->ssi_srx_phys; 425 426 dma_private->ssi_fifo_depth = dma->ssi_fifo_depth; 427 dma_private->dma_channel = dma->channel; 428 dma_private->irq = dma->irq; 429 dma_private->substream = substream; 430 dma_private->ld_buf_phys = ld_buf_phys; 431 dma_private->dma_buf_phys = substream->dma_buffer.addr; 432 433 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio", 434 dma_private); 435 if (ret) { 436 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 437 dma_private->irq, ret); 438 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 439 dma_private, dma_private->ld_buf_phys); 440 return ret; 441 } 442 443 dma->assigned = true; 444 445 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 446 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 447 runtime->private_data = dma_private; 448 449 /* Program the fixed DMA controller parameters */ 450 451 dma_channel = dma_private->dma_channel; 452 453 temp_link = dma_private->ld_buf_phys + 454 sizeof(struct fsl_dma_link_descriptor); 455 456 for (i = 0; i < NUM_DMA_LINKS; i++) { 457 dma_private->link[i].next = cpu_to_be64(temp_link); 458 459 temp_link += sizeof(struct fsl_dma_link_descriptor); 460 } 461 /* The last link descriptor points to the first */ 462 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 463 464 /* Tell the DMA controller where the first link descriptor is */ 465 out_be32(&dma_channel->clndar, 466 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 467 out_be32(&dma_channel->eclndar, 468 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 469 470 /* The manual says the BCR must be clear before enabling EMP */ 471 out_be32(&dma_channel->bcr, 0); 472 473 /* 474 * Program the mode register for interrupts, external master control, 475 * and source/destination hold. Also clear the Channel Abort bit. 476 */ 477 mr = in_be32(&dma_channel->mr) & 478 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 479 480 /* 481 * We want External Master Start and External Master Pause enabled, 482 * because the SSI is controlling the DMA controller. We want the DMA 483 * controller to be set up in advance, and then we signal only the SSI 484 * to start transferring. 485 * 486 * We want End-Of-Segment Interrupts enabled, because this will generate 487 * an interrupt at the end of each segment (each link descriptor 488 * represents one segment). Each DMA segment is the same thing as an 489 * ALSA period, so this is how we get an interrupt at the end of every 490 * period. 491 * 492 * We want Error Interrupt enabled, so that we can get an error if 493 * the DMA controller is mis-programmed somehow. 494 */ 495 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 496 CCSR_DMA_MR_EMS_EN; 497 498 /* For playback, we want the destination address to be held. For 499 capture, set the source address to be held. */ 500 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 501 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 502 503 out_be32(&dma_channel->mr, mr); 504 505 return 0; 506 } 507 508 /** 509 * fsl_dma_hw_params: continue initializing the DMA links 510 * 511 * This function obtains hardware parameters about the opened stream and 512 * programs the DMA controller accordingly. 513 * 514 * One drawback of big-endian is that when copying integers of different 515 * sizes to a fixed-sized register, the address to which the integer must be 516 * copied is dependent on the size of the integer. 517 * 518 * For example, if P is the address of a 32-bit register, and X is a 32-bit 519 * integer, then X should be copied to address P. However, if X is a 16-bit 520 * integer, then it should be copied to P+2. If X is an 8-bit register, 521 * then it should be copied to P+3. 522 * 523 * So for playback of 8-bit samples, the DMA controller must transfer single 524 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 525 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 526 * 527 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 528 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 529 * and 8 bytes at a time). So we do not support packed 24-bit samples. 530 * 24-bit data must be padded to 32 bits. 531 */ 532 static int fsl_dma_hw_params(struct snd_soc_component *component, 533 struct snd_pcm_substream *substream, 534 struct snd_pcm_hw_params *hw_params) 535 { 536 struct snd_pcm_runtime *runtime = substream->runtime; 537 struct fsl_dma_private *dma_private = runtime->private_data; 538 struct device *dev = component->dev; 539 540 /* Number of bits per sample */ 541 unsigned int sample_bits = 542 snd_pcm_format_physical_width(params_format(hw_params)); 543 544 /* Number of bytes per frame */ 545 unsigned int sample_bytes = sample_bits / 8; 546 547 /* Bus address of SSI STX register */ 548 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; 549 550 /* Size of the DMA buffer, in bytes */ 551 size_t buffer_size = params_buffer_bytes(hw_params); 552 553 /* Number of bytes per period */ 554 size_t period_size = params_period_bytes(hw_params); 555 556 /* Pointer to next period */ 557 dma_addr_t temp_addr = substream->dma_buffer.addr; 558 559 /* Pointer to DMA controller */ 560 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 561 562 u32 mr; /* DMA Mode Register */ 563 564 unsigned int i; 565 566 /* Initialize our DMA tracking variables */ 567 dma_private->period_size = period_size; 568 dma_private->num_periods = params_periods(hw_params); 569 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 570 dma_private->dma_buf_next = dma_private->dma_buf_phys + 571 (NUM_DMA_LINKS * period_size); 572 573 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 574 /* This happens if the number of periods == NUM_DMA_LINKS */ 575 dma_private->dma_buf_next = dma_private->dma_buf_phys; 576 577 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 578 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 579 580 /* Due to a quirk of the SSI's STX register, the target address 581 * for the DMA operations depends on the sample size. So we calculate 582 * that offset here. While we're at it, also tell the DMA controller 583 * how much data to transfer per sample. 584 */ 585 switch (sample_bits) { 586 case 8: 587 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 588 ssi_sxx_phys += 3; 589 break; 590 case 16: 591 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 592 ssi_sxx_phys += 2; 593 break; 594 case 32: 595 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 596 break; 597 default: 598 /* We should never get here */ 599 dev_err(dev, "unsupported sample size %u\n", sample_bits); 600 return -EINVAL; 601 } 602 603 /* 604 * BWC determines how many bytes are sent/received before the DMA 605 * controller checks the SSI to see if it needs to stop. BWC should 606 * always be a multiple of the frame size, so that we always transmit 607 * whole frames. Each frame occupies two slots in the FIFO. The 608 * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two 609 * (MR[BWC] can only represent even powers of two). 610 * 611 * To simplify the process, we set BWC to the largest value that is 612 * less than or equal to the FIFO watermark. For playback, this ensures 613 * that we transfer the maximum amount without overrunning the FIFO. 614 * For capture, this ensures that we transfer the maximum amount without 615 * underrunning the FIFO. 616 * 617 * f = SSI FIFO depth 618 * w = SSI watermark value (which equals f - 2) 619 * b = DMA bandwidth count (in bytes) 620 * s = sample size (in bytes, which equals frame_size * 2) 621 * 622 * For playback, we never transmit more than the transmit FIFO 623 * watermark, otherwise we might write more data than the FIFO can hold. 624 * The watermark is equal to the FIFO depth minus two. 625 * 626 * For capture, two equations must hold: 627 * w > f - (b / s) 628 * w >= b / s 629 * 630 * So, b > 2 * s, but b must also be <= s * w. To simplify, we set 631 * b = s * w, which is equal to 632 * (dma_private->ssi_fifo_depth - 2) * sample_bytes. 633 */ 634 mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes); 635 636 out_be32(&dma_channel->mr, mr); 637 638 for (i = 0; i < NUM_DMA_LINKS; i++) { 639 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 640 641 link->count = cpu_to_be32(period_size); 642 643 /* The snoop bit tells the DMA controller whether it should tell 644 * the ECM to snoop during a read or write to an address. For 645 * audio, we use DMA to transfer data between memory and an I/O 646 * device (the SSI's STX0 or SRX0 register). Snooping is only 647 * needed if there is a cache, so we need to snoop memory 648 * addresses only. For playback, that means we snoop the source 649 * but not the destination. For capture, we snoop the 650 * destination but not the source. 651 * 652 * Note that failing to snoop properly is unlikely to cause 653 * cache incoherency if the period size is larger than the 654 * size of L1 cache. This is because filling in one period will 655 * flush out the data for the previous period. So if you 656 * increased period_bytes_min to a large enough size, you might 657 * get more performance by not snooping, and you'll still be 658 * okay. You'll need to update fsl_dma_update_pointers() also. 659 */ 660 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 661 link->source_addr = cpu_to_be32(temp_addr); 662 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 663 upper_32_bits(temp_addr)); 664 665 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 666 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 667 upper_32_bits(ssi_sxx_phys)); 668 } else { 669 link->source_addr = cpu_to_be32(ssi_sxx_phys); 670 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 671 upper_32_bits(ssi_sxx_phys)); 672 673 link->dest_addr = cpu_to_be32(temp_addr); 674 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 675 upper_32_bits(temp_addr)); 676 } 677 678 temp_addr += period_size; 679 } 680 681 return 0; 682 } 683 684 /** 685 * fsl_dma_pointer: determine the current position of the DMA transfer 686 * 687 * This function is called by ALSA when ALSA wants to know where in the 688 * stream buffer the hardware currently is. 689 * 690 * For playback, the SAR register contains the physical address of the most 691 * recent DMA transfer. For capture, the value is in the DAR register. 692 * 693 * The base address of the buffer is stored in the source_addr field of the 694 * first link descriptor. 695 */ 696 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_soc_component *component, 697 struct snd_pcm_substream *substream) 698 { 699 struct snd_pcm_runtime *runtime = substream->runtime; 700 struct fsl_dma_private *dma_private = runtime->private_data; 701 struct device *dev = component->dev; 702 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 703 dma_addr_t position; 704 snd_pcm_uframes_t frames; 705 706 /* Obtain the current DMA pointer, but don't read the ESAD bits if we 707 * only have 32-bit DMA addresses. This function is typically called 708 * in interrupt context, so we need to optimize it. 709 */ 710 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 711 position = in_be32(&dma_channel->sar); 712 #ifdef CONFIG_PHYS_64BIT 713 position |= (u64)(in_be32(&dma_channel->satr) & 714 CCSR_DMA_ATR_ESAD_MASK) << 32; 715 #endif 716 } else { 717 position = in_be32(&dma_channel->dar); 718 #ifdef CONFIG_PHYS_64BIT 719 position |= (u64)(in_be32(&dma_channel->datr) & 720 CCSR_DMA_ATR_ESAD_MASK) << 32; 721 #endif 722 } 723 724 /* 725 * When capture is started, the SSI immediately starts to fill its FIFO. 726 * This means that the DMA controller is not started until the FIFO is 727 * full. However, ALSA calls this function before that happens, when 728 * MR.DAR is still zero. In this case, just return zero to indicate 729 * that nothing has been received yet. 730 */ 731 if (!position) 732 return 0; 733 734 if ((position < dma_private->dma_buf_phys) || 735 (position > dma_private->dma_buf_end)) { 736 dev_err(dev, "dma pointer is out of range, halting stream\n"); 737 return SNDRV_PCM_POS_XRUN; 738 } 739 740 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 741 742 /* 743 * If the current address is just past the end of the buffer, wrap it 744 * around. 745 */ 746 if (frames == runtime->buffer_size) 747 frames = 0; 748 749 return frames; 750 } 751 752 /** 753 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 754 * 755 * Release the resources allocated in fsl_dma_hw_params() and de-program the 756 * registers. 757 * 758 * This function can be called multiple times. 759 */ 760 static int fsl_dma_hw_free(struct snd_soc_component *component, 761 struct snd_pcm_substream *substream) 762 { 763 struct snd_pcm_runtime *runtime = substream->runtime; 764 struct fsl_dma_private *dma_private = runtime->private_data; 765 766 if (dma_private) { 767 struct ccsr_dma_channel __iomem *dma_channel; 768 769 dma_channel = dma_private->dma_channel; 770 771 /* Stop the DMA */ 772 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 773 out_be32(&dma_channel->mr, 0); 774 775 /* Reset all the other registers */ 776 out_be32(&dma_channel->sr, -1); 777 out_be32(&dma_channel->clndar, 0); 778 out_be32(&dma_channel->eclndar, 0); 779 out_be32(&dma_channel->satr, 0); 780 out_be32(&dma_channel->sar, 0); 781 out_be32(&dma_channel->datr, 0); 782 out_be32(&dma_channel->dar, 0); 783 out_be32(&dma_channel->bcr, 0); 784 out_be32(&dma_channel->nlndar, 0); 785 out_be32(&dma_channel->enlndar, 0); 786 } 787 788 return 0; 789 } 790 791 /** 792 * fsl_dma_close: close the stream. 793 */ 794 static int fsl_dma_close(struct snd_soc_component *component, 795 struct snd_pcm_substream *substream) 796 { 797 struct snd_pcm_runtime *runtime = substream->runtime; 798 struct fsl_dma_private *dma_private = runtime->private_data; 799 struct device *dev = component->dev; 800 struct dma_object *dma = 801 container_of(component->driver, struct dma_object, dai); 802 803 if (dma_private) { 804 if (dma_private->irq) 805 free_irq(dma_private->irq, dma_private); 806 807 /* Deallocate the fsl_dma_private structure */ 808 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 809 dma_private, dma_private->ld_buf_phys); 810 substream->runtime->private_data = NULL; 811 } 812 813 dma->assigned = false; 814 815 return 0; 816 } 817 818 /* 819 * Remove this PCM driver. 820 */ 821 static void fsl_dma_free_dma_buffers(struct snd_soc_component *component, 822 struct snd_pcm *pcm) 823 { 824 struct snd_pcm_substream *substream; 825 unsigned int i; 826 827 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 828 substream = pcm->streams[i].substream; 829 if (substream) { 830 snd_dma_free_pages(&substream->dma_buffer); 831 substream->dma_buffer.area = NULL; 832 substream->dma_buffer.addr = 0; 833 } 834 } 835 } 836 837 /** 838 * find_ssi_node -- returns the SSI node that points to its DMA channel node 839 * 840 * Although this DMA driver attempts to operate independently of the other 841 * devices, it still needs to determine some information about the SSI device 842 * that it's working with. Unfortunately, the device tree does not contain 843 * a pointer from the DMA channel node to the SSI node -- the pointer goes the 844 * other way. So we need to scan the device tree for SSI nodes until we find 845 * the one that points to the given DMA channel node. It's ugly, but at least 846 * it's contained in this one function. 847 */ 848 static struct device_node *find_ssi_node(struct device_node *dma_channel_np) 849 { 850 struct device_node *ssi_np, *np; 851 852 for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") { 853 /* Check each DMA phandle to see if it points to us. We 854 * assume that device_node pointers are a valid comparison. 855 */ 856 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0); 857 of_node_put(np); 858 if (np == dma_channel_np) 859 return ssi_np; 860 861 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0); 862 of_node_put(np); 863 if (np == dma_channel_np) 864 return ssi_np; 865 } 866 867 return NULL; 868 } 869 870 static int fsl_soc_dma_probe(struct platform_device *pdev) 871 { 872 struct dma_object *dma; 873 struct device_node *np = pdev->dev.of_node; 874 struct device_node *ssi_np; 875 struct resource res; 876 const uint32_t *iprop; 877 int ret; 878 879 /* Find the SSI node that points to us. */ 880 ssi_np = find_ssi_node(np); 881 if (!ssi_np) { 882 dev_err(&pdev->dev, "cannot find parent SSI node\n"); 883 return -ENODEV; 884 } 885 886 ret = of_address_to_resource(ssi_np, 0, &res); 887 if (ret) { 888 dev_err(&pdev->dev, "could not determine resources for %pOF\n", 889 ssi_np); 890 of_node_put(ssi_np); 891 return ret; 892 } 893 894 dma = kzalloc(sizeof(*dma), GFP_KERNEL); 895 if (!dma) { 896 of_node_put(ssi_np); 897 return -ENOMEM; 898 } 899 900 dma->dai.name = DRV_NAME; 901 dma->dai.open = fsl_dma_open; 902 dma->dai.close = fsl_dma_close; 903 dma->dai.hw_params = fsl_dma_hw_params; 904 dma->dai.hw_free = fsl_dma_hw_free; 905 dma->dai.pointer = fsl_dma_pointer; 906 dma->dai.pcm_construct = fsl_dma_new; 907 dma->dai.pcm_destruct = fsl_dma_free_dma_buffers; 908 909 /* Store the SSI-specific information that we need */ 910 dma->ssi_stx_phys = res.start + REG_SSI_STX0; 911 dma->ssi_srx_phys = res.start + REG_SSI_SRX0; 912 913 iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL); 914 if (iprop) 915 dma->ssi_fifo_depth = be32_to_cpup(iprop); 916 else 917 /* Older 8610 DTs didn't have the fifo-depth property */ 918 dma->ssi_fifo_depth = 8; 919 920 of_node_put(ssi_np); 921 922 ret = devm_snd_soc_register_component(&pdev->dev, &dma->dai, NULL, 0); 923 if (ret) { 924 dev_err(&pdev->dev, "could not register platform\n"); 925 kfree(dma); 926 return ret; 927 } 928 929 dma->channel = of_iomap(np, 0); 930 dma->irq = irq_of_parse_and_map(np, 0); 931 932 dev_set_drvdata(&pdev->dev, dma); 933 934 return 0; 935 } 936 937 static int fsl_soc_dma_remove(struct platform_device *pdev) 938 { 939 struct dma_object *dma = dev_get_drvdata(&pdev->dev); 940 941 iounmap(dma->channel); 942 irq_dispose_mapping(dma->irq); 943 kfree(dma); 944 945 return 0; 946 } 947 948 static const struct of_device_id fsl_soc_dma_ids[] = { 949 { .compatible = "fsl,ssi-dma-channel", }, 950 {} 951 }; 952 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids); 953 954 static struct platform_driver fsl_soc_dma_driver = { 955 .driver = { 956 .name = "fsl-pcm-audio", 957 .of_match_table = fsl_soc_dma_ids, 958 }, 959 .probe = fsl_soc_dma_probe, 960 .remove = fsl_soc_dma_remove, 961 }; 962 963 module_platform_driver(fsl_soc_dma_driver); 964 965 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 966 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver"); 967 MODULE_LICENSE("GPL v2"); 968