1 /* 2 * Freescale DMA ALSA SoC PCM driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2010 Freescale Semiconductor, Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 * 12 * This driver implements ASoC support for the Elo DMA controller, which is 13 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 14 * the PCM driver is what handles the DMA buffer. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/interrupt.h> 22 #include <linux/delay.h> 23 #include <linux/gfp.h> 24 #include <linux/of_address.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_platform.h> 27 #include <linux/list.h> 28 #include <linux/slab.h> 29 30 #include <sound/core.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/soc.h> 34 35 #include <asm/io.h> 36 37 #include "fsl_dma.h" 38 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */ 39 40 #define DRV_NAME "fsl_dma" 41 42 /* 43 * The formats that the DMA controller supports, which is anything 44 * that is 8, 16, or 32 bits. 45 */ 46 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 47 SNDRV_PCM_FMTBIT_U8 | \ 48 SNDRV_PCM_FMTBIT_S16_LE | \ 49 SNDRV_PCM_FMTBIT_S16_BE | \ 50 SNDRV_PCM_FMTBIT_U16_LE | \ 51 SNDRV_PCM_FMTBIT_U16_BE | \ 52 SNDRV_PCM_FMTBIT_S24_LE | \ 53 SNDRV_PCM_FMTBIT_S24_BE | \ 54 SNDRV_PCM_FMTBIT_U24_LE | \ 55 SNDRV_PCM_FMTBIT_U24_BE | \ 56 SNDRV_PCM_FMTBIT_S32_LE | \ 57 SNDRV_PCM_FMTBIT_S32_BE | \ 58 SNDRV_PCM_FMTBIT_U32_LE | \ 59 SNDRV_PCM_FMTBIT_U32_BE) 60 struct dma_object { 61 struct snd_soc_component_driver dai; 62 dma_addr_t ssi_stx_phys; 63 dma_addr_t ssi_srx_phys; 64 unsigned int ssi_fifo_depth; 65 struct ccsr_dma_channel __iomem *channel; 66 unsigned int irq; 67 bool assigned; 68 }; 69 70 /* 71 * The number of DMA links to use. Two is the bare minimum, but if you 72 * have really small links you might need more. 73 */ 74 #define NUM_DMA_LINKS 2 75 76 /** fsl_dma_private: p-substream DMA data 77 * 78 * Each substream has a 1-to-1 association with a DMA channel. 79 * 80 * The link[] array is first because it needs to be aligned on a 32-byte 81 * boundary, so putting it first will ensure alignment without padding the 82 * structure. 83 * 84 * @link[]: array of link descriptors 85 * @dma_channel: pointer to the DMA channel's registers 86 * @irq: IRQ for this DMA channel 87 * @substream: pointer to the substream object, needed by the ISR 88 * @ssi_sxx_phys: bus address of the STX or SRX register to use 89 * @ld_buf_phys: physical address of the LD buffer 90 * @current_link: index into link[] of the link currently being processed 91 * @dma_buf_phys: physical address of the DMA buffer 92 * @dma_buf_next: physical address of the next period to process 93 * @dma_buf_end: physical address of the byte after the end of the DMA 94 * @buffer period_size: the size of a single period 95 * @num_periods: the number of periods in the DMA buffer 96 */ 97 struct fsl_dma_private { 98 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 99 struct ccsr_dma_channel __iomem *dma_channel; 100 unsigned int irq; 101 struct snd_pcm_substream *substream; 102 dma_addr_t ssi_sxx_phys; 103 unsigned int ssi_fifo_depth; 104 dma_addr_t ld_buf_phys; 105 unsigned int current_link; 106 dma_addr_t dma_buf_phys; 107 dma_addr_t dma_buf_next; 108 dma_addr_t dma_buf_end; 109 size_t period_size; 110 unsigned int num_periods; 111 }; 112 113 /** 114 * fsl_dma_hardare: define characteristics of the PCM hardware. 115 * 116 * The PCM hardware is the Freescale DMA controller. This structure defines 117 * the capabilities of that hardware. 118 * 119 * Since the sampling rate and data format are not controlled by the DMA 120 * controller, we specify no limits for those values. The only exception is 121 * period_bytes_min, which is set to a reasonably low value to prevent the 122 * DMA controller from generating too many interrupts per second. 123 * 124 * Since each link descriptor has a 32-bit byte count field, we set 125 * period_bytes_max to the largest 32-bit number. We also have no maximum 126 * number of periods. 127 * 128 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a 129 * limitation in the SSI driver requires the sample rates for playback and 130 * capture to be the same. 131 */ 132 static const struct snd_pcm_hardware fsl_dma_hardware = { 133 134 .info = SNDRV_PCM_INFO_INTERLEAVED | 135 SNDRV_PCM_INFO_MMAP | 136 SNDRV_PCM_INFO_MMAP_VALID | 137 SNDRV_PCM_INFO_JOINT_DUPLEX | 138 SNDRV_PCM_INFO_PAUSE, 139 .formats = FSLDMA_PCM_FORMATS, 140 .period_bytes_min = 512, /* A reasonable limit */ 141 .period_bytes_max = (u32) -1, 142 .periods_min = NUM_DMA_LINKS, 143 .periods_max = (unsigned int) -1, 144 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 145 }; 146 147 /** 148 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 149 * 150 * This function should be called by the ISR whenever the DMA controller 151 * halts data transfer. 152 */ 153 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 154 { 155 snd_pcm_stop_xrun(substream); 156 } 157 158 /** 159 * fsl_dma_update_pointers - update LD pointers to point to the next period 160 * 161 * As each period is completed, this function changes the the link 162 * descriptor pointers for that period to point to the next period. 163 */ 164 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 165 { 166 struct fsl_dma_link_descriptor *link = 167 &dma_private->link[dma_private->current_link]; 168 169 /* Update our link descriptors to point to the next period. On a 36-bit 170 * system, we also need to update the ESAD bits. We also set (keep) the 171 * snoop bits. See the comments in fsl_dma_hw_params() about snooping. 172 */ 173 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 174 link->source_addr = cpu_to_be32(dma_private->dma_buf_next); 175 #ifdef CONFIG_PHYS_64BIT 176 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 177 upper_32_bits(dma_private->dma_buf_next)); 178 #endif 179 } else { 180 link->dest_addr = cpu_to_be32(dma_private->dma_buf_next); 181 #ifdef CONFIG_PHYS_64BIT 182 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 183 upper_32_bits(dma_private->dma_buf_next)); 184 #endif 185 } 186 187 /* Update our variables for next time */ 188 dma_private->dma_buf_next += dma_private->period_size; 189 190 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 191 dma_private->dma_buf_next = dma_private->dma_buf_phys; 192 193 if (++dma_private->current_link >= NUM_DMA_LINKS) 194 dma_private->current_link = 0; 195 } 196 197 /** 198 * fsl_dma_isr: interrupt handler for the DMA controller 199 * 200 * @irq: IRQ of the DMA channel 201 * @dev_id: pointer to the dma_private structure for this DMA channel 202 */ 203 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 204 { 205 struct fsl_dma_private *dma_private = dev_id; 206 struct snd_pcm_substream *substream = dma_private->substream; 207 struct snd_soc_pcm_runtime *rtd = substream->private_data; 208 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); 209 struct device *dev = component->dev; 210 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 211 irqreturn_t ret = IRQ_NONE; 212 u32 sr, sr2 = 0; 213 214 /* We got an interrupt, so read the status register to see what we 215 were interrupted for. 216 */ 217 sr = in_be32(&dma_channel->sr); 218 219 if (sr & CCSR_DMA_SR_TE) { 220 dev_err(dev, "dma transmit error\n"); 221 fsl_dma_abort_stream(substream); 222 sr2 |= CCSR_DMA_SR_TE; 223 ret = IRQ_HANDLED; 224 } 225 226 if (sr & CCSR_DMA_SR_CH) 227 ret = IRQ_HANDLED; 228 229 if (sr & CCSR_DMA_SR_PE) { 230 dev_err(dev, "dma programming error\n"); 231 fsl_dma_abort_stream(substream); 232 sr2 |= CCSR_DMA_SR_PE; 233 ret = IRQ_HANDLED; 234 } 235 236 if (sr & CCSR_DMA_SR_EOLNI) { 237 sr2 |= CCSR_DMA_SR_EOLNI; 238 ret = IRQ_HANDLED; 239 } 240 241 if (sr & CCSR_DMA_SR_CB) 242 ret = IRQ_HANDLED; 243 244 if (sr & CCSR_DMA_SR_EOSI) { 245 /* Tell ALSA we completed a period. */ 246 snd_pcm_period_elapsed(substream); 247 248 /* 249 * Update our link descriptors to point to the next period. We 250 * only need to do this if the number of periods is not equal to 251 * the number of links. 252 */ 253 if (dma_private->num_periods != NUM_DMA_LINKS) 254 fsl_dma_update_pointers(dma_private); 255 256 sr2 |= CCSR_DMA_SR_EOSI; 257 ret = IRQ_HANDLED; 258 } 259 260 if (sr & CCSR_DMA_SR_EOLSI) { 261 sr2 |= CCSR_DMA_SR_EOLSI; 262 ret = IRQ_HANDLED; 263 } 264 265 /* Clear the bits that we set */ 266 if (sr2) 267 out_be32(&dma_channel->sr, sr2); 268 269 return ret; 270 } 271 272 /** 273 * fsl_dma_new: initialize this PCM driver. 274 * 275 * This function is called when the codec driver calls snd_soc_new_pcms(), 276 * once for each .dai_link in the machine driver's snd_soc_card 277 * structure. 278 * 279 * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which 280 * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM 281 * is specified. Therefore, any DMA buffers we allocate will always be in low 282 * memory, but we support for 36-bit physical addresses anyway. 283 * 284 * Regardless of where the memory is actually allocated, since the device can 285 * technically DMA to any 36-bit address, we do need to set the DMA mask to 36. 286 */ 287 static int fsl_dma_new(struct snd_soc_pcm_runtime *rtd) 288 { 289 struct snd_card *card = rtd->card->snd_card; 290 struct snd_pcm *pcm = rtd->pcm; 291 int ret; 292 293 ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(36)); 294 if (ret) 295 return ret; 296 297 /* Some codecs have separate DAIs for playback and capture, so we 298 * should allocate a DMA buffer only for the streams that are valid. 299 */ 300 301 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) { 302 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 303 fsl_dma_hardware.buffer_bytes_max, 304 &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer); 305 if (ret) { 306 dev_err(card->dev, "can't alloc playback dma buffer\n"); 307 return ret; 308 } 309 } 310 311 if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) { 312 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 313 fsl_dma_hardware.buffer_bytes_max, 314 &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer); 315 if (ret) { 316 dev_err(card->dev, "can't alloc capture dma buffer\n"); 317 snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer); 318 return ret; 319 } 320 } 321 322 return 0; 323 } 324 325 /** 326 * fsl_dma_open: open a new substream. 327 * 328 * Each substream has its own DMA buffer. 329 * 330 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 331 * descriptors that ping-pong from one period to the next. For example, if 332 * there are six periods and two link descriptors, this is how they look 333 * before playback starts: 334 * 335 * The last link descriptor 336 * ____________ points back to the first 337 * | | 338 * V | 339 * ___ ___ | 340 * | |->| |->| 341 * |___| |___| 342 * | | 343 * | | 344 * V V 345 * _________________________________________ 346 * | | | | | | | The DMA buffer is 347 * | | | | | | | divided into 6 parts 348 * |______|______|______|______|______|______| 349 * 350 * and here's how they look after the first period is finished playing: 351 * 352 * ____________ 353 * | | 354 * V | 355 * ___ ___ | 356 * | |->| |->| 357 * |___| |___| 358 * | | 359 * |______________ 360 * | | 361 * V V 362 * _________________________________________ 363 * | | | | | | | 364 * | | | | | | | 365 * |______|______|______|______|______|______| 366 * 367 * The first link descriptor now points to the third period. The DMA 368 * controller is currently playing the second period. When it finishes, it 369 * will jump back to the first descriptor and play the third period. 370 * 371 * There are four reasons we do this: 372 * 373 * 1. The only way to get the DMA controller to automatically restart the 374 * transfer when it gets to the end of the buffer is to use chaining 375 * mode. Basic direct mode doesn't offer that feature. 376 * 2. We need to receive an interrupt at the end of every period. The DMA 377 * controller can generate an interrupt at the end of every link transfer 378 * (aka segment). Making each period into a DMA segment will give us the 379 * interrupts we need. 380 * 3. By creating only two link descriptors, regardless of the number of 381 * periods, we do not need to reallocate the link descriptors if the 382 * number of periods changes. 383 * 4. All of the audio data is still stored in a single, contiguous DMA 384 * buffer, which is what ALSA expects. We're just dividing it into 385 * contiguous parts, and creating a link descriptor for each one. 386 */ 387 static int fsl_dma_open(struct snd_pcm_substream *substream) 388 { 389 struct snd_pcm_runtime *runtime = substream->runtime; 390 struct snd_soc_pcm_runtime *rtd = substream->private_data; 391 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); 392 struct device *dev = component->dev; 393 struct dma_object *dma = 394 container_of(component->driver, struct dma_object, dai); 395 struct fsl_dma_private *dma_private; 396 struct ccsr_dma_channel __iomem *dma_channel; 397 dma_addr_t ld_buf_phys; 398 u64 temp_link; /* Pointer to next link descriptor */ 399 u32 mr; 400 unsigned int channel; 401 int ret = 0; 402 unsigned int i; 403 404 /* 405 * Reject any DMA buffer whose size is not a multiple of the period 406 * size. We need to make sure that the DMA buffer can be evenly divided 407 * into periods. 408 */ 409 ret = snd_pcm_hw_constraint_integer(runtime, 410 SNDRV_PCM_HW_PARAM_PERIODS); 411 if (ret < 0) { 412 dev_err(dev, "invalid buffer size\n"); 413 return ret; 414 } 415 416 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 417 418 if (dma->assigned) { 419 dev_err(dev, "dma channel already assigned\n"); 420 return -EBUSY; 421 } 422 423 dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private), 424 &ld_buf_phys, GFP_KERNEL); 425 if (!dma_private) { 426 dev_err(dev, "can't allocate dma private data\n"); 427 return -ENOMEM; 428 } 429 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 430 dma_private->ssi_sxx_phys = dma->ssi_stx_phys; 431 else 432 dma_private->ssi_sxx_phys = dma->ssi_srx_phys; 433 434 dma_private->ssi_fifo_depth = dma->ssi_fifo_depth; 435 dma_private->dma_channel = dma->channel; 436 dma_private->irq = dma->irq; 437 dma_private->substream = substream; 438 dma_private->ld_buf_phys = ld_buf_phys; 439 dma_private->dma_buf_phys = substream->dma_buffer.addr; 440 441 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio", 442 dma_private); 443 if (ret) { 444 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 445 dma_private->irq, ret); 446 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 447 dma_private, dma_private->ld_buf_phys); 448 return ret; 449 } 450 451 dma->assigned = true; 452 453 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 454 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 455 runtime->private_data = dma_private; 456 457 /* Program the fixed DMA controller parameters */ 458 459 dma_channel = dma_private->dma_channel; 460 461 temp_link = dma_private->ld_buf_phys + 462 sizeof(struct fsl_dma_link_descriptor); 463 464 for (i = 0; i < NUM_DMA_LINKS; i++) { 465 dma_private->link[i].next = cpu_to_be64(temp_link); 466 467 temp_link += sizeof(struct fsl_dma_link_descriptor); 468 } 469 /* The last link descriptor points to the first */ 470 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 471 472 /* Tell the DMA controller where the first link descriptor is */ 473 out_be32(&dma_channel->clndar, 474 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 475 out_be32(&dma_channel->eclndar, 476 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 477 478 /* The manual says the BCR must be clear before enabling EMP */ 479 out_be32(&dma_channel->bcr, 0); 480 481 /* 482 * Program the mode register for interrupts, external master control, 483 * and source/destination hold. Also clear the Channel Abort bit. 484 */ 485 mr = in_be32(&dma_channel->mr) & 486 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 487 488 /* 489 * We want External Master Start and External Master Pause enabled, 490 * because the SSI is controlling the DMA controller. We want the DMA 491 * controller to be set up in advance, and then we signal only the SSI 492 * to start transferring. 493 * 494 * We want End-Of-Segment Interrupts enabled, because this will generate 495 * an interrupt at the end of each segment (each link descriptor 496 * represents one segment). Each DMA segment is the same thing as an 497 * ALSA period, so this is how we get an interrupt at the end of every 498 * period. 499 * 500 * We want Error Interrupt enabled, so that we can get an error if 501 * the DMA controller is mis-programmed somehow. 502 */ 503 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 504 CCSR_DMA_MR_EMS_EN; 505 506 /* For playback, we want the destination address to be held. For 507 capture, set the source address to be held. */ 508 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 509 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 510 511 out_be32(&dma_channel->mr, mr); 512 513 return 0; 514 } 515 516 /** 517 * fsl_dma_hw_params: continue initializing the DMA links 518 * 519 * This function obtains hardware parameters about the opened stream and 520 * programs the DMA controller accordingly. 521 * 522 * One drawback of big-endian is that when copying integers of different 523 * sizes to a fixed-sized register, the address to which the integer must be 524 * copied is dependent on the size of the integer. 525 * 526 * For example, if P is the address of a 32-bit register, and X is a 32-bit 527 * integer, then X should be copied to address P. However, if X is a 16-bit 528 * integer, then it should be copied to P+2. If X is an 8-bit register, 529 * then it should be copied to P+3. 530 * 531 * So for playback of 8-bit samples, the DMA controller must transfer single 532 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 533 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 534 * 535 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 536 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 537 * and 8 bytes at a time). So we do not support packed 24-bit samples. 538 * 24-bit data must be padded to 32 bits. 539 */ 540 static int fsl_dma_hw_params(struct snd_pcm_substream *substream, 541 struct snd_pcm_hw_params *hw_params) 542 { 543 struct snd_pcm_runtime *runtime = substream->runtime; 544 struct fsl_dma_private *dma_private = runtime->private_data; 545 struct snd_soc_pcm_runtime *rtd = substream->private_data; 546 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); 547 struct device *dev = component->dev; 548 549 /* Number of bits per sample */ 550 unsigned int sample_bits = 551 snd_pcm_format_physical_width(params_format(hw_params)); 552 553 /* Number of bytes per frame */ 554 unsigned int sample_bytes = sample_bits / 8; 555 556 /* Bus address of SSI STX register */ 557 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; 558 559 /* Size of the DMA buffer, in bytes */ 560 size_t buffer_size = params_buffer_bytes(hw_params); 561 562 /* Number of bytes per period */ 563 size_t period_size = params_period_bytes(hw_params); 564 565 /* Pointer to next period */ 566 dma_addr_t temp_addr = substream->dma_buffer.addr; 567 568 /* Pointer to DMA controller */ 569 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 570 571 u32 mr; /* DMA Mode Register */ 572 573 unsigned int i; 574 575 /* Initialize our DMA tracking variables */ 576 dma_private->period_size = period_size; 577 dma_private->num_periods = params_periods(hw_params); 578 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 579 dma_private->dma_buf_next = dma_private->dma_buf_phys + 580 (NUM_DMA_LINKS * period_size); 581 582 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 583 /* This happens if the number of periods == NUM_DMA_LINKS */ 584 dma_private->dma_buf_next = dma_private->dma_buf_phys; 585 586 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 587 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 588 589 /* Due to a quirk of the SSI's STX register, the target address 590 * for the DMA operations depends on the sample size. So we calculate 591 * that offset here. While we're at it, also tell the DMA controller 592 * how much data to transfer per sample. 593 */ 594 switch (sample_bits) { 595 case 8: 596 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 597 ssi_sxx_phys += 3; 598 break; 599 case 16: 600 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 601 ssi_sxx_phys += 2; 602 break; 603 case 32: 604 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 605 break; 606 default: 607 /* We should never get here */ 608 dev_err(dev, "unsupported sample size %u\n", sample_bits); 609 return -EINVAL; 610 } 611 612 /* 613 * BWC determines how many bytes are sent/received before the DMA 614 * controller checks the SSI to see if it needs to stop. BWC should 615 * always be a multiple of the frame size, so that we always transmit 616 * whole frames. Each frame occupies two slots in the FIFO. The 617 * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two 618 * (MR[BWC] can only represent even powers of two). 619 * 620 * To simplify the process, we set BWC to the largest value that is 621 * less than or equal to the FIFO watermark. For playback, this ensures 622 * that we transfer the maximum amount without overrunning the FIFO. 623 * For capture, this ensures that we transfer the maximum amount without 624 * underrunning the FIFO. 625 * 626 * f = SSI FIFO depth 627 * w = SSI watermark value (which equals f - 2) 628 * b = DMA bandwidth count (in bytes) 629 * s = sample size (in bytes, which equals frame_size * 2) 630 * 631 * For playback, we never transmit more than the transmit FIFO 632 * watermark, otherwise we might write more data than the FIFO can hold. 633 * The watermark is equal to the FIFO depth minus two. 634 * 635 * For capture, two equations must hold: 636 * w > f - (b / s) 637 * w >= b / s 638 * 639 * So, b > 2 * s, but b must also be <= s * w. To simplify, we set 640 * b = s * w, which is equal to 641 * (dma_private->ssi_fifo_depth - 2) * sample_bytes. 642 */ 643 mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes); 644 645 out_be32(&dma_channel->mr, mr); 646 647 for (i = 0; i < NUM_DMA_LINKS; i++) { 648 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 649 650 link->count = cpu_to_be32(period_size); 651 652 /* The snoop bit tells the DMA controller whether it should tell 653 * the ECM to snoop during a read or write to an address. For 654 * audio, we use DMA to transfer data between memory and an I/O 655 * device (the SSI's STX0 or SRX0 register). Snooping is only 656 * needed if there is a cache, so we need to snoop memory 657 * addresses only. For playback, that means we snoop the source 658 * but not the destination. For capture, we snoop the 659 * destination but not the source. 660 * 661 * Note that failing to snoop properly is unlikely to cause 662 * cache incoherency if the period size is larger than the 663 * size of L1 cache. This is because filling in one period will 664 * flush out the data for the previous period. So if you 665 * increased period_bytes_min to a large enough size, you might 666 * get more performance by not snooping, and you'll still be 667 * okay. You'll need to update fsl_dma_update_pointers() also. 668 */ 669 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 670 link->source_addr = cpu_to_be32(temp_addr); 671 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 672 upper_32_bits(temp_addr)); 673 674 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 675 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 676 upper_32_bits(ssi_sxx_phys)); 677 } else { 678 link->source_addr = cpu_to_be32(ssi_sxx_phys); 679 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 680 upper_32_bits(ssi_sxx_phys)); 681 682 link->dest_addr = cpu_to_be32(temp_addr); 683 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 684 upper_32_bits(temp_addr)); 685 } 686 687 temp_addr += period_size; 688 } 689 690 return 0; 691 } 692 693 /** 694 * fsl_dma_pointer: determine the current position of the DMA transfer 695 * 696 * This function is called by ALSA when ALSA wants to know where in the 697 * stream buffer the hardware currently is. 698 * 699 * For playback, the SAR register contains the physical address of the most 700 * recent DMA transfer. For capture, the value is in the DAR register. 701 * 702 * The base address of the buffer is stored in the source_addr field of the 703 * first link descriptor. 704 */ 705 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream) 706 { 707 struct snd_pcm_runtime *runtime = substream->runtime; 708 struct fsl_dma_private *dma_private = runtime->private_data; 709 struct snd_soc_pcm_runtime *rtd = substream->private_data; 710 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); 711 struct device *dev = component->dev; 712 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 713 dma_addr_t position; 714 snd_pcm_uframes_t frames; 715 716 /* Obtain the current DMA pointer, but don't read the ESAD bits if we 717 * only have 32-bit DMA addresses. This function is typically called 718 * in interrupt context, so we need to optimize it. 719 */ 720 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 721 position = in_be32(&dma_channel->sar); 722 #ifdef CONFIG_PHYS_64BIT 723 position |= (u64)(in_be32(&dma_channel->satr) & 724 CCSR_DMA_ATR_ESAD_MASK) << 32; 725 #endif 726 } else { 727 position = in_be32(&dma_channel->dar); 728 #ifdef CONFIG_PHYS_64BIT 729 position |= (u64)(in_be32(&dma_channel->datr) & 730 CCSR_DMA_ATR_ESAD_MASK) << 32; 731 #endif 732 } 733 734 /* 735 * When capture is started, the SSI immediately starts to fill its FIFO. 736 * This means that the DMA controller is not started until the FIFO is 737 * full. However, ALSA calls this function before that happens, when 738 * MR.DAR is still zero. In this case, just return zero to indicate 739 * that nothing has been received yet. 740 */ 741 if (!position) 742 return 0; 743 744 if ((position < dma_private->dma_buf_phys) || 745 (position > dma_private->dma_buf_end)) { 746 dev_err(dev, "dma pointer is out of range, halting stream\n"); 747 return SNDRV_PCM_POS_XRUN; 748 } 749 750 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 751 752 /* 753 * If the current address is just past the end of the buffer, wrap it 754 * around. 755 */ 756 if (frames == runtime->buffer_size) 757 frames = 0; 758 759 return frames; 760 } 761 762 /** 763 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 764 * 765 * Release the resources allocated in fsl_dma_hw_params() and de-program the 766 * registers. 767 * 768 * This function can be called multiple times. 769 */ 770 static int fsl_dma_hw_free(struct snd_pcm_substream *substream) 771 { 772 struct snd_pcm_runtime *runtime = substream->runtime; 773 struct fsl_dma_private *dma_private = runtime->private_data; 774 775 if (dma_private) { 776 struct ccsr_dma_channel __iomem *dma_channel; 777 778 dma_channel = dma_private->dma_channel; 779 780 /* Stop the DMA */ 781 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 782 out_be32(&dma_channel->mr, 0); 783 784 /* Reset all the other registers */ 785 out_be32(&dma_channel->sr, -1); 786 out_be32(&dma_channel->clndar, 0); 787 out_be32(&dma_channel->eclndar, 0); 788 out_be32(&dma_channel->satr, 0); 789 out_be32(&dma_channel->sar, 0); 790 out_be32(&dma_channel->datr, 0); 791 out_be32(&dma_channel->dar, 0); 792 out_be32(&dma_channel->bcr, 0); 793 out_be32(&dma_channel->nlndar, 0); 794 out_be32(&dma_channel->enlndar, 0); 795 } 796 797 return 0; 798 } 799 800 /** 801 * fsl_dma_close: close the stream. 802 */ 803 static int fsl_dma_close(struct snd_pcm_substream *substream) 804 { 805 struct snd_pcm_runtime *runtime = substream->runtime; 806 struct fsl_dma_private *dma_private = runtime->private_data; 807 struct snd_soc_pcm_runtime *rtd = substream->private_data; 808 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); 809 struct device *dev = component->dev; 810 struct dma_object *dma = 811 container_of(component->driver, struct dma_object, dai); 812 813 if (dma_private) { 814 if (dma_private->irq) 815 free_irq(dma_private->irq, dma_private); 816 817 /* Deallocate the fsl_dma_private structure */ 818 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 819 dma_private, dma_private->ld_buf_phys); 820 substream->runtime->private_data = NULL; 821 } 822 823 dma->assigned = false; 824 825 return 0; 826 } 827 828 /* 829 * Remove this PCM driver. 830 */ 831 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm) 832 { 833 struct snd_pcm_substream *substream; 834 unsigned int i; 835 836 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 837 substream = pcm->streams[i].substream; 838 if (substream) { 839 snd_dma_free_pages(&substream->dma_buffer); 840 substream->dma_buffer.area = NULL; 841 substream->dma_buffer.addr = 0; 842 } 843 } 844 } 845 846 /** 847 * find_ssi_node -- returns the SSI node that points to its DMA channel node 848 * 849 * Although this DMA driver attempts to operate independently of the other 850 * devices, it still needs to determine some information about the SSI device 851 * that it's working with. Unfortunately, the device tree does not contain 852 * a pointer from the DMA channel node to the SSI node -- the pointer goes the 853 * other way. So we need to scan the device tree for SSI nodes until we find 854 * the one that points to the given DMA channel node. It's ugly, but at least 855 * it's contained in this one function. 856 */ 857 static struct device_node *find_ssi_node(struct device_node *dma_channel_np) 858 { 859 struct device_node *ssi_np, *np; 860 861 for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") { 862 /* Check each DMA phandle to see if it points to us. We 863 * assume that device_node pointers are a valid comparison. 864 */ 865 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0); 866 of_node_put(np); 867 if (np == dma_channel_np) 868 return ssi_np; 869 870 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0); 871 of_node_put(np); 872 if (np == dma_channel_np) 873 return ssi_np; 874 } 875 876 return NULL; 877 } 878 879 static const struct snd_pcm_ops fsl_dma_ops = { 880 .open = fsl_dma_open, 881 .close = fsl_dma_close, 882 .ioctl = snd_pcm_lib_ioctl, 883 .hw_params = fsl_dma_hw_params, 884 .hw_free = fsl_dma_hw_free, 885 .pointer = fsl_dma_pointer, 886 }; 887 888 static int fsl_soc_dma_probe(struct platform_device *pdev) 889 { 890 struct dma_object *dma; 891 struct device_node *np = pdev->dev.of_node; 892 struct device_node *ssi_np; 893 struct resource res; 894 const uint32_t *iprop; 895 int ret; 896 897 /* Find the SSI node that points to us. */ 898 ssi_np = find_ssi_node(np); 899 if (!ssi_np) { 900 dev_err(&pdev->dev, "cannot find parent SSI node\n"); 901 return -ENODEV; 902 } 903 904 ret = of_address_to_resource(ssi_np, 0, &res); 905 if (ret) { 906 dev_err(&pdev->dev, "could not determine resources for %pOF\n", 907 ssi_np); 908 of_node_put(ssi_np); 909 return ret; 910 } 911 912 dma = kzalloc(sizeof(*dma), GFP_KERNEL); 913 if (!dma) { 914 of_node_put(ssi_np); 915 return -ENOMEM; 916 } 917 918 dma->dai.name = DRV_NAME; 919 dma->dai.ops = &fsl_dma_ops; 920 dma->dai.pcm_new = fsl_dma_new; 921 dma->dai.pcm_free = fsl_dma_free_dma_buffers; 922 923 /* Store the SSI-specific information that we need */ 924 dma->ssi_stx_phys = res.start + REG_SSI_STX0; 925 dma->ssi_srx_phys = res.start + REG_SSI_SRX0; 926 927 iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL); 928 if (iprop) 929 dma->ssi_fifo_depth = be32_to_cpup(iprop); 930 else 931 /* Older 8610 DTs didn't have the fifo-depth property */ 932 dma->ssi_fifo_depth = 8; 933 934 of_node_put(ssi_np); 935 936 ret = devm_snd_soc_register_component(&pdev->dev, &dma->dai, NULL, 0); 937 if (ret) { 938 dev_err(&pdev->dev, "could not register platform\n"); 939 kfree(dma); 940 return ret; 941 } 942 943 dma->channel = of_iomap(np, 0); 944 dma->irq = irq_of_parse_and_map(np, 0); 945 946 dev_set_drvdata(&pdev->dev, dma); 947 948 return 0; 949 } 950 951 static int fsl_soc_dma_remove(struct platform_device *pdev) 952 { 953 struct dma_object *dma = dev_get_drvdata(&pdev->dev); 954 955 iounmap(dma->channel); 956 irq_dispose_mapping(dma->irq); 957 kfree(dma); 958 959 return 0; 960 } 961 962 static const struct of_device_id fsl_soc_dma_ids[] = { 963 { .compatible = "fsl,ssi-dma-channel", }, 964 {} 965 }; 966 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids); 967 968 static struct platform_driver fsl_soc_dma_driver = { 969 .driver = { 970 .name = "fsl-pcm-audio", 971 .of_match_table = fsl_soc_dma_ids, 972 }, 973 .probe = fsl_soc_dma_probe, 974 .remove = fsl_soc_dma_remove, 975 }; 976 977 module_platform_driver(fsl_soc_dma_driver); 978 979 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 980 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver"); 981 MODULE_LICENSE("GPL v2"); 982