1 /* 2 * Freescale DMA ALSA SoC PCM driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2010 Freescale Semiconductor, Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 * 12 * This driver implements ASoC support for the Elo DMA controller, which is 13 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 14 * the PCM driver is what handles the DMA buffer. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/interrupt.h> 22 #include <linux/delay.h> 23 #include <linux/gfp.h> 24 #include <linux/of_address.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_platform.h> 27 #include <linux/list.h> 28 #include <linux/slab.h> 29 30 #include <sound/core.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/soc.h> 34 35 #include <asm/io.h> 36 37 #include "fsl_dma.h" 38 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */ 39 40 /* 41 * The formats that the DMA controller supports, which is anything 42 * that is 8, 16, or 32 bits. 43 */ 44 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 45 SNDRV_PCM_FMTBIT_U8 | \ 46 SNDRV_PCM_FMTBIT_S16_LE | \ 47 SNDRV_PCM_FMTBIT_S16_BE | \ 48 SNDRV_PCM_FMTBIT_U16_LE | \ 49 SNDRV_PCM_FMTBIT_U16_BE | \ 50 SNDRV_PCM_FMTBIT_S24_LE | \ 51 SNDRV_PCM_FMTBIT_S24_BE | \ 52 SNDRV_PCM_FMTBIT_U24_LE | \ 53 SNDRV_PCM_FMTBIT_U24_BE | \ 54 SNDRV_PCM_FMTBIT_S32_LE | \ 55 SNDRV_PCM_FMTBIT_S32_BE | \ 56 SNDRV_PCM_FMTBIT_U32_LE | \ 57 SNDRV_PCM_FMTBIT_U32_BE) 58 59 #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ 60 SNDRV_PCM_RATE_CONTINUOUS) 61 62 struct dma_object { 63 struct snd_soc_platform_driver dai; 64 dma_addr_t ssi_stx_phys; 65 dma_addr_t ssi_srx_phys; 66 unsigned int ssi_fifo_depth; 67 struct ccsr_dma_channel __iomem *channel; 68 unsigned int irq; 69 bool assigned; 70 char path[1]; 71 }; 72 73 /* 74 * The number of DMA links to use. Two is the bare minimum, but if you 75 * have really small links you might need more. 76 */ 77 #define NUM_DMA_LINKS 2 78 79 /** fsl_dma_private: p-substream DMA data 80 * 81 * Each substream has a 1-to-1 association with a DMA channel. 82 * 83 * The link[] array is first because it needs to be aligned on a 32-byte 84 * boundary, so putting it first will ensure alignment without padding the 85 * structure. 86 * 87 * @link[]: array of link descriptors 88 * @dma_channel: pointer to the DMA channel's registers 89 * @irq: IRQ for this DMA channel 90 * @substream: pointer to the substream object, needed by the ISR 91 * @ssi_sxx_phys: bus address of the STX or SRX register to use 92 * @ld_buf_phys: physical address of the LD buffer 93 * @current_link: index into link[] of the link currently being processed 94 * @dma_buf_phys: physical address of the DMA buffer 95 * @dma_buf_next: physical address of the next period to process 96 * @dma_buf_end: physical address of the byte after the end of the DMA 97 * @buffer period_size: the size of a single period 98 * @num_periods: the number of periods in the DMA buffer 99 */ 100 struct fsl_dma_private { 101 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 102 struct ccsr_dma_channel __iomem *dma_channel; 103 unsigned int irq; 104 struct snd_pcm_substream *substream; 105 dma_addr_t ssi_sxx_phys; 106 unsigned int ssi_fifo_depth; 107 dma_addr_t ld_buf_phys; 108 unsigned int current_link; 109 dma_addr_t dma_buf_phys; 110 dma_addr_t dma_buf_next; 111 dma_addr_t dma_buf_end; 112 size_t period_size; 113 unsigned int num_periods; 114 }; 115 116 /** 117 * fsl_dma_hardare: define characteristics of the PCM hardware. 118 * 119 * The PCM hardware is the Freescale DMA controller. This structure defines 120 * the capabilities of that hardware. 121 * 122 * Since the sampling rate and data format are not controlled by the DMA 123 * controller, we specify no limits for those values. The only exception is 124 * period_bytes_min, which is set to a reasonably low value to prevent the 125 * DMA controller from generating too many interrupts per second. 126 * 127 * Since each link descriptor has a 32-bit byte count field, we set 128 * period_bytes_max to the largest 32-bit number. We also have no maximum 129 * number of periods. 130 * 131 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a 132 * limitation in the SSI driver requires the sample rates for playback and 133 * capture to be the same. 134 */ 135 static const struct snd_pcm_hardware fsl_dma_hardware = { 136 137 .info = SNDRV_PCM_INFO_INTERLEAVED | 138 SNDRV_PCM_INFO_MMAP | 139 SNDRV_PCM_INFO_MMAP_VALID | 140 SNDRV_PCM_INFO_JOINT_DUPLEX | 141 SNDRV_PCM_INFO_PAUSE, 142 .formats = FSLDMA_PCM_FORMATS, 143 .rates = FSLDMA_PCM_RATES, 144 .rate_min = 5512, 145 .rate_max = 192000, 146 .period_bytes_min = 512, /* A reasonable limit */ 147 .period_bytes_max = (u32) -1, 148 .periods_min = NUM_DMA_LINKS, 149 .periods_max = (unsigned int) -1, 150 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 151 }; 152 153 /** 154 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 155 * 156 * This function should be called by the ISR whenever the DMA controller 157 * halts data transfer. 158 */ 159 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 160 { 161 unsigned long flags; 162 163 snd_pcm_stream_lock_irqsave(substream, flags); 164 165 if (snd_pcm_running(substream)) 166 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); 167 168 snd_pcm_stream_unlock_irqrestore(substream, flags); 169 } 170 171 /** 172 * fsl_dma_update_pointers - update LD pointers to point to the next period 173 * 174 * As each period is completed, this function changes the the link 175 * descriptor pointers for that period to point to the next period. 176 */ 177 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 178 { 179 struct fsl_dma_link_descriptor *link = 180 &dma_private->link[dma_private->current_link]; 181 182 /* Update our link descriptors to point to the next period. On a 36-bit 183 * system, we also need to update the ESAD bits. We also set (keep) the 184 * snoop bits. See the comments in fsl_dma_hw_params() about snooping. 185 */ 186 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 187 link->source_addr = cpu_to_be32(dma_private->dma_buf_next); 188 #ifdef CONFIG_PHYS_64BIT 189 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 190 upper_32_bits(dma_private->dma_buf_next)); 191 #endif 192 } else { 193 link->dest_addr = cpu_to_be32(dma_private->dma_buf_next); 194 #ifdef CONFIG_PHYS_64BIT 195 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 196 upper_32_bits(dma_private->dma_buf_next)); 197 #endif 198 } 199 200 /* Update our variables for next time */ 201 dma_private->dma_buf_next += dma_private->period_size; 202 203 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 204 dma_private->dma_buf_next = dma_private->dma_buf_phys; 205 206 if (++dma_private->current_link >= NUM_DMA_LINKS) 207 dma_private->current_link = 0; 208 } 209 210 /** 211 * fsl_dma_isr: interrupt handler for the DMA controller 212 * 213 * @irq: IRQ of the DMA channel 214 * @dev_id: pointer to the dma_private structure for this DMA channel 215 */ 216 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 217 { 218 struct fsl_dma_private *dma_private = dev_id; 219 struct snd_pcm_substream *substream = dma_private->substream; 220 struct snd_soc_pcm_runtime *rtd = substream->private_data; 221 struct device *dev = rtd->platform->dev; 222 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 223 irqreturn_t ret = IRQ_NONE; 224 u32 sr, sr2 = 0; 225 226 /* We got an interrupt, so read the status register to see what we 227 were interrupted for. 228 */ 229 sr = in_be32(&dma_channel->sr); 230 231 if (sr & CCSR_DMA_SR_TE) { 232 dev_err(dev, "dma transmit error\n"); 233 fsl_dma_abort_stream(substream); 234 sr2 |= CCSR_DMA_SR_TE; 235 ret = IRQ_HANDLED; 236 } 237 238 if (sr & CCSR_DMA_SR_CH) 239 ret = IRQ_HANDLED; 240 241 if (sr & CCSR_DMA_SR_PE) { 242 dev_err(dev, "dma programming error\n"); 243 fsl_dma_abort_stream(substream); 244 sr2 |= CCSR_DMA_SR_PE; 245 ret = IRQ_HANDLED; 246 } 247 248 if (sr & CCSR_DMA_SR_EOLNI) { 249 sr2 |= CCSR_DMA_SR_EOLNI; 250 ret = IRQ_HANDLED; 251 } 252 253 if (sr & CCSR_DMA_SR_CB) 254 ret = IRQ_HANDLED; 255 256 if (sr & CCSR_DMA_SR_EOSI) { 257 /* Tell ALSA we completed a period. */ 258 snd_pcm_period_elapsed(substream); 259 260 /* 261 * Update our link descriptors to point to the next period. We 262 * only need to do this if the number of periods is not equal to 263 * the number of links. 264 */ 265 if (dma_private->num_periods != NUM_DMA_LINKS) 266 fsl_dma_update_pointers(dma_private); 267 268 sr2 |= CCSR_DMA_SR_EOSI; 269 ret = IRQ_HANDLED; 270 } 271 272 if (sr & CCSR_DMA_SR_EOLSI) { 273 sr2 |= CCSR_DMA_SR_EOLSI; 274 ret = IRQ_HANDLED; 275 } 276 277 /* Clear the bits that we set */ 278 if (sr2) 279 out_be32(&dma_channel->sr, sr2); 280 281 return ret; 282 } 283 284 /** 285 * fsl_dma_new: initialize this PCM driver. 286 * 287 * This function is called when the codec driver calls snd_soc_new_pcms(), 288 * once for each .dai_link in the machine driver's snd_soc_card 289 * structure. 290 * 291 * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which 292 * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM 293 * is specified. Therefore, any DMA buffers we allocate will always be in low 294 * memory, but we support for 36-bit physical addresses anyway. 295 * 296 * Regardless of where the memory is actually allocated, since the device can 297 * technically DMA to any 36-bit address, we do need to set the DMA mask to 36. 298 */ 299 static int fsl_dma_new(struct snd_soc_pcm_runtime *rtd) 300 { 301 struct snd_card *card = rtd->card->snd_card; 302 struct snd_pcm *pcm = rtd->pcm; 303 static u64 fsl_dma_dmamask = DMA_BIT_MASK(36); 304 int ret; 305 306 if (!card->dev->dma_mask) 307 card->dev->dma_mask = &fsl_dma_dmamask; 308 309 if (!card->dev->coherent_dma_mask) 310 card->dev->coherent_dma_mask = fsl_dma_dmamask; 311 312 /* Some codecs have separate DAIs for playback and capture, so we 313 * should allocate a DMA buffer only for the streams that are valid. 314 */ 315 316 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) { 317 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 318 fsl_dma_hardware.buffer_bytes_max, 319 &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer); 320 if (ret) { 321 dev_err(card->dev, "can't alloc playback dma buffer\n"); 322 return ret; 323 } 324 } 325 326 if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) { 327 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 328 fsl_dma_hardware.buffer_bytes_max, 329 &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer); 330 if (ret) { 331 dev_err(card->dev, "can't alloc capture dma buffer\n"); 332 snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer); 333 return ret; 334 } 335 } 336 337 return 0; 338 } 339 340 /** 341 * fsl_dma_open: open a new substream. 342 * 343 * Each substream has its own DMA buffer. 344 * 345 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 346 * descriptors that ping-pong from one period to the next. For example, if 347 * there are six periods and two link descriptors, this is how they look 348 * before playback starts: 349 * 350 * The last link descriptor 351 * ____________ points back to the first 352 * | | 353 * V | 354 * ___ ___ | 355 * | |->| |->| 356 * |___| |___| 357 * | | 358 * | | 359 * V V 360 * _________________________________________ 361 * | | | | | | | The DMA buffer is 362 * | | | | | | | divided into 6 parts 363 * |______|______|______|______|______|______| 364 * 365 * and here's how they look after the first period is finished playing: 366 * 367 * ____________ 368 * | | 369 * V | 370 * ___ ___ | 371 * | |->| |->| 372 * |___| |___| 373 * | | 374 * |______________ 375 * | | 376 * V V 377 * _________________________________________ 378 * | | | | | | | 379 * | | | | | | | 380 * |______|______|______|______|______|______| 381 * 382 * The first link descriptor now points to the third period. The DMA 383 * controller is currently playing the second period. When it finishes, it 384 * will jump back to the first descriptor and play the third period. 385 * 386 * There are four reasons we do this: 387 * 388 * 1. The only way to get the DMA controller to automatically restart the 389 * transfer when it gets to the end of the buffer is to use chaining 390 * mode. Basic direct mode doesn't offer that feature. 391 * 2. We need to receive an interrupt at the end of every period. The DMA 392 * controller can generate an interrupt at the end of every link transfer 393 * (aka segment). Making each period into a DMA segment will give us the 394 * interrupts we need. 395 * 3. By creating only two link descriptors, regardless of the number of 396 * periods, we do not need to reallocate the link descriptors if the 397 * number of periods changes. 398 * 4. All of the audio data is still stored in a single, contiguous DMA 399 * buffer, which is what ALSA expects. We're just dividing it into 400 * contiguous parts, and creating a link descriptor for each one. 401 */ 402 static int fsl_dma_open(struct snd_pcm_substream *substream) 403 { 404 struct snd_pcm_runtime *runtime = substream->runtime; 405 struct snd_soc_pcm_runtime *rtd = substream->private_data; 406 struct device *dev = rtd->platform->dev; 407 struct dma_object *dma = 408 container_of(rtd->platform->driver, struct dma_object, dai); 409 struct fsl_dma_private *dma_private; 410 struct ccsr_dma_channel __iomem *dma_channel; 411 dma_addr_t ld_buf_phys; 412 u64 temp_link; /* Pointer to next link descriptor */ 413 u32 mr; 414 unsigned int channel; 415 int ret = 0; 416 unsigned int i; 417 418 /* 419 * Reject any DMA buffer whose size is not a multiple of the period 420 * size. We need to make sure that the DMA buffer can be evenly divided 421 * into periods. 422 */ 423 ret = snd_pcm_hw_constraint_integer(runtime, 424 SNDRV_PCM_HW_PARAM_PERIODS); 425 if (ret < 0) { 426 dev_err(dev, "invalid buffer size\n"); 427 return ret; 428 } 429 430 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 431 432 if (dma->assigned) { 433 dev_err(dev, "dma channel already assigned\n"); 434 return -EBUSY; 435 } 436 437 dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private), 438 &ld_buf_phys, GFP_KERNEL); 439 if (!dma_private) { 440 dev_err(dev, "can't allocate dma private data\n"); 441 return -ENOMEM; 442 } 443 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 444 dma_private->ssi_sxx_phys = dma->ssi_stx_phys; 445 else 446 dma_private->ssi_sxx_phys = dma->ssi_srx_phys; 447 448 dma_private->ssi_fifo_depth = dma->ssi_fifo_depth; 449 dma_private->dma_channel = dma->channel; 450 dma_private->irq = dma->irq; 451 dma_private->substream = substream; 452 dma_private->ld_buf_phys = ld_buf_phys; 453 dma_private->dma_buf_phys = substream->dma_buffer.addr; 454 455 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio", 456 dma_private); 457 if (ret) { 458 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 459 dma_private->irq, ret); 460 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 461 dma_private, dma_private->ld_buf_phys); 462 return ret; 463 } 464 465 dma->assigned = 1; 466 467 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 468 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 469 runtime->private_data = dma_private; 470 471 /* Program the fixed DMA controller parameters */ 472 473 dma_channel = dma_private->dma_channel; 474 475 temp_link = dma_private->ld_buf_phys + 476 sizeof(struct fsl_dma_link_descriptor); 477 478 for (i = 0; i < NUM_DMA_LINKS; i++) { 479 dma_private->link[i].next = cpu_to_be64(temp_link); 480 481 temp_link += sizeof(struct fsl_dma_link_descriptor); 482 } 483 /* The last link descriptor points to the first */ 484 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 485 486 /* Tell the DMA controller where the first link descriptor is */ 487 out_be32(&dma_channel->clndar, 488 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 489 out_be32(&dma_channel->eclndar, 490 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 491 492 /* The manual says the BCR must be clear before enabling EMP */ 493 out_be32(&dma_channel->bcr, 0); 494 495 /* 496 * Program the mode register for interrupts, external master control, 497 * and source/destination hold. Also clear the Channel Abort bit. 498 */ 499 mr = in_be32(&dma_channel->mr) & 500 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 501 502 /* 503 * We want External Master Start and External Master Pause enabled, 504 * because the SSI is controlling the DMA controller. We want the DMA 505 * controller to be set up in advance, and then we signal only the SSI 506 * to start transferring. 507 * 508 * We want End-Of-Segment Interrupts enabled, because this will generate 509 * an interrupt at the end of each segment (each link descriptor 510 * represents one segment). Each DMA segment is the same thing as an 511 * ALSA period, so this is how we get an interrupt at the end of every 512 * period. 513 * 514 * We want Error Interrupt enabled, so that we can get an error if 515 * the DMA controller is mis-programmed somehow. 516 */ 517 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 518 CCSR_DMA_MR_EMS_EN; 519 520 /* For playback, we want the destination address to be held. For 521 capture, set the source address to be held. */ 522 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 523 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 524 525 out_be32(&dma_channel->mr, mr); 526 527 return 0; 528 } 529 530 /** 531 * fsl_dma_hw_params: continue initializing the DMA links 532 * 533 * This function obtains hardware parameters about the opened stream and 534 * programs the DMA controller accordingly. 535 * 536 * One drawback of big-endian is that when copying integers of different 537 * sizes to a fixed-sized register, the address to which the integer must be 538 * copied is dependent on the size of the integer. 539 * 540 * For example, if P is the address of a 32-bit register, and X is a 32-bit 541 * integer, then X should be copied to address P. However, if X is a 16-bit 542 * integer, then it should be copied to P+2. If X is an 8-bit register, 543 * then it should be copied to P+3. 544 * 545 * So for playback of 8-bit samples, the DMA controller must transfer single 546 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 547 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 548 * 549 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 550 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 551 * and 8 bytes at a time). So we do not support packed 24-bit samples. 552 * 24-bit data must be padded to 32 bits. 553 */ 554 static int fsl_dma_hw_params(struct snd_pcm_substream *substream, 555 struct snd_pcm_hw_params *hw_params) 556 { 557 struct snd_pcm_runtime *runtime = substream->runtime; 558 struct fsl_dma_private *dma_private = runtime->private_data; 559 struct snd_soc_pcm_runtime *rtd = substream->private_data; 560 struct device *dev = rtd->platform->dev; 561 562 /* Number of bits per sample */ 563 unsigned int sample_bits = 564 snd_pcm_format_physical_width(params_format(hw_params)); 565 566 /* Number of bytes per frame */ 567 unsigned int sample_bytes = sample_bits / 8; 568 569 /* Bus address of SSI STX register */ 570 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; 571 572 /* Size of the DMA buffer, in bytes */ 573 size_t buffer_size = params_buffer_bytes(hw_params); 574 575 /* Number of bytes per period */ 576 size_t period_size = params_period_bytes(hw_params); 577 578 /* Pointer to next period */ 579 dma_addr_t temp_addr = substream->dma_buffer.addr; 580 581 /* Pointer to DMA controller */ 582 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 583 584 u32 mr; /* DMA Mode Register */ 585 586 unsigned int i; 587 588 /* Initialize our DMA tracking variables */ 589 dma_private->period_size = period_size; 590 dma_private->num_periods = params_periods(hw_params); 591 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 592 dma_private->dma_buf_next = dma_private->dma_buf_phys + 593 (NUM_DMA_LINKS * period_size); 594 595 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 596 /* This happens if the number of periods == NUM_DMA_LINKS */ 597 dma_private->dma_buf_next = dma_private->dma_buf_phys; 598 599 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 600 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 601 602 /* Due to a quirk of the SSI's STX register, the target address 603 * for the DMA operations depends on the sample size. So we calculate 604 * that offset here. While we're at it, also tell the DMA controller 605 * how much data to transfer per sample. 606 */ 607 switch (sample_bits) { 608 case 8: 609 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 610 ssi_sxx_phys += 3; 611 break; 612 case 16: 613 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 614 ssi_sxx_phys += 2; 615 break; 616 case 32: 617 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 618 break; 619 default: 620 /* We should never get here */ 621 dev_err(dev, "unsupported sample size %u\n", sample_bits); 622 return -EINVAL; 623 } 624 625 /* 626 * BWC determines how many bytes are sent/received before the DMA 627 * controller checks the SSI to see if it needs to stop. BWC should 628 * always be a multiple of the frame size, so that we always transmit 629 * whole frames. Each frame occupies two slots in the FIFO. The 630 * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two 631 * (MR[BWC] can only represent even powers of two). 632 * 633 * To simplify the process, we set BWC to the largest value that is 634 * less than or equal to the FIFO watermark. For playback, this ensures 635 * that we transfer the maximum amount without overrunning the FIFO. 636 * For capture, this ensures that we transfer the maximum amount without 637 * underrunning the FIFO. 638 * 639 * f = SSI FIFO depth 640 * w = SSI watermark value (which equals f - 2) 641 * b = DMA bandwidth count (in bytes) 642 * s = sample size (in bytes, which equals frame_size * 2) 643 * 644 * For playback, we never transmit more than the transmit FIFO 645 * watermark, otherwise we might write more data than the FIFO can hold. 646 * The watermark is equal to the FIFO depth minus two. 647 * 648 * For capture, two equations must hold: 649 * w > f - (b / s) 650 * w >= b / s 651 * 652 * So, b > 2 * s, but b must also be <= s * w. To simplify, we set 653 * b = s * w, which is equal to 654 * (dma_private->ssi_fifo_depth - 2) * sample_bytes. 655 */ 656 mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes); 657 658 out_be32(&dma_channel->mr, mr); 659 660 for (i = 0; i < NUM_DMA_LINKS; i++) { 661 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 662 663 link->count = cpu_to_be32(period_size); 664 665 /* The snoop bit tells the DMA controller whether it should tell 666 * the ECM to snoop during a read or write to an address. For 667 * audio, we use DMA to transfer data between memory and an I/O 668 * device (the SSI's STX0 or SRX0 register). Snooping is only 669 * needed if there is a cache, so we need to snoop memory 670 * addresses only. For playback, that means we snoop the source 671 * but not the destination. For capture, we snoop the 672 * destination but not the source. 673 * 674 * Note that failing to snoop properly is unlikely to cause 675 * cache incoherency if the period size is larger than the 676 * size of L1 cache. This is because filling in one period will 677 * flush out the data for the previous period. So if you 678 * increased period_bytes_min to a large enough size, you might 679 * get more performance by not snooping, and you'll still be 680 * okay. You'll need to update fsl_dma_update_pointers() also. 681 */ 682 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 683 link->source_addr = cpu_to_be32(temp_addr); 684 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 685 upper_32_bits(temp_addr)); 686 687 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 688 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 689 upper_32_bits(ssi_sxx_phys)); 690 } else { 691 link->source_addr = cpu_to_be32(ssi_sxx_phys); 692 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 693 upper_32_bits(ssi_sxx_phys)); 694 695 link->dest_addr = cpu_to_be32(temp_addr); 696 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 697 upper_32_bits(temp_addr)); 698 } 699 700 temp_addr += period_size; 701 } 702 703 return 0; 704 } 705 706 /** 707 * fsl_dma_pointer: determine the current position of the DMA transfer 708 * 709 * This function is called by ALSA when ALSA wants to know where in the 710 * stream buffer the hardware currently is. 711 * 712 * For playback, the SAR register contains the physical address of the most 713 * recent DMA transfer. For capture, the value is in the DAR register. 714 * 715 * The base address of the buffer is stored in the source_addr field of the 716 * first link descriptor. 717 */ 718 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream) 719 { 720 struct snd_pcm_runtime *runtime = substream->runtime; 721 struct fsl_dma_private *dma_private = runtime->private_data; 722 struct snd_soc_pcm_runtime *rtd = substream->private_data; 723 struct device *dev = rtd->platform->dev; 724 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 725 dma_addr_t position; 726 snd_pcm_uframes_t frames; 727 728 /* Obtain the current DMA pointer, but don't read the ESAD bits if we 729 * only have 32-bit DMA addresses. This function is typically called 730 * in interrupt context, so we need to optimize it. 731 */ 732 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 733 position = in_be32(&dma_channel->sar); 734 #ifdef CONFIG_PHYS_64BIT 735 position |= (u64)(in_be32(&dma_channel->satr) & 736 CCSR_DMA_ATR_ESAD_MASK) << 32; 737 #endif 738 } else { 739 position = in_be32(&dma_channel->dar); 740 #ifdef CONFIG_PHYS_64BIT 741 position |= (u64)(in_be32(&dma_channel->datr) & 742 CCSR_DMA_ATR_ESAD_MASK) << 32; 743 #endif 744 } 745 746 /* 747 * When capture is started, the SSI immediately starts to fill its FIFO. 748 * This means that the DMA controller is not started until the FIFO is 749 * full. However, ALSA calls this function before that happens, when 750 * MR.DAR is still zero. In this case, just return zero to indicate 751 * that nothing has been received yet. 752 */ 753 if (!position) 754 return 0; 755 756 if ((position < dma_private->dma_buf_phys) || 757 (position > dma_private->dma_buf_end)) { 758 dev_err(dev, "dma pointer is out of range, halting stream\n"); 759 return SNDRV_PCM_POS_XRUN; 760 } 761 762 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 763 764 /* 765 * If the current address is just past the end of the buffer, wrap it 766 * around. 767 */ 768 if (frames == runtime->buffer_size) 769 frames = 0; 770 771 return frames; 772 } 773 774 /** 775 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 776 * 777 * Release the resources allocated in fsl_dma_hw_params() and de-program the 778 * registers. 779 * 780 * This function can be called multiple times. 781 */ 782 static int fsl_dma_hw_free(struct snd_pcm_substream *substream) 783 { 784 struct snd_pcm_runtime *runtime = substream->runtime; 785 struct fsl_dma_private *dma_private = runtime->private_data; 786 787 if (dma_private) { 788 struct ccsr_dma_channel __iomem *dma_channel; 789 790 dma_channel = dma_private->dma_channel; 791 792 /* Stop the DMA */ 793 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 794 out_be32(&dma_channel->mr, 0); 795 796 /* Reset all the other registers */ 797 out_be32(&dma_channel->sr, -1); 798 out_be32(&dma_channel->clndar, 0); 799 out_be32(&dma_channel->eclndar, 0); 800 out_be32(&dma_channel->satr, 0); 801 out_be32(&dma_channel->sar, 0); 802 out_be32(&dma_channel->datr, 0); 803 out_be32(&dma_channel->dar, 0); 804 out_be32(&dma_channel->bcr, 0); 805 out_be32(&dma_channel->nlndar, 0); 806 out_be32(&dma_channel->enlndar, 0); 807 } 808 809 return 0; 810 } 811 812 /** 813 * fsl_dma_close: close the stream. 814 */ 815 static int fsl_dma_close(struct snd_pcm_substream *substream) 816 { 817 struct snd_pcm_runtime *runtime = substream->runtime; 818 struct fsl_dma_private *dma_private = runtime->private_data; 819 struct snd_soc_pcm_runtime *rtd = substream->private_data; 820 struct device *dev = rtd->platform->dev; 821 struct dma_object *dma = 822 container_of(rtd->platform->driver, struct dma_object, dai); 823 824 if (dma_private) { 825 if (dma_private->irq) 826 free_irq(dma_private->irq, dma_private); 827 828 /* Deallocate the fsl_dma_private structure */ 829 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 830 dma_private, dma_private->ld_buf_phys); 831 substream->runtime->private_data = NULL; 832 } 833 834 dma->assigned = 0; 835 836 return 0; 837 } 838 839 /* 840 * Remove this PCM driver. 841 */ 842 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm) 843 { 844 struct snd_pcm_substream *substream; 845 unsigned int i; 846 847 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 848 substream = pcm->streams[i].substream; 849 if (substream) { 850 snd_dma_free_pages(&substream->dma_buffer); 851 substream->dma_buffer.area = NULL; 852 substream->dma_buffer.addr = 0; 853 } 854 } 855 } 856 857 /** 858 * find_ssi_node -- returns the SSI node that points to his DMA channel node 859 * 860 * Although this DMA driver attempts to operate independently of the other 861 * devices, it still needs to determine some information about the SSI device 862 * that it's working with. Unfortunately, the device tree does not contain 863 * a pointer from the DMA channel node to the SSI node -- the pointer goes the 864 * other way. So we need to scan the device tree for SSI nodes until we find 865 * the one that points to the given DMA channel node. It's ugly, but at least 866 * it's contained in this one function. 867 */ 868 static struct device_node *find_ssi_node(struct device_node *dma_channel_np) 869 { 870 struct device_node *ssi_np, *np; 871 872 for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") { 873 /* Check each DMA phandle to see if it points to us. We 874 * assume that device_node pointers are a valid comparison. 875 */ 876 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0); 877 of_node_put(np); 878 if (np == dma_channel_np) 879 return ssi_np; 880 881 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0); 882 of_node_put(np); 883 if (np == dma_channel_np) 884 return ssi_np; 885 } 886 887 return NULL; 888 } 889 890 static struct snd_pcm_ops fsl_dma_ops = { 891 .open = fsl_dma_open, 892 .close = fsl_dma_close, 893 .ioctl = snd_pcm_lib_ioctl, 894 .hw_params = fsl_dma_hw_params, 895 .hw_free = fsl_dma_hw_free, 896 .pointer = fsl_dma_pointer, 897 }; 898 899 static int fsl_soc_dma_probe(struct platform_device *pdev) 900 { 901 struct dma_object *dma; 902 struct device_node *np = pdev->dev.of_node; 903 struct device_node *ssi_np; 904 struct resource res; 905 const uint32_t *iprop; 906 int ret; 907 908 /* Find the SSI node that points to us. */ 909 ssi_np = find_ssi_node(np); 910 if (!ssi_np) { 911 dev_err(&pdev->dev, "cannot find parent SSI node\n"); 912 return -ENODEV; 913 } 914 915 ret = of_address_to_resource(ssi_np, 0, &res); 916 if (ret) { 917 dev_err(&pdev->dev, "could not determine resources for %s\n", 918 ssi_np->full_name); 919 of_node_put(ssi_np); 920 return ret; 921 } 922 923 dma = kzalloc(sizeof(*dma) + strlen(np->full_name), GFP_KERNEL); 924 if (!dma) { 925 dev_err(&pdev->dev, "could not allocate dma object\n"); 926 of_node_put(ssi_np); 927 return -ENOMEM; 928 } 929 930 strcpy(dma->path, np->full_name); 931 dma->dai.ops = &fsl_dma_ops; 932 dma->dai.pcm_new = fsl_dma_new; 933 dma->dai.pcm_free = fsl_dma_free_dma_buffers; 934 935 /* Store the SSI-specific information that we need */ 936 dma->ssi_stx_phys = res.start + offsetof(struct ccsr_ssi, stx0); 937 dma->ssi_srx_phys = res.start + offsetof(struct ccsr_ssi, srx0); 938 939 iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL); 940 if (iprop) 941 dma->ssi_fifo_depth = be32_to_cpup(iprop); 942 else 943 /* Older 8610 DTs didn't have the fifo-depth property */ 944 dma->ssi_fifo_depth = 8; 945 946 of_node_put(ssi_np); 947 948 ret = snd_soc_register_platform(&pdev->dev, &dma->dai); 949 if (ret) { 950 dev_err(&pdev->dev, "could not register platform\n"); 951 kfree(dma); 952 return ret; 953 } 954 955 dma->channel = of_iomap(np, 0); 956 dma->irq = irq_of_parse_and_map(np, 0); 957 958 dev_set_drvdata(&pdev->dev, dma); 959 960 return 0; 961 } 962 963 static int fsl_soc_dma_remove(struct platform_device *pdev) 964 { 965 struct dma_object *dma = dev_get_drvdata(&pdev->dev); 966 967 snd_soc_unregister_platform(&pdev->dev); 968 iounmap(dma->channel); 969 irq_dispose_mapping(dma->irq); 970 kfree(dma); 971 972 return 0; 973 } 974 975 static const struct of_device_id fsl_soc_dma_ids[] = { 976 { .compatible = "fsl,ssi-dma-channel", }, 977 {} 978 }; 979 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids); 980 981 static struct platform_driver fsl_soc_dma_driver = { 982 .driver = { 983 .name = "fsl-pcm-audio", 984 .owner = THIS_MODULE, 985 .of_match_table = fsl_soc_dma_ids, 986 }, 987 .probe = fsl_soc_dma_probe, 988 .remove = fsl_soc_dma_remove, 989 }; 990 991 module_platform_driver(fsl_soc_dma_driver); 992 993 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 994 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver"); 995 MODULE_LICENSE("GPL v2"); 996