1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // cs35l41.c -- CS35l41 ALSA SoC audio driver 4 // 5 // Copyright 2017-2021 Cirrus Logic, Inc. 6 // 7 // Author: David Rhodes <david.rhodes@cirrus.com> 8 9 #include <linux/acpi.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/of_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/property.h> 19 #include <sound/initval.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/soc-dapm.h> 24 #include <sound/tlv.h> 25 26 #include "cs35l41.h" 27 28 static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = { 29 "VA", 30 "VP", 31 }; 32 33 struct cs35l41_pll_sysclk_config { 34 int freq; 35 int clk_cfg; 36 }; 37 38 static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = { 39 { 32768, 0x00 }, 40 { 8000, 0x01 }, 41 { 11025, 0x02 }, 42 { 12000, 0x03 }, 43 { 16000, 0x04 }, 44 { 22050, 0x05 }, 45 { 24000, 0x06 }, 46 { 32000, 0x07 }, 47 { 44100, 0x08 }, 48 { 48000, 0x09 }, 49 { 88200, 0x0A }, 50 { 96000, 0x0B }, 51 { 128000, 0x0C }, 52 { 176400, 0x0D }, 53 { 192000, 0x0E }, 54 { 256000, 0x0F }, 55 { 352800, 0x10 }, 56 { 384000, 0x11 }, 57 { 512000, 0x12 }, 58 { 705600, 0x13 }, 59 { 750000, 0x14 }, 60 { 768000, 0x15 }, 61 { 1000000, 0x16 }, 62 { 1024000, 0x17 }, 63 { 1200000, 0x18 }, 64 { 1411200, 0x19 }, 65 { 1500000, 0x1A }, 66 { 1536000, 0x1B }, 67 { 2000000, 0x1C }, 68 { 2048000, 0x1D }, 69 { 2400000, 0x1E }, 70 { 2822400, 0x1F }, 71 { 3000000, 0x20 }, 72 { 3072000, 0x21 }, 73 { 3200000, 0x22 }, 74 { 4000000, 0x23 }, 75 { 4096000, 0x24 }, 76 { 4800000, 0x25 }, 77 { 5644800, 0x26 }, 78 { 6000000, 0x27 }, 79 { 6144000, 0x28 }, 80 { 6250000, 0x29 }, 81 { 6400000, 0x2A }, 82 { 6500000, 0x2B }, 83 { 6750000, 0x2C }, 84 { 7526400, 0x2D }, 85 { 8000000, 0x2E }, 86 { 8192000, 0x2F }, 87 { 9600000, 0x30 }, 88 { 11289600, 0x31 }, 89 { 12000000, 0x32 }, 90 { 12288000, 0x33 }, 91 { 12500000, 0x34 }, 92 { 12800000, 0x35 }, 93 { 13000000, 0x36 }, 94 { 13500000, 0x37 }, 95 { 19200000, 0x38 }, 96 { 22579200, 0x39 }, 97 { 24000000, 0x3A }, 98 { 24576000, 0x3B }, 99 { 25000000, 0x3C }, 100 { 25600000, 0x3D }, 101 { 26000000, 0x3E }, 102 { 27000000, 0x3F }, 103 }; 104 105 struct cs35l41_fs_mon_config { 106 int freq; 107 unsigned int fs1; 108 unsigned int fs2; 109 }; 110 111 static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = { 112 { 32768, 2254, 3754 }, 113 { 8000, 9220, 15364 }, 114 { 11025, 6148, 10244 }, 115 { 12000, 6148, 10244 }, 116 { 16000, 4612, 7684 }, 117 { 22050, 3076, 5124 }, 118 { 24000, 3076, 5124 }, 119 { 32000, 2308, 3844 }, 120 { 44100, 1540, 2564 }, 121 { 48000, 1540, 2564 }, 122 { 88200, 772, 1284 }, 123 { 96000, 772, 1284 }, 124 { 128000, 580, 964 }, 125 { 176400, 388, 644 }, 126 { 192000, 388, 644 }, 127 { 256000, 292, 484 }, 128 { 352800, 196, 324 }, 129 { 384000, 196, 324 }, 130 { 512000, 148, 244 }, 131 { 705600, 100, 164 }, 132 { 750000, 100, 164 }, 133 { 768000, 100, 164 }, 134 { 1000000, 76, 124 }, 135 { 1024000, 76, 124 }, 136 { 1200000, 64, 104 }, 137 { 1411200, 52, 84 }, 138 { 1500000, 52, 84 }, 139 { 1536000, 52, 84 }, 140 { 2000000, 40, 64 }, 141 { 2048000, 40, 64 }, 142 { 2400000, 34, 54 }, 143 { 2822400, 28, 44 }, 144 { 3000000, 28, 44 }, 145 { 3072000, 28, 44 }, 146 { 3200000, 27, 42 }, 147 { 4000000, 22, 34 }, 148 { 4096000, 22, 34 }, 149 { 4800000, 19, 29 }, 150 { 5644800, 16, 24 }, 151 { 6000000, 16, 24 }, 152 { 6144000, 16, 24 }, 153 }; 154 155 static int cs35l41_get_fs_mon_config_index(int freq) 156 { 157 int i; 158 159 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) { 160 if (cs35l41_fs_mon[i].freq == freq) 161 return i; 162 } 163 164 return -EINVAL; 165 } 166 167 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv, 168 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 169 1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200)); 170 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1); 171 172 static const struct snd_kcontrol_new dre_ctrl = 173 SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0); 174 175 static const char * const cs35l41_pcm_sftramp_text[] = { 176 "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms" 177 }; 178 179 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, 180 CS35L41_AMP_DIG_VOL_CTRL, 0, 181 cs35l41_pcm_sftramp_text); 182 183 static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w, 184 struct snd_kcontrol *kcontrol, int event) 185 { 186 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 187 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 188 int ret; 189 190 switch (event) { 191 case SND_SOC_DAPM_PRE_PMU: 192 if (cs35l41->dsp.cs_dsp.booted) 193 return 0; 194 195 return wm_adsp_early_event(w, kcontrol, event); 196 case SND_SOC_DAPM_PRE_PMD: 197 if (cs35l41->dsp.preloaded) 198 return 0; 199 200 if (cs35l41->dsp.cs_dsp.running) { 201 ret = wm_adsp_event(w, kcontrol, event); 202 if (ret) 203 return ret; 204 } 205 206 return wm_adsp_early_event(w, kcontrol, event); 207 default: 208 return 0; 209 } 210 } 211 212 static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w, 213 struct snd_kcontrol *kcontrol, int event) 214 { 215 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 216 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 217 unsigned int fw_status; 218 int ret; 219 220 switch (event) { 221 case SND_SOC_DAPM_POST_PMU: 222 if (!cs35l41->dsp.cs_dsp.running) 223 return wm_adsp_event(w, kcontrol, event); 224 225 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &fw_status); 226 if (ret < 0) { 227 dev_err(cs35l41->dev, 228 "Failed to read firmware status: %d\n", ret); 229 return ret; 230 } 231 232 switch (fw_status) { 233 case CSPL_MBOX_STS_RUNNING: 234 case CSPL_MBOX_STS_PAUSED: 235 break; 236 default: 237 dev_err(cs35l41->dev, "Firmware status is invalid: %u\n", 238 fw_status); 239 return -EINVAL; 240 } 241 242 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap, 243 CSPL_MBOX_CMD_RESUME); 244 case SND_SOC_DAPM_PRE_PMD: 245 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap, 246 CSPL_MBOX_CMD_PAUSE); 247 default: 248 return 0; 249 } 250 } 251 252 static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"}; 253 static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32}; 254 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum, 255 CS35L41_DAC_PCM1_SRC, 256 0, CS35L41_ASP_SOURCE_MASK, 257 cs35l41_pcm_source_texts, 258 cs35l41_pcm_source_values); 259 260 static const struct snd_kcontrol_new pcm_source_mux = 261 SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum); 262 263 static const char * const cs35l41_tx_input_texts[] = { 264 "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON", 265 "VPMON", "VBSTMON", "DSPTX1", "DSPTX2" 266 }; 267 268 static const unsigned int cs35l41_tx_input_values[] = { 269 0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2, 270 CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON, 271 CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2 272 }; 273 274 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum, 275 CS35L41_ASP_TX1_SRC, 276 0, CS35L41_ASP_SOURCE_MASK, 277 cs35l41_tx_input_texts, 278 cs35l41_tx_input_values); 279 280 static const struct snd_kcontrol_new asp_tx1_mux = 281 SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum); 282 283 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum, 284 CS35L41_ASP_TX2_SRC, 285 0, CS35L41_ASP_SOURCE_MASK, 286 cs35l41_tx_input_texts, 287 cs35l41_tx_input_values); 288 289 static const struct snd_kcontrol_new asp_tx2_mux = 290 SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum); 291 292 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum, 293 CS35L41_ASP_TX3_SRC, 294 0, CS35L41_ASP_SOURCE_MASK, 295 cs35l41_tx_input_texts, 296 cs35l41_tx_input_values); 297 298 static const struct snd_kcontrol_new asp_tx3_mux = 299 SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum); 300 301 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum, 302 CS35L41_ASP_TX4_SRC, 303 0, CS35L41_ASP_SOURCE_MASK, 304 cs35l41_tx_input_texts, 305 cs35l41_tx_input_values); 306 307 static const struct snd_kcontrol_new asp_tx4_mux = 308 SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum); 309 310 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum, 311 CS35L41_DSP1_RX1_SRC, 312 0, CS35L41_ASP_SOURCE_MASK, 313 cs35l41_tx_input_texts, 314 cs35l41_tx_input_values); 315 316 static const struct snd_kcontrol_new dsp_rx1_mux = 317 SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum); 318 319 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum, 320 CS35L41_DSP1_RX2_SRC, 321 0, CS35L41_ASP_SOURCE_MASK, 322 cs35l41_tx_input_texts, 323 cs35l41_tx_input_values); 324 325 static const struct snd_kcontrol_new dsp_rx2_mux = 326 SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum); 327 328 static const struct snd_kcontrol_new cs35l41_aud_controls[] = { 329 SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL, 330 3, 0x4CF, 0x391, dig_vol_tlv), 331 SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0, 332 amp_gain_tlv), 333 SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp), 334 SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0), 335 SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0), 336 SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0), 337 SOC_SINGLE("Aux Noise Gate CH1 Switch", 338 CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0), 339 SOC_SINGLE("Aux Noise Gate CH1 Entry Delay", 340 CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0), 341 SOC_SINGLE("Aux Noise Gate CH1 Threshold", 342 CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0), 343 SOC_SINGLE("Aux Noise Gate CH2 Entry Delay", 344 CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0), 345 SOC_SINGLE("Aux Noise Gate CH2 Switch", 346 CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0), 347 SOC_SINGLE("Aux Noise Gate CH2 Threshold", 348 CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0), 349 SOC_SINGLE("SCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0), 350 SOC_SINGLE("LRCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0), 351 SOC_SINGLE("Invert Class D Switch", CS35L41_AMP_DIG_VOL_CTRL, 352 CS35L41_AMP_INV_PCM_SHIFT, 1, 0), 353 SOC_SINGLE("Amp Gain ZC Switch", CS35L41_AMP_GAIN_CTRL, 354 CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0), 355 WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), 356 WM_ADSP_FW_CONTROL("DSP1", 0), 357 }; 358 359 static void cs35l41_boost_enable(struct cs35l41_private *cs35l41, unsigned int enable) 360 { 361 switch (cs35l41->hw_cfg.bst_type) { 362 case CS35L41_INT_BOOST: 363 case CS35L41_SHD_BOOST_ACTV: 364 enable = enable ? CS35L41_BST_EN_DEFAULT : CS35L41_BST_DIS_FET_OFF; 365 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, 366 enable << CS35L41_BST_EN_SHIFT); 367 break; 368 default: 369 break; 370 } 371 } 372 373 374 static void cs35l41_error_release(struct cs35l41_private *cs35l41, unsigned int irq_err_bit, 375 unsigned int rel_err_bit) 376 { 377 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, irq_err_bit); 378 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 379 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, rel_err_bit); 380 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, 0); 381 } 382 383 static irqreturn_t cs35l41_irq(int irq, void *data) 384 { 385 struct cs35l41_private *cs35l41 = data; 386 unsigned int status[4] = { 0, 0, 0, 0 }; 387 unsigned int masks[4] = { 0, 0, 0, 0 }; 388 int ret = IRQ_NONE; 389 unsigned int i; 390 391 pm_runtime_get_sync(cs35l41->dev); 392 393 for (i = 0; i < ARRAY_SIZE(status); i++) { 394 regmap_read(cs35l41->regmap, 395 CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE), 396 &status[i]); 397 regmap_read(cs35l41->regmap, 398 CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE), 399 &masks[i]); 400 } 401 402 /* Check to see if unmasked bits are active */ 403 if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) && 404 !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) 405 goto done; 406 407 if (status[3] & CS35L41_OTP_BOOT_DONE) { 408 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4, 409 CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE); 410 } 411 412 /* 413 * The following interrupts require a 414 * protection release cycle to get the 415 * speaker out of Safe-Mode. 416 */ 417 if (status[0] & CS35L41_AMP_SHORT_ERR) { 418 dev_crit_ratelimited(cs35l41->dev, "Amp short error\n"); 419 cs35l41_error_release(cs35l41, CS35L41_AMP_SHORT_ERR, CS35L41_AMP_SHORT_ERR_RLS); 420 ret = IRQ_HANDLED; 421 } 422 423 if (status[0] & CS35L41_TEMP_WARN) { 424 dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n"); 425 cs35l41_error_release(cs35l41, CS35L41_TEMP_WARN, CS35L41_TEMP_WARN_ERR_RLS); 426 ret = IRQ_HANDLED; 427 } 428 429 if (status[0] & CS35L41_TEMP_ERR) { 430 dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n"); 431 cs35l41_error_release(cs35l41, CS35L41_TEMP_ERR, CS35L41_TEMP_ERR_RLS); 432 ret = IRQ_HANDLED; 433 } 434 435 if (status[0] & CS35L41_BST_OVP_ERR) { 436 dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n"); 437 cs35l41_boost_enable(cs35l41, 0); 438 cs35l41_error_release(cs35l41, CS35L41_BST_OVP_ERR, CS35L41_BST_OVP_ERR_RLS); 439 cs35l41_boost_enable(cs35l41, 1); 440 ret = IRQ_HANDLED; 441 } 442 443 if (status[0] & CS35L41_BST_DCM_UVP_ERR) { 444 dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n"); 445 cs35l41_boost_enable(cs35l41, 0); 446 cs35l41_error_release(cs35l41, CS35L41_BST_DCM_UVP_ERR, CS35L41_BST_UVP_ERR_RLS); 447 cs35l41_boost_enable(cs35l41, 1); 448 ret = IRQ_HANDLED; 449 } 450 451 if (status[0] & CS35L41_BST_SHORT_ERR) { 452 dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n"); 453 cs35l41_boost_enable(cs35l41, 0); 454 cs35l41_error_release(cs35l41, CS35L41_BST_SHORT_ERR, CS35L41_BST_SHORT_ERR_RLS); 455 cs35l41_boost_enable(cs35l41, 1); 456 ret = IRQ_HANDLED; 457 } 458 459 if (status[2] & CS35L41_PLL_LOCK) { 460 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS3, CS35L41_PLL_LOCK); 461 complete(&cs35l41->pll_lock); 462 ret = IRQ_HANDLED; 463 } 464 465 done: 466 pm_runtime_mark_last_busy(cs35l41->dev); 467 pm_runtime_put_autosuspend(cs35l41->dev); 468 469 return ret; 470 } 471 472 static const struct reg_sequence cs35l41_pup_patch[] = { 473 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 474 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 475 { 0x00002084, 0x002F1AA0 }, 476 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 477 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 478 }; 479 480 static const struct reg_sequence cs35l41_pdn_patch[] = { 481 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 482 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 483 { 0x00002084, 0x002F1AA3 }, 484 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 485 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 486 }; 487 488 static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w, 489 struct snd_kcontrol *kcontrol, int event) 490 { 491 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 492 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 493 unsigned int val; 494 int ret = 0; 495 496 switch (event) { 497 case SND_SOC_DAPM_PRE_PMU: 498 regmap_multi_reg_write_bypassed(cs35l41->regmap, 499 cs35l41_pup_patch, 500 ARRAY_SIZE(cs35l41_pup_patch)); 501 502 cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 1, 503 &cs35l41->pll_lock); 504 break; 505 case SND_SOC_DAPM_POST_PMD: 506 cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 0, 507 &cs35l41->pll_lock); 508 509 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 510 val, val & CS35L41_PDN_DONE_MASK, 511 1000, 100000); 512 if (ret) 513 dev_warn(cs35l41->dev, "PDN failed: %d\n", ret); 514 515 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 516 CS35L41_PDN_DONE_MASK); 517 518 regmap_multi_reg_write_bypassed(cs35l41->regmap, 519 cs35l41_pdn_patch, 520 ARRAY_SIZE(cs35l41_pdn_patch)); 521 break; 522 default: 523 dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event); 524 ret = -EINVAL; 525 } 526 527 return ret; 528 } 529 530 static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = { 531 SND_SOC_DAPM_SPK("DSP1 Preload", NULL), 532 SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0, 533 cs35l41_dsp_preload_ev, 534 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 535 SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, 536 cs35l41_dsp_audio_ev, 537 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 538 539 SND_SOC_DAPM_OUTPUT("SPK"), 540 541 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0), 542 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0), 543 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0), 544 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0), 545 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0), 546 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0), 547 548 SND_SOC_DAPM_SIGGEN("VSENSE"), 549 SND_SOC_DAPM_SIGGEN("ISENSE"), 550 SND_SOC_DAPM_SIGGEN("VP"), 551 SND_SOC_DAPM_SIGGEN("VBST"), 552 SND_SOC_DAPM_SIGGEN("TEMP"), 553 554 SND_SOC_DAPM_SUPPLY("VMON", CS35L41_PWR_CTRL2, 12, 0, NULL, 0), 555 SND_SOC_DAPM_SUPPLY("IMON", CS35L41_PWR_CTRL2, 13, 0, NULL, 0), 556 SND_SOC_DAPM_SUPPLY("VPMON", CS35L41_PWR_CTRL2, 8, 0, NULL, 0), 557 SND_SOC_DAPM_SUPPLY("VBSTMON", CS35L41_PWR_CTRL2, 9, 0, NULL, 0), 558 SND_SOC_DAPM_SUPPLY("TEMPMON", CS35L41_PWR_CTRL2, 10, 0, NULL, 0), 559 560 SND_SOC_DAPM_ADC("VMON ADC", NULL, SND_SOC_NOPM, 0, 0), 561 SND_SOC_DAPM_ADC("IMON ADC", NULL, SND_SOC_NOPM, 0, 0), 562 SND_SOC_DAPM_ADC("VPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 563 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, SND_SOC_NOPM, 0, 0), 564 SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 565 566 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0), 567 568 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0, 569 cs35l41_main_amp_event, 570 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 571 572 SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux), 573 SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux), 574 SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux), 575 SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux), 576 SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux), 577 SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux), 578 SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux), 579 SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl), 580 }; 581 582 static const struct snd_soc_dapm_route cs35l41_audio_map[] = { 583 {"DSP RX1 Source", "ASPRX1", "ASPRX1"}, 584 {"DSP RX1 Source", "ASPRX2", "ASPRX2"}, 585 {"DSP RX2 Source", "ASPRX1", "ASPRX1"}, 586 {"DSP RX2 Source", "ASPRX2", "ASPRX2"}, 587 588 {"DSP1", NULL, "DSP RX1 Source"}, 589 {"DSP1", NULL, "DSP RX2 Source"}, 590 591 {"ASP TX1 Source", "VMON", "VMON ADC"}, 592 {"ASP TX1 Source", "IMON", "IMON ADC"}, 593 {"ASP TX1 Source", "VPMON", "VPMON ADC"}, 594 {"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"}, 595 {"ASP TX1 Source", "DSPTX1", "DSP1"}, 596 {"ASP TX1 Source", "DSPTX2", "DSP1"}, 597 {"ASP TX1 Source", "ASPRX1", "ASPRX1" }, 598 {"ASP TX1 Source", "ASPRX2", "ASPRX2" }, 599 {"ASP TX2 Source", "VMON", "VMON ADC"}, 600 {"ASP TX2 Source", "IMON", "IMON ADC"}, 601 {"ASP TX2 Source", "VPMON", "VPMON ADC"}, 602 {"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"}, 603 {"ASP TX2 Source", "DSPTX1", "DSP1"}, 604 {"ASP TX2 Source", "DSPTX2", "DSP1"}, 605 {"ASP TX2 Source", "ASPRX1", "ASPRX1" }, 606 {"ASP TX2 Source", "ASPRX2", "ASPRX2" }, 607 {"ASP TX3 Source", "VMON", "VMON ADC"}, 608 {"ASP TX3 Source", "IMON", "IMON ADC"}, 609 {"ASP TX3 Source", "VPMON", "VPMON ADC"}, 610 {"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"}, 611 {"ASP TX3 Source", "DSPTX1", "DSP1"}, 612 {"ASP TX3 Source", "DSPTX2", "DSP1"}, 613 {"ASP TX3 Source", "ASPRX1", "ASPRX1" }, 614 {"ASP TX3 Source", "ASPRX2", "ASPRX2" }, 615 {"ASP TX4 Source", "VMON", "VMON ADC"}, 616 {"ASP TX4 Source", "IMON", "IMON ADC"}, 617 {"ASP TX4 Source", "VPMON", "VPMON ADC"}, 618 {"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"}, 619 {"ASP TX4 Source", "DSPTX1", "DSP1"}, 620 {"ASP TX4 Source", "DSPTX2", "DSP1"}, 621 {"ASP TX4 Source", "ASPRX1", "ASPRX1" }, 622 {"ASP TX4 Source", "ASPRX2", "ASPRX2" }, 623 {"ASPTX1", NULL, "ASP TX1 Source"}, 624 {"ASPTX2", NULL, "ASP TX2 Source"}, 625 {"ASPTX3", NULL, "ASP TX3 Source"}, 626 {"ASPTX4", NULL, "ASP TX4 Source"}, 627 {"AMP Capture", NULL, "ASPTX1"}, 628 {"AMP Capture", NULL, "ASPTX2"}, 629 {"AMP Capture", NULL, "ASPTX3"}, 630 {"AMP Capture", NULL, "ASPTX4"}, 631 632 {"DSP1", NULL, "VMON"}, 633 {"DSP1", NULL, "IMON"}, 634 {"DSP1", NULL, "VPMON"}, 635 {"DSP1", NULL, "VBSTMON"}, 636 {"DSP1", NULL, "TEMPMON"}, 637 638 {"VMON ADC", NULL, "VMON"}, 639 {"IMON ADC", NULL, "IMON"}, 640 {"VPMON ADC", NULL, "VPMON"}, 641 {"VBSTMON ADC", NULL, "VBSTMON"}, 642 {"TEMPMON ADC", NULL, "TEMPMON"}, 643 644 {"VMON ADC", NULL, "VSENSE"}, 645 {"IMON ADC", NULL, "ISENSE"}, 646 {"VPMON ADC", NULL, "VP"}, 647 {"VBSTMON ADC", NULL, "VBST"}, 648 {"TEMPMON ADC", NULL, "TEMP"}, 649 650 {"DSP1 Preload", NULL, "DSP1 Preloader"}, 651 {"DSP1", NULL, "DSP1 Preloader"}, 652 653 {"ASPRX1", NULL, "AMP Playback"}, 654 {"ASPRX2", NULL, "AMP Playback"}, 655 {"DRE", "Switch", "CLASS H"}, 656 {"Main AMP", NULL, "CLASS H"}, 657 {"Main AMP", NULL, "DRE"}, 658 {"SPK", NULL, "Main AMP"}, 659 660 {"PCM Source", "ASP", "ASPRX1"}, 661 {"PCM Source", "DSP", "DSP1"}, 662 {"CLASS H", NULL, "PCM Source"}, 663 }; 664 665 static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_n, 666 unsigned int *tx_slot, unsigned int rx_n, unsigned int *rx_slot) 667 { 668 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 669 670 return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_n, tx_slot, rx_n, rx_slot); 671 } 672 673 static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 674 { 675 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 676 unsigned int daifmt = 0; 677 678 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 679 case SND_SOC_DAIFMT_CBP_CFP: 680 daifmt |= CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK; 681 break; 682 case SND_SOC_DAIFMT_CBC_CFC: 683 break; 684 default: 685 dev_warn(cs35l41->dev, "Mixed provider/consumer mode unsupported\n"); 686 return -EINVAL; 687 } 688 689 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 690 case SND_SOC_DAIFMT_DSP_A: 691 break; 692 case SND_SOC_DAIFMT_I2S: 693 daifmt |= 2 << CS35L41_ASP_FMT_SHIFT; 694 break; 695 default: 696 dev_warn(cs35l41->dev, "Invalid or unsupported DAI format\n"); 697 return -EINVAL; 698 } 699 700 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 701 case SND_SOC_DAIFMT_NB_IF: 702 daifmt |= CS35L41_LRCLK_INV_MASK; 703 break; 704 case SND_SOC_DAIFMT_IB_NF: 705 daifmt |= CS35L41_SCLK_INV_MASK; 706 break; 707 case SND_SOC_DAIFMT_IB_IF: 708 daifmt |= CS35L41_LRCLK_INV_MASK | CS35L41_SCLK_INV_MASK; 709 break; 710 case SND_SOC_DAIFMT_NB_NF: 711 break; 712 default: 713 dev_warn(cs35l41->dev, "Invalid DAI clock INV\n"); 714 return -EINVAL; 715 } 716 717 return regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 718 CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK | 719 CS35L41_ASP_FMT_MASK | CS35L41_LRCLK_INV_MASK | 720 CS35L41_SCLK_INV_MASK, daifmt); 721 } 722 723 struct cs35l41_global_fs_config { 724 int rate; 725 int fs_cfg; 726 }; 727 728 static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = { 729 { 12000, 0x01 }, 730 { 24000, 0x02 }, 731 { 48000, 0x03 }, 732 { 96000, 0x04 }, 733 { 192000, 0x05 }, 734 { 11025, 0x09 }, 735 { 22050, 0x0A }, 736 { 44100, 0x0B }, 737 { 88200, 0x0C }, 738 { 176400, 0x0D }, 739 { 8000, 0x11 }, 740 { 16000, 0x12 }, 741 { 32000, 0x13 }, 742 }; 743 744 static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream, 745 struct snd_pcm_hw_params *params, 746 struct snd_soc_dai *dai) 747 { 748 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 749 unsigned int rate = params_rate(params); 750 u8 asp_wl; 751 int i; 752 753 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) { 754 if (rate == cs35l41_fs_rates[i].rate) 755 break; 756 } 757 758 if (i >= ARRAY_SIZE(cs35l41_fs_rates)) { 759 dev_err(cs35l41->dev, "Unsupported rate: %u\n", rate); 760 return -EINVAL; 761 } 762 763 asp_wl = params_width(params); 764 765 if (i < ARRAY_SIZE(cs35l41_fs_rates)) 766 regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL, 767 CS35L41_GLOBAL_FS_MASK, 768 cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT); 769 770 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 771 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 772 CS35L41_ASP_WIDTH_RX_MASK, 773 asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT); 774 regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL, 775 CS35L41_ASP_RX_WL_MASK, 776 asp_wl << CS35L41_ASP_RX_WL_SHIFT); 777 } else { 778 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 779 CS35L41_ASP_WIDTH_TX_MASK, 780 asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT); 781 regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL, 782 CS35L41_ASP_TX_WL_MASK, 783 asp_wl << CS35L41_ASP_TX_WL_SHIFT); 784 } 785 786 return 0; 787 } 788 789 static int cs35l41_get_clk_config(int freq) 790 { 791 int i; 792 793 for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) { 794 if (cs35l41_pll_sysclk[i].freq == freq) 795 return cs35l41_pll_sysclk[i].clk_cfg; 796 } 797 798 return -EINVAL; 799 } 800 801 static const unsigned int cs35l41_src_rates[] = { 802 8000, 12000, 11025, 16000, 22050, 24000, 32000, 803 44100, 48000, 88200, 96000, 176400, 192000 804 }; 805 806 static const struct snd_pcm_hw_constraint_list cs35l41_constraints = { 807 .count = ARRAY_SIZE(cs35l41_src_rates), 808 .list = cs35l41_src_rates, 809 }; 810 811 static int cs35l41_pcm_startup(struct snd_pcm_substream *substream, 812 struct snd_soc_dai *dai) 813 { 814 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 815 816 reinit_completion(&cs35l41->pll_lock); 817 818 if (substream->runtime) 819 return snd_pcm_hw_constraint_list(substream->runtime, 0, 820 SNDRV_PCM_HW_PARAM_RATE, 821 &cs35l41_constraints); 822 return 0; 823 } 824 825 static int cs35l41_component_set_sysclk(struct snd_soc_component *component, 826 int clk_id, int source, 827 unsigned int freq, int dir) 828 { 829 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 830 int extclk_cfg, clksrc; 831 832 switch (clk_id) { 833 case CS35L41_CLKID_SCLK: 834 clksrc = CS35L41_PLLSRC_SCLK; 835 break; 836 case CS35L41_CLKID_LRCLK: 837 clksrc = CS35L41_PLLSRC_LRCLK; 838 break; 839 case CS35L41_CLKID_MCLK: 840 clksrc = CS35L41_PLLSRC_MCLK; 841 break; 842 default: 843 dev_err(cs35l41->dev, "Invalid CLK Config\n"); 844 return -EINVAL; 845 } 846 847 extclk_cfg = cs35l41_get_clk_config(freq); 848 849 if (extclk_cfg < 0) { 850 dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n", 851 extclk_cfg, freq); 852 return -EINVAL; 853 } 854 855 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 856 CS35L41_PLL_OPENLOOP_MASK, 857 1 << CS35L41_PLL_OPENLOOP_SHIFT); 858 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 859 CS35L41_REFCLK_FREQ_MASK, 860 extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT); 861 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 862 CS35L41_PLL_CLK_EN_MASK, 863 0 << CS35L41_PLL_CLK_EN_SHIFT); 864 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 865 CS35L41_PLL_CLK_SEL_MASK, clksrc); 866 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 867 CS35L41_PLL_OPENLOOP_MASK, 868 0 << CS35L41_PLL_OPENLOOP_SHIFT); 869 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 870 CS35L41_PLL_CLK_EN_MASK, 871 1 << CS35L41_PLL_CLK_EN_SHIFT); 872 873 return 0; 874 } 875 876 static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai, 877 int clk_id, unsigned int freq, int dir) 878 { 879 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 880 unsigned int fs1_val; 881 unsigned int fs2_val; 882 unsigned int val; 883 int fsindex; 884 885 fsindex = cs35l41_get_fs_mon_config_index(freq); 886 if (fsindex < 0) { 887 dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq); 888 return -EINVAL; 889 } 890 891 dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq); 892 893 if (freq <= 6144000) { 894 /* Use the lookup table */ 895 fs1_val = cs35l41_fs_mon[fsindex].fs1; 896 fs2_val = cs35l41_fs_mon[fsindex].fs2; 897 } else { 898 /* Use hard-coded values */ 899 fs1_val = 0x10; 900 fs2_val = 0x24; 901 } 902 903 val = fs1_val; 904 val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK; 905 regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val); 906 907 return 0; 908 } 909 910 static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) 911 { 912 struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg; 913 int ret; 914 915 if (!hw_cfg->valid) 916 return -EINVAL; 917 918 if (hw_cfg->bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH) 919 return -EINVAL; 920 921 /* Required */ 922 ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg); 923 if (ret) 924 return ret; 925 926 /* Optional */ 927 if (hw_cfg->dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && hw_cfg->dout_hiz >= 0) 928 regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, CS35L41_ASP_DOUT_HIZ_MASK, 929 hw_cfg->dout_hiz); 930 931 return 0; 932 } 933 934 static const struct snd_soc_dapm_route cs35l41_ext_bst_routes[] = { 935 {"Main AMP", NULL, "VSPK"}, 936 }; 937 938 static const struct snd_soc_dapm_widget cs35l41_ext_bst_widget[] = { 939 SND_SOC_DAPM_SUPPLY("VSPK", CS35L41_GPIO1_CTRL1, CS35L41_GPIO_LVL_SHIFT, 0, NULL, 0), 940 }; 941 942 static int cs35l41_component_probe(struct snd_soc_component *component) 943 { 944 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 945 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 946 int ret; 947 948 if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) { 949 ret = snd_soc_dapm_new_controls(dapm, cs35l41_ext_bst_widget, 950 ARRAY_SIZE(cs35l41_ext_bst_widget)); 951 if (ret) 952 return ret; 953 954 ret = snd_soc_dapm_add_routes(dapm, cs35l41_ext_bst_routes, 955 ARRAY_SIZE(cs35l41_ext_bst_routes)); 956 if (ret) 957 return ret; 958 } 959 960 return wm_adsp2_component_probe(&cs35l41->dsp, component); 961 } 962 963 static void cs35l41_component_remove(struct snd_soc_component *component) 964 { 965 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 966 967 wm_adsp2_component_remove(&cs35l41->dsp, component); 968 } 969 970 static const struct snd_soc_dai_ops cs35l41_ops = { 971 .startup = cs35l41_pcm_startup, 972 .set_fmt = cs35l41_set_dai_fmt, 973 .hw_params = cs35l41_pcm_hw_params, 974 .set_sysclk = cs35l41_dai_set_sysclk, 975 .set_channel_map = cs35l41_set_channel_map, 976 }; 977 978 static struct snd_soc_dai_driver cs35l41_dai[] = { 979 { 980 .name = "cs35l41-pcm", 981 .id = 0, 982 .playback = { 983 .stream_name = "AMP Playback", 984 .channels_min = 1, 985 .channels_max = 2, 986 .rates = SNDRV_PCM_RATE_KNOT, 987 .formats = CS35L41_RX_FORMATS, 988 }, 989 .capture = { 990 .stream_name = "AMP Capture", 991 .channels_min = 1, 992 .channels_max = 4, 993 .rates = SNDRV_PCM_RATE_KNOT, 994 .formats = CS35L41_TX_FORMATS, 995 }, 996 .ops = &cs35l41_ops, 997 .symmetric_rate = 1, 998 }, 999 }; 1000 1001 static const struct snd_soc_component_driver soc_component_dev_cs35l41 = { 1002 .name = "cs35l41-codec", 1003 .probe = cs35l41_component_probe, 1004 .remove = cs35l41_component_remove, 1005 1006 .dapm_widgets = cs35l41_dapm_widgets, 1007 .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets), 1008 .dapm_routes = cs35l41_audio_map, 1009 .num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map), 1010 1011 .controls = cs35l41_aud_controls, 1012 .num_controls = ARRAY_SIZE(cs35l41_aud_controls), 1013 .set_sysclk = cs35l41_component_set_sysclk, 1014 1015 .endianness = 1, 1016 }; 1017 1018 static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cfg) 1019 { 1020 struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1; 1021 struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2; 1022 unsigned int val; 1023 int ret; 1024 1025 /* Some ACPI systems received the Shared Boost feature before the upstream driver, 1026 * leaving those systems with deprecated _DSD properties. 1027 * To correctly configure those systems add shared-boost-active and shared-boost-passive 1028 * properties mapped to the correct value in boost-type. 1029 * These two are not DT properties and should not be used in new systems designs. 1030 */ 1031 if (device_property_read_bool(dev, "cirrus,shared-boost-active")) { 1032 hw_cfg->bst_type = CS35L41_SHD_BOOST_ACTV; 1033 } else if (device_property_read_bool(dev, "cirrus,shared-boost-passive")) { 1034 hw_cfg->bst_type = CS35L41_SHD_BOOST_PASS; 1035 } else { 1036 ret = device_property_read_u32(dev, "cirrus,boost-type", &val); 1037 if (ret >= 0) 1038 hw_cfg->bst_type = val; 1039 } 1040 1041 ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val); 1042 if (ret >= 0) 1043 hw_cfg->bst_ipk = val; 1044 else 1045 hw_cfg->bst_ipk = -1; 1046 1047 ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val); 1048 if (ret >= 0) 1049 hw_cfg->bst_ind = val; 1050 else 1051 hw_cfg->bst_ind = -1; 1052 1053 ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val); 1054 if (ret >= 0) 1055 hw_cfg->bst_cap = val; 1056 else 1057 hw_cfg->bst_cap = -1; 1058 1059 ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val); 1060 if (ret >= 0) 1061 hw_cfg->dout_hiz = val; 1062 else 1063 hw_cfg->dout_hiz = -1; 1064 1065 /* GPIO1 Pin Config */ 1066 gpio1->pol_inv = device_property_read_bool(dev, "cirrus,gpio1-polarity-invert"); 1067 gpio1->out_en = device_property_read_bool(dev, "cirrus,gpio1-output-enable"); 1068 ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", &val); 1069 if (ret >= 0) { 1070 gpio1->func = val; 1071 gpio1->valid = true; 1072 } 1073 1074 /* GPIO2 Pin Config */ 1075 gpio2->pol_inv = device_property_read_bool(dev, "cirrus,gpio2-polarity-invert"); 1076 gpio2->out_en = device_property_read_bool(dev, "cirrus,gpio2-output-enable"); 1077 ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", &val); 1078 if (ret >= 0) { 1079 gpio2->func = val; 1080 gpio2->valid = true; 1081 } 1082 1083 hw_cfg->valid = true; 1084 1085 return 0; 1086 } 1087 1088 static int cs35l41_dsp_init(struct cs35l41_private *cs35l41) 1089 { 1090 struct wm_adsp *dsp; 1091 int ret; 1092 1093 dsp = &cs35l41->dsp; 1094 dsp->part = "cs35l41"; 1095 dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */ 1096 dsp->toggle_preload = true; 1097 1098 cs35l41_configure_cs_dsp(cs35l41->dev, cs35l41->regmap, &dsp->cs_dsp); 1099 1100 ret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap); 1101 if (ret < 0) 1102 return ret; 1103 1104 ret = wm_halo_init(dsp); 1105 if (ret) { 1106 dev_err(cs35l41->dev, "wm_halo_init failed: %d\n", ret); 1107 return ret; 1108 } 1109 1110 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC, 1111 CS35L41_INPUT_SRC_VPMON); 1112 if (ret < 0) { 1113 dev_err(cs35l41->dev, "Write INPUT_SRC_VPMON failed: %d\n", ret); 1114 goto err_dsp; 1115 } 1116 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC, 1117 CS35L41_INPUT_SRC_CLASSH); 1118 if (ret < 0) { 1119 dev_err(cs35l41->dev, "Write INPUT_SRC_CLASSH failed: %d\n", ret); 1120 goto err_dsp; 1121 } 1122 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC, 1123 CS35L41_INPUT_SRC_TEMPMON); 1124 if (ret < 0) { 1125 dev_err(cs35l41->dev, "Write INPUT_SRC_TEMPMON failed: %d\n", ret); 1126 goto err_dsp; 1127 } 1128 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC, 1129 CS35L41_INPUT_SRC_RSVD); 1130 if (ret < 0) { 1131 dev_err(cs35l41->dev, "Write INPUT_SRC_RSVD failed: %d\n", ret); 1132 goto err_dsp; 1133 } 1134 1135 return 0; 1136 1137 err_dsp: 1138 wm_adsp2_remove(dsp); 1139 1140 return ret; 1141 } 1142 1143 static int cs35l41_acpi_get_name(struct cs35l41_private *cs35l41) 1144 { 1145 acpi_handle handle = ACPI_HANDLE(cs35l41->dev); 1146 const char *sub; 1147 1148 /* If there is no ACPI_HANDLE, there is no ACPI for this system, return 0 */ 1149 if (!handle) 1150 return 0; 1151 1152 sub = acpi_get_subsystem_id(handle); 1153 if (IS_ERR(sub)) { 1154 /* If bad ACPI, return 0 and fallback to legacy firmware path, otherwise fail */ 1155 if (PTR_ERR(sub) == -ENODATA) 1156 return 0; 1157 else 1158 return PTR_ERR(sub); 1159 } 1160 1161 cs35l41->dsp.system_name = sub; 1162 dev_dbg(cs35l41->dev, "Subsystem ID: %s\n", cs35l41->dsp.system_name); 1163 1164 return 0; 1165 } 1166 1167 int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg *hw_cfg) 1168 { 1169 u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match; 1170 int irq_pol = 0; 1171 int ret; 1172 1173 if (hw_cfg) { 1174 cs35l41->hw_cfg = *hw_cfg; 1175 } else { 1176 ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->hw_cfg); 1177 if (ret != 0) 1178 return ret; 1179 } 1180 1181 for (i = 0; i < CS35L41_NUM_SUPPLIES; i++) 1182 cs35l41->supplies[i].supply = cs35l41_supplies[i]; 1183 1184 ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES, 1185 cs35l41->supplies); 1186 if (ret != 0) { 1187 dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", ret); 1188 return ret; 1189 } 1190 1191 ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1192 if (ret != 0) { 1193 dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", ret); 1194 return ret; 1195 } 1196 1197 /* returning NULL can be an option if in stereo mode */ 1198 cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset", 1199 GPIOD_OUT_LOW); 1200 if (IS_ERR(cs35l41->reset_gpio)) { 1201 ret = PTR_ERR(cs35l41->reset_gpio); 1202 cs35l41->reset_gpio = NULL; 1203 if (ret == -EBUSY) { 1204 dev_info(cs35l41->dev, 1205 "Reset line busy, assuming shared reset\n"); 1206 } else { 1207 dev_err(cs35l41->dev, 1208 "Failed to get reset GPIO: %d\n", ret); 1209 goto err; 1210 } 1211 } 1212 if (cs35l41->reset_gpio) { 1213 /* satisfy minimum reset pulse width spec */ 1214 usleep_range(2000, 2100); 1215 gpiod_set_value_cansleep(cs35l41->reset_gpio, 1); 1216 } 1217 1218 usleep_range(2000, 2100); 1219 1220 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4, 1221 int_status, int_status & CS35L41_OTP_BOOT_DONE, 1222 1000, 100000); 1223 if (ret) { 1224 dev_err(cs35l41->dev, 1225 "Failed waiting for OTP_BOOT_DONE: %d\n", ret); 1226 goto err; 1227 } 1228 1229 regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status); 1230 if (int_status & CS35L41_OTP_BOOT_ERR) { 1231 dev_err(cs35l41->dev, "OTP Boot error\n"); 1232 ret = -EINVAL; 1233 goto err; 1234 } 1235 1236 ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id); 1237 if (ret < 0) { 1238 dev_err(cs35l41->dev, "Get Device ID failed: %d\n", ret); 1239 goto err; 1240 } 1241 1242 ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid); 1243 if (ret < 0) { 1244 dev_err(cs35l41->dev, "Get Revision ID failed: %d\n", ret); 1245 goto err; 1246 } 1247 1248 mtl_revid = reg_revid & CS35L41_MTLREVID_MASK; 1249 1250 /* CS35L41 will have even MTLREVID 1251 * CS35L41R will have odd MTLREVID 1252 */ 1253 chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID; 1254 if (regid != chipid_match) { 1255 dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n", 1256 regid, chipid_match); 1257 ret = -ENODEV; 1258 goto err; 1259 } 1260 1261 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap); 1262 1263 ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid); 1264 if (ret) 1265 goto err; 1266 1267 ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap); 1268 if (ret < 0) { 1269 dev_err(cs35l41->dev, "OTP Unpack failed: %d\n", ret); 1270 goto err; 1271 } 1272 1273 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); 1274 1275 irq_pol = cs35l41_gpio_config(cs35l41->regmap, &cs35l41->hw_cfg); 1276 1277 /* Set interrupt masks for critical errors */ 1278 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 1279 CS35L41_INT1_MASK_DEFAULT); 1280 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS || 1281 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV) 1282 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK, 1283 0 << CS35L41_INT3_PLL_LOCK_SHIFT); 1284 1285 ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq, 1286 IRQF_ONESHOT | IRQF_SHARED | irq_pol, 1287 "cs35l41", cs35l41); 1288 if (ret != 0) { 1289 dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret); 1290 goto err; 1291 } 1292 1293 ret = cs35l41_set_pdata(cs35l41); 1294 if (ret < 0) { 1295 dev_err(cs35l41->dev, "Set pdata failed: %d\n", ret); 1296 goto err; 1297 } 1298 1299 ret = cs35l41_acpi_get_name(cs35l41); 1300 if (ret < 0) 1301 goto err; 1302 1303 ret = cs35l41_dsp_init(cs35l41); 1304 if (ret < 0) 1305 goto err; 1306 1307 init_completion(&cs35l41->pll_lock); 1308 1309 pm_runtime_set_autosuspend_delay(cs35l41->dev, 3000); 1310 pm_runtime_use_autosuspend(cs35l41->dev); 1311 pm_runtime_mark_last_busy(cs35l41->dev); 1312 pm_runtime_set_active(cs35l41->dev); 1313 pm_runtime_get_noresume(cs35l41->dev); 1314 pm_runtime_enable(cs35l41->dev); 1315 1316 ret = devm_snd_soc_register_component(cs35l41->dev, 1317 &soc_component_dev_cs35l41, 1318 cs35l41_dai, ARRAY_SIZE(cs35l41_dai)); 1319 if (ret < 0) { 1320 dev_err(cs35l41->dev, "Register codec failed: %d\n", ret); 1321 goto err_pm; 1322 } 1323 1324 pm_runtime_put_autosuspend(cs35l41->dev); 1325 1326 dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n", 1327 regid, reg_revid); 1328 1329 return 0; 1330 1331 err_pm: 1332 pm_runtime_disable(cs35l41->dev); 1333 pm_runtime_put_noidle(cs35l41->dev); 1334 1335 wm_adsp2_remove(&cs35l41->dsp); 1336 err: 1337 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1338 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1339 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1340 1341 return ret; 1342 } 1343 EXPORT_SYMBOL_GPL(cs35l41_probe); 1344 1345 void cs35l41_remove(struct cs35l41_private *cs35l41) 1346 { 1347 pm_runtime_get_sync(cs35l41->dev); 1348 pm_runtime_disable(cs35l41->dev); 1349 1350 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF); 1351 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS || 1352 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV) 1353 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK, 1354 1 << CS35L41_INT3_PLL_LOCK_SHIFT); 1355 kfree(cs35l41->dsp.system_name); 1356 wm_adsp2_remove(&cs35l41->dsp); 1357 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1358 1359 pm_runtime_put_noidle(cs35l41->dev); 1360 1361 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1362 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1363 } 1364 EXPORT_SYMBOL_GPL(cs35l41_remove); 1365 1366 static int __maybe_unused cs35l41_runtime_suspend(struct device *dev) 1367 { 1368 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1369 1370 dev_dbg(cs35l41->dev, "Runtime suspend\n"); 1371 1372 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running) 1373 return 0; 1374 1375 cs35l41_enter_hibernate(dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1376 1377 regcache_cache_only(cs35l41->regmap, true); 1378 regcache_mark_dirty(cs35l41->regmap); 1379 1380 return 0; 1381 } 1382 1383 static int __maybe_unused cs35l41_runtime_resume(struct device *dev) 1384 { 1385 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1386 int ret; 1387 1388 dev_dbg(cs35l41->dev, "Runtime resume\n"); 1389 1390 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running) 1391 return 0; 1392 1393 regcache_cache_only(cs35l41->regmap, false); 1394 1395 ret = cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap); 1396 if (ret) 1397 return ret; 1398 1399 /* Test key needs to be unlocked to allow the OTP settings to re-apply */ 1400 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap); 1401 ret = regcache_sync(cs35l41->regmap); 1402 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); 1403 if (ret) { 1404 dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret); 1405 return ret; 1406 } 1407 cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, &cs35l41->hw_cfg); 1408 1409 return 0; 1410 } 1411 1412 static int __maybe_unused cs35l41_sys_suspend(struct device *dev) 1413 { 1414 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1415 1416 dev_dbg(cs35l41->dev, "System suspend, disabling IRQ\n"); 1417 disable_irq(cs35l41->irq); 1418 1419 return 0; 1420 } 1421 1422 static int __maybe_unused cs35l41_sys_suspend_noirq(struct device *dev) 1423 { 1424 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1425 1426 dev_dbg(cs35l41->dev, "Late system suspend, reenabling IRQ\n"); 1427 enable_irq(cs35l41->irq); 1428 1429 return 0; 1430 } 1431 1432 static int __maybe_unused cs35l41_sys_resume_noirq(struct device *dev) 1433 { 1434 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1435 1436 dev_dbg(cs35l41->dev, "Early system resume, disabling IRQ\n"); 1437 disable_irq(cs35l41->irq); 1438 1439 return 0; 1440 } 1441 1442 static int __maybe_unused cs35l41_sys_resume(struct device *dev) 1443 { 1444 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1445 1446 dev_dbg(cs35l41->dev, "System resume, reenabling IRQ\n"); 1447 enable_irq(cs35l41->irq); 1448 1449 return 0; 1450 } 1451 1452 const struct dev_pm_ops cs35l41_pm_ops = { 1453 SET_RUNTIME_PM_OPS(cs35l41_runtime_suspend, cs35l41_runtime_resume, NULL) 1454 1455 SET_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend, cs35l41_sys_resume) 1456 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend_noirq, cs35l41_sys_resume_noirq) 1457 }; 1458 EXPORT_SYMBOL_GPL(cs35l41_pm_ops); 1459 1460 MODULE_DESCRIPTION("ASoC CS35L41 driver"); 1461 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>"); 1462 MODULE_LICENSE("GPL"); 1463