1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // cs35l41.c -- CS35l41 ALSA SoC audio driver 4 // 5 // Copyright 2017-2021 Cirrus Logic, Inc. 6 // 7 // Author: David Rhodes <david.rhodes@cirrus.com> 8 9 #include <linux/acpi.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/of_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/property.h> 19 #include <sound/initval.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/soc-dapm.h> 24 #include <sound/tlv.h> 25 26 #include "cs35l41.h" 27 28 static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = { 29 "VA", 30 "VP", 31 }; 32 33 struct cs35l41_pll_sysclk_config { 34 int freq; 35 int clk_cfg; 36 }; 37 38 static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = { 39 { 32768, 0x00 }, 40 { 8000, 0x01 }, 41 { 11025, 0x02 }, 42 { 12000, 0x03 }, 43 { 16000, 0x04 }, 44 { 22050, 0x05 }, 45 { 24000, 0x06 }, 46 { 32000, 0x07 }, 47 { 44100, 0x08 }, 48 { 48000, 0x09 }, 49 { 88200, 0x0A }, 50 { 96000, 0x0B }, 51 { 128000, 0x0C }, 52 { 176400, 0x0D }, 53 { 192000, 0x0E }, 54 { 256000, 0x0F }, 55 { 352800, 0x10 }, 56 { 384000, 0x11 }, 57 { 512000, 0x12 }, 58 { 705600, 0x13 }, 59 { 750000, 0x14 }, 60 { 768000, 0x15 }, 61 { 1000000, 0x16 }, 62 { 1024000, 0x17 }, 63 { 1200000, 0x18 }, 64 { 1411200, 0x19 }, 65 { 1500000, 0x1A }, 66 { 1536000, 0x1B }, 67 { 2000000, 0x1C }, 68 { 2048000, 0x1D }, 69 { 2400000, 0x1E }, 70 { 2822400, 0x1F }, 71 { 3000000, 0x20 }, 72 { 3072000, 0x21 }, 73 { 3200000, 0x22 }, 74 { 4000000, 0x23 }, 75 { 4096000, 0x24 }, 76 { 4800000, 0x25 }, 77 { 5644800, 0x26 }, 78 { 6000000, 0x27 }, 79 { 6144000, 0x28 }, 80 { 6250000, 0x29 }, 81 { 6400000, 0x2A }, 82 { 6500000, 0x2B }, 83 { 6750000, 0x2C }, 84 { 7526400, 0x2D }, 85 { 8000000, 0x2E }, 86 { 8192000, 0x2F }, 87 { 9600000, 0x30 }, 88 { 11289600, 0x31 }, 89 { 12000000, 0x32 }, 90 { 12288000, 0x33 }, 91 { 12500000, 0x34 }, 92 { 12800000, 0x35 }, 93 { 13000000, 0x36 }, 94 { 13500000, 0x37 }, 95 { 19200000, 0x38 }, 96 { 22579200, 0x39 }, 97 { 24000000, 0x3A }, 98 { 24576000, 0x3B }, 99 { 25000000, 0x3C }, 100 { 25600000, 0x3D }, 101 { 26000000, 0x3E }, 102 { 27000000, 0x3F }, 103 }; 104 105 struct cs35l41_fs_mon_config { 106 int freq; 107 unsigned int fs1; 108 unsigned int fs2; 109 }; 110 111 static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = { 112 { 32768, 2254, 3754 }, 113 { 8000, 9220, 15364 }, 114 { 11025, 6148, 10244 }, 115 { 12000, 6148, 10244 }, 116 { 16000, 4612, 7684 }, 117 { 22050, 3076, 5124 }, 118 { 24000, 3076, 5124 }, 119 { 32000, 2308, 3844 }, 120 { 44100, 1540, 2564 }, 121 { 48000, 1540, 2564 }, 122 { 88200, 772, 1284 }, 123 { 96000, 772, 1284 }, 124 { 128000, 580, 964 }, 125 { 176400, 388, 644 }, 126 { 192000, 388, 644 }, 127 { 256000, 292, 484 }, 128 { 352800, 196, 324 }, 129 { 384000, 196, 324 }, 130 { 512000, 148, 244 }, 131 { 705600, 100, 164 }, 132 { 750000, 100, 164 }, 133 { 768000, 100, 164 }, 134 { 1000000, 76, 124 }, 135 { 1024000, 76, 124 }, 136 { 1200000, 64, 104 }, 137 { 1411200, 52, 84 }, 138 { 1500000, 52, 84 }, 139 { 1536000, 52, 84 }, 140 { 2000000, 40, 64 }, 141 { 2048000, 40, 64 }, 142 { 2400000, 34, 54 }, 143 { 2822400, 28, 44 }, 144 { 3000000, 28, 44 }, 145 { 3072000, 28, 44 }, 146 { 3200000, 27, 42 }, 147 { 4000000, 22, 34 }, 148 { 4096000, 22, 34 }, 149 { 4800000, 19, 29 }, 150 { 5644800, 16, 24 }, 151 { 6000000, 16, 24 }, 152 { 6144000, 16, 24 }, 153 }; 154 155 static int cs35l41_get_fs_mon_config_index(int freq) 156 { 157 int i; 158 159 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) { 160 if (cs35l41_fs_mon[i].freq == freq) 161 return i; 162 } 163 164 return -EINVAL; 165 } 166 167 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv, 168 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 169 1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200)); 170 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1); 171 172 static const struct snd_kcontrol_new dre_ctrl = 173 SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0); 174 175 static const char * const cs35l41_pcm_sftramp_text[] = { 176 "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms" 177 }; 178 179 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, 180 CS35L41_AMP_DIG_VOL_CTRL, 0, 181 cs35l41_pcm_sftramp_text); 182 183 static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w, 184 struct snd_kcontrol *kcontrol, int event) 185 { 186 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 187 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 188 int ret; 189 190 switch (event) { 191 case SND_SOC_DAPM_PRE_PMU: 192 if (cs35l41->dsp.cs_dsp.booted) 193 return 0; 194 195 return wm_adsp_early_event(w, kcontrol, event); 196 case SND_SOC_DAPM_PRE_PMD: 197 if (cs35l41->dsp.preloaded) 198 return 0; 199 200 if (cs35l41->dsp.cs_dsp.running) { 201 ret = wm_adsp_event(w, kcontrol, event); 202 if (ret) 203 return ret; 204 } 205 206 return wm_adsp_early_event(w, kcontrol, event); 207 default: 208 return 0; 209 } 210 } 211 212 static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w, 213 struct snd_kcontrol *kcontrol, int event) 214 { 215 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 216 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 217 unsigned int fw_status; 218 int ret; 219 220 switch (event) { 221 case SND_SOC_DAPM_POST_PMU: 222 if (!cs35l41->dsp.cs_dsp.running) 223 return wm_adsp_event(w, kcontrol, event); 224 225 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &fw_status); 226 if (ret < 0) { 227 dev_err(cs35l41->dev, 228 "Failed to read firmware status: %d\n", ret); 229 return ret; 230 } 231 232 switch (fw_status) { 233 case CSPL_MBOX_STS_RUNNING: 234 case CSPL_MBOX_STS_PAUSED: 235 break; 236 default: 237 dev_err(cs35l41->dev, "Firmware status is invalid: %u\n", 238 fw_status); 239 return -EINVAL; 240 } 241 242 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap, 243 CSPL_MBOX_CMD_RESUME); 244 case SND_SOC_DAPM_PRE_PMD: 245 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap, 246 CSPL_MBOX_CMD_PAUSE); 247 default: 248 return 0; 249 } 250 } 251 252 static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"}; 253 static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32}; 254 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum, 255 CS35L41_DAC_PCM1_SRC, 256 0, CS35L41_ASP_SOURCE_MASK, 257 cs35l41_pcm_source_texts, 258 cs35l41_pcm_source_values); 259 260 static const struct snd_kcontrol_new pcm_source_mux = 261 SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum); 262 263 static const char * const cs35l41_tx_input_texts[] = { 264 "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON", 265 "VPMON", "VBSTMON", "DSPTX1", "DSPTX2" 266 }; 267 268 static const unsigned int cs35l41_tx_input_values[] = { 269 0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2, 270 CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON, 271 CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2 272 }; 273 274 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum, 275 CS35L41_ASP_TX1_SRC, 276 0, CS35L41_ASP_SOURCE_MASK, 277 cs35l41_tx_input_texts, 278 cs35l41_tx_input_values); 279 280 static const struct snd_kcontrol_new asp_tx1_mux = 281 SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum); 282 283 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum, 284 CS35L41_ASP_TX2_SRC, 285 0, CS35L41_ASP_SOURCE_MASK, 286 cs35l41_tx_input_texts, 287 cs35l41_tx_input_values); 288 289 static const struct snd_kcontrol_new asp_tx2_mux = 290 SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum); 291 292 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum, 293 CS35L41_ASP_TX3_SRC, 294 0, CS35L41_ASP_SOURCE_MASK, 295 cs35l41_tx_input_texts, 296 cs35l41_tx_input_values); 297 298 static const struct snd_kcontrol_new asp_tx3_mux = 299 SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum); 300 301 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum, 302 CS35L41_ASP_TX4_SRC, 303 0, CS35L41_ASP_SOURCE_MASK, 304 cs35l41_tx_input_texts, 305 cs35l41_tx_input_values); 306 307 static const struct snd_kcontrol_new asp_tx4_mux = 308 SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum); 309 310 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum, 311 CS35L41_DSP1_RX1_SRC, 312 0, CS35L41_ASP_SOURCE_MASK, 313 cs35l41_tx_input_texts, 314 cs35l41_tx_input_values); 315 316 static const struct snd_kcontrol_new dsp_rx1_mux = 317 SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum); 318 319 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum, 320 CS35L41_DSP1_RX2_SRC, 321 0, CS35L41_ASP_SOURCE_MASK, 322 cs35l41_tx_input_texts, 323 cs35l41_tx_input_values); 324 325 static const struct snd_kcontrol_new dsp_rx2_mux = 326 SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum); 327 328 static const struct snd_kcontrol_new cs35l41_aud_controls[] = { 329 SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL, 330 3, 0x4CF, 0x391, dig_vol_tlv), 331 SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0, 332 amp_gain_tlv), 333 SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp), 334 SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0), 335 SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0), 336 SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0), 337 SOC_SINGLE("Aux Noise Gate CH1 Switch", 338 CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0), 339 SOC_SINGLE("Aux Noise Gate CH1 Entry Delay", 340 CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0), 341 SOC_SINGLE("Aux Noise Gate CH1 Threshold", 342 CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0), 343 SOC_SINGLE("Aux Noise Gate CH2 Entry Delay", 344 CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0), 345 SOC_SINGLE("Aux Noise Gate CH2 Switch", 346 CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0), 347 SOC_SINGLE("Aux Noise Gate CH2 Threshold", 348 CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0), 349 SOC_SINGLE("SCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0), 350 SOC_SINGLE("LRCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0), 351 SOC_SINGLE("Invert Class D Switch", CS35L41_AMP_DIG_VOL_CTRL, 352 CS35L41_AMP_INV_PCM_SHIFT, 1, 0), 353 SOC_SINGLE("Amp Gain ZC Switch", CS35L41_AMP_GAIN_CTRL, 354 CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0), 355 WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), 356 WM_ADSP_FW_CONTROL("DSP1", 0), 357 }; 358 359 static void cs35l41_boost_enable(struct cs35l41_private *cs35l41, unsigned int enable) 360 { 361 switch (cs35l41->hw_cfg.bst_type) { 362 case CS35L41_INT_BOOST: 363 enable = enable ? CS35L41_BST_EN_DEFAULT : CS35L41_BST_DIS_FET_OFF; 364 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, 365 enable << CS35L41_BST_EN_SHIFT); 366 break; 367 default: 368 break; 369 } 370 } 371 372 373 static void cs35l41_error_release(struct cs35l41_private *cs35l41, unsigned int irq_err_bit, 374 unsigned int rel_err_bit) 375 { 376 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, irq_err_bit); 377 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 378 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, rel_err_bit); 379 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, 0); 380 } 381 382 static irqreturn_t cs35l41_irq(int irq, void *data) 383 { 384 struct cs35l41_private *cs35l41 = data; 385 unsigned int status[4] = { 0, 0, 0, 0 }; 386 unsigned int masks[4] = { 0, 0, 0, 0 }; 387 int ret = IRQ_NONE; 388 unsigned int i; 389 390 pm_runtime_get_sync(cs35l41->dev); 391 392 for (i = 0; i < ARRAY_SIZE(status); i++) { 393 regmap_read(cs35l41->regmap, 394 CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE), 395 &status[i]); 396 regmap_read(cs35l41->regmap, 397 CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE), 398 &masks[i]); 399 } 400 401 /* Check to see if unmasked bits are active */ 402 if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) && 403 !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) 404 goto done; 405 406 if (status[3] & CS35L41_OTP_BOOT_DONE) { 407 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4, 408 CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE); 409 } 410 411 /* 412 * The following interrupts require a 413 * protection release cycle to get the 414 * speaker out of Safe-Mode. 415 */ 416 if (status[0] & CS35L41_AMP_SHORT_ERR) { 417 dev_crit_ratelimited(cs35l41->dev, "Amp short error\n"); 418 cs35l41_error_release(cs35l41, CS35L41_AMP_SHORT_ERR, CS35L41_AMP_SHORT_ERR_RLS); 419 ret = IRQ_HANDLED; 420 } 421 422 if (status[0] & CS35L41_TEMP_WARN) { 423 dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n"); 424 cs35l41_error_release(cs35l41, CS35L41_TEMP_WARN, CS35L41_TEMP_WARN_ERR_RLS); 425 ret = IRQ_HANDLED; 426 } 427 428 if (status[0] & CS35L41_TEMP_ERR) { 429 dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n"); 430 cs35l41_error_release(cs35l41, CS35L41_TEMP_ERR, CS35L41_TEMP_ERR_RLS); 431 ret = IRQ_HANDLED; 432 } 433 434 if (status[0] & CS35L41_BST_OVP_ERR) { 435 dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n"); 436 cs35l41_boost_enable(cs35l41, 0); 437 cs35l41_error_release(cs35l41, CS35L41_BST_OVP_ERR, CS35L41_BST_OVP_ERR_RLS); 438 cs35l41_boost_enable(cs35l41, 1); 439 ret = IRQ_HANDLED; 440 } 441 442 if (status[0] & CS35L41_BST_DCM_UVP_ERR) { 443 dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n"); 444 cs35l41_boost_enable(cs35l41, 0); 445 cs35l41_error_release(cs35l41, CS35L41_BST_DCM_UVP_ERR, CS35L41_BST_UVP_ERR_RLS); 446 cs35l41_boost_enable(cs35l41, 1); 447 ret = IRQ_HANDLED; 448 } 449 450 if (status[0] & CS35L41_BST_SHORT_ERR) { 451 dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n"); 452 cs35l41_boost_enable(cs35l41, 0); 453 cs35l41_error_release(cs35l41, CS35L41_BST_SHORT_ERR, CS35L41_BST_SHORT_ERR_RLS); 454 cs35l41_boost_enable(cs35l41, 1); 455 ret = IRQ_HANDLED; 456 } 457 458 done: 459 pm_runtime_mark_last_busy(cs35l41->dev); 460 pm_runtime_put_autosuspend(cs35l41->dev); 461 462 return ret; 463 } 464 465 static const struct reg_sequence cs35l41_pup_patch[] = { 466 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 467 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 468 { 0x00002084, 0x002F1AA0 }, 469 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 470 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 471 }; 472 473 static const struct reg_sequence cs35l41_pdn_patch[] = { 474 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 475 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 476 { 0x00002084, 0x002F1AA3 }, 477 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 478 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 479 }; 480 481 static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w, 482 struct snd_kcontrol *kcontrol, int event) 483 { 484 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 485 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 486 unsigned int val; 487 int ret = 0; 488 489 switch (event) { 490 case SND_SOC_DAPM_PRE_PMU: 491 regmap_multi_reg_write_bypassed(cs35l41->regmap, 492 cs35l41_pup_patch, 493 ARRAY_SIZE(cs35l41_pup_patch)); 494 495 cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 1); 496 break; 497 case SND_SOC_DAPM_POST_PMD: 498 cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 0); 499 500 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 501 val, val & CS35L41_PDN_DONE_MASK, 502 1000, 100000); 503 if (ret) 504 dev_warn(cs35l41->dev, "PDN failed: %d\n", ret); 505 506 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 507 CS35L41_PDN_DONE_MASK); 508 509 regmap_multi_reg_write_bypassed(cs35l41->regmap, 510 cs35l41_pdn_patch, 511 ARRAY_SIZE(cs35l41_pdn_patch)); 512 break; 513 default: 514 dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event); 515 ret = -EINVAL; 516 } 517 518 return ret; 519 } 520 521 static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = { 522 SND_SOC_DAPM_SPK("DSP1 Preload", NULL), 523 SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0, 524 cs35l41_dsp_preload_ev, 525 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 526 SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, 527 cs35l41_dsp_audio_ev, 528 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 529 530 SND_SOC_DAPM_OUTPUT("SPK"), 531 532 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0), 533 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0), 534 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0), 535 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0), 536 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0), 537 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0), 538 539 SND_SOC_DAPM_SIGGEN("VSENSE"), 540 SND_SOC_DAPM_SIGGEN("ISENSE"), 541 SND_SOC_DAPM_SIGGEN("VP"), 542 SND_SOC_DAPM_SIGGEN("VBST"), 543 SND_SOC_DAPM_SIGGEN("TEMP"), 544 545 SND_SOC_DAPM_SUPPLY("VMON", CS35L41_PWR_CTRL2, 12, 0, NULL, 0), 546 SND_SOC_DAPM_SUPPLY("IMON", CS35L41_PWR_CTRL2, 13, 0, NULL, 0), 547 SND_SOC_DAPM_SUPPLY("VPMON", CS35L41_PWR_CTRL2, 8, 0, NULL, 0), 548 SND_SOC_DAPM_SUPPLY("VBSTMON", CS35L41_PWR_CTRL2, 9, 0, NULL, 0), 549 SND_SOC_DAPM_SUPPLY("TEMPMON", CS35L41_PWR_CTRL2, 10, 0, NULL, 0), 550 551 SND_SOC_DAPM_ADC("VMON ADC", NULL, SND_SOC_NOPM, 0, 0), 552 SND_SOC_DAPM_ADC("IMON ADC", NULL, SND_SOC_NOPM, 0, 0), 553 SND_SOC_DAPM_ADC("VPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 554 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, SND_SOC_NOPM, 0, 0), 555 SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 556 557 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0), 558 559 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0, 560 cs35l41_main_amp_event, 561 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 562 563 SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux), 564 SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux), 565 SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux), 566 SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux), 567 SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux), 568 SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux), 569 SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux), 570 SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl), 571 }; 572 573 static const struct snd_soc_dapm_route cs35l41_audio_map[] = { 574 {"DSP RX1 Source", "ASPRX1", "ASPRX1"}, 575 {"DSP RX1 Source", "ASPRX2", "ASPRX2"}, 576 {"DSP RX2 Source", "ASPRX1", "ASPRX1"}, 577 {"DSP RX2 Source", "ASPRX2", "ASPRX2"}, 578 579 {"DSP1", NULL, "DSP RX1 Source"}, 580 {"DSP1", NULL, "DSP RX2 Source"}, 581 582 {"ASP TX1 Source", "VMON", "VMON ADC"}, 583 {"ASP TX1 Source", "IMON", "IMON ADC"}, 584 {"ASP TX1 Source", "VPMON", "VPMON ADC"}, 585 {"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"}, 586 {"ASP TX1 Source", "DSPTX1", "DSP1"}, 587 {"ASP TX1 Source", "DSPTX2", "DSP1"}, 588 {"ASP TX1 Source", "ASPRX1", "ASPRX1" }, 589 {"ASP TX1 Source", "ASPRX2", "ASPRX2" }, 590 {"ASP TX2 Source", "VMON", "VMON ADC"}, 591 {"ASP TX2 Source", "IMON", "IMON ADC"}, 592 {"ASP TX2 Source", "VPMON", "VPMON ADC"}, 593 {"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"}, 594 {"ASP TX2 Source", "DSPTX1", "DSP1"}, 595 {"ASP TX2 Source", "DSPTX2", "DSP1"}, 596 {"ASP TX2 Source", "ASPRX1", "ASPRX1" }, 597 {"ASP TX2 Source", "ASPRX2", "ASPRX2" }, 598 {"ASP TX3 Source", "VMON", "VMON ADC"}, 599 {"ASP TX3 Source", "IMON", "IMON ADC"}, 600 {"ASP TX3 Source", "VPMON", "VPMON ADC"}, 601 {"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"}, 602 {"ASP TX3 Source", "DSPTX1", "DSP1"}, 603 {"ASP TX3 Source", "DSPTX2", "DSP1"}, 604 {"ASP TX3 Source", "ASPRX1", "ASPRX1" }, 605 {"ASP TX3 Source", "ASPRX2", "ASPRX2" }, 606 {"ASP TX4 Source", "VMON", "VMON ADC"}, 607 {"ASP TX4 Source", "IMON", "IMON ADC"}, 608 {"ASP TX4 Source", "VPMON", "VPMON ADC"}, 609 {"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"}, 610 {"ASP TX4 Source", "DSPTX1", "DSP1"}, 611 {"ASP TX4 Source", "DSPTX2", "DSP1"}, 612 {"ASP TX4 Source", "ASPRX1", "ASPRX1" }, 613 {"ASP TX4 Source", "ASPRX2", "ASPRX2" }, 614 {"ASPTX1", NULL, "ASP TX1 Source"}, 615 {"ASPTX2", NULL, "ASP TX2 Source"}, 616 {"ASPTX3", NULL, "ASP TX3 Source"}, 617 {"ASPTX4", NULL, "ASP TX4 Source"}, 618 {"AMP Capture", NULL, "ASPTX1"}, 619 {"AMP Capture", NULL, "ASPTX2"}, 620 {"AMP Capture", NULL, "ASPTX3"}, 621 {"AMP Capture", NULL, "ASPTX4"}, 622 623 {"DSP1", NULL, "VMON"}, 624 {"DSP1", NULL, "IMON"}, 625 {"DSP1", NULL, "VPMON"}, 626 {"DSP1", NULL, "VBSTMON"}, 627 {"DSP1", NULL, "TEMPMON"}, 628 629 {"VMON ADC", NULL, "VMON"}, 630 {"IMON ADC", NULL, "IMON"}, 631 {"VPMON ADC", NULL, "VPMON"}, 632 {"VBSTMON ADC", NULL, "VBSTMON"}, 633 {"TEMPMON ADC", NULL, "TEMPMON"}, 634 635 {"VMON ADC", NULL, "VSENSE"}, 636 {"IMON ADC", NULL, "ISENSE"}, 637 {"VPMON ADC", NULL, "VP"}, 638 {"VBSTMON ADC", NULL, "VBST"}, 639 {"TEMPMON ADC", NULL, "TEMP"}, 640 641 {"DSP1 Preload", NULL, "DSP1 Preloader"}, 642 {"DSP1", NULL, "DSP1 Preloader"}, 643 644 {"ASPRX1", NULL, "AMP Playback"}, 645 {"ASPRX2", NULL, "AMP Playback"}, 646 {"DRE", "Switch", "CLASS H"}, 647 {"Main AMP", NULL, "CLASS H"}, 648 {"Main AMP", NULL, "DRE"}, 649 {"SPK", NULL, "Main AMP"}, 650 651 {"PCM Source", "ASP", "ASPRX1"}, 652 {"PCM Source", "DSP", "DSP1"}, 653 {"CLASS H", NULL, "PCM Source"}, 654 }; 655 656 static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_n, 657 unsigned int *tx_slot, unsigned int rx_n, unsigned int *rx_slot) 658 { 659 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 660 661 return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_n, tx_slot, rx_n, rx_slot); 662 } 663 664 static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 665 { 666 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 667 unsigned int daifmt = 0; 668 669 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 670 case SND_SOC_DAIFMT_CBP_CFP: 671 daifmt |= CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK; 672 break; 673 case SND_SOC_DAIFMT_CBC_CFC: 674 break; 675 default: 676 dev_warn(cs35l41->dev, "Mixed provider/consumer mode unsupported\n"); 677 return -EINVAL; 678 } 679 680 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 681 case SND_SOC_DAIFMT_DSP_A: 682 break; 683 case SND_SOC_DAIFMT_I2S: 684 daifmt |= 2 << CS35L41_ASP_FMT_SHIFT; 685 break; 686 default: 687 dev_warn(cs35l41->dev, "Invalid or unsupported DAI format\n"); 688 return -EINVAL; 689 } 690 691 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 692 case SND_SOC_DAIFMT_NB_IF: 693 daifmt |= CS35L41_LRCLK_INV_MASK; 694 break; 695 case SND_SOC_DAIFMT_IB_NF: 696 daifmt |= CS35L41_SCLK_INV_MASK; 697 break; 698 case SND_SOC_DAIFMT_IB_IF: 699 daifmt |= CS35L41_LRCLK_INV_MASK | CS35L41_SCLK_INV_MASK; 700 break; 701 case SND_SOC_DAIFMT_NB_NF: 702 break; 703 default: 704 dev_warn(cs35l41->dev, "Invalid DAI clock INV\n"); 705 return -EINVAL; 706 } 707 708 return regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 709 CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK | 710 CS35L41_ASP_FMT_MASK | CS35L41_LRCLK_INV_MASK | 711 CS35L41_SCLK_INV_MASK, daifmt); 712 } 713 714 struct cs35l41_global_fs_config { 715 int rate; 716 int fs_cfg; 717 }; 718 719 static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = { 720 { 12000, 0x01 }, 721 { 24000, 0x02 }, 722 { 48000, 0x03 }, 723 { 96000, 0x04 }, 724 { 192000, 0x05 }, 725 { 11025, 0x09 }, 726 { 22050, 0x0A }, 727 { 44100, 0x0B }, 728 { 88200, 0x0C }, 729 { 176400, 0x0D }, 730 { 8000, 0x11 }, 731 { 16000, 0x12 }, 732 { 32000, 0x13 }, 733 }; 734 735 static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream, 736 struct snd_pcm_hw_params *params, 737 struct snd_soc_dai *dai) 738 { 739 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 740 unsigned int rate = params_rate(params); 741 u8 asp_wl; 742 int i; 743 744 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) { 745 if (rate == cs35l41_fs_rates[i].rate) 746 break; 747 } 748 749 if (i >= ARRAY_SIZE(cs35l41_fs_rates)) { 750 dev_err(cs35l41->dev, "Unsupported rate: %u\n", rate); 751 return -EINVAL; 752 } 753 754 asp_wl = params_width(params); 755 756 if (i < ARRAY_SIZE(cs35l41_fs_rates)) 757 regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL, 758 CS35L41_GLOBAL_FS_MASK, 759 cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT); 760 761 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 762 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 763 CS35L41_ASP_WIDTH_RX_MASK, 764 asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT); 765 regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL, 766 CS35L41_ASP_RX_WL_MASK, 767 asp_wl << CS35L41_ASP_RX_WL_SHIFT); 768 } else { 769 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 770 CS35L41_ASP_WIDTH_TX_MASK, 771 asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT); 772 regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL, 773 CS35L41_ASP_TX_WL_MASK, 774 asp_wl << CS35L41_ASP_TX_WL_SHIFT); 775 } 776 777 return 0; 778 } 779 780 static int cs35l41_get_clk_config(int freq) 781 { 782 int i; 783 784 for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) { 785 if (cs35l41_pll_sysclk[i].freq == freq) 786 return cs35l41_pll_sysclk[i].clk_cfg; 787 } 788 789 return -EINVAL; 790 } 791 792 static const unsigned int cs35l41_src_rates[] = { 793 8000, 12000, 11025, 16000, 22050, 24000, 32000, 794 44100, 48000, 88200, 96000, 176400, 192000 795 }; 796 797 static const struct snd_pcm_hw_constraint_list cs35l41_constraints = { 798 .count = ARRAY_SIZE(cs35l41_src_rates), 799 .list = cs35l41_src_rates, 800 }; 801 802 static int cs35l41_pcm_startup(struct snd_pcm_substream *substream, 803 struct snd_soc_dai *dai) 804 { 805 if (substream->runtime) 806 return snd_pcm_hw_constraint_list(substream->runtime, 0, 807 SNDRV_PCM_HW_PARAM_RATE, 808 &cs35l41_constraints); 809 return 0; 810 } 811 812 static int cs35l41_component_set_sysclk(struct snd_soc_component *component, 813 int clk_id, int source, 814 unsigned int freq, int dir) 815 { 816 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 817 int extclk_cfg, clksrc; 818 819 switch (clk_id) { 820 case CS35L41_CLKID_SCLK: 821 clksrc = CS35L41_PLLSRC_SCLK; 822 break; 823 case CS35L41_CLKID_LRCLK: 824 clksrc = CS35L41_PLLSRC_LRCLK; 825 break; 826 case CS35L41_CLKID_MCLK: 827 clksrc = CS35L41_PLLSRC_MCLK; 828 break; 829 default: 830 dev_err(cs35l41->dev, "Invalid CLK Config\n"); 831 return -EINVAL; 832 } 833 834 extclk_cfg = cs35l41_get_clk_config(freq); 835 836 if (extclk_cfg < 0) { 837 dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n", 838 extclk_cfg, freq); 839 return -EINVAL; 840 } 841 842 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 843 CS35L41_PLL_OPENLOOP_MASK, 844 1 << CS35L41_PLL_OPENLOOP_SHIFT); 845 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 846 CS35L41_REFCLK_FREQ_MASK, 847 extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT); 848 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 849 CS35L41_PLL_CLK_EN_MASK, 850 0 << CS35L41_PLL_CLK_EN_SHIFT); 851 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 852 CS35L41_PLL_CLK_SEL_MASK, clksrc); 853 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 854 CS35L41_PLL_OPENLOOP_MASK, 855 0 << CS35L41_PLL_OPENLOOP_SHIFT); 856 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 857 CS35L41_PLL_CLK_EN_MASK, 858 1 << CS35L41_PLL_CLK_EN_SHIFT); 859 860 return 0; 861 } 862 863 static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai, 864 int clk_id, unsigned int freq, int dir) 865 { 866 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 867 unsigned int fs1_val; 868 unsigned int fs2_val; 869 unsigned int val; 870 int fsindex; 871 872 fsindex = cs35l41_get_fs_mon_config_index(freq); 873 if (fsindex < 0) { 874 dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq); 875 return -EINVAL; 876 } 877 878 dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq); 879 880 if (freq <= 6144000) { 881 /* Use the lookup table */ 882 fs1_val = cs35l41_fs_mon[fsindex].fs1; 883 fs2_val = cs35l41_fs_mon[fsindex].fs2; 884 } else { 885 /* Use hard-coded values */ 886 fs1_val = 0x10; 887 fs2_val = 0x24; 888 } 889 890 val = fs1_val; 891 val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK; 892 regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val); 893 894 return 0; 895 } 896 897 static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) 898 { 899 struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg; 900 int ret; 901 902 if (!hw_cfg->valid) 903 return -EINVAL; 904 905 if (hw_cfg->bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH) 906 return -EINVAL; 907 908 /* Required */ 909 ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg); 910 if (ret) 911 return ret; 912 913 /* Optional */ 914 if (hw_cfg->dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && hw_cfg->dout_hiz >= 0) 915 regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, CS35L41_ASP_DOUT_HIZ_MASK, 916 hw_cfg->dout_hiz); 917 918 return 0; 919 } 920 921 static const struct snd_soc_dapm_route cs35l41_ext_bst_routes[] = { 922 {"Main AMP", NULL, "VSPK"}, 923 }; 924 925 static const struct snd_soc_dapm_widget cs35l41_ext_bst_widget[] = { 926 SND_SOC_DAPM_SUPPLY("VSPK", CS35L41_GPIO1_CTRL1, CS35L41_GPIO_LVL_SHIFT, 0, NULL, 0), 927 }; 928 929 static int cs35l41_component_probe(struct snd_soc_component *component) 930 { 931 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 932 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 933 int ret; 934 935 if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) { 936 ret = snd_soc_dapm_new_controls(dapm, cs35l41_ext_bst_widget, 937 ARRAY_SIZE(cs35l41_ext_bst_widget)); 938 if (ret) 939 return ret; 940 941 ret = snd_soc_dapm_add_routes(dapm, cs35l41_ext_bst_routes, 942 ARRAY_SIZE(cs35l41_ext_bst_routes)); 943 if (ret) 944 return ret; 945 } 946 947 return wm_adsp2_component_probe(&cs35l41->dsp, component); 948 } 949 950 static void cs35l41_component_remove(struct snd_soc_component *component) 951 { 952 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 953 954 wm_adsp2_component_remove(&cs35l41->dsp, component); 955 } 956 957 static const struct snd_soc_dai_ops cs35l41_ops = { 958 .startup = cs35l41_pcm_startup, 959 .set_fmt = cs35l41_set_dai_fmt, 960 .hw_params = cs35l41_pcm_hw_params, 961 .set_sysclk = cs35l41_dai_set_sysclk, 962 .set_channel_map = cs35l41_set_channel_map, 963 }; 964 965 static struct snd_soc_dai_driver cs35l41_dai[] = { 966 { 967 .name = "cs35l41-pcm", 968 .id = 0, 969 .playback = { 970 .stream_name = "AMP Playback", 971 .channels_min = 1, 972 .channels_max = 2, 973 .rates = SNDRV_PCM_RATE_KNOT, 974 .formats = CS35L41_RX_FORMATS, 975 }, 976 .capture = { 977 .stream_name = "AMP Capture", 978 .channels_min = 1, 979 .channels_max = 4, 980 .rates = SNDRV_PCM_RATE_KNOT, 981 .formats = CS35L41_TX_FORMATS, 982 }, 983 .ops = &cs35l41_ops, 984 .symmetric_rate = 1, 985 }, 986 }; 987 988 static const struct snd_soc_component_driver soc_component_dev_cs35l41 = { 989 .name = "cs35l41-codec", 990 .probe = cs35l41_component_probe, 991 .remove = cs35l41_component_remove, 992 993 .dapm_widgets = cs35l41_dapm_widgets, 994 .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets), 995 .dapm_routes = cs35l41_audio_map, 996 .num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map), 997 998 .controls = cs35l41_aud_controls, 999 .num_controls = ARRAY_SIZE(cs35l41_aud_controls), 1000 .set_sysclk = cs35l41_component_set_sysclk, 1001 1002 .endianness = 1, 1003 }; 1004 1005 static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cfg) 1006 { 1007 struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1; 1008 struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2; 1009 unsigned int val; 1010 int ret; 1011 1012 ret = device_property_read_u32(dev, "cirrus,boost-type", &val); 1013 if (ret >= 0) 1014 hw_cfg->bst_type = val; 1015 1016 ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val); 1017 if (ret >= 0) 1018 hw_cfg->bst_ipk = val; 1019 else 1020 hw_cfg->bst_ipk = -1; 1021 1022 ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val); 1023 if (ret >= 0) 1024 hw_cfg->bst_ind = val; 1025 else 1026 hw_cfg->bst_ind = -1; 1027 1028 ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val); 1029 if (ret >= 0) 1030 hw_cfg->bst_cap = val; 1031 else 1032 hw_cfg->bst_cap = -1; 1033 1034 ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val); 1035 if (ret >= 0) 1036 hw_cfg->dout_hiz = val; 1037 else 1038 hw_cfg->dout_hiz = -1; 1039 1040 /* GPIO1 Pin Config */ 1041 gpio1->pol_inv = device_property_read_bool(dev, "cirrus,gpio1-polarity-invert"); 1042 gpio1->out_en = device_property_read_bool(dev, "cirrus,gpio1-output-enable"); 1043 ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", &val); 1044 if (ret >= 0) { 1045 gpio1->func = val; 1046 gpio1->valid = true; 1047 } 1048 1049 /* GPIO2 Pin Config */ 1050 gpio2->pol_inv = device_property_read_bool(dev, "cirrus,gpio2-polarity-invert"); 1051 gpio2->out_en = device_property_read_bool(dev, "cirrus,gpio2-output-enable"); 1052 ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", &val); 1053 if (ret >= 0) { 1054 gpio2->func = val; 1055 gpio2->valid = true; 1056 } 1057 1058 hw_cfg->valid = true; 1059 1060 return 0; 1061 } 1062 1063 static int cs35l41_dsp_init(struct cs35l41_private *cs35l41) 1064 { 1065 struct wm_adsp *dsp; 1066 int ret; 1067 1068 dsp = &cs35l41->dsp; 1069 dsp->part = "cs35l41"; 1070 dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */ 1071 dsp->toggle_preload = true; 1072 1073 cs35l41_configure_cs_dsp(cs35l41->dev, cs35l41->regmap, &dsp->cs_dsp); 1074 1075 ret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap); 1076 if (ret < 0) 1077 return ret; 1078 1079 ret = wm_halo_init(dsp); 1080 if (ret) { 1081 dev_err(cs35l41->dev, "wm_halo_init failed: %d\n", ret); 1082 return ret; 1083 } 1084 1085 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC, 1086 CS35L41_INPUT_SRC_VPMON); 1087 if (ret < 0) { 1088 dev_err(cs35l41->dev, "Write INPUT_SRC_VPMON failed: %d\n", ret); 1089 goto err_dsp; 1090 } 1091 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC, 1092 CS35L41_INPUT_SRC_CLASSH); 1093 if (ret < 0) { 1094 dev_err(cs35l41->dev, "Write INPUT_SRC_CLASSH failed: %d\n", ret); 1095 goto err_dsp; 1096 } 1097 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC, 1098 CS35L41_INPUT_SRC_TEMPMON); 1099 if (ret < 0) { 1100 dev_err(cs35l41->dev, "Write INPUT_SRC_TEMPMON failed: %d\n", ret); 1101 goto err_dsp; 1102 } 1103 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC, 1104 CS35L41_INPUT_SRC_RSVD); 1105 if (ret < 0) { 1106 dev_err(cs35l41->dev, "Write INPUT_SRC_RSVD failed: %d\n", ret); 1107 goto err_dsp; 1108 } 1109 1110 return 0; 1111 1112 err_dsp: 1113 wm_adsp2_remove(dsp); 1114 1115 return ret; 1116 } 1117 1118 static int cs35l41_acpi_get_name(struct cs35l41_private *cs35l41) 1119 { 1120 acpi_handle handle = ACPI_HANDLE(cs35l41->dev); 1121 const char *sub; 1122 1123 /* If there is no ACPI_HANDLE, there is no ACPI for this system, return 0 */ 1124 if (!handle) 1125 return 0; 1126 1127 sub = acpi_get_subsystem_id(handle); 1128 if (IS_ERR(sub)) { 1129 /* If bad ACPI, return 0 and fallback to legacy firmware path, otherwise fail */ 1130 if (PTR_ERR(sub) == -ENODATA) 1131 return 0; 1132 else 1133 return PTR_ERR(sub); 1134 } 1135 1136 cs35l41->dsp.system_name = sub; 1137 dev_dbg(cs35l41->dev, "Subsystem ID: %s\n", cs35l41->dsp.system_name); 1138 1139 return 0; 1140 } 1141 1142 int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg *hw_cfg) 1143 { 1144 u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match; 1145 int irq_pol = 0; 1146 int ret; 1147 1148 if (hw_cfg) { 1149 cs35l41->hw_cfg = *hw_cfg; 1150 } else { 1151 ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->hw_cfg); 1152 if (ret != 0) 1153 return ret; 1154 } 1155 1156 for (i = 0; i < CS35L41_NUM_SUPPLIES; i++) 1157 cs35l41->supplies[i].supply = cs35l41_supplies[i]; 1158 1159 ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES, 1160 cs35l41->supplies); 1161 if (ret != 0) { 1162 dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", ret); 1163 return ret; 1164 } 1165 1166 ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1167 if (ret != 0) { 1168 dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", ret); 1169 return ret; 1170 } 1171 1172 /* returning NULL can be an option if in stereo mode */ 1173 cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset", 1174 GPIOD_OUT_LOW); 1175 if (IS_ERR(cs35l41->reset_gpio)) { 1176 ret = PTR_ERR(cs35l41->reset_gpio); 1177 cs35l41->reset_gpio = NULL; 1178 if (ret == -EBUSY) { 1179 dev_info(cs35l41->dev, 1180 "Reset line busy, assuming shared reset\n"); 1181 } else { 1182 dev_err(cs35l41->dev, 1183 "Failed to get reset GPIO: %d\n", ret); 1184 goto err; 1185 } 1186 } 1187 if (cs35l41->reset_gpio) { 1188 /* satisfy minimum reset pulse width spec */ 1189 usleep_range(2000, 2100); 1190 gpiod_set_value_cansleep(cs35l41->reset_gpio, 1); 1191 } 1192 1193 usleep_range(2000, 2100); 1194 1195 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4, 1196 int_status, int_status & CS35L41_OTP_BOOT_DONE, 1197 1000, 100000); 1198 if (ret) { 1199 dev_err(cs35l41->dev, 1200 "Failed waiting for OTP_BOOT_DONE: %d\n", ret); 1201 goto err; 1202 } 1203 1204 regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status); 1205 if (int_status & CS35L41_OTP_BOOT_ERR) { 1206 dev_err(cs35l41->dev, "OTP Boot error\n"); 1207 ret = -EINVAL; 1208 goto err; 1209 } 1210 1211 ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id); 1212 if (ret < 0) { 1213 dev_err(cs35l41->dev, "Get Device ID failed: %d\n", ret); 1214 goto err; 1215 } 1216 1217 ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid); 1218 if (ret < 0) { 1219 dev_err(cs35l41->dev, "Get Revision ID failed: %d\n", ret); 1220 goto err; 1221 } 1222 1223 mtl_revid = reg_revid & CS35L41_MTLREVID_MASK; 1224 1225 /* CS35L41 will have even MTLREVID 1226 * CS35L41R will have odd MTLREVID 1227 */ 1228 chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID; 1229 if (regid != chipid_match) { 1230 dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n", 1231 regid, chipid_match); 1232 ret = -ENODEV; 1233 goto err; 1234 } 1235 1236 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap); 1237 1238 ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid); 1239 if (ret) 1240 goto err; 1241 1242 ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap); 1243 if (ret < 0) { 1244 dev_err(cs35l41->dev, "OTP Unpack failed: %d\n", ret); 1245 goto err; 1246 } 1247 1248 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); 1249 1250 irq_pol = cs35l41_gpio_config(cs35l41->regmap, &cs35l41->hw_cfg); 1251 1252 /* Set interrupt masks for critical errors */ 1253 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 1254 CS35L41_INT1_MASK_DEFAULT); 1255 1256 ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq, 1257 IRQF_ONESHOT | IRQF_SHARED | irq_pol, 1258 "cs35l41", cs35l41); 1259 if (ret != 0) { 1260 dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret); 1261 goto err; 1262 } 1263 1264 ret = cs35l41_set_pdata(cs35l41); 1265 if (ret < 0) { 1266 dev_err(cs35l41->dev, "Set pdata failed: %d\n", ret); 1267 goto err; 1268 } 1269 1270 ret = cs35l41_acpi_get_name(cs35l41); 1271 if (ret < 0) 1272 goto err; 1273 1274 ret = cs35l41_dsp_init(cs35l41); 1275 if (ret < 0) 1276 goto err; 1277 1278 pm_runtime_set_autosuspend_delay(cs35l41->dev, 3000); 1279 pm_runtime_use_autosuspend(cs35l41->dev); 1280 pm_runtime_mark_last_busy(cs35l41->dev); 1281 pm_runtime_set_active(cs35l41->dev); 1282 pm_runtime_get_noresume(cs35l41->dev); 1283 pm_runtime_enable(cs35l41->dev); 1284 1285 ret = devm_snd_soc_register_component(cs35l41->dev, 1286 &soc_component_dev_cs35l41, 1287 cs35l41_dai, ARRAY_SIZE(cs35l41_dai)); 1288 if (ret < 0) { 1289 dev_err(cs35l41->dev, "Register codec failed: %d\n", ret); 1290 goto err_pm; 1291 } 1292 1293 pm_runtime_put_autosuspend(cs35l41->dev); 1294 1295 dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n", 1296 regid, reg_revid); 1297 1298 return 0; 1299 1300 err_pm: 1301 pm_runtime_disable(cs35l41->dev); 1302 pm_runtime_put_noidle(cs35l41->dev); 1303 1304 wm_adsp2_remove(&cs35l41->dsp); 1305 err: 1306 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1307 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1308 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1309 1310 return ret; 1311 } 1312 EXPORT_SYMBOL_GPL(cs35l41_probe); 1313 1314 void cs35l41_remove(struct cs35l41_private *cs35l41) 1315 { 1316 pm_runtime_get_sync(cs35l41->dev); 1317 pm_runtime_disable(cs35l41->dev); 1318 1319 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF); 1320 kfree(cs35l41->dsp.system_name); 1321 wm_adsp2_remove(&cs35l41->dsp); 1322 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1323 1324 pm_runtime_put_noidle(cs35l41->dev); 1325 1326 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1327 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1328 } 1329 EXPORT_SYMBOL_GPL(cs35l41_remove); 1330 1331 static int __maybe_unused cs35l41_runtime_suspend(struct device *dev) 1332 { 1333 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1334 1335 dev_dbg(cs35l41->dev, "Runtime suspend\n"); 1336 1337 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running) 1338 return 0; 1339 1340 cs35l41_enter_hibernate(dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1341 1342 regcache_cache_only(cs35l41->regmap, true); 1343 regcache_mark_dirty(cs35l41->regmap); 1344 1345 return 0; 1346 } 1347 1348 static int __maybe_unused cs35l41_runtime_resume(struct device *dev) 1349 { 1350 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1351 int ret; 1352 1353 dev_dbg(cs35l41->dev, "Runtime resume\n"); 1354 1355 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running) 1356 return 0; 1357 1358 regcache_cache_only(cs35l41->regmap, false); 1359 1360 ret = cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap); 1361 if (ret) 1362 return ret; 1363 1364 /* Test key needs to be unlocked to allow the OTP settings to re-apply */ 1365 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap); 1366 ret = regcache_sync(cs35l41->regmap); 1367 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); 1368 if (ret) { 1369 dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret); 1370 return ret; 1371 } 1372 cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, &cs35l41->hw_cfg); 1373 1374 return 0; 1375 } 1376 1377 static int __maybe_unused cs35l41_sys_suspend(struct device *dev) 1378 { 1379 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1380 1381 dev_dbg(cs35l41->dev, "System suspend, disabling IRQ\n"); 1382 disable_irq(cs35l41->irq); 1383 1384 return 0; 1385 } 1386 1387 static int __maybe_unused cs35l41_sys_suspend_noirq(struct device *dev) 1388 { 1389 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1390 1391 dev_dbg(cs35l41->dev, "Late system suspend, reenabling IRQ\n"); 1392 enable_irq(cs35l41->irq); 1393 1394 return 0; 1395 } 1396 1397 static int __maybe_unused cs35l41_sys_resume_noirq(struct device *dev) 1398 { 1399 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1400 1401 dev_dbg(cs35l41->dev, "Early system resume, disabling IRQ\n"); 1402 disable_irq(cs35l41->irq); 1403 1404 return 0; 1405 } 1406 1407 static int __maybe_unused cs35l41_sys_resume(struct device *dev) 1408 { 1409 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1410 1411 dev_dbg(cs35l41->dev, "System resume, reenabling IRQ\n"); 1412 enable_irq(cs35l41->irq); 1413 1414 return 0; 1415 } 1416 1417 const struct dev_pm_ops cs35l41_pm_ops = { 1418 SET_RUNTIME_PM_OPS(cs35l41_runtime_suspend, cs35l41_runtime_resume, NULL) 1419 1420 SET_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend, cs35l41_sys_resume) 1421 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend_noirq, cs35l41_sys_resume_noirq) 1422 }; 1423 EXPORT_SYMBOL_GPL(cs35l41_pm_ops); 1424 1425 MODULE_DESCRIPTION("ASoC CS35L41 driver"); 1426 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>"); 1427 MODULE_LICENSE("GPL"); 1428