1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // cs35l41.c -- CS35l41 ALSA SoC audio driver 4 // 5 // Copyright 2017-2021 Cirrus Logic, Inc. 6 // 7 // Author: David Rhodes <david.rhodes@cirrus.com> 8 9 #include <linux/delay.h> 10 #include <linux/err.h> 11 #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/of_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/property.h> 18 #include <sound/initval.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/soc-dapm.h> 23 #include <sound/tlv.h> 24 25 #include "cs35l41.h" 26 27 static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = { 28 "VA", 29 "VP", 30 }; 31 32 struct cs35l41_pll_sysclk_config { 33 int freq; 34 int clk_cfg; 35 }; 36 37 static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = { 38 { 32768, 0x00 }, 39 { 8000, 0x01 }, 40 { 11025, 0x02 }, 41 { 12000, 0x03 }, 42 { 16000, 0x04 }, 43 { 22050, 0x05 }, 44 { 24000, 0x06 }, 45 { 32000, 0x07 }, 46 { 44100, 0x08 }, 47 { 48000, 0x09 }, 48 { 88200, 0x0A }, 49 { 96000, 0x0B }, 50 { 128000, 0x0C }, 51 { 176400, 0x0D }, 52 { 192000, 0x0E }, 53 { 256000, 0x0F }, 54 { 352800, 0x10 }, 55 { 384000, 0x11 }, 56 { 512000, 0x12 }, 57 { 705600, 0x13 }, 58 { 750000, 0x14 }, 59 { 768000, 0x15 }, 60 { 1000000, 0x16 }, 61 { 1024000, 0x17 }, 62 { 1200000, 0x18 }, 63 { 1411200, 0x19 }, 64 { 1500000, 0x1A }, 65 { 1536000, 0x1B }, 66 { 2000000, 0x1C }, 67 { 2048000, 0x1D }, 68 { 2400000, 0x1E }, 69 { 2822400, 0x1F }, 70 { 3000000, 0x20 }, 71 { 3072000, 0x21 }, 72 { 3200000, 0x22 }, 73 { 4000000, 0x23 }, 74 { 4096000, 0x24 }, 75 { 4800000, 0x25 }, 76 { 5644800, 0x26 }, 77 { 6000000, 0x27 }, 78 { 6144000, 0x28 }, 79 { 6250000, 0x29 }, 80 { 6400000, 0x2A }, 81 { 6500000, 0x2B }, 82 { 6750000, 0x2C }, 83 { 7526400, 0x2D }, 84 { 8000000, 0x2E }, 85 { 8192000, 0x2F }, 86 { 9600000, 0x30 }, 87 { 11289600, 0x31 }, 88 { 12000000, 0x32 }, 89 { 12288000, 0x33 }, 90 { 12500000, 0x34 }, 91 { 12800000, 0x35 }, 92 { 13000000, 0x36 }, 93 { 13500000, 0x37 }, 94 { 19200000, 0x38 }, 95 { 22579200, 0x39 }, 96 { 24000000, 0x3A }, 97 { 24576000, 0x3B }, 98 { 25000000, 0x3C }, 99 { 25600000, 0x3D }, 100 { 26000000, 0x3E }, 101 { 27000000, 0x3F }, 102 }; 103 104 struct cs35l41_fs_mon_config { 105 int freq; 106 unsigned int fs1; 107 unsigned int fs2; 108 }; 109 110 static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = { 111 { 32768, 2254, 3754 }, 112 { 8000, 9220, 15364 }, 113 { 11025, 6148, 10244 }, 114 { 12000, 6148, 10244 }, 115 { 16000, 4612, 7684 }, 116 { 22050, 3076, 5124 }, 117 { 24000, 3076, 5124 }, 118 { 32000, 2308, 3844 }, 119 { 44100, 1540, 2564 }, 120 { 48000, 1540, 2564 }, 121 { 88200, 772, 1284 }, 122 { 96000, 772, 1284 }, 123 { 128000, 580, 964 }, 124 { 176400, 388, 644 }, 125 { 192000, 388, 644 }, 126 { 256000, 292, 484 }, 127 { 352800, 196, 324 }, 128 { 384000, 196, 324 }, 129 { 512000, 148, 244 }, 130 { 705600, 100, 164 }, 131 { 750000, 100, 164 }, 132 { 768000, 100, 164 }, 133 { 1000000, 76, 124 }, 134 { 1024000, 76, 124 }, 135 { 1200000, 64, 104 }, 136 { 1411200, 52, 84 }, 137 { 1500000, 52, 84 }, 138 { 1536000, 52, 84 }, 139 { 2000000, 40, 64 }, 140 { 2048000, 40, 64 }, 141 { 2400000, 34, 54 }, 142 { 2822400, 28, 44 }, 143 { 3000000, 28, 44 }, 144 { 3072000, 28, 44 }, 145 { 3200000, 27, 42 }, 146 { 4000000, 22, 34 }, 147 { 4096000, 22, 34 }, 148 { 4800000, 19, 29 }, 149 { 5644800, 16, 24 }, 150 { 6000000, 16, 24 }, 151 { 6144000, 16, 24 }, 152 }; 153 154 static int cs35l41_get_fs_mon_config_index(int freq) 155 { 156 int i; 157 158 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) { 159 if (cs35l41_fs_mon[i].freq == freq) 160 return i; 161 } 162 163 return -EINVAL; 164 } 165 166 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv, 167 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 168 1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200)); 169 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1); 170 171 static const struct snd_kcontrol_new dre_ctrl = 172 SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0); 173 174 static const char * const cs35l41_pcm_sftramp_text[] = { 175 "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms" 176 }; 177 178 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, 179 CS35L41_AMP_DIG_VOL_CTRL, 0, 180 cs35l41_pcm_sftramp_text); 181 182 static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w, 183 struct snd_kcontrol *kcontrol, int event) 184 { 185 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 186 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 187 int ret; 188 189 switch (event) { 190 case SND_SOC_DAPM_PRE_PMU: 191 if (cs35l41->dsp.cs_dsp.booted) 192 return 0; 193 194 return wm_adsp_early_event(w, kcontrol, event); 195 case SND_SOC_DAPM_PRE_PMD: 196 if (cs35l41->dsp.preloaded) 197 return 0; 198 199 if (cs35l41->dsp.cs_dsp.running) { 200 ret = wm_adsp_event(w, kcontrol, event); 201 if (ret) 202 return ret; 203 } 204 205 return wm_adsp_early_event(w, kcontrol, event); 206 default: 207 return 0; 208 } 209 } 210 211 static bool cs35l41_check_cspl_mbox_sts(enum cs35l41_cspl_mbox_cmd cmd, 212 enum cs35l41_cspl_mbox_status sts) 213 { 214 switch (cmd) { 215 case CSPL_MBOX_CMD_NONE: 216 case CSPL_MBOX_CMD_UNKNOWN_CMD: 217 return true; 218 case CSPL_MBOX_CMD_PAUSE: 219 case CSPL_MBOX_CMD_OUT_OF_HIBERNATE: 220 return (sts == CSPL_MBOX_STS_PAUSED); 221 case CSPL_MBOX_CMD_RESUME: 222 return (sts == CSPL_MBOX_STS_RUNNING); 223 case CSPL_MBOX_CMD_REINIT: 224 return (sts == CSPL_MBOX_STS_RUNNING); 225 case CSPL_MBOX_CMD_STOP_PRE_REINIT: 226 return (sts == CSPL_MBOX_STS_RDY_FOR_REINIT); 227 default: 228 return false; 229 } 230 } 231 232 static int cs35l41_set_cspl_mbox_cmd(struct cs35l41_private *cs35l41, 233 enum cs35l41_cspl_mbox_cmd cmd) 234 { 235 unsigned int sts = 0, i; 236 int ret; 237 238 // Set mailbox cmd 239 ret = regmap_write(cs35l41->regmap, CS35L41_DSP_VIRT1_MBOX_1, cmd); 240 if (ret < 0) { 241 if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE) 242 dev_err(cs35l41->dev, "Failed to write MBOX: %d\n", ret); 243 return ret; 244 } 245 246 // Read mailbox status and verify it is appropriate for the given cmd 247 for (i = 0; i < 5; i++) { 248 usleep_range(1000, 1100); 249 250 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &sts); 251 if (ret < 0) { 252 dev_err(cs35l41->dev, "Failed to read MBOX STS: %d\n", ret); 253 continue; 254 } 255 256 if (!cs35l41_check_cspl_mbox_sts(cmd, sts)) { 257 dev_dbg(cs35l41->dev, 258 "[%u] cmd %u returned invalid sts %u", 259 i, cmd, sts); 260 } else { 261 return 0; 262 } 263 } 264 265 dev_err(cs35l41->dev, 266 "Failed to set mailbox cmd %u (status %u)\n", 267 cmd, sts); 268 269 return -ENOMSG; 270 } 271 272 static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w, 273 struct snd_kcontrol *kcontrol, int event) 274 { 275 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 276 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 277 unsigned int fw_status; 278 int ret; 279 280 switch (event) { 281 case SND_SOC_DAPM_POST_PMU: 282 if (!cs35l41->dsp.cs_dsp.running) 283 return wm_adsp_event(w, kcontrol, event); 284 285 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &fw_status); 286 if (ret < 0) { 287 dev_err(cs35l41->dev, 288 "Failed to read firmware status: %d\n", ret); 289 return ret; 290 } 291 292 switch (fw_status) { 293 case CSPL_MBOX_STS_RUNNING: 294 case CSPL_MBOX_STS_PAUSED: 295 break; 296 default: 297 dev_err(cs35l41->dev, "Firmware status is invalid: %u\n", 298 fw_status); 299 return -EINVAL; 300 } 301 302 return cs35l41_set_cspl_mbox_cmd(cs35l41, CSPL_MBOX_CMD_RESUME); 303 case SND_SOC_DAPM_PRE_PMD: 304 return cs35l41_set_cspl_mbox_cmd(cs35l41, CSPL_MBOX_CMD_PAUSE); 305 default: 306 return 0; 307 } 308 } 309 310 static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"}; 311 static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32}; 312 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum, 313 CS35L41_DAC_PCM1_SRC, 314 0, CS35L41_ASP_SOURCE_MASK, 315 cs35l41_pcm_source_texts, 316 cs35l41_pcm_source_values); 317 318 static const struct snd_kcontrol_new pcm_source_mux = 319 SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum); 320 321 static const char * const cs35l41_tx_input_texts[] = { 322 "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON", 323 "VPMON", "VBSTMON", "DSPTX1", "DSPTX2" 324 }; 325 326 static const unsigned int cs35l41_tx_input_values[] = { 327 0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2, 328 CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON, 329 CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2 330 }; 331 332 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum, 333 CS35L41_ASP_TX1_SRC, 334 0, CS35L41_ASP_SOURCE_MASK, 335 cs35l41_tx_input_texts, 336 cs35l41_tx_input_values); 337 338 static const struct snd_kcontrol_new asp_tx1_mux = 339 SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum); 340 341 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum, 342 CS35L41_ASP_TX2_SRC, 343 0, CS35L41_ASP_SOURCE_MASK, 344 cs35l41_tx_input_texts, 345 cs35l41_tx_input_values); 346 347 static const struct snd_kcontrol_new asp_tx2_mux = 348 SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum); 349 350 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum, 351 CS35L41_ASP_TX3_SRC, 352 0, CS35L41_ASP_SOURCE_MASK, 353 cs35l41_tx_input_texts, 354 cs35l41_tx_input_values); 355 356 static const struct snd_kcontrol_new asp_tx3_mux = 357 SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum); 358 359 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum, 360 CS35L41_ASP_TX4_SRC, 361 0, CS35L41_ASP_SOURCE_MASK, 362 cs35l41_tx_input_texts, 363 cs35l41_tx_input_values); 364 365 static const struct snd_kcontrol_new asp_tx4_mux = 366 SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum); 367 368 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum, 369 CS35L41_DSP1_RX1_SRC, 370 0, CS35L41_ASP_SOURCE_MASK, 371 cs35l41_tx_input_texts, 372 cs35l41_tx_input_values); 373 374 static const struct snd_kcontrol_new dsp_rx1_mux = 375 SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum); 376 377 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum, 378 CS35L41_DSP1_RX2_SRC, 379 0, CS35L41_ASP_SOURCE_MASK, 380 cs35l41_tx_input_texts, 381 cs35l41_tx_input_values); 382 383 static const struct snd_kcontrol_new dsp_rx2_mux = 384 SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum); 385 386 static const struct snd_kcontrol_new cs35l41_aud_controls[] = { 387 SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL, 388 3, 0x4CF, 0x391, dig_vol_tlv), 389 SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0, 390 amp_gain_tlv), 391 SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp), 392 SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0), 393 SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0), 394 SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0), 395 SOC_SINGLE("Aux Noise Gate CH1 Enable", 396 CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0), 397 SOC_SINGLE("Aux Noise Gate CH1 Entry Delay", 398 CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0), 399 SOC_SINGLE("Aux Noise Gate CH1 Threshold", 400 CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0), 401 SOC_SINGLE("Aux Noise Gate CH2 Entry Delay", 402 CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0), 403 SOC_SINGLE("Aux Noise Gate CH2 Enable", 404 CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0), 405 SOC_SINGLE("Aux Noise Gate CH2 Threshold", 406 CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0), 407 SOC_SINGLE("SCLK Force", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0), 408 SOC_SINGLE("LRCLK Force", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0), 409 SOC_SINGLE("Invert Class D", CS35L41_AMP_DIG_VOL_CTRL, 410 CS35L41_AMP_INV_PCM_SHIFT, 1, 0), 411 SOC_SINGLE("Amp Gain ZC", CS35L41_AMP_GAIN_CTRL, 412 CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0), 413 WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), 414 WM_ADSP_FW_CONTROL("DSP1", 0), 415 }; 416 417 static irqreturn_t cs35l41_irq(int irq, void *data) 418 { 419 struct cs35l41_private *cs35l41 = data; 420 unsigned int status[4] = { 0, 0, 0, 0 }; 421 unsigned int masks[4] = { 0, 0, 0, 0 }; 422 int ret = IRQ_NONE; 423 unsigned int i; 424 425 pm_runtime_get_sync(cs35l41->dev); 426 427 for (i = 0; i < ARRAY_SIZE(status); i++) { 428 regmap_read(cs35l41->regmap, 429 CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE), 430 &status[i]); 431 regmap_read(cs35l41->regmap, 432 CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE), 433 &masks[i]); 434 } 435 436 /* Check to see if unmasked bits are active */ 437 if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) && 438 !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) 439 goto done; 440 441 if (status[3] & CS35L41_OTP_BOOT_DONE) { 442 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4, 443 CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE); 444 } 445 446 /* 447 * The following interrupts require a 448 * protection release cycle to get the 449 * speaker out of Safe-Mode. 450 */ 451 if (status[0] & CS35L41_AMP_SHORT_ERR) { 452 dev_crit_ratelimited(cs35l41->dev, "Amp short error\n"); 453 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 454 CS35L41_AMP_SHORT_ERR); 455 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 456 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 457 CS35L41_AMP_SHORT_ERR_RLS, 458 CS35L41_AMP_SHORT_ERR_RLS); 459 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 460 CS35L41_AMP_SHORT_ERR_RLS, 0); 461 ret = IRQ_HANDLED; 462 } 463 464 if (status[0] & CS35L41_TEMP_WARN) { 465 dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n"); 466 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 467 CS35L41_TEMP_WARN); 468 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 469 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 470 CS35L41_TEMP_WARN_ERR_RLS, 471 CS35L41_TEMP_WARN_ERR_RLS); 472 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 473 CS35L41_TEMP_WARN_ERR_RLS, 0); 474 ret = IRQ_HANDLED; 475 } 476 477 if (status[0] & CS35L41_TEMP_ERR) { 478 dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n"); 479 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 480 CS35L41_TEMP_ERR); 481 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 482 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 483 CS35L41_TEMP_ERR_RLS, 484 CS35L41_TEMP_ERR_RLS); 485 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 486 CS35L41_TEMP_ERR_RLS, 0); 487 ret = IRQ_HANDLED; 488 } 489 490 if (status[0] & CS35L41_BST_OVP_ERR) { 491 dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n"); 492 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 493 CS35L41_BST_EN_MASK, 0); 494 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 495 CS35L41_BST_OVP_ERR); 496 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 497 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 498 CS35L41_BST_OVP_ERR_RLS, 499 CS35L41_BST_OVP_ERR_RLS); 500 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 501 CS35L41_BST_OVP_ERR_RLS, 0); 502 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 503 CS35L41_BST_EN_MASK, 504 CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); 505 ret = IRQ_HANDLED; 506 } 507 508 if (status[0] & CS35L41_BST_DCM_UVP_ERR) { 509 dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n"); 510 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 511 CS35L41_BST_EN_MASK, 0); 512 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 513 CS35L41_BST_DCM_UVP_ERR); 514 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 515 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 516 CS35L41_BST_UVP_ERR_RLS, 517 CS35L41_BST_UVP_ERR_RLS); 518 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 519 CS35L41_BST_UVP_ERR_RLS, 0); 520 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 521 CS35L41_BST_EN_MASK, 522 CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); 523 ret = IRQ_HANDLED; 524 } 525 526 if (status[0] & CS35L41_BST_SHORT_ERR) { 527 dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n"); 528 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 529 CS35L41_BST_EN_MASK, 0); 530 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 531 CS35L41_BST_SHORT_ERR); 532 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 533 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 534 CS35L41_BST_SHORT_ERR_RLS, 535 CS35L41_BST_SHORT_ERR_RLS); 536 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 537 CS35L41_BST_SHORT_ERR_RLS, 0); 538 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 539 CS35L41_BST_EN_MASK, 540 CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); 541 ret = IRQ_HANDLED; 542 } 543 544 done: 545 pm_runtime_mark_last_busy(cs35l41->dev); 546 pm_runtime_put_autosuspend(cs35l41->dev); 547 548 return ret; 549 } 550 551 static const struct reg_sequence cs35l41_pup_patch[] = { 552 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 553 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 554 { 0x00002084, 0x002F1AA0 }, 555 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 556 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 557 }; 558 559 static const struct reg_sequence cs35l41_pdn_patch[] = { 560 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 561 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 562 { 0x00002084, 0x002F1AA3 }, 563 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 564 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 565 }; 566 567 static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w, 568 struct snd_kcontrol *kcontrol, int event) 569 { 570 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 571 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 572 unsigned int val; 573 int ret = 0; 574 575 switch (event) { 576 case SND_SOC_DAPM_PRE_PMU: 577 regmap_multi_reg_write_bypassed(cs35l41->regmap, 578 cs35l41_pup_patch, 579 ARRAY_SIZE(cs35l41_pup_patch)); 580 581 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL1, 582 CS35L41_GLOBAL_EN_MASK, 583 1 << CS35L41_GLOBAL_EN_SHIFT); 584 585 usleep_range(1000, 1100); 586 break; 587 case SND_SOC_DAPM_POST_PMD: 588 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL1, 589 CS35L41_GLOBAL_EN_MASK, 0); 590 591 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 592 val, val & CS35L41_PDN_DONE_MASK, 593 1000, 100000); 594 if (ret) 595 dev_warn(cs35l41->dev, "PDN failed: %d\n", ret); 596 597 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 598 CS35L41_PDN_DONE_MASK); 599 600 regmap_multi_reg_write_bypassed(cs35l41->regmap, 601 cs35l41_pdn_patch, 602 ARRAY_SIZE(cs35l41_pdn_patch)); 603 break; 604 default: 605 dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event); 606 ret = -EINVAL; 607 } 608 609 return ret; 610 } 611 612 static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = { 613 SND_SOC_DAPM_SPK("DSP1 Preload", NULL), 614 SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0, 615 cs35l41_dsp_preload_ev, 616 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 617 SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, 618 cs35l41_dsp_audio_ev, 619 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 620 621 SND_SOC_DAPM_OUTPUT("SPK"), 622 623 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0), 624 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0), 625 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0), 626 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0), 627 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0), 628 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0), 629 630 SND_SOC_DAPM_SIGGEN("VSENSE"), 631 SND_SOC_DAPM_SIGGEN("ISENSE"), 632 SND_SOC_DAPM_SIGGEN("VP"), 633 SND_SOC_DAPM_SIGGEN("VBST"), 634 SND_SOC_DAPM_SIGGEN("TEMP"), 635 636 SND_SOC_DAPM_SUPPLY("VMON", CS35L41_PWR_CTRL2, 12, 0, NULL, 0), 637 SND_SOC_DAPM_SUPPLY("IMON", CS35L41_PWR_CTRL2, 13, 0, NULL, 0), 638 SND_SOC_DAPM_SUPPLY("VPMON", CS35L41_PWR_CTRL2, 8, 0, NULL, 0), 639 SND_SOC_DAPM_SUPPLY("VBSTMON", CS35L41_PWR_CTRL2, 9, 0, NULL, 0), 640 SND_SOC_DAPM_SUPPLY("TEMPMON", CS35L41_PWR_CTRL2, 10, 0, NULL, 0), 641 642 SND_SOC_DAPM_ADC("VMON ADC", NULL, SND_SOC_NOPM, 0, 0), 643 SND_SOC_DAPM_ADC("IMON ADC", NULL, SND_SOC_NOPM, 0, 0), 644 SND_SOC_DAPM_ADC("VPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 645 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, SND_SOC_NOPM, 0, 0), 646 SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 647 648 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0), 649 650 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0, 651 cs35l41_main_amp_event, 652 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 653 654 SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux), 655 SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux), 656 SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux), 657 SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux), 658 SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux), 659 SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux), 660 SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux), 661 SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl), 662 }; 663 664 static const struct snd_soc_dapm_route cs35l41_audio_map[] = { 665 {"DSP RX1 Source", "ASPRX1", "ASPRX1"}, 666 {"DSP RX1 Source", "ASPRX2", "ASPRX2"}, 667 {"DSP RX2 Source", "ASPRX1", "ASPRX1"}, 668 {"DSP RX2 Source", "ASPRX2", "ASPRX2"}, 669 670 {"DSP1", NULL, "DSP RX1 Source"}, 671 {"DSP1", NULL, "DSP RX2 Source"}, 672 673 {"ASP TX1 Source", "VMON", "VMON ADC"}, 674 {"ASP TX1 Source", "IMON", "IMON ADC"}, 675 {"ASP TX1 Source", "VPMON", "VPMON ADC"}, 676 {"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"}, 677 {"ASP TX1 Source", "DSPTX1", "DSP1"}, 678 {"ASP TX1 Source", "DSPTX2", "DSP1"}, 679 {"ASP TX1 Source", "ASPRX1", "ASPRX1" }, 680 {"ASP TX1 Source", "ASPRX2", "ASPRX2" }, 681 {"ASP TX2 Source", "VMON", "VMON ADC"}, 682 {"ASP TX2 Source", "IMON", "IMON ADC"}, 683 {"ASP TX2 Source", "VPMON", "VPMON ADC"}, 684 {"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"}, 685 {"ASP TX2 Source", "DSPTX1", "DSP1"}, 686 {"ASP TX2 Source", "DSPTX2", "DSP1"}, 687 {"ASP TX2 Source", "ASPRX1", "ASPRX1" }, 688 {"ASP TX2 Source", "ASPRX2", "ASPRX2" }, 689 {"ASP TX3 Source", "VMON", "VMON ADC"}, 690 {"ASP TX3 Source", "IMON", "IMON ADC"}, 691 {"ASP TX3 Source", "VPMON", "VPMON ADC"}, 692 {"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"}, 693 {"ASP TX3 Source", "DSPTX1", "DSP1"}, 694 {"ASP TX3 Source", "DSPTX2", "DSP1"}, 695 {"ASP TX3 Source", "ASPRX1", "ASPRX1" }, 696 {"ASP TX3 Source", "ASPRX2", "ASPRX2" }, 697 {"ASP TX4 Source", "VMON", "VMON ADC"}, 698 {"ASP TX4 Source", "IMON", "IMON ADC"}, 699 {"ASP TX4 Source", "VPMON", "VPMON ADC"}, 700 {"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"}, 701 {"ASP TX4 Source", "DSPTX1", "DSP1"}, 702 {"ASP TX4 Source", "DSPTX2", "DSP1"}, 703 {"ASP TX4 Source", "ASPRX1", "ASPRX1" }, 704 {"ASP TX4 Source", "ASPRX2", "ASPRX2" }, 705 {"ASPTX1", NULL, "ASP TX1 Source"}, 706 {"ASPTX2", NULL, "ASP TX2 Source"}, 707 {"ASPTX3", NULL, "ASP TX3 Source"}, 708 {"ASPTX4", NULL, "ASP TX4 Source"}, 709 {"AMP Capture", NULL, "ASPTX1"}, 710 {"AMP Capture", NULL, "ASPTX2"}, 711 {"AMP Capture", NULL, "ASPTX3"}, 712 {"AMP Capture", NULL, "ASPTX4"}, 713 714 {"DSP1", NULL, "VMON"}, 715 {"DSP1", NULL, "IMON"}, 716 {"DSP1", NULL, "VPMON"}, 717 {"DSP1", NULL, "VBSTMON"}, 718 {"DSP1", NULL, "TEMPMON"}, 719 720 {"VMON ADC", NULL, "VMON"}, 721 {"IMON ADC", NULL, "IMON"}, 722 {"VPMON ADC", NULL, "VPMON"}, 723 {"VBSTMON ADC", NULL, "VBSTMON"}, 724 {"TEMPMON ADC", NULL, "TEMPMON"}, 725 726 {"VMON ADC", NULL, "VSENSE"}, 727 {"IMON ADC", NULL, "ISENSE"}, 728 {"VPMON ADC", NULL, "VP"}, 729 {"VBSTMON ADC", NULL, "VBST"}, 730 {"TEMPMON ADC", NULL, "TEMP"}, 731 732 {"DSP1 Preload", NULL, "DSP1 Preloader"}, 733 {"DSP1", NULL, "DSP1 Preloader"}, 734 735 {"ASPRX1", NULL, "AMP Playback"}, 736 {"ASPRX2", NULL, "AMP Playback"}, 737 {"DRE", "Switch", "CLASS H"}, 738 {"Main AMP", NULL, "CLASS H"}, 739 {"Main AMP", NULL, "DRE"}, 740 {"SPK", NULL, "Main AMP"}, 741 742 {"PCM Source", "ASP", "ASPRX1"}, 743 {"PCM Source", "DSP", "DSP1"}, 744 {"CLASS H", NULL, "PCM Source"}, 745 }; 746 747 static const struct cs_dsp_region cs35l41_dsp1_regions[] = { 748 { .type = WMFW_HALO_PM_PACKED, .base = CS35L41_DSP1_PMEM_0 }, 749 { .type = WMFW_HALO_XM_PACKED, .base = CS35L41_DSP1_XMEM_PACK_0 }, 750 { .type = WMFW_HALO_YM_PACKED, .base = CS35L41_DSP1_YMEM_PACK_0 }, 751 {. type = WMFW_ADSP2_XM, .base = CS35L41_DSP1_XMEM_UNPACK24_0}, 752 {. type = WMFW_ADSP2_YM, .base = CS35L41_DSP1_YMEM_UNPACK24_0}, 753 }; 754 755 static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_n, 756 unsigned int *tx_slot, unsigned int rx_n, unsigned int *rx_slot) 757 { 758 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 759 760 return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_n, tx_slot, rx_n, rx_slot); 761 } 762 763 static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 764 { 765 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 766 unsigned int daifmt = 0; 767 768 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 769 case SND_SOC_DAIFMT_CBP_CFP: 770 daifmt |= CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK; 771 break; 772 case SND_SOC_DAIFMT_CBC_CFC: 773 break; 774 default: 775 dev_warn(cs35l41->dev, "Mixed provider/consumer mode unsupported\n"); 776 return -EINVAL; 777 } 778 779 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 780 case SND_SOC_DAIFMT_DSP_A: 781 break; 782 case SND_SOC_DAIFMT_I2S: 783 daifmt |= 2 << CS35L41_ASP_FMT_SHIFT; 784 break; 785 default: 786 dev_warn(cs35l41->dev, "Invalid or unsupported DAI format\n"); 787 return -EINVAL; 788 } 789 790 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 791 case SND_SOC_DAIFMT_NB_IF: 792 daifmt |= CS35L41_LRCLK_INV_MASK; 793 break; 794 case SND_SOC_DAIFMT_IB_NF: 795 daifmt |= CS35L41_SCLK_INV_MASK; 796 break; 797 case SND_SOC_DAIFMT_IB_IF: 798 daifmt |= CS35L41_LRCLK_INV_MASK | CS35L41_SCLK_INV_MASK; 799 break; 800 case SND_SOC_DAIFMT_NB_NF: 801 break; 802 default: 803 dev_warn(cs35l41->dev, "Invalid DAI clock INV\n"); 804 return -EINVAL; 805 } 806 807 return regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 808 CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK | 809 CS35L41_ASP_FMT_MASK | CS35L41_LRCLK_INV_MASK | 810 CS35L41_SCLK_INV_MASK, daifmt); 811 } 812 813 struct cs35l41_global_fs_config { 814 int rate; 815 int fs_cfg; 816 }; 817 818 static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = { 819 { 12000, 0x01 }, 820 { 24000, 0x02 }, 821 { 48000, 0x03 }, 822 { 96000, 0x04 }, 823 { 192000, 0x05 }, 824 { 11025, 0x09 }, 825 { 22050, 0x0A }, 826 { 44100, 0x0B }, 827 { 88200, 0x0C }, 828 { 176400, 0x0D }, 829 { 8000, 0x11 }, 830 { 16000, 0x12 }, 831 { 32000, 0x13 }, 832 }; 833 834 static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream, 835 struct snd_pcm_hw_params *params, 836 struct snd_soc_dai *dai) 837 { 838 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 839 unsigned int rate = params_rate(params); 840 u8 asp_wl; 841 int i; 842 843 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) { 844 if (rate == cs35l41_fs_rates[i].rate) 845 break; 846 } 847 848 if (i >= ARRAY_SIZE(cs35l41_fs_rates)) { 849 dev_err(cs35l41->dev, "Unsupported rate: %u\n", rate); 850 return -EINVAL; 851 } 852 853 asp_wl = params_width(params); 854 855 if (i < ARRAY_SIZE(cs35l41_fs_rates)) 856 regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL, 857 CS35L41_GLOBAL_FS_MASK, 858 cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT); 859 860 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 861 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 862 CS35L41_ASP_WIDTH_RX_MASK, 863 asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT); 864 regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL, 865 CS35L41_ASP_RX_WL_MASK, 866 asp_wl << CS35L41_ASP_RX_WL_SHIFT); 867 } else { 868 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 869 CS35L41_ASP_WIDTH_TX_MASK, 870 asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT); 871 regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL, 872 CS35L41_ASP_TX_WL_MASK, 873 asp_wl << CS35L41_ASP_TX_WL_SHIFT); 874 } 875 876 return 0; 877 } 878 879 static int cs35l41_get_clk_config(int freq) 880 { 881 int i; 882 883 for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) { 884 if (cs35l41_pll_sysclk[i].freq == freq) 885 return cs35l41_pll_sysclk[i].clk_cfg; 886 } 887 888 return -EINVAL; 889 } 890 891 static const unsigned int cs35l41_src_rates[] = { 892 8000, 12000, 11025, 16000, 22050, 24000, 32000, 893 44100, 48000, 88200, 96000, 176400, 192000 894 }; 895 896 static const struct snd_pcm_hw_constraint_list cs35l41_constraints = { 897 .count = ARRAY_SIZE(cs35l41_src_rates), 898 .list = cs35l41_src_rates, 899 }; 900 901 static int cs35l41_pcm_startup(struct snd_pcm_substream *substream, 902 struct snd_soc_dai *dai) 903 { 904 if (substream->runtime) 905 return snd_pcm_hw_constraint_list(substream->runtime, 0, 906 SNDRV_PCM_HW_PARAM_RATE, 907 &cs35l41_constraints); 908 return 0; 909 } 910 911 static int cs35l41_component_set_sysclk(struct snd_soc_component *component, 912 int clk_id, int source, 913 unsigned int freq, int dir) 914 { 915 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 916 int extclk_cfg, clksrc; 917 918 switch (clk_id) { 919 case CS35L41_CLKID_SCLK: 920 clksrc = CS35L41_PLLSRC_SCLK; 921 break; 922 case CS35L41_CLKID_LRCLK: 923 clksrc = CS35L41_PLLSRC_LRCLK; 924 break; 925 case CS35L41_CLKID_MCLK: 926 clksrc = CS35L41_PLLSRC_MCLK; 927 break; 928 default: 929 dev_err(cs35l41->dev, "Invalid CLK Config\n"); 930 return -EINVAL; 931 } 932 933 extclk_cfg = cs35l41_get_clk_config(freq); 934 935 if (extclk_cfg < 0) { 936 dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n", 937 extclk_cfg, freq); 938 return -EINVAL; 939 } 940 941 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 942 CS35L41_PLL_OPENLOOP_MASK, 943 1 << CS35L41_PLL_OPENLOOP_SHIFT); 944 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 945 CS35L41_REFCLK_FREQ_MASK, 946 extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT); 947 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 948 CS35L41_PLL_CLK_EN_MASK, 949 0 << CS35L41_PLL_CLK_EN_SHIFT); 950 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 951 CS35L41_PLL_CLK_SEL_MASK, clksrc); 952 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 953 CS35L41_PLL_OPENLOOP_MASK, 954 0 << CS35L41_PLL_OPENLOOP_SHIFT); 955 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 956 CS35L41_PLL_CLK_EN_MASK, 957 1 << CS35L41_PLL_CLK_EN_SHIFT); 958 959 return 0; 960 } 961 962 static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai, 963 int clk_id, unsigned int freq, int dir) 964 { 965 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 966 unsigned int fs1_val; 967 unsigned int fs2_val; 968 unsigned int val; 969 int fsindex; 970 971 fsindex = cs35l41_get_fs_mon_config_index(freq); 972 if (fsindex < 0) { 973 dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq); 974 return -EINVAL; 975 } 976 977 dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq); 978 979 if (freq <= 6144000) { 980 /* Use the lookup table */ 981 fs1_val = cs35l41_fs_mon[fsindex].fs1; 982 fs2_val = cs35l41_fs_mon[fsindex].fs2; 983 } else { 984 /* Use hard-coded values */ 985 fs1_val = 0x10; 986 fs2_val = 0x24; 987 } 988 989 val = fs1_val; 990 val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK; 991 regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val); 992 993 return 0; 994 } 995 996 static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) 997 { 998 int ret; 999 1000 /* Set Platform Data */ 1001 /* Required */ 1002 if (cs35l41->pdata.bst_ipk && 1003 cs35l41->pdata.bst_ind && cs35l41->pdata.bst_cap) { 1004 ret = cs35l41_boost_config(cs35l41->dev, cs35l41->regmap, cs35l41->pdata.bst_ind, 1005 cs35l41->pdata.bst_cap, cs35l41->pdata.bst_ipk); 1006 if (ret) { 1007 dev_err(cs35l41->dev, "Error in Boost DT config: %d\n", ret); 1008 return ret; 1009 } 1010 } else { 1011 dev_err(cs35l41->dev, "Incomplete Boost component DT config\n"); 1012 return -EINVAL; 1013 } 1014 1015 /* Optional */ 1016 if (cs35l41->pdata.dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && 1017 cs35l41->pdata.dout_hiz >= 0) 1018 regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, 1019 CS35L41_ASP_DOUT_HIZ_MASK, 1020 cs35l41->pdata.dout_hiz); 1021 1022 return 0; 1023 } 1024 1025 static int cs35l41_irq_gpio_config(struct cs35l41_private *cs35l41) 1026 { 1027 struct cs35l41_irq_cfg *irq_gpio_cfg1 = &cs35l41->pdata.irq_config1; 1028 struct cs35l41_irq_cfg *irq_gpio_cfg2 = &cs35l41->pdata.irq_config2; 1029 int irq_pol = IRQF_TRIGGER_NONE; 1030 1031 regmap_update_bits(cs35l41->regmap, CS35L41_GPIO1_CTRL1, 1032 CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, 1033 irq_gpio_cfg1->irq_pol_inv << CS35L41_GPIO_POL_SHIFT | 1034 !irq_gpio_cfg1->irq_out_en << CS35L41_GPIO_DIR_SHIFT); 1035 1036 regmap_update_bits(cs35l41->regmap, CS35L41_GPIO2_CTRL1, 1037 CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, 1038 irq_gpio_cfg2->irq_pol_inv << CS35L41_GPIO_POL_SHIFT | 1039 !irq_gpio_cfg2->irq_out_en << CS35L41_GPIO_DIR_SHIFT); 1040 1041 regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, 1042 CS35L41_GPIO1_CTRL_MASK | CS35L41_GPIO2_CTRL_MASK, 1043 irq_gpio_cfg1->irq_src_sel << CS35L41_GPIO1_CTRL_SHIFT | 1044 irq_gpio_cfg2->irq_src_sel << CS35L41_GPIO2_CTRL_SHIFT); 1045 1046 if ((irq_gpio_cfg2->irq_src_sel == 1047 (CS35L41_GPIO_CTRL_ACTV_LO | CS35L41_VALID_PDATA)) || 1048 (irq_gpio_cfg2->irq_src_sel == 1049 (CS35L41_GPIO_CTRL_OPEN_INT | CS35L41_VALID_PDATA))) 1050 irq_pol = IRQF_TRIGGER_LOW; 1051 else if (irq_gpio_cfg2->irq_src_sel == 1052 (CS35L41_GPIO_CTRL_ACTV_HI | CS35L41_VALID_PDATA)) 1053 irq_pol = IRQF_TRIGGER_HIGH; 1054 1055 return irq_pol; 1056 } 1057 1058 static int cs35l41_component_probe(struct snd_soc_component *component) 1059 { 1060 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 1061 1062 return wm_adsp2_component_probe(&cs35l41->dsp, component); 1063 } 1064 1065 static void cs35l41_component_remove(struct snd_soc_component *component) 1066 { 1067 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 1068 1069 wm_adsp2_component_remove(&cs35l41->dsp, component); 1070 } 1071 1072 static const struct snd_soc_dai_ops cs35l41_ops = { 1073 .startup = cs35l41_pcm_startup, 1074 .set_fmt = cs35l41_set_dai_fmt, 1075 .hw_params = cs35l41_pcm_hw_params, 1076 .set_sysclk = cs35l41_dai_set_sysclk, 1077 .set_channel_map = cs35l41_set_channel_map, 1078 }; 1079 1080 static struct snd_soc_dai_driver cs35l41_dai[] = { 1081 { 1082 .name = "cs35l41-pcm", 1083 .id = 0, 1084 .playback = { 1085 .stream_name = "AMP Playback", 1086 .channels_min = 1, 1087 .channels_max = 2, 1088 .rates = SNDRV_PCM_RATE_KNOT, 1089 .formats = CS35L41_RX_FORMATS, 1090 }, 1091 .capture = { 1092 .stream_name = "AMP Capture", 1093 .channels_min = 1, 1094 .channels_max = 4, 1095 .rates = SNDRV_PCM_RATE_KNOT, 1096 .formats = CS35L41_TX_FORMATS, 1097 }, 1098 .ops = &cs35l41_ops, 1099 .symmetric_rate = 1, 1100 }, 1101 }; 1102 1103 static const struct snd_soc_component_driver soc_component_dev_cs35l41 = { 1104 .name = "cs35l41-codec", 1105 .probe = cs35l41_component_probe, 1106 .remove = cs35l41_component_remove, 1107 1108 .dapm_widgets = cs35l41_dapm_widgets, 1109 .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets), 1110 .dapm_routes = cs35l41_audio_map, 1111 .num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map), 1112 1113 .controls = cs35l41_aud_controls, 1114 .num_controls = ARRAY_SIZE(cs35l41_aud_controls), 1115 .set_sysclk = cs35l41_component_set_sysclk, 1116 }; 1117 1118 static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_platform_data *pdata) 1119 { 1120 struct cs35l41_irq_cfg *irq_gpio1_config = &pdata->irq_config1; 1121 struct cs35l41_irq_cfg *irq_gpio2_config = &pdata->irq_config2; 1122 unsigned int val; 1123 int ret; 1124 1125 ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val); 1126 if (ret >= 0) 1127 pdata->bst_ipk = val; 1128 1129 ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val); 1130 if (ret >= 0) 1131 pdata->bst_ind = val; 1132 1133 ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val); 1134 if (ret >= 0) 1135 pdata->bst_cap = val; 1136 1137 ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val); 1138 if (ret >= 0) 1139 pdata->dout_hiz = val; 1140 else 1141 pdata->dout_hiz = -1; 1142 1143 /* GPIO1 Pin Config */ 1144 irq_gpio1_config->irq_pol_inv = device_property_read_bool(dev, 1145 "cirrus,gpio1-polarity-invert"); 1146 irq_gpio1_config->irq_out_en = device_property_read_bool(dev, 1147 "cirrus,gpio1-output-enable"); 1148 ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", 1149 &val); 1150 if (ret >= 0) 1151 irq_gpio1_config->irq_src_sel = val | CS35L41_VALID_PDATA; 1152 1153 /* GPIO2 Pin Config */ 1154 irq_gpio2_config->irq_pol_inv = device_property_read_bool(dev, 1155 "cirrus,gpio2-polarity-invert"); 1156 irq_gpio2_config->irq_out_en = device_property_read_bool(dev, 1157 "cirrus,gpio2-output-enable"); 1158 ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", 1159 &val); 1160 if (ret >= 0) 1161 irq_gpio2_config->irq_src_sel = val | CS35L41_VALID_PDATA; 1162 1163 return 0; 1164 } 1165 1166 static const struct reg_sequence cs35l41_fs_errata_patch[] = { 1167 { CS35L41_DSP1_RX1_RATE, 0x00000001 }, 1168 { CS35L41_DSP1_RX2_RATE, 0x00000001 }, 1169 { CS35L41_DSP1_RX3_RATE, 0x00000001 }, 1170 { CS35L41_DSP1_RX4_RATE, 0x00000001 }, 1171 { CS35L41_DSP1_RX5_RATE, 0x00000001 }, 1172 { CS35L41_DSP1_RX6_RATE, 0x00000001 }, 1173 { CS35L41_DSP1_RX7_RATE, 0x00000001 }, 1174 { CS35L41_DSP1_RX8_RATE, 0x00000001 }, 1175 { CS35L41_DSP1_TX1_RATE, 0x00000001 }, 1176 { CS35L41_DSP1_TX2_RATE, 0x00000001 }, 1177 { CS35L41_DSP1_TX3_RATE, 0x00000001 }, 1178 { CS35L41_DSP1_TX4_RATE, 0x00000001 }, 1179 { CS35L41_DSP1_TX5_RATE, 0x00000001 }, 1180 { CS35L41_DSP1_TX6_RATE, 0x00000001 }, 1181 { CS35L41_DSP1_TX7_RATE, 0x00000001 }, 1182 { CS35L41_DSP1_TX8_RATE, 0x00000001 }, 1183 }; 1184 1185 static int cs35l41_dsp_init(struct cs35l41_private *cs35l41) 1186 { 1187 struct wm_adsp *dsp; 1188 int ret; 1189 1190 dsp = &cs35l41->dsp; 1191 dsp->part = "cs35l41"; 1192 dsp->cs_dsp.num = 1; 1193 dsp->cs_dsp.type = WMFW_HALO; 1194 dsp->cs_dsp.rev = 0; 1195 dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */ 1196 dsp->toggle_preload = true; 1197 dsp->cs_dsp.dev = cs35l41->dev; 1198 dsp->cs_dsp.regmap = cs35l41->regmap; 1199 dsp->cs_dsp.base = CS35L41_DSP1_CTRL_BASE; 1200 dsp->cs_dsp.base_sysinfo = CS35L41_DSP1_SYS_ID; 1201 dsp->cs_dsp.mem = cs35l41_dsp1_regions; 1202 dsp->cs_dsp.num_mems = ARRAY_SIZE(cs35l41_dsp1_regions); 1203 dsp->cs_dsp.lock_regions = 0xFFFFFFFF; 1204 1205 ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_fs_errata_patch, 1206 ARRAY_SIZE(cs35l41_fs_errata_patch)); 1207 if (ret < 0) { 1208 dev_err(cs35l41->dev, "Failed to write fs errata: %d\n", ret); 1209 return ret; 1210 } 1211 1212 ret = wm_halo_init(dsp); 1213 if (ret) { 1214 dev_err(cs35l41->dev, "wm_halo_init failed: %d\n", ret); 1215 return ret; 1216 } 1217 1218 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC, 1219 CS35L41_INPUT_SRC_VPMON); 1220 if (ret < 0) { 1221 dev_err(cs35l41->dev, "Write INPUT_SRC_VPMON failed: %d\n", ret); 1222 goto err_dsp; 1223 } 1224 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC, 1225 CS35L41_INPUT_SRC_CLASSH); 1226 if (ret < 0) { 1227 dev_err(cs35l41->dev, "Write INPUT_SRC_CLASSH failed: %d\n", ret); 1228 goto err_dsp; 1229 } 1230 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC, 1231 CS35L41_INPUT_SRC_TEMPMON); 1232 if (ret < 0) { 1233 dev_err(cs35l41->dev, "Write INPUT_SRC_TEMPMON failed: %d\n", ret); 1234 goto err_dsp; 1235 } 1236 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC, 1237 CS35L41_INPUT_SRC_RSVD); 1238 if (ret < 0) { 1239 dev_err(cs35l41->dev, "Write INPUT_SRC_RSVD failed: %d\n", ret); 1240 goto err_dsp; 1241 } 1242 1243 return 0; 1244 1245 err_dsp: 1246 wm_adsp2_remove(dsp); 1247 1248 return ret; 1249 } 1250 1251 int cs35l41_probe(struct cs35l41_private *cs35l41, 1252 struct cs35l41_platform_data *pdata) 1253 { 1254 u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match; 1255 int irq_pol = 0; 1256 int ret; 1257 1258 if (pdata) { 1259 cs35l41->pdata = *pdata; 1260 } else { 1261 ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->pdata); 1262 if (ret != 0) 1263 return ret; 1264 } 1265 1266 for (i = 0; i < CS35L41_NUM_SUPPLIES; i++) 1267 cs35l41->supplies[i].supply = cs35l41_supplies[i]; 1268 1269 ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES, 1270 cs35l41->supplies); 1271 if (ret != 0) { 1272 dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", ret); 1273 return ret; 1274 } 1275 1276 ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1277 if (ret != 0) { 1278 dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", ret); 1279 return ret; 1280 } 1281 1282 /* returning NULL can be an option if in stereo mode */ 1283 cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset", 1284 GPIOD_OUT_LOW); 1285 if (IS_ERR(cs35l41->reset_gpio)) { 1286 ret = PTR_ERR(cs35l41->reset_gpio); 1287 cs35l41->reset_gpio = NULL; 1288 if (ret == -EBUSY) { 1289 dev_info(cs35l41->dev, 1290 "Reset line busy, assuming shared reset\n"); 1291 } else { 1292 dev_err(cs35l41->dev, 1293 "Failed to get reset GPIO: %d\n", ret); 1294 goto err; 1295 } 1296 } 1297 if (cs35l41->reset_gpio) { 1298 /* satisfy minimum reset pulse width spec */ 1299 usleep_range(2000, 2100); 1300 gpiod_set_value_cansleep(cs35l41->reset_gpio, 1); 1301 } 1302 1303 usleep_range(2000, 2100); 1304 1305 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4, 1306 int_status, int_status & CS35L41_OTP_BOOT_DONE, 1307 1000, 100000); 1308 if (ret) { 1309 dev_err(cs35l41->dev, 1310 "Failed waiting for OTP_BOOT_DONE: %d\n", ret); 1311 goto err; 1312 } 1313 1314 regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status); 1315 if (int_status & CS35L41_OTP_BOOT_ERR) { 1316 dev_err(cs35l41->dev, "OTP Boot error\n"); 1317 ret = -EINVAL; 1318 goto err; 1319 } 1320 1321 ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id); 1322 if (ret < 0) { 1323 dev_err(cs35l41->dev, "Get Device ID failed: %d\n", ret); 1324 goto err; 1325 } 1326 1327 ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid); 1328 if (ret < 0) { 1329 dev_err(cs35l41->dev, "Get Revision ID failed: %d\n", ret); 1330 goto err; 1331 } 1332 1333 mtl_revid = reg_revid & CS35L41_MTLREVID_MASK; 1334 1335 /* CS35L41 will have even MTLREVID 1336 * CS35L41R will have odd MTLREVID 1337 */ 1338 chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID; 1339 if (regid != chipid_match) { 1340 dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n", 1341 regid, chipid_match); 1342 ret = -ENODEV; 1343 goto err; 1344 } 1345 1346 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap); 1347 1348 ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid); 1349 if (ret) 1350 goto err; 1351 1352 ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap); 1353 if (ret < 0) { 1354 dev_err(cs35l41->dev, "OTP Unpack failed: %d\n", ret); 1355 goto err; 1356 } 1357 1358 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); 1359 1360 irq_pol = cs35l41_irq_gpio_config(cs35l41); 1361 1362 /* Set interrupt masks for critical errors */ 1363 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 1364 CS35L41_INT1_MASK_DEFAULT); 1365 1366 ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq, 1367 IRQF_ONESHOT | IRQF_SHARED | irq_pol, 1368 "cs35l41", cs35l41); 1369 if (ret != 0) { 1370 dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret); 1371 goto err; 1372 } 1373 1374 ret = cs35l41_set_pdata(cs35l41); 1375 if (ret < 0) { 1376 dev_err(cs35l41->dev, "Set pdata failed: %d\n", ret); 1377 goto err; 1378 } 1379 1380 ret = cs35l41_dsp_init(cs35l41); 1381 if (ret < 0) 1382 goto err; 1383 1384 pm_runtime_set_autosuspend_delay(cs35l41->dev, 3000); 1385 pm_runtime_use_autosuspend(cs35l41->dev); 1386 pm_runtime_mark_last_busy(cs35l41->dev); 1387 pm_runtime_set_active(cs35l41->dev); 1388 pm_runtime_get_noresume(cs35l41->dev); 1389 pm_runtime_enable(cs35l41->dev); 1390 1391 ret = devm_snd_soc_register_component(cs35l41->dev, 1392 &soc_component_dev_cs35l41, 1393 cs35l41_dai, ARRAY_SIZE(cs35l41_dai)); 1394 if (ret < 0) { 1395 dev_err(cs35l41->dev, "Register codec failed: %d\n", ret); 1396 goto err_pm; 1397 } 1398 1399 pm_runtime_put_autosuspend(cs35l41->dev); 1400 1401 dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n", 1402 regid, reg_revid); 1403 1404 return 0; 1405 1406 err_pm: 1407 pm_runtime_disable(cs35l41->dev); 1408 pm_runtime_put_noidle(cs35l41->dev); 1409 1410 wm_adsp2_remove(&cs35l41->dsp); 1411 err: 1412 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1413 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1414 1415 return ret; 1416 } 1417 EXPORT_SYMBOL_GPL(cs35l41_probe); 1418 1419 void cs35l41_remove(struct cs35l41_private *cs35l41) 1420 { 1421 pm_runtime_get_sync(cs35l41->dev); 1422 pm_runtime_disable(cs35l41->dev); 1423 1424 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF); 1425 wm_adsp2_remove(&cs35l41->dsp); 1426 1427 pm_runtime_put_noidle(cs35l41->dev); 1428 1429 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1430 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1431 } 1432 EXPORT_SYMBOL_GPL(cs35l41_remove); 1433 1434 static int __maybe_unused cs35l41_runtime_suspend(struct device *dev) 1435 { 1436 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1437 1438 dev_dbg(cs35l41->dev, "Runtime suspend\n"); 1439 1440 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running) 1441 return 0; 1442 1443 dev_dbg(cs35l41->dev, "Enter hibernate\n"); 1444 1445 regmap_write(cs35l41->regmap, CS35L41_WAKESRC_CTL, 0x0088); 1446 regmap_write(cs35l41->regmap, CS35L41_WAKESRC_CTL, 0x0188); 1447 1448 // Don't wait for ACK since bus activity would wake the device 1449 regmap_write(cs35l41->regmap, CS35L41_DSP_VIRT1_MBOX_1, 1450 CSPL_MBOX_CMD_HIBERNATE); 1451 1452 regcache_cache_only(cs35l41->regmap, true); 1453 regcache_mark_dirty(cs35l41->regmap); 1454 1455 return 0; 1456 } 1457 1458 static void cs35l41_wait_for_pwrmgt_sts(struct cs35l41_private *cs35l41) 1459 { 1460 const int pwrmgt_retries = 10; 1461 unsigned int sts; 1462 int i, ret; 1463 1464 for (i = 0; i < pwrmgt_retries; i++) { 1465 ret = regmap_read(cs35l41->regmap, CS35L41_PWRMGT_STS, &sts); 1466 if (ret) 1467 dev_err(cs35l41->dev, "Failed to read PWRMGT_STS: %d\n", ret); 1468 else if (!(sts & CS35L41_WR_PEND_STS_MASK)) 1469 return; 1470 1471 udelay(20); 1472 } 1473 1474 dev_err(cs35l41->dev, "Timed out reading PWRMGT_STS\n"); 1475 } 1476 1477 static int cs35l41_exit_hibernate(struct cs35l41_private *cs35l41) 1478 { 1479 const int wake_retries = 20; 1480 const int sleep_retries = 5; 1481 int ret, i, j; 1482 1483 for (i = 0; i < sleep_retries; i++) { 1484 dev_dbg(cs35l41->dev, "Exit hibernate\n"); 1485 1486 for (j = 0; j < wake_retries; j++) { 1487 ret = cs35l41_set_cspl_mbox_cmd(cs35l41, 1488 CSPL_MBOX_CMD_OUT_OF_HIBERNATE); 1489 if (!ret) 1490 break; 1491 1492 usleep_range(100, 200); 1493 } 1494 1495 if (j < wake_retries) { 1496 dev_dbg(cs35l41->dev, "Wake success at cycle: %d\n", j); 1497 return 0; 1498 } 1499 1500 dev_err(cs35l41->dev, "Wake failed, re-enter hibernate: %d\n", ret); 1501 1502 cs35l41_wait_for_pwrmgt_sts(cs35l41); 1503 regmap_write(cs35l41->regmap, CS35L41_WAKESRC_CTL, 0x0088); 1504 1505 cs35l41_wait_for_pwrmgt_sts(cs35l41); 1506 regmap_write(cs35l41->regmap, CS35L41_WAKESRC_CTL, 0x0188); 1507 1508 cs35l41_wait_for_pwrmgt_sts(cs35l41); 1509 regmap_write(cs35l41->regmap, CS35L41_PWRMGT_CTL, 0x3); 1510 } 1511 1512 dev_err(cs35l41->dev, "Timed out waking device\n"); 1513 1514 return -ETIMEDOUT; 1515 } 1516 1517 static int __maybe_unused cs35l41_runtime_resume(struct device *dev) 1518 { 1519 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1520 int ret; 1521 1522 dev_dbg(cs35l41->dev, "Runtime resume\n"); 1523 1524 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running) 1525 return 0; 1526 1527 regcache_cache_only(cs35l41->regmap, false); 1528 1529 ret = cs35l41_exit_hibernate(cs35l41); 1530 if (ret) 1531 return ret; 1532 1533 /* Test key needs to be unlocked to allow the OTP settings to re-apply */ 1534 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap); 1535 ret = regcache_sync(cs35l41->regmap); 1536 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); 1537 if (ret) { 1538 dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret); 1539 return ret; 1540 } 1541 1542 return 0; 1543 } 1544 1545 static int __maybe_unused cs35l41_sys_suspend(struct device *dev) 1546 { 1547 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1548 1549 dev_dbg(cs35l41->dev, "System suspend, disabling IRQ\n"); 1550 disable_irq(cs35l41->irq); 1551 1552 return 0; 1553 } 1554 1555 static int __maybe_unused cs35l41_sys_suspend_noirq(struct device *dev) 1556 { 1557 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1558 1559 dev_dbg(cs35l41->dev, "Late system suspend, reenabling IRQ\n"); 1560 enable_irq(cs35l41->irq); 1561 1562 return 0; 1563 } 1564 1565 static int __maybe_unused cs35l41_sys_resume_noirq(struct device *dev) 1566 { 1567 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1568 1569 dev_dbg(cs35l41->dev, "Early system resume, disabling IRQ\n"); 1570 disable_irq(cs35l41->irq); 1571 1572 return 0; 1573 } 1574 1575 static int __maybe_unused cs35l41_sys_resume(struct device *dev) 1576 { 1577 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1578 1579 dev_dbg(cs35l41->dev, "System resume, reenabling IRQ\n"); 1580 enable_irq(cs35l41->irq); 1581 1582 return 0; 1583 } 1584 1585 const struct dev_pm_ops cs35l41_pm_ops = { 1586 SET_RUNTIME_PM_OPS(cs35l41_runtime_suspend, cs35l41_runtime_resume, NULL) 1587 1588 SET_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend, cs35l41_sys_resume) 1589 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend_noirq, cs35l41_sys_resume_noirq) 1590 }; 1591 EXPORT_SYMBOL_GPL(cs35l41_pm_ops); 1592 1593 MODULE_DESCRIPTION("ASoC CS35L41 driver"); 1594 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>"); 1595 MODULE_LICENSE("GPL"); 1596