1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // cs35l41.c -- CS35l41 ALSA SoC audio driver 4 // 5 // Copyright 2017-2021 Cirrus Logic, Inc. 6 // 7 // Author: David Rhodes <david.rhodes@cirrus.com> 8 9 #include <linux/acpi.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/of_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/property.h> 19 #include <sound/initval.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/soc-dapm.h> 24 #include <sound/tlv.h> 25 26 #include "cs35l41.h" 27 28 static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = { 29 "VA", 30 "VP", 31 }; 32 33 struct cs35l41_pll_sysclk_config { 34 int freq; 35 int clk_cfg; 36 }; 37 38 static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = { 39 { 32768, 0x00 }, 40 { 8000, 0x01 }, 41 { 11025, 0x02 }, 42 { 12000, 0x03 }, 43 { 16000, 0x04 }, 44 { 22050, 0x05 }, 45 { 24000, 0x06 }, 46 { 32000, 0x07 }, 47 { 44100, 0x08 }, 48 { 48000, 0x09 }, 49 { 88200, 0x0A }, 50 { 96000, 0x0B }, 51 { 128000, 0x0C }, 52 { 176400, 0x0D }, 53 { 192000, 0x0E }, 54 { 256000, 0x0F }, 55 { 352800, 0x10 }, 56 { 384000, 0x11 }, 57 { 512000, 0x12 }, 58 { 705600, 0x13 }, 59 { 750000, 0x14 }, 60 { 768000, 0x15 }, 61 { 1000000, 0x16 }, 62 { 1024000, 0x17 }, 63 { 1200000, 0x18 }, 64 { 1411200, 0x19 }, 65 { 1500000, 0x1A }, 66 { 1536000, 0x1B }, 67 { 2000000, 0x1C }, 68 { 2048000, 0x1D }, 69 { 2400000, 0x1E }, 70 { 2822400, 0x1F }, 71 { 3000000, 0x20 }, 72 { 3072000, 0x21 }, 73 { 3200000, 0x22 }, 74 { 4000000, 0x23 }, 75 { 4096000, 0x24 }, 76 { 4800000, 0x25 }, 77 { 5644800, 0x26 }, 78 { 6000000, 0x27 }, 79 { 6144000, 0x28 }, 80 { 6250000, 0x29 }, 81 { 6400000, 0x2A }, 82 { 6500000, 0x2B }, 83 { 6750000, 0x2C }, 84 { 7526400, 0x2D }, 85 { 8000000, 0x2E }, 86 { 8192000, 0x2F }, 87 { 9600000, 0x30 }, 88 { 11289600, 0x31 }, 89 { 12000000, 0x32 }, 90 { 12288000, 0x33 }, 91 { 12500000, 0x34 }, 92 { 12800000, 0x35 }, 93 { 13000000, 0x36 }, 94 { 13500000, 0x37 }, 95 { 19200000, 0x38 }, 96 { 22579200, 0x39 }, 97 { 24000000, 0x3A }, 98 { 24576000, 0x3B }, 99 { 25000000, 0x3C }, 100 { 25600000, 0x3D }, 101 { 26000000, 0x3E }, 102 { 27000000, 0x3F }, 103 }; 104 105 struct cs35l41_fs_mon_config { 106 int freq; 107 unsigned int fs1; 108 unsigned int fs2; 109 }; 110 111 static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = { 112 { 32768, 2254, 3754 }, 113 { 8000, 9220, 15364 }, 114 { 11025, 6148, 10244 }, 115 { 12000, 6148, 10244 }, 116 { 16000, 4612, 7684 }, 117 { 22050, 3076, 5124 }, 118 { 24000, 3076, 5124 }, 119 { 32000, 2308, 3844 }, 120 { 44100, 1540, 2564 }, 121 { 48000, 1540, 2564 }, 122 { 88200, 772, 1284 }, 123 { 96000, 772, 1284 }, 124 { 128000, 580, 964 }, 125 { 176400, 388, 644 }, 126 { 192000, 388, 644 }, 127 { 256000, 292, 484 }, 128 { 352800, 196, 324 }, 129 { 384000, 196, 324 }, 130 { 512000, 148, 244 }, 131 { 705600, 100, 164 }, 132 { 750000, 100, 164 }, 133 { 768000, 100, 164 }, 134 { 1000000, 76, 124 }, 135 { 1024000, 76, 124 }, 136 { 1200000, 64, 104 }, 137 { 1411200, 52, 84 }, 138 { 1500000, 52, 84 }, 139 { 1536000, 52, 84 }, 140 { 2000000, 40, 64 }, 141 { 2048000, 40, 64 }, 142 { 2400000, 34, 54 }, 143 { 2822400, 28, 44 }, 144 { 3000000, 28, 44 }, 145 { 3072000, 28, 44 }, 146 { 3200000, 27, 42 }, 147 { 4000000, 22, 34 }, 148 { 4096000, 22, 34 }, 149 { 4800000, 19, 29 }, 150 { 5644800, 16, 24 }, 151 { 6000000, 16, 24 }, 152 { 6144000, 16, 24 }, 153 }; 154 155 static int cs35l41_get_fs_mon_config_index(int freq) 156 { 157 int i; 158 159 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) { 160 if (cs35l41_fs_mon[i].freq == freq) 161 return i; 162 } 163 164 return -EINVAL; 165 } 166 167 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv, 168 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 169 1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200)); 170 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1); 171 172 static const struct snd_kcontrol_new dre_ctrl = 173 SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0); 174 175 static const char * const cs35l41_pcm_sftramp_text[] = { 176 "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms" 177 }; 178 179 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, 180 CS35L41_AMP_DIG_VOL_CTRL, 0, 181 cs35l41_pcm_sftramp_text); 182 183 static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w, 184 struct snd_kcontrol *kcontrol, int event) 185 { 186 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 187 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 188 int ret; 189 190 switch (event) { 191 case SND_SOC_DAPM_PRE_PMU: 192 if (cs35l41->dsp.cs_dsp.booted) 193 return 0; 194 195 return wm_adsp_early_event(w, kcontrol, event); 196 case SND_SOC_DAPM_PRE_PMD: 197 if (cs35l41->dsp.preloaded) 198 return 0; 199 200 if (cs35l41->dsp.cs_dsp.running) { 201 ret = wm_adsp_event(w, kcontrol, event); 202 if (ret) 203 return ret; 204 } 205 206 return wm_adsp_early_event(w, kcontrol, event); 207 default: 208 return 0; 209 } 210 } 211 212 static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w, 213 struct snd_kcontrol *kcontrol, int event) 214 { 215 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 216 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 217 unsigned int fw_status; 218 int ret; 219 220 switch (event) { 221 case SND_SOC_DAPM_POST_PMU: 222 if (!cs35l41->dsp.cs_dsp.running) 223 return wm_adsp_event(w, kcontrol, event); 224 225 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &fw_status); 226 if (ret < 0) { 227 dev_err(cs35l41->dev, 228 "Failed to read firmware status: %d\n", ret); 229 return ret; 230 } 231 232 switch (fw_status) { 233 case CSPL_MBOX_STS_RUNNING: 234 case CSPL_MBOX_STS_PAUSED: 235 break; 236 default: 237 dev_err(cs35l41->dev, "Firmware status is invalid: %u\n", 238 fw_status); 239 return -EINVAL; 240 } 241 242 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap, 243 CSPL_MBOX_CMD_RESUME); 244 case SND_SOC_DAPM_PRE_PMD: 245 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap, 246 CSPL_MBOX_CMD_PAUSE); 247 default: 248 return 0; 249 } 250 } 251 252 static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"}; 253 static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32}; 254 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum, 255 CS35L41_DAC_PCM1_SRC, 256 0, CS35L41_ASP_SOURCE_MASK, 257 cs35l41_pcm_source_texts, 258 cs35l41_pcm_source_values); 259 260 static const struct snd_kcontrol_new pcm_source_mux = 261 SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum); 262 263 static const char * const cs35l41_tx_input_texts[] = { 264 "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON", 265 "VPMON", "VBSTMON", "DSPTX1", "DSPTX2" 266 }; 267 268 static const unsigned int cs35l41_tx_input_values[] = { 269 0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2, 270 CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON, 271 CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2 272 }; 273 274 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum, 275 CS35L41_ASP_TX1_SRC, 276 0, CS35L41_ASP_SOURCE_MASK, 277 cs35l41_tx_input_texts, 278 cs35l41_tx_input_values); 279 280 static const struct snd_kcontrol_new asp_tx1_mux = 281 SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum); 282 283 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum, 284 CS35L41_ASP_TX2_SRC, 285 0, CS35L41_ASP_SOURCE_MASK, 286 cs35l41_tx_input_texts, 287 cs35l41_tx_input_values); 288 289 static const struct snd_kcontrol_new asp_tx2_mux = 290 SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum); 291 292 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum, 293 CS35L41_ASP_TX3_SRC, 294 0, CS35L41_ASP_SOURCE_MASK, 295 cs35l41_tx_input_texts, 296 cs35l41_tx_input_values); 297 298 static const struct snd_kcontrol_new asp_tx3_mux = 299 SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum); 300 301 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum, 302 CS35L41_ASP_TX4_SRC, 303 0, CS35L41_ASP_SOURCE_MASK, 304 cs35l41_tx_input_texts, 305 cs35l41_tx_input_values); 306 307 static const struct snd_kcontrol_new asp_tx4_mux = 308 SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum); 309 310 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum, 311 CS35L41_DSP1_RX1_SRC, 312 0, CS35L41_ASP_SOURCE_MASK, 313 cs35l41_tx_input_texts, 314 cs35l41_tx_input_values); 315 316 static const struct snd_kcontrol_new dsp_rx1_mux = 317 SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum); 318 319 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum, 320 CS35L41_DSP1_RX2_SRC, 321 0, CS35L41_ASP_SOURCE_MASK, 322 cs35l41_tx_input_texts, 323 cs35l41_tx_input_values); 324 325 static const struct snd_kcontrol_new dsp_rx2_mux = 326 SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum); 327 328 static const struct snd_kcontrol_new cs35l41_aud_controls[] = { 329 SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL, 330 3, 0x4CF, 0x391, dig_vol_tlv), 331 SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0, 332 amp_gain_tlv), 333 SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp), 334 SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0), 335 SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0), 336 SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0), 337 SOC_SINGLE("Aux Noise Gate CH1 Switch", 338 CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0), 339 SOC_SINGLE("Aux Noise Gate CH1 Entry Delay", 340 CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0), 341 SOC_SINGLE("Aux Noise Gate CH1 Threshold", 342 CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0), 343 SOC_SINGLE("Aux Noise Gate CH2 Entry Delay", 344 CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0), 345 SOC_SINGLE("Aux Noise Gate CH2 Switch", 346 CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0), 347 SOC_SINGLE("Aux Noise Gate CH2 Threshold", 348 CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0), 349 SOC_SINGLE("SCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0), 350 SOC_SINGLE("LRCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0), 351 SOC_SINGLE("Invert Class D Switch", CS35L41_AMP_DIG_VOL_CTRL, 352 CS35L41_AMP_INV_PCM_SHIFT, 1, 0), 353 SOC_SINGLE("Amp Gain ZC Switch", CS35L41_AMP_GAIN_CTRL, 354 CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0), 355 WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), 356 WM_ADSP_FW_CONTROL("DSP1", 0), 357 }; 358 359 static void cs35l41_boost_enable(struct cs35l41_private *cs35l41, unsigned int enable) 360 { 361 switch (cs35l41->hw_cfg.bst_type) { 362 case CS35L41_INT_BOOST: 363 enable = enable ? CS35L41_BST_EN_DEFAULT : CS35L41_BST_DIS_FET_OFF; 364 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, 365 enable << CS35L41_BST_EN_SHIFT); 366 break; 367 default: 368 break; 369 } 370 } 371 372 static irqreturn_t cs35l41_irq(int irq, void *data) 373 { 374 struct cs35l41_private *cs35l41 = data; 375 unsigned int status[4] = { 0, 0, 0, 0 }; 376 unsigned int masks[4] = { 0, 0, 0, 0 }; 377 int ret = IRQ_NONE; 378 unsigned int i; 379 380 pm_runtime_get_sync(cs35l41->dev); 381 382 for (i = 0; i < ARRAY_SIZE(status); i++) { 383 regmap_read(cs35l41->regmap, 384 CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE), 385 &status[i]); 386 regmap_read(cs35l41->regmap, 387 CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE), 388 &masks[i]); 389 } 390 391 /* Check to see if unmasked bits are active */ 392 if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) && 393 !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) 394 goto done; 395 396 if (status[3] & CS35L41_OTP_BOOT_DONE) { 397 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4, 398 CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE); 399 } 400 401 /* 402 * The following interrupts require a 403 * protection release cycle to get the 404 * speaker out of Safe-Mode. 405 */ 406 if (status[0] & CS35L41_AMP_SHORT_ERR) { 407 dev_crit_ratelimited(cs35l41->dev, "Amp short error\n"); 408 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 409 CS35L41_AMP_SHORT_ERR); 410 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 411 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 412 CS35L41_AMP_SHORT_ERR_RLS, 413 CS35L41_AMP_SHORT_ERR_RLS); 414 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 415 CS35L41_AMP_SHORT_ERR_RLS, 0); 416 ret = IRQ_HANDLED; 417 } 418 419 if (status[0] & CS35L41_TEMP_WARN) { 420 dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n"); 421 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 422 CS35L41_TEMP_WARN); 423 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 424 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 425 CS35L41_TEMP_WARN_ERR_RLS, 426 CS35L41_TEMP_WARN_ERR_RLS); 427 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 428 CS35L41_TEMP_WARN_ERR_RLS, 0); 429 ret = IRQ_HANDLED; 430 } 431 432 if (status[0] & CS35L41_TEMP_ERR) { 433 dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n"); 434 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 435 CS35L41_TEMP_ERR); 436 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 437 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 438 CS35L41_TEMP_ERR_RLS, 439 CS35L41_TEMP_ERR_RLS); 440 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 441 CS35L41_TEMP_ERR_RLS, 0); 442 ret = IRQ_HANDLED; 443 } 444 445 if (status[0] & CS35L41_BST_OVP_ERR) { 446 dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n"); 447 cs35l41_boost_enable(cs35l41, 0); 448 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 449 CS35L41_BST_OVP_ERR); 450 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 451 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 452 CS35L41_BST_OVP_ERR_RLS, 453 CS35L41_BST_OVP_ERR_RLS); 454 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 455 CS35L41_BST_OVP_ERR_RLS, 0); 456 cs35l41_boost_enable(cs35l41, 1); 457 ret = IRQ_HANDLED; 458 } 459 460 if (status[0] & CS35L41_BST_DCM_UVP_ERR) { 461 dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n"); 462 cs35l41_boost_enable(cs35l41, 0); 463 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 464 CS35L41_BST_DCM_UVP_ERR); 465 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 466 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 467 CS35L41_BST_UVP_ERR_RLS, 468 CS35L41_BST_UVP_ERR_RLS); 469 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 470 CS35L41_BST_UVP_ERR_RLS, 0); 471 cs35l41_boost_enable(cs35l41, 1); 472 ret = IRQ_HANDLED; 473 } 474 475 if (status[0] & CS35L41_BST_SHORT_ERR) { 476 dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n"); 477 cs35l41_boost_enable(cs35l41, 0); 478 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 479 CS35L41_BST_SHORT_ERR); 480 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 481 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 482 CS35L41_BST_SHORT_ERR_RLS, 483 CS35L41_BST_SHORT_ERR_RLS); 484 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 485 CS35L41_BST_SHORT_ERR_RLS, 0); 486 cs35l41_boost_enable(cs35l41, 1); 487 ret = IRQ_HANDLED; 488 } 489 490 done: 491 pm_runtime_mark_last_busy(cs35l41->dev); 492 pm_runtime_put_autosuspend(cs35l41->dev); 493 494 return ret; 495 } 496 497 static const struct reg_sequence cs35l41_pup_patch[] = { 498 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 499 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 500 { 0x00002084, 0x002F1AA0 }, 501 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 502 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 503 }; 504 505 static const struct reg_sequence cs35l41_pdn_patch[] = { 506 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 507 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 508 { 0x00002084, 0x002F1AA3 }, 509 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 510 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 511 }; 512 513 static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w, 514 struct snd_kcontrol *kcontrol, int event) 515 { 516 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 517 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 518 unsigned int val; 519 int ret = 0; 520 521 switch (event) { 522 case SND_SOC_DAPM_PRE_PMU: 523 regmap_multi_reg_write_bypassed(cs35l41->regmap, 524 cs35l41_pup_patch, 525 ARRAY_SIZE(cs35l41_pup_patch)); 526 527 cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 1); 528 break; 529 case SND_SOC_DAPM_POST_PMD: 530 cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 0); 531 532 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 533 val, val & CS35L41_PDN_DONE_MASK, 534 1000, 100000); 535 if (ret) 536 dev_warn(cs35l41->dev, "PDN failed: %d\n", ret); 537 538 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 539 CS35L41_PDN_DONE_MASK); 540 541 regmap_multi_reg_write_bypassed(cs35l41->regmap, 542 cs35l41_pdn_patch, 543 ARRAY_SIZE(cs35l41_pdn_patch)); 544 break; 545 default: 546 dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event); 547 ret = -EINVAL; 548 } 549 550 return ret; 551 } 552 553 static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = { 554 SND_SOC_DAPM_SPK("DSP1 Preload", NULL), 555 SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0, 556 cs35l41_dsp_preload_ev, 557 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 558 SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, 559 cs35l41_dsp_audio_ev, 560 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 561 562 SND_SOC_DAPM_OUTPUT("SPK"), 563 564 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0), 565 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0), 566 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0), 567 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0), 568 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0), 569 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0), 570 571 SND_SOC_DAPM_SIGGEN("VSENSE"), 572 SND_SOC_DAPM_SIGGEN("ISENSE"), 573 SND_SOC_DAPM_SIGGEN("VP"), 574 SND_SOC_DAPM_SIGGEN("VBST"), 575 SND_SOC_DAPM_SIGGEN("TEMP"), 576 577 SND_SOC_DAPM_SUPPLY("VMON", CS35L41_PWR_CTRL2, 12, 0, NULL, 0), 578 SND_SOC_DAPM_SUPPLY("IMON", CS35L41_PWR_CTRL2, 13, 0, NULL, 0), 579 SND_SOC_DAPM_SUPPLY("VPMON", CS35L41_PWR_CTRL2, 8, 0, NULL, 0), 580 SND_SOC_DAPM_SUPPLY("VBSTMON", CS35L41_PWR_CTRL2, 9, 0, NULL, 0), 581 SND_SOC_DAPM_SUPPLY("TEMPMON", CS35L41_PWR_CTRL2, 10, 0, NULL, 0), 582 583 SND_SOC_DAPM_ADC("VMON ADC", NULL, SND_SOC_NOPM, 0, 0), 584 SND_SOC_DAPM_ADC("IMON ADC", NULL, SND_SOC_NOPM, 0, 0), 585 SND_SOC_DAPM_ADC("VPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 586 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, SND_SOC_NOPM, 0, 0), 587 SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 588 589 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0), 590 591 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0, 592 cs35l41_main_amp_event, 593 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 594 595 SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux), 596 SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux), 597 SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux), 598 SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux), 599 SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux), 600 SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux), 601 SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux), 602 SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl), 603 }; 604 605 static const struct snd_soc_dapm_route cs35l41_audio_map[] = { 606 {"DSP RX1 Source", "ASPRX1", "ASPRX1"}, 607 {"DSP RX1 Source", "ASPRX2", "ASPRX2"}, 608 {"DSP RX2 Source", "ASPRX1", "ASPRX1"}, 609 {"DSP RX2 Source", "ASPRX2", "ASPRX2"}, 610 611 {"DSP1", NULL, "DSP RX1 Source"}, 612 {"DSP1", NULL, "DSP RX2 Source"}, 613 614 {"ASP TX1 Source", "VMON", "VMON ADC"}, 615 {"ASP TX1 Source", "IMON", "IMON ADC"}, 616 {"ASP TX1 Source", "VPMON", "VPMON ADC"}, 617 {"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"}, 618 {"ASP TX1 Source", "DSPTX1", "DSP1"}, 619 {"ASP TX1 Source", "DSPTX2", "DSP1"}, 620 {"ASP TX1 Source", "ASPRX1", "ASPRX1" }, 621 {"ASP TX1 Source", "ASPRX2", "ASPRX2" }, 622 {"ASP TX2 Source", "VMON", "VMON ADC"}, 623 {"ASP TX2 Source", "IMON", "IMON ADC"}, 624 {"ASP TX2 Source", "VPMON", "VPMON ADC"}, 625 {"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"}, 626 {"ASP TX2 Source", "DSPTX1", "DSP1"}, 627 {"ASP TX2 Source", "DSPTX2", "DSP1"}, 628 {"ASP TX2 Source", "ASPRX1", "ASPRX1" }, 629 {"ASP TX2 Source", "ASPRX2", "ASPRX2" }, 630 {"ASP TX3 Source", "VMON", "VMON ADC"}, 631 {"ASP TX3 Source", "IMON", "IMON ADC"}, 632 {"ASP TX3 Source", "VPMON", "VPMON ADC"}, 633 {"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"}, 634 {"ASP TX3 Source", "DSPTX1", "DSP1"}, 635 {"ASP TX3 Source", "DSPTX2", "DSP1"}, 636 {"ASP TX3 Source", "ASPRX1", "ASPRX1" }, 637 {"ASP TX3 Source", "ASPRX2", "ASPRX2" }, 638 {"ASP TX4 Source", "VMON", "VMON ADC"}, 639 {"ASP TX4 Source", "IMON", "IMON ADC"}, 640 {"ASP TX4 Source", "VPMON", "VPMON ADC"}, 641 {"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"}, 642 {"ASP TX4 Source", "DSPTX1", "DSP1"}, 643 {"ASP TX4 Source", "DSPTX2", "DSP1"}, 644 {"ASP TX4 Source", "ASPRX1", "ASPRX1" }, 645 {"ASP TX4 Source", "ASPRX2", "ASPRX2" }, 646 {"ASPTX1", NULL, "ASP TX1 Source"}, 647 {"ASPTX2", NULL, "ASP TX2 Source"}, 648 {"ASPTX3", NULL, "ASP TX3 Source"}, 649 {"ASPTX4", NULL, "ASP TX4 Source"}, 650 {"AMP Capture", NULL, "ASPTX1"}, 651 {"AMP Capture", NULL, "ASPTX2"}, 652 {"AMP Capture", NULL, "ASPTX3"}, 653 {"AMP Capture", NULL, "ASPTX4"}, 654 655 {"DSP1", NULL, "VMON"}, 656 {"DSP1", NULL, "IMON"}, 657 {"DSP1", NULL, "VPMON"}, 658 {"DSP1", NULL, "VBSTMON"}, 659 {"DSP1", NULL, "TEMPMON"}, 660 661 {"VMON ADC", NULL, "VMON"}, 662 {"IMON ADC", NULL, "IMON"}, 663 {"VPMON ADC", NULL, "VPMON"}, 664 {"VBSTMON ADC", NULL, "VBSTMON"}, 665 {"TEMPMON ADC", NULL, "TEMPMON"}, 666 667 {"VMON ADC", NULL, "VSENSE"}, 668 {"IMON ADC", NULL, "ISENSE"}, 669 {"VPMON ADC", NULL, "VP"}, 670 {"VBSTMON ADC", NULL, "VBST"}, 671 {"TEMPMON ADC", NULL, "TEMP"}, 672 673 {"DSP1 Preload", NULL, "DSP1 Preloader"}, 674 {"DSP1", NULL, "DSP1 Preloader"}, 675 676 {"ASPRX1", NULL, "AMP Playback"}, 677 {"ASPRX2", NULL, "AMP Playback"}, 678 {"DRE", "Switch", "CLASS H"}, 679 {"Main AMP", NULL, "CLASS H"}, 680 {"Main AMP", NULL, "DRE"}, 681 {"SPK", NULL, "Main AMP"}, 682 683 {"PCM Source", "ASP", "ASPRX1"}, 684 {"PCM Source", "DSP", "DSP1"}, 685 {"CLASS H", NULL, "PCM Source"}, 686 }; 687 688 static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_n, 689 unsigned int *tx_slot, unsigned int rx_n, unsigned int *rx_slot) 690 { 691 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 692 693 return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_n, tx_slot, rx_n, rx_slot); 694 } 695 696 static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 697 { 698 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 699 unsigned int daifmt = 0; 700 701 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 702 case SND_SOC_DAIFMT_CBP_CFP: 703 daifmt |= CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK; 704 break; 705 case SND_SOC_DAIFMT_CBC_CFC: 706 break; 707 default: 708 dev_warn(cs35l41->dev, "Mixed provider/consumer mode unsupported\n"); 709 return -EINVAL; 710 } 711 712 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 713 case SND_SOC_DAIFMT_DSP_A: 714 break; 715 case SND_SOC_DAIFMT_I2S: 716 daifmt |= 2 << CS35L41_ASP_FMT_SHIFT; 717 break; 718 default: 719 dev_warn(cs35l41->dev, "Invalid or unsupported DAI format\n"); 720 return -EINVAL; 721 } 722 723 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 724 case SND_SOC_DAIFMT_NB_IF: 725 daifmt |= CS35L41_LRCLK_INV_MASK; 726 break; 727 case SND_SOC_DAIFMT_IB_NF: 728 daifmt |= CS35L41_SCLK_INV_MASK; 729 break; 730 case SND_SOC_DAIFMT_IB_IF: 731 daifmt |= CS35L41_LRCLK_INV_MASK | CS35L41_SCLK_INV_MASK; 732 break; 733 case SND_SOC_DAIFMT_NB_NF: 734 break; 735 default: 736 dev_warn(cs35l41->dev, "Invalid DAI clock INV\n"); 737 return -EINVAL; 738 } 739 740 return regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 741 CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK | 742 CS35L41_ASP_FMT_MASK | CS35L41_LRCLK_INV_MASK | 743 CS35L41_SCLK_INV_MASK, daifmt); 744 } 745 746 struct cs35l41_global_fs_config { 747 int rate; 748 int fs_cfg; 749 }; 750 751 static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = { 752 { 12000, 0x01 }, 753 { 24000, 0x02 }, 754 { 48000, 0x03 }, 755 { 96000, 0x04 }, 756 { 192000, 0x05 }, 757 { 11025, 0x09 }, 758 { 22050, 0x0A }, 759 { 44100, 0x0B }, 760 { 88200, 0x0C }, 761 { 176400, 0x0D }, 762 { 8000, 0x11 }, 763 { 16000, 0x12 }, 764 { 32000, 0x13 }, 765 }; 766 767 static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream, 768 struct snd_pcm_hw_params *params, 769 struct snd_soc_dai *dai) 770 { 771 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 772 unsigned int rate = params_rate(params); 773 u8 asp_wl; 774 int i; 775 776 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) { 777 if (rate == cs35l41_fs_rates[i].rate) 778 break; 779 } 780 781 if (i >= ARRAY_SIZE(cs35l41_fs_rates)) { 782 dev_err(cs35l41->dev, "Unsupported rate: %u\n", rate); 783 return -EINVAL; 784 } 785 786 asp_wl = params_width(params); 787 788 if (i < ARRAY_SIZE(cs35l41_fs_rates)) 789 regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL, 790 CS35L41_GLOBAL_FS_MASK, 791 cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT); 792 793 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 794 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 795 CS35L41_ASP_WIDTH_RX_MASK, 796 asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT); 797 regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL, 798 CS35L41_ASP_RX_WL_MASK, 799 asp_wl << CS35L41_ASP_RX_WL_SHIFT); 800 } else { 801 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 802 CS35L41_ASP_WIDTH_TX_MASK, 803 asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT); 804 regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL, 805 CS35L41_ASP_TX_WL_MASK, 806 asp_wl << CS35L41_ASP_TX_WL_SHIFT); 807 } 808 809 return 0; 810 } 811 812 static int cs35l41_get_clk_config(int freq) 813 { 814 int i; 815 816 for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) { 817 if (cs35l41_pll_sysclk[i].freq == freq) 818 return cs35l41_pll_sysclk[i].clk_cfg; 819 } 820 821 return -EINVAL; 822 } 823 824 static const unsigned int cs35l41_src_rates[] = { 825 8000, 12000, 11025, 16000, 22050, 24000, 32000, 826 44100, 48000, 88200, 96000, 176400, 192000 827 }; 828 829 static const struct snd_pcm_hw_constraint_list cs35l41_constraints = { 830 .count = ARRAY_SIZE(cs35l41_src_rates), 831 .list = cs35l41_src_rates, 832 }; 833 834 static int cs35l41_pcm_startup(struct snd_pcm_substream *substream, 835 struct snd_soc_dai *dai) 836 { 837 if (substream->runtime) 838 return snd_pcm_hw_constraint_list(substream->runtime, 0, 839 SNDRV_PCM_HW_PARAM_RATE, 840 &cs35l41_constraints); 841 return 0; 842 } 843 844 static int cs35l41_component_set_sysclk(struct snd_soc_component *component, 845 int clk_id, int source, 846 unsigned int freq, int dir) 847 { 848 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 849 int extclk_cfg, clksrc; 850 851 switch (clk_id) { 852 case CS35L41_CLKID_SCLK: 853 clksrc = CS35L41_PLLSRC_SCLK; 854 break; 855 case CS35L41_CLKID_LRCLK: 856 clksrc = CS35L41_PLLSRC_LRCLK; 857 break; 858 case CS35L41_CLKID_MCLK: 859 clksrc = CS35L41_PLLSRC_MCLK; 860 break; 861 default: 862 dev_err(cs35l41->dev, "Invalid CLK Config\n"); 863 return -EINVAL; 864 } 865 866 extclk_cfg = cs35l41_get_clk_config(freq); 867 868 if (extclk_cfg < 0) { 869 dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n", 870 extclk_cfg, freq); 871 return -EINVAL; 872 } 873 874 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 875 CS35L41_PLL_OPENLOOP_MASK, 876 1 << CS35L41_PLL_OPENLOOP_SHIFT); 877 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 878 CS35L41_REFCLK_FREQ_MASK, 879 extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT); 880 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 881 CS35L41_PLL_CLK_EN_MASK, 882 0 << CS35L41_PLL_CLK_EN_SHIFT); 883 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 884 CS35L41_PLL_CLK_SEL_MASK, clksrc); 885 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 886 CS35L41_PLL_OPENLOOP_MASK, 887 0 << CS35L41_PLL_OPENLOOP_SHIFT); 888 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 889 CS35L41_PLL_CLK_EN_MASK, 890 1 << CS35L41_PLL_CLK_EN_SHIFT); 891 892 return 0; 893 } 894 895 static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai, 896 int clk_id, unsigned int freq, int dir) 897 { 898 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 899 unsigned int fs1_val; 900 unsigned int fs2_val; 901 unsigned int val; 902 int fsindex; 903 904 fsindex = cs35l41_get_fs_mon_config_index(freq); 905 if (fsindex < 0) { 906 dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq); 907 return -EINVAL; 908 } 909 910 dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq); 911 912 if (freq <= 6144000) { 913 /* Use the lookup table */ 914 fs1_val = cs35l41_fs_mon[fsindex].fs1; 915 fs2_val = cs35l41_fs_mon[fsindex].fs2; 916 } else { 917 /* Use hard-coded values */ 918 fs1_val = 0x10; 919 fs2_val = 0x24; 920 } 921 922 val = fs1_val; 923 val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK; 924 regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val); 925 926 return 0; 927 } 928 929 static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) 930 { 931 struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg; 932 int ret; 933 934 if (!hw_cfg->valid) 935 return -EINVAL; 936 937 if (hw_cfg->bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH) 938 return -EINVAL; 939 940 /* Required */ 941 ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg); 942 if (ret) 943 return ret; 944 945 /* Optional */ 946 if (hw_cfg->dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && hw_cfg->dout_hiz >= 0) 947 regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, CS35L41_ASP_DOUT_HIZ_MASK, 948 hw_cfg->dout_hiz); 949 950 return 0; 951 } 952 953 static const struct snd_soc_dapm_route cs35l41_ext_bst_routes[] = { 954 {"Main AMP", NULL, "VSPK"}, 955 }; 956 957 static const struct snd_soc_dapm_widget cs35l41_ext_bst_widget[] = { 958 SND_SOC_DAPM_SUPPLY("VSPK", CS35L41_GPIO1_CTRL1, CS35L41_GPIO_LVL_SHIFT, 0, NULL, 0), 959 }; 960 961 static int cs35l41_component_probe(struct snd_soc_component *component) 962 { 963 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 964 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 965 int ret; 966 967 if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) { 968 ret = snd_soc_dapm_new_controls(dapm, cs35l41_ext_bst_widget, 969 ARRAY_SIZE(cs35l41_ext_bst_widget)); 970 if (ret) 971 return ret; 972 973 ret = snd_soc_dapm_add_routes(dapm, cs35l41_ext_bst_routes, 974 ARRAY_SIZE(cs35l41_ext_bst_routes)); 975 if (ret) 976 return ret; 977 } 978 979 return wm_adsp2_component_probe(&cs35l41->dsp, component); 980 } 981 982 static void cs35l41_component_remove(struct snd_soc_component *component) 983 { 984 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 985 986 wm_adsp2_component_remove(&cs35l41->dsp, component); 987 } 988 989 static const struct snd_soc_dai_ops cs35l41_ops = { 990 .startup = cs35l41_pcm_startup, 991 .set_fmt = cs35l41_set_dai_fmt, 992 .hw_params = cs35l41_pcm_hw_params, 993 .set_sysclk = cs35l41_dai_set_sysclk, 994 .set_channel_map = cs35l41_set_channel_map, 995 }; 996 997 static struct snd_soc_dai_driver cs35l41_dai[] = { 998 { 999 .name = "cs35l41-pcm", 1000 .id = 0, 1001 .playback = { 1002 .stream_name = "AMP Playback", 1003 .channels_min = 1, 1004 .channels_max = 2, 1005 .rates = SNDRV_PCM_RATE_KNOT, 1006 .formats = CS35L41_RX_FORMATS, 1007 }, 1008 .capture = { 1009 .stream_name = "AMP Capture", 1010 .channels_min = 1, 1011 .channels_max = 4, 1012 .rates = SNDRV_PCM_RATE_KNOT, 1013 .formats = CS35L41_TX_FORMATS, 1014 }, 1015 .ops = &cs35l41_ops, 1016 .symmetric_rate = 1, 1017 }, 1018 }; 1019 1020 static const struct snd_soc_component_driver soc_component_dev_cs35l41 = { 1021 .name = "cs35l41-codec", 1022 .probe = cs35l41_component_probe, 1023 .remove = cs35l41_component_remove, 1024 1025 .dapm_widgets = cs35l41_dapm_widgets, 1026 .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets), 1027 .dapm_routes = cs35l41_audio_map, 1028 .num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map), 1029 1030 .controls = cs35l41_aud_controls, 1031 .num_controls = ARRAY_SIZE(cs35l41_aud_controls), 1032 .set_sysclk = cs35l41_component_set_sysclk, 1033 1034 .endianness = 1, 1035 }; 1036 1037 static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cfg) 1038 { 1039 struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1; 1040 struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2; 1041 unsigned int val; 1042 int ret; 1043 1044 ret = device_property_read_u32(dev, "cirrus,boost-type", &val); 1045 if (ret >= 0) 1046 hw_cfg->bst_type = val; 1047 1048 ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val); 1049 if (ret >= 0) 1050 hw_cfg->bst_ipk = val; 1051 else 1052 hw_cfg->bst_ipk = -1; 1053 1054 ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val); 1055 if (ret >= 0) 1056 hw_cfg->bst_ind = val; 1057 else 1058 hw_cfg->bst_ind = -1; 1059 1060 ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val); 1061 if (ret >= 0) 1062 hw_cfg->bst_cap = val; 1063 else 1064 hw_cfg->bst_cap = -1; 1065 1066 ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val); 1067 if (ret >= 0) 1068 hw_cfg->dout_hiz = val; 1069 else 1070 hw_cfg->dout_hiz = -1; 1071 1072 /* GPIO1 Pin Config */ 1073 gpio1->pol_inv = device_property_read_bool(dev, "cirrus,gpio1-polarity-invert"); 1074 gpio1->out_en = device_property_read_bool(dev, "cirrus,gpio1-output-enable"); 1075 ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", &val); 1076 if (ret >= 0) { 1077 gpio1->func = val; 1078 gpio1->valid = true; 1079 } 1080 1081 /* GPIO2 Pin Config */ 1082 gpio2->pol_inv = device_property_read_bool(dev, "cirrus,gpio2-polarity-invert"); 1083 gpio2->out_en = device_property_read_bool(dev, "cirrus,gpio2-output-enable"); 1084 ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", &val); 1085 if (ret >= 0) { 1086 gpio2->func = val; 1087 gpio2->valid = true; 1088 } 1089 1090 hw_cfg->valid = true; 1091 1092 return 0; 1093 } 1094 1095 static int cs35l41_dsp_init(struct cs35l41_private *cs35l41) 1096 { 1097 struct wm_adsp *dsp; 1098 int ret; 1099 1100 dsp = &cs35l41->dsp; 1101 dsp->part = "cs35l41"; 1102 dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */ 1103 dsp->toggle_preload = true; 1104 1105 cs35l41_configure_cs_dsp(cs35l41->dev, cs35l41->regmap, &dsp->cs_dsp); 1106 1107 ret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap); 1108 if (ret < 0) 1109 return ret; 1110 1111 ret = wm_halo_init(dsp); 1112 if (ret) { 1113 dev_err(cs35l41->dev, "wm_halo_init failed: %d\n", ret); 1114 return ret; 1115 } 1116 1117 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC, 1118 CS35L41_INPUT_SRC_VPMON); 1119 if (ret < 0) { 1120 dev_err(cs35l41->dev, "Write INPUT_SRC_VPMON failed: %d\n", ret); 1121 goto err_dsp; 1122 } 1123 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC, 1124 CS35L41_INPUT_SRC_CLASSH); 1125 if (ret < 0) { 1126 dev_err(cs35l41->dev, "Write INPUT_SRC_CLASSH failed: %d\n", ret); 1127 goto err_dsp; 1128 } 1129 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC, 1130 CS35L41_INPUT_SRC_TEMPMON); 1131 if (ret < 0) { 1132 dev_err(cs35l41->dev, "Write INPUT_SRC_TEMPMON failed: %d\n", ret); 1133 goto err_dsp; 1134 } 1135 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC, 1136 CS35L41_INPUT_SRC_RSVD); 1137 if (ret < 0) { 1138 dev_err(cs35l41->dev, "Write INPUT_SRC_RSVD failed: %d\n", ret); 1139 goto err_dsp; 1140 } 1141 1142 return 0; 1143 1144 err_dsp: 1145 wm_adsp2_remove(dsp); 1146 1147 return ret; 1148 } 1149 1150 static int cs35l41_acpi_get_name(struct cs35l41_private *cs35l41) 1151 { 1152 acpi_handle handle = ACPI_HANDLE(cs35l41->dev); 1153 const char *sub; 1154 1155 /* If there is no ACPI_HANDLE, there is no ACPI for this system, return 0 */ 1156 if (!handle) 1157 return 0; 1158 1159 sub = acpi_get_subsystem_id(handle); 1160 if (IS_ERR(sub)) { 1161 /* If bad ACPI, return 0 and fallback to legacy firmware path, otherwise fail */ 1162 if (PTR_ERR(sub) == -ENODATA) 1163 return 0; 1164 else 1165 return PTR_ERR(sub); 1166 } 1167 1168 cs35l41->dsp.system_name = sub; 1169 dev_dbg(cs35l41->dev, "Subsystem ID: %s\n", cs35l41->dsp.system_name); 1170 1171 return 0; 1172 } 1173 1174 int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg *hw_cfg) 1175 { 1176 u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match; 1177 int irq_pol = 0; 1178 int ret; 1179 1180 if (hw_cfg) { 1181 cs35l41->hw_cfg = *hw_cfg; 1182 } else { 1183 ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->hw_cfg); 1184 if (ret != 0) 1185 return ret; 1186 } 1187 1188 for (i = 0; i < CS35L41_NUM_SUPPLIES; i++) 1189 cs35l41->supplies[i].supply = cs35l41_supplies[i]; 1190 1191 ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES, 1192 cs35l41->supplies); 1193 if (ret != 0) { 1194 dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", ret); 1195 return ret; 1196 } 1197 1198 ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1199 if (ret != 0) { 1200 dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", ret); 1201 return ret; 1202 } 1203 1204 /* returning NULL can be an option if in stereo mode */ 1205 cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset", 1206 GPIOD_OUT_LOW); 1207 if (IS_ERR(cs35l41->reset_gpio)) { 1208 ret = PTR_ERR(cs35l41->reset_gpio); 1209 cs35l41->reset_gpio = NULL; 1210 if (ret == -EBUSY) { 1211 dev_info(cs35l41->dev, 1212 "Reset line busy, assuming shared reset\n"); 1213 } else { 1214 dev_err(cs35l41->dev, 1215 "Failed to get reset GPIO: %d\n", ret); 1216 goto err; 1217 } 1218 } 1219 if (cs35l41->reset_gpio) { 1220 /* satisfy minimum reset pulse width spec */ 1221 usleep_range(2000, 2100); 1222 gpiod_set_value_cansleep(cs35l41->reset_gpio, 1); 1223 } 1224 1225 usleep_range(2000, 2100); 1226 1227 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4, 1228 int_status, int_status & CS35L41_OTP_BOOT_DONE, 1229 1000, 100000); 1230 if (ret) { 1231 dev_err(cs35l41->dev, 1232 "Failed waiting for OTP_BOOT_DONE: %d\n", ret); 1233 goto err; 1234 } 1235 1236 regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status); 1237 if (int_status & CS35L41_OTP_BOOT_ERR) { 1238 dev_err(cs35l41->dev, "OTP Boot error\n"); 1239 ret = -EINVAL; 1240 goto err; 1241 } 1242 1243 ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id); 1244 if (ret < 0) { 1245 dev_err(cs35l41->dev, "Get Device ID failed: %d\n", ret); 1246 goto err; 1247 } 1248 1249 ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid); 1250 if (ret < 0) { 1251 dev_err(cs35l41->dev, "Get Revision ID failed: %d\n", ret); 1252 goto err; 1253 } 1254 1255 mtl_revid = reg_revid & CS35L41_MTLREVID_MASK; 1256 1257 /* CS35L41 will have even MTLREVID 1258 * CS35L41R will have odd MTLREVID 1259 */ 1260 chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID; 1261 if (regid != chipid_match) { 1262 dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n", 1263 regid, chipid_match); 1264 ret = -ENODEV; 1265 goto err; 1266 } 1267 1268 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap); 1269 1270 ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid); 1271 if (ret) 1272 goto err; 1273 1274 ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap); 1275 if (ret < 0) { 1276 dev_err(cs35l41->dev, "OTP Unpack failed: %d\n", ret); 1277 goto err; 1278 } 1279 1280 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); 1281 1282 irq_pol = cs35l41_gpio_config(cs35l41->regmap, &cs35l41->hw_cfg); 1283 1284 /* Set interrupt masks for critical errors */ 1285 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 1286 CS35L41_INT1_MASK_DEFAULT); 1287 1288 ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq, 1289 IRQF_ONESHOT | IRQF_SHARED | irq_pol, 1290 "cs35l41", cs35l41); 1291 if (ret != 0) { 1292 dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret); 1293 goto err; 1294 } 1295 1296 ret = cs35l41_set_pdata(cs35l41); 1297 if (ret < 0) { 1298 dev_err(cs35l41->dev, "Set pdata failed: %d\n", ret); 1299 goto err; 1300 } 1301 1302 ret = cs35l41_acpi_get_name(cs35l41); 1303 if (ret < 0) 1304 goto err; 1305 1306 ret = cs35l41_dsp_init(cs35l41); 1307 if (ret < 0) 1308 goto err; 1309 1310 pm_runtime_set_autosuspend_delay(cs35l41->dev, 3000); 1311 pm_runtime_use_autosuspend(cs35l41->dev); 1312 pm_runtime_mark_last_busy(cs35l41->dev); 1313 pm_runtime_set_active(cs35l41->dev); 1314 pm_runtime_get_noresume(cs35l41->dev); 1315 pm_runtime_enable(cs35l41->dev); 1316 1317 ret = devm_snd_soc_register_component(cs35l41->dev, 1318 &soc_component_dev_cs35l41, 1319 cs35l41_dai, ARRAY_SIZE(cs35l41_dai)); 1320 if (ret < 0) { 1321 dev_err(cs35l41->dev, "Register codec failed: %d\n", ret); 1322 goto err_pm; 1323 } 1324 1325 pm_runtime_put_autosuspend(cs35l41->dev); 1326 1327 dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n", 1328 regid, reg_revid); 1329 1330 return 0; 1331 1332 err_pm: 1333 pm_runtime_disable(cs35l41->dev); 1334 pm_runtime_put_noidle(cs35l41->dev); 1335 1336 wm_adsp2_remove(&cs35l41->dsp); 1337 err: 1338 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1339 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1340 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1341 1342 return ret; 1343 } 1344 EXPORT_SYMBOL_GPL(cs35l41_probe); 1345 1346 void cs35l41_remove(struct cs35l41_private *cs35l41) 1347 { 1348 pm_runtime_get_sync(cs35l41->dev); 1349 pm_runtime_disable(cs35l41->dev); 1350 1351 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF); 1352 kfree(cs35l41->dsp.system_name); 1353 wm_adsp2_remove(&cs35l41->dsp); 1354 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1355 1356 pm_runtime_put_noidle(cs35l41->dev); 1357 1358 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1359 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1360 } 1361 EXPORT_SYMBOL_GPL(cs35l41_remove); 1362 1363 static int __maybe_unused cs35l41_runtime_suspend(struct device *dev) 1364 { 1365 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1366 1367 dev_dbg(cs35l41->dev, "Runtime suspend\n"); 1368 1369 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running) 1370 return 0; 1371 1372 cs35l41_enter_hibernate(dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1373 1374 regcache_cache_only(cs35l41->regmap, true); 1375 regcache_mark_dirty(cs35l41->regmap); 1376 1377 return 0; 1378 } 1379 1380 static int __maybe_unused cs35l41_runtime_resume(struct device *dev) 1381 { 1382 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1383 int ret; 1384 1385 dev_dbg(cs35l41->dev, "Runtime resume\n"); 1386 1387 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running) 1388 return 0; 1389 1390 regcache_cache_only(cs35l41->regmap, false); 1391 1392 ret = cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap); 1393 if (ret) 1394 return ret; 1395 1396 /* Test key needs to be unlocked to allow the OTP settings to re-apply */ 1397 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap); 1398 ret = regcache_sync(cs35l41->regmap); 1399 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); 1400 if (ret) { 1401 dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret); 1402 return ret; 1403 } 1404 cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, &cs35l41->hw_cfg); 1405 1406 return 0; 1407 } 1408 1409 static int __maybe_unused cs35l41_sys_suspend(struct device *dev) 1410 { 1411 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1412 1413 dev_dbg(cs35l41->dev, "System suspend, disabling IRQ\n"); 1414 disable_irq(cs35l41->irq); 1415 1416 return 0; 1417 } 1418 1419 static int __maybe_unused cs35l41_sys_suspend_noirq(struct device *dev) 1420 { 1421 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1422 1423 dev_dbg(cs35l41->dev, "Late system suspend, reenabling IRQ\n"); 1424 enable_irq(cs35l41->irq); 1425 1426 return 0; 1427 } 1428 1429 static int __maybe_unused cs35l41_sys_resume_noirq(struct device *dev) 1430 { 1431 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1432 1433 dev_dbg(cs35l41->dev, "Early system resume, disabling IRQ\n"); 1434 disable_irq(cs35l41->irq); 1435 1436 return 0; 1437 } 1438 1439 static int __maybe_unused cs35l41_sys_resume(struct device *dev) 1440 { 1441 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1442 1443 dev_dbg(cs35l41->dev, "System resume, reenabling IRQ\n"); 1444 enable_irq(cs35l41->irq); 1445 1446 return 0; 1447 } 1448 1449 const struct dev_pm_ops cs35l41_pm_ops = { 1450 SET_RUNTIME_PM_OPS(cs35l41_runtime_suspend, cs35l41_runtime_resume, NULL) 1451 1452 SET_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend, cs35l41_sys_resume) 1453 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend_noirq, cs35l41_sys_resume_noirq) 1454 }; 1455 EXPORT_SYMBOL_GPL(cs35l41_pm_ops); 1456 1457 MODULE_DESCRIPTION("ASoC CS35L41 driver"); 1458 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>"); 1459 MODULE_LICENSE("GPL"); 1460