1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // cs35l41.c -- CS35l41 ALSA SoC audio driver 4 // 5 // Copyright 2017-2021 Cirrus Logic, Inc. 6 // 7 // Author: David Rhodes <david.rhodes@cirrus.com> 8 9 #include <linux/acpi.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/of_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/property.h> 19 #include <sound/initval.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/soc-dapm.h> 24 #include <sound/tlv.h> 25 26 #include "cs35l41.h" 27 28 static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = { 29 "VA", 30 "VP", 31 }; 32 33 struct cs35l41_pll_sysclk_config { 34 int freq; 35 int clk_cfg; 36 }; 37 38 static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = { 39 { 32768, 0x00 }, 40 { 8000, 0x01 }, 41 { 11025, 0x02 }, 42 { 12000, 0x03 }, 43 { 16000, 0x04 }, 44 { 22050, 0x05 }, 45 { 24000, 0x06 }, 46 { 32000, 0x07 }, 47 { 44100, 0x08 }, 48 { 48000, 0x09 }, 49 { 88200, 0x0A }, 50 { 96000, 0x0B }, 51 { 128000, 0x0C }, 52 { 176400, 0x0D }, 53 { 192000, 0x0E }, 54 { 256000, 0x0F }, 55 { 352800, 0x10 }, 56 { 384000, 0x11 }, 57 { 512000, 0x12 }, 58 { 705600, 0x13 }, 59 { 750000, 0x14 }, 60 { 768000, 0x15 }, 61 { 1000000, 0x16 }, 62 { 1024000, 0x17 }, 63 { 1200000, 0x18 }, 64 { 1411200, 0x19 }, 65 { 1500000, 0x1A }, 66 { 1536000, 0x1B }, 67 { 2000000, 0x1C }, 68 { 2048000, 0x1D }, 69 { 2400000, 0x1E }, 70 { 2822400, 0x1F }, 71 { 3000000, 0x20 }, 72 { 3072000, 0x21 }, 73 { 3200000, 0x22 }, 74 { 4000000, 0x23 }, 75 { 4096000, 0x24 }, 76 { 4800000, 0x25 }, 77 { 5644800, 0x26 }, 78 { 6000000, 0x27 }, 79 { 6144000, 0x28 }, 80 { 6250000, 0x29 }, 81 { 6400000, 0x2A }, 82 { 6500000, 0x2B }, 83 { 6750000, 0x2C }, 84 { 7526400, 0x2D }, 85 { 8000000, 0x2E }, 86 { 8192000, 0x2F }, 87 { 9600000, 0x30 }, 88 { 11289600, 0x31 }, 89 { 12000000, 0x32 }, 90 { 12288000, 0x33 }, 91 { 12500000, 0x34 }, 92 { 12800000, 0x35 }, 93 { 13000000, 0x36 }, 94 { 13500000, 0x37 }, 95 { 19200000, 0x38 }, 96 { 22579200, 0x39 }, 97 { 24000000, 0x3A }, 98 { 24576000, 0x3B }, 99 { 25000000, 0x3C }, 100 { 25600000, 0x3D }, 101 { 26000000, 0x3E }, 102 { 27000000, 0x3F }, 103 }; 104 105 struct cs35l41_fs_mon_config { 106 int freq; 107 unsigned int fs1; 108 unsigned int fs2; 109 }; 110 111 static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = { 112 { 32768, 2254, 3754 }, 113 { 8000, 9220, 15364 }, 114 { 11025, 6148, 10244 }, 115 { 12000, 6148, 10244 }, 116 { 16000, 4612, 7684 }, 117 { 22050, 3076, 5124 }, 118 { 24000, 3076, 5124 }, 119 { 32000, 2308, 3844 }, 120 { 44100, 1540, 2564 }, 121 { 48000, 1540, 2564 }, 122 { 88200, 772, 1284 }, 123 { 96000, 772, 1284 }, 124 { 128000, 580, 964 }, 125 { 176400, 388, 644 }, 126 { 192000, 388, 644 }, 127 { 256000, 292, 484 }, 128 { 352800, 196, 324 }, 129 { 384000, 196, 324 }, 130 { 512000, 148, 244 }, 131 { 705600, 100, 164 }, 132 { 750000, 100, 164 }, 133 { 768000, 100, 164 }, 134 { 1000000, 76, 124 }, 135 { 1024000, 76, 124 }, 136 { 1200000, 64, 104 }, 137 { 1411200, 52, 84 }, 138 { 1500000, 52, 84 }, 139 { 1536000, 52, 84 }, 140 { 2000000, 40, 64 }, 141 { 2048000, 40, 64 }, 142 { 2400000, 34, 54 }, 143 { 2822400, 28, 44 }, 144 { 3000000, 28, 44 }, 145 { 3072000, 28, 44 }, 146 { 3200000, 27, 42 }, 147 { 4000000, 22, 34 }, 148 { 4096000, 22, 34 }, 149 { 4800000, 19, 29 }, 150 { 5644800, 16, 24 }, 151 { 6000000, 16, 24 }, 152 { 6144000, 16, 24 }, 153 { 12288000, 0, 0 }, 154 }; 155 156 static int cs35l41_get_fs_mon_config_index(int freq) 157 { 158 int i; 159 160 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) { 161 if (cs35l41_fs_mon[i].freq == freq) 162 return i; 163 } 164 165 return -EINVAL; 166 } 167 168 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv, 169 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 170 1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200)); 171 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1); 172 173 static const struct snd_kcontrol_new dre_ctrl = 174 SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0); 175 176 static const char * const cs35l41_pcm_sftramp_text[] = { 177 "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms" 178 }; 179 180 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, 181 CS35L41_AMP_DIG_VOL_CTRL, 0, 182 cs35l41_pcm_sftramp_text); 183 184 static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w, 185 struct snd_kcontrol *kcontrol, int event) 186 { 187 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 188 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 189 int ret; 190 191 switch (event) { 192 case SND_SOC_DAPM_PRE_PMU: 193 if (cs35l41->dsp.cs_dsp.booted) 194 return 0; 195 196 return wm_adsp_early_event(w, kcontrol, event); 197 case SND_SOC_DAPM_PRE_PMD: 198 if (cs35l41->dsp.preloaded) 199 return 0; 200 201 if (cs35l41->dsp.cs_dsp.running) { 202 ret = wm_adsp_event(w, kcontrol, event); 203 if (ret) 204 return ret; 205 } 206 207 return wm_adsp_early_event(w, kcontrol, event); 208 default: 209 return 0; 210 } 211 } 212 213 static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w, 214 struct snd_kcontrol *kcontrol, int event) 215 { 216 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 217 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 218 unsigned int fw_status; 219 int ret; 220 221 switch (event) { 222 case SND_SOC_DAPM_POST_PMU: 223 if (!cs35l41->dsp.cs_dsp.running) 224 return wm_adsp_event(w, kcontrol, event); 225 226 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &fw_status); 227 if (ret < 0) { 228 dev_err(cs35l41->dev, 229 "Failed to read firmware status: %d\n", ret); 230 return ret; 231 } 232 233 switch (fw_status) { 234 case CSPL_MBOX_STS_RUNNING: 235 case CSPL_MBOX_STS_PAUSED: 236 break; 237 default: 238 dev_err(cs35l41->dev, "Firmware status is invalid: %u\n", 239 fw_status); 240 return -EINVAL; 241 } 242 243 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap, 244 CSPL_MBOX_CMD_RESUME); 245 case SND_SOC_DAPM_PRE_PMD: 246 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap, 247 CSPL_MBOX_CMD_PAUSE); 248 default: 249 return 0; 250 } 251 } 252 253 static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"}; 254 static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32}; 255 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum, 256 CS35L41_DAC_PCM1_SRC, 257 0, CS35L41_ASP_SOURCE_MASK, 258 cs35l41_pcm_source_texts, 259 cs35l41_pcm_source_values); 260 261 static const struct snd_kcontrol_new pcm_source_mux = 262 SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum); 263 264 static const char * const cs35l41_tx_input_texts[] = { 265 "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON", 266 "VPMON", "VBSTMON", "DSPTX1", "DSPTX2" 267 }; 268 269 static const unsigned int cs35l41_tx_input_values[] = { 270 0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2, 271 CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON, 272 CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2 273 }; 274 275 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum, 276 CS35L41_ASP_TX1_SRC, 277 0, CS35L41_ASP_SOURCE_MASK, 278 cs35l41_tx_input_texts, 279 cs35l41_tx_input_values); 280 281 static const struct snd_kcontrol_new asp_tx1_mux = 282 SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum); 283 284 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum, 285 CS35L41_ASP_TX2_SRC, 286 0, CS35L41_ASP_SOURCE_MASK, 287 cs35l41_tx_input_texts, 288 cs35l41_tx_input_values); 289 290 static const struct snd_kcontrol_new asp_tx2_mux = 291 SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum); 292 293 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum, 294 CS35L41_ASP_TX3_SRC, 295 0, CS35L41_ASP_SOURCE_MASK, 296 cs35l41_tx_input_texts, 297 cs35l41_tx_input_values); 298 299 static const struct snd_kcontrol_new asp_tx3_mux = 300 SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum); 301 302 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum, 303 CS35L41_ASP_TX4_SRC, 304 0, CS35L41_ASP_SOURCE_MASK, 305 cs35l41_tx_input_texts, 306 cs35l41_tx_input_values); 307 308 static const struct snd_kcontrol_new asp_tx4_mux = 309 SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum); 310 311 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum, 312 CS35L41_DSP1_RX1_SRC, 313 0, CS35L41_ASP_SOURCE_MASK, 314 cs35l41_tx_input_texts, 315 cs35l41_tx_input_values); 316 317 static const struct snd_kcontrol_new dsp_rx1_mux = 318 SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum); 319 320 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum, 321 CS35L41_DSP1_RX2_SRC, 322 0, CS35L41_ASP_SOURCE_MASK, 323 cs35l41_tx_input_texts, 324 cs35l41_tx_input_values); 325 326 static const struct snd_kcontrol_new dsp_rx2_mux = 327 SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum); 328 329 static const struct snd_kcontrol_new cs35l41_aud_controls[] = { 330 SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL, 331 3, 0x4CF, 0x391, dig_vol_tlv), 332 SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0, 333 amp_gain_tlv), 334 SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp), 335 SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0), 336 SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0), 337 SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0), 338 SOC_SINGLE("Aux Noise Gate CH1 Switch", 339 CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0), 340 SOC_SINGLE("Aux Noise Gate CH1 Entry Delay", 341 CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0), 342 SOC_SINGLE("Aux Noise Gate CH1 Threshold", 343 CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0), 344 SOC_SINGLE("Aux Noise Gate CH2 Entry Delay", 345 CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0), 346 SOC_SINGLE("Aux Noise Gate CH2 Switch", 347 CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0), 348 SOC_SINGLE("Aux Noise Gate CH2 Threshold", 349 CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0), 350 SOC_SINGLE("SCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0), 351 SOC_SINGLE("LRCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0), 352 SOC_SINGLE("Invert Class D Switch", CS35L41_AMP_DIG_VOL_CTRL, 353 CS35L41_AMP_INV_PCM_SHIFT, 1, 0), 354 SOC_SINGLE("Amp Gain ZC Switch", CS35L41_AMP_GAIN_CTRL, 355 CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0), 356 WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), 357 WM_ADSP_FW_CONTROL("DSP1", 0), 358 }; 359 360 static void cs35l41_boost_enable(struct cs35l41_private *cs35l41, unsigned int enable) 361 { 362 switch (cs35l41->hw_cfg.bst_type) { 363 case CS35L41_INT_BOOST: 364 case CS35L41_SHD_BOOST_ACTV: 365 enable = enable ? CS35L41_BST_EN_DEFAULT : CS35L41_BST_DIS_FET_OFF; 366 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, 367 enable << CS35L41_BST_EN_SHIFT); 368 break; 369 default: 370 break; 371 } 372 } 373 374 375 static void cs35l41_error_release(struct cs35l41_private *cs35l41, unsigned int irq_err_bit, 376 unsigned int rel_err_bit) 377 { 378 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, irq_err_bit); 379 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 380 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, rel_err_bit); 381 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, 0); 382 } 383 384 static irqreturn_t cs35l41_irq(int irq, void *data) 385 { 386 struct cs35l41_private *cs35l41 = data; 387 unsigned int status[4] = { 0, 0, 0, 0 }; 388 unsigned int masks[4] = { 0, 0, 0, 0 }; 389 int ret = IRQ_NONE; 390 unsigned int i; 391 392 pm_runtime_get_sync(cs35l41->dev); 393 394 for (i = 0; i < ARRAY_SIZE(status); i++) { 395 regmap_read(cs35l41->regmap, 396 CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE), 397 &status[i]); 398 regmap_read(cs35l41->regmap, 399 CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE), 400 &masks[i]); 401 } 402 403 /* Check to see if unmasked bits are active */ 404 if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) && 405 !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) 406 goto done; 407 408 if (status[3] & CS35L41_OTP_BOOT_DONE) { 409 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4, 410 CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE); 411 } 412 413 /* 414 * The following interrupts require a 415 * protection release cycle to get the 416 * speaker out of Safe-Mode. 417 */ 418 if (status[0] & CS35L41_AMP_SHORT_ERR) { 419 dev_crit_ratelimited(cs35l41->dev, "Amp short error\n"); 420 cs35l41_error_release(cs35l41, CS35L41_AMP_SHORT_ERR, CS35L41_AMP_SHORT_ERR_RLS); 421 ret = IRQ_HANDLED; 422 } 423 424 if (status[0] & CS35L41_TEMP_WARN) { 425 dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n"); 426 cs35l41_error_release(cs35l41, CS35L41_TEMP_WARN, CS35L41_TEMP_WARN_ERR_RLS); 427 ret = IRQ_HANDLED; 428 } 429 430 if (status[0] & CS35L41_TEMP_ERR) { 431 dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n"); 432 cs35l41_error_release(cs35l41, CS35L41_TEMP_ERR, CS35L41_TEMP_ERR_RLS); 433 ret = IRQ_HANDLED; 434 } 435 436 if (status[0] & CS35L41_BST_OVP_ERR) { 437 dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n"); 438 cs35l41_boost_enable(cs35l41, 0); 439 cs35l41_error_release(cs35l41, CS35L41_BST_OVP_ERR, CS35L41_BST_OVP_ERR_RLS); 440 cs35l41_boost_enable(cs35l41, 1); 441 ret = IRQ_HANDLED; 442 } 443 444 if (status[0] & CS35L41_BST_DCM_UVP_ERR) { 445 dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n"); 446 cs35l41_boost_enable(cs35l41, 0); 447 cs35l41_error_release(cs35l41, CS35L41_BST_DCM_UVP_ERR, CS35L41_BST_UVP_ERR_RLS); 448 cs35l41_boost_enable(cs35l41, 1); 449 ret = IRQ_HANDLED; 450 } 451 452 if (status[0] & CS35L41_BST_SHORT_ERR) { 453 dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n"); 454 cs35l41_boost_enable(cs35l41, 0); 455 cs35l41_error_release(cs35l41, CS35L41_BST_SHORT_ERR, CS35L41_BST_SHORT_ERR_RLS); 456 cs35l41_boost_enable(cs35l41, 1); 457 ret = IRQ_HANDLED; 458 } 459 460 if (status[2] & CS35L41_PLL_LOCK) { 461 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS3, CS35L41_PLL_LOCK); 462 complete(&cs35l41->pll_lock); 463 ret = IRQ_HANDLED; 464 } 465 466 done: 467 pm_runtime_mark_last_busy(cs35l41->dev); 468 pm_runtime_put_autosuspend(cs35l41->dev); 469 470 return ret; 471 } 472 473 static const struct reg_sequence cs35l41_pup_patch[] = { 474 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 475 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 476 { 0x00002084, 0x002F1AA0 }, 477 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 478 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 479 }; 480 481 static const struct reg_sequence cs35l41_pdn_patch[] = { 482 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 483 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 484 { 0x00002084, 0x002F1AA3 }, 485 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 486 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 487 }; 488 489 static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w, 490 struct snd_kcontrol *kcontrol, int event) 491 { 492 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 493 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 494 unsigned int val; 495 int ret = 0; 496 497 switch (event) { 498 case SND_SOC_DAPM_PRE_PMU: 499 regmap_multi_reg_write_bypassed(cs35l41->regmap, 500 cs35l41_pup_patch, 501 ARRAY_SIZE(cs35l41_pup_patch)); 502 503 cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 1, 504 &cs35l41->pll_lock); 505 break; 506 case SND_SOC_DAPM_POST_PMD: 507 cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 0, 508 &cs35l41->pll_lock); 509 510 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 511 val, val & CS35L41_PDN_DONE_MASK, 512 1000, 100000); 513 if (ret) 514 dev_warn(cs35l41->dev, "PDN failed: %d\n", ret); 515 516 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 517 CS35L41_PDN_DONE_MASK); 518 519 regmap_multi_reg_write_bypassed(cs35l41->regmap, 520 cs35l41_pdn_patch, 521 ARRAY_SIZE(cs35l41_pdn_patch)); 522 break; 523 default: 524 dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event); 525 ret = -EINVAL; 526 } 527 528 return ret; 529 } 530 531 static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = { 532 SND_SOC_DAPM_SPK("DSP1 Preload", NULL), 533 SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0, 534 cs35l41_dsp_preload_ev, 535 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 536 SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, 537 cs35l41_dsp_audio_ev, 538 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 539 540 SND_SOC_DAPM_OUTPUT("SPK"), 541 542 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0), 543 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0), 544 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0), 545 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0), 546 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0), 547 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0), 548 549 SND_SOC_DAPM_SIGGEN("VSENSE"), 550 SND_SOC_DAPM_SIGGEN("ISENSE"), 551 SND_SOC_DAPM_SIGGEN("VP"), 552 SND_SOC_DAPM_SIGGEN("VBST"), 553 SND_SOC_DAPM_SIGGEN("TEMP"), 554 555 SND_SOC_DAPM_SUPPLY("VMON", CS35L41_PWR_CTRL2, 12, 0, NULL, 0), 556 SND_SOC_DAPM_SUPPLY("IMON", CS35L41_PWR_CTRL2, 13, 0, NULL, 0), 557 SND_SOC_DAPM_SUPPLY("VPMON", CS35L41_PWR_CTRL2, 8, 0, NULL, 0), 558 SND_SOC_DAPM_SUPPLY("VBSTMON", CS35L41_PWR_CTRL2, 9, 0, NULL, 0), 559 SND_SOC_DAPM_SUPPLY("TEMPMON", CS35L41_PWR_CTRL2, 10, 0, NULL, 0), 560 561 SND_SOC_DAPM_ADC("VMON ADC", NULL, SND_SOC_NOPM, 0, 0), 562 SND_SOC_DAPM_ADC("IMON ADC", NULL, SND_SOC_NOPM, 0, 0), 563 SND_SOC_DAPM_ADC("VPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 564 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, SND_SOC_NOPM, 0, 0), 565 SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 566 567 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0), 568 569 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0, 570 cs35l41_main_amp_event, 571 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 572 573 SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux), 574 SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux), 575 SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux), 576 SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux), 577 SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux), 578 SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux), 579 SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux), 580 SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl), 581 }; 582 583 static const struct snd_soc_dapm_route cs35l41_audio_map[] = { 584 {"DSP RX1 Source", "ASPRX1", "ASPRX1"}, 585 {"DSP RX1 Source", "ASPRX2", "ASPRX2"}, 586 {"DSP RX2 Source", "ASPRX1", "ASPRX1"}, 587 {"DSP RX2 Source", "ASPRX2", "ASPRX2"}, 588 589 {"DSP1", NULL, "DSP RX1 Source"}, 590 {"DSP1", NULL, "DSP RX2 Source"}, 591 592 {"ASP TX1 Source", "VMON", "VMON ADC"}, 593 {"ASP TX1 Source", "IMON", "IMON ADC"}, 594 {"ASP TX1 Source", "VPMON", "VPMON ADC"}, 595 {"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"}, 596 {"ASP TX1 Source", "DSPTX1", "DSP1"}, 597 {"ASP TX1 Source", "DSPTX2", "DSP1"}, 598 {"ASP TX1 Source", "ASPRX1", "ASPRX1" }, 599 {"ASP TX1 Source", "ASPRX2", "ASPRX2" }, 600 {"ASP TX2 Source", "VMON", "VMON ADC"}, 601 {"ASP TX2 Source", "IMON", "IMON ADC"}, 602 {"ASP TX2 Source", "VPMON", "VPMON ADC"}, 603 {"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"}, 604 {"ASP TX2 Source", "DSPTX1", "DSP1"}, 605 {"ASP TX2 Source", "DSPTX2", "DSP1"}, 606 {"ASP TX2 Source", "ASPRX1", "ASPRX1" }, 607 {"ASP TX2 Source", "ASPRX2", "ASPRX2" }, 608 {"ASP TX3 Source", "VMON", "VMON ADC"}, 609 {"ASP TX3 Source", "IMON", "IMON ADC"}, 610 {"ASP TX3 Source", "VPMON", "VPMON ADC"}, 611 {"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"}, 612 {"ASP TX3 Source", "DSPTX1", "DSP1"}, 613 {"ASP TX3 Source", "DSPTX2", "DSP1"}, 614 {"ASP TX3 Source", "ASPRX1", "ASPRX1" }, 615 {"ASP TX3 Source", "ASPRX2", "ASPRX2" }, 616 {"ASP TX4 Source", "VMON", "VMON ADC"}, 617 {"ASP TX4 Source", "IMON", "IMON ADC"}, 618 {"ASP TX4 Source", "VPMON", "VPMON ADC"}, 619 {"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"}, 620 {"ASP TX4 Source", "DSPTX1", "DSP1"}, 621 {"ASP TX4 Source", "DSPTX2", "DSP1"}, 622 {"ASP TX4 Source", "ASPRX1", "ASPRX1" }, 623 {"ASP TX4 Source", "ASPRX2", "ASPRX2" }, 624 {"ASPTX1", NULL, "ASP TX1 Source"}, 625 {"ASPTX2", NULL, "ASP TX2 Source"}, 626 {"ASPTX3", NULL, "ASP TX3 Source"}, 627 {"ASPTX4", NULL, "ASP TX4 Source"}, 628 {"AMP Capture", NULL, "ASPTX1"}, 629 {"AMP Capture", NULL, "ASPTX2"}, 630 {"AMP Capture", NULL, "ASPTX3"}, 631 {"AMP Capture", NULL, "ASPTX4"}, 632 633 {"DSP1", NULL, "VMON"}, 634 {"DSP1", NULL, "IMON"}, 635 {"DSP1", NULL, "VPMON"}, 636 {"DSP1", NULL, "VBSTMON"}, 637 {"DSP1", NULL, "TEMPMON"}, 638 639 {"VMON ADC", NULL, "VMON"}, 640 {"IMON ADC", NULL, "IMON"}, 641 {"VPMON ADC", NULL, "VPMON"}, 642 {"VBSTMON ADC", NULL, "VBSTMON"}, 643 {"TEMPMON ADC", NULL, "TEMPMON"}, 644 645 {"VMON ADC", NULL, "VSENSE"}, 646 {"IMON ADC", NULL, "ISENSE"}, 647 {"VPMON ADC", NULL, "VP"}, 648 {"VBSTMON ADC", NULL, "VBST"}, 649 {"TEMPMON ADC", NULL, "TEMP"}, 650 651 {"DSP1 Preload", NULL, "DSP1 Preloader"}, 652 {"DSP1", NULL, "DSP1 Preloader"}, 653 654 {"ASPRX1", NULL, "AMP Playback"}, 655 {"ASPRX2", NULL, "AMP Playback"}, 656 {"DRE", "Switch", "CLASS H"}, 657 {"Main AMP", NULL, "CLASS H"}, 658 {"Main AMP", NULL, "DRE"}, 659 {"SPK", NULL, "Main AMP"}, 660 661 {"PCM Source", "ASP", "ASPRX1"}, 662 {"PCM Source", "DSP", "DSP1"}, 663 {"CLASS H", NULL, "PCM Source"}, 664 }; 665 666 static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_n, 667 unsigned int *tx_slot, unsigned int rx_n, unsigned int *rx_slot) 668 { 669 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 670 671 return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_n, tx_slot, rx_n, rx_slot); 672 } 673 674 static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 675 { 676 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 677 unsigned int daifmt = 0; 678 679 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 680 case SND_SOC_DAIFMT_CBP_CFP: 681 daifmt |= CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK; 682 break; 683 case SND_SOC_DAIFMT_CBC_CFC: 684 break; 685 default: 686 dev_warn(cs35l41->dev, "Mixed provider/consumer mode unsupported\n"); 687 return -EINVAL; 688 } 689 690 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 691 case SND_SOC_DAIFMT_DSP_A: 692 break; 693 case SND_SOC_DAIFMT_I2S: 694 daifmt |= 2 << CS35L41_ASP_FMT_SHIFT; 695 break; 696 default: 697 dev_warn(cs35l41->dev, "Invalid or unsupported DAI format\n"); 698 return -EINVAL; 699 } 700 701 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 702 case SND_SOC_DAIFMT_NB_IF: 703 daifmt |= CS35L41_LRCLK_INV_MASK; 704 break; 705 case SND_SOC_DAIFMT_IB_NF: 706 daifmt |= CS35L41_SCLK_INV_MASK; 707 break; 708 case SND_SOC_DAIFMT_IB_IF: 709 daifmt |= CS35L41_LRCLK_INV_MASK | CS35L41_SCLK_INV_MASK; 710 break; 711 case SND_SOC_DAIFMT_NB_NF: 712 break; 713 default: 714 dev_warn(cs35l41->dev, "Invalid DAI clock INV\n"); 715 return -EINVAL; 716 } 717 718 return regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 719 CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK | 720 CS35L41_ASP_FMT_MASK | CS35L41_LRCLK_INV_MASK | 721 CS35L41_SCLK_INV_MASK, daifmt); 722 } 723 724 struct cs35l41_global_fs_config { 725 int rate; 726 int fs_cfg; 727 }; 728 729 static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = { 730 { 12000, 0x01 }, 731 { 24000, 0x02 }, 732 { 48000, 0x03 }, 733 { 96000, 0x04 }, 734 { 192000, 0x05 }, 735 { 11025, 0x09 }, 736 { 22050, 0x0A }, 737 { 44100, 0x0B }, 738 { 88200, 0x0C }, 739 { 176400, 0x0D }, 740 { 8000, 0x11 }, 741 { 16000, 0x12 }, 742 { 32000, 0x13 }, 743 }; 744 745 static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream, 746 struct snd_pcm_hw_params *params, 747 struct snd_soc_dai *dai) 748 { 749 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 750 unsigned int rate = params_rate(params); 751 u8 asp_wl; 752 int i; 753 754 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) { 755 if (rate == cs35l41_fs_rates[i].rate) 756 break; 757 } 758 759 if (i >= ARRAY_SIZE(cs35l41_fs_rates)) { 760 dev_err(cs35l41->dev, "Unsupported rate: %u\n", rate); 761 return -EINVAL; 762 } 763 764 asp_wl = params_width(params); 765 766 if (i < ARRAY_SIZE(cs35l41_fs_rates)) 767 regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL, 768 CS35L41_GLOBAL_FS_MASK, 769 cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT); 770 771 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 772 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 773 CS35L41_ASP_WIDTH_RX_MASK, 774 asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT); 775 regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL, 776 CS35L41_ASP_RX_WL_MASK, 777 asp_wl << CS35L41_ASP_RX_WL_SHIFT); 778 } else { 779 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 780 CS35L41_ASP_WIDTH_TX_MASK, 781 asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT); 782 regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL, 783 CS35L41_ASP_TX_WL_MASK, 784 asp_wl << CS35L41_ASP_TX_WL_SHIFT); 785 } 786 787 return 0; 788 } 789 790 static int cs35l41_get_clk_config(int freq) 791 { 792 int i; 793 794 for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) { 795 if (cs35l41_pll_sysclk[i].freq == freq) 796 return cs35l41_pll_sysclk[i].clk_cfg; 797 } 798 799 return -EINVAL; 800 } 801 802 static const unsigned int cs35l41_src_rates[] = { 803 8000, 12000, 11025, 16000, 22050, 24000, 32000, 804 44100, 48000, 88200, 96000, 176400, 192000 805 }; 806 807 static const struct snd_pcm_hw_constraint_list cs35l41_constraints = { 808 .count = ARRAY_SIZE(cs35l41_src_rates), 809 .list = cs35l41_src_rates, 810 }; 811 812 static int cs35l41_pcm_startup(struct snd_pcm_substream *substream, 813 struct snd_soc_dai *dai) 814 { 815 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 816 817 reinit_completion(&cs35l41->pll_lock); 818 819 if (substream->runtime) 820 return snd_pcm_hw_constraint_list(substream->runtime, 0, 821 SNDRV_PCM_HW_PARAM_RATE, 822 &cs35l41_constraints); 823 return 0; 824 } 825 826 static int cs35l41_component_set_sysclk(struct snd_soc_component *component, 827 int clk_id, int source, 828 unsigned int freq, int dir) 829 { 830 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 831 int extclk_cfg, clksrc; 832 833 switch (clk_id) { 834 case CS35L41_CLKID_SCLK: 835 clksrc = CS35L41_PLLSRC_SCLK; 836 break; 837 case CS35L41_CLKID_LRCLK: 838 clksrc = CS35L41_PLLSRC_LRCLK; 839 break; 840 case CS35L41_CLKID_MCLK: 841 clksrc = CS35L41_PLLSRC_MCLK; 842 break; 843 default: 844 dev_err(cs35l41->dev, "Invalid CLK Config\n"); 845 return -EINVAL; 846 } 847 848 extclk_cfg = cs35l41_get_clk_config(freq); 849 850 if (extclk_cfg < 0) { 851 dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n", 852 extclk_cfg, freq); 853 return -EINVAL; 854 } 855 856 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 857 CS35L41_PLL_OPENLOOP_MASK, 858 1 << CS35L41_PLL_OPENLOOP_SHIFT); 859 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 860 CS35L41_REFCLK_FREQ_MASK, 861 extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT); 862 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 863 CS35L41_PLL_CLK_EN_MASK, 864 0 << CS35L41_PLL_CLK_EN_SHIFT); 865 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 866 CS35L41_PLL_CLK_SEL_MASK, clksrc); 867 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 868 CS35L41_PLL_OPENLOOP_MASK, 869 0 << CS35L41_PLL_OPENLOOP_SHIFT); 870 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 871 CS35L41_PLL_CLK_EN_MASK, 872 1 << CS35L41_PLL_CLK_EN_SHIFT); 873 874 return 0; 875 } 876 877 static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai, 878 int clk_id, unsigned int freq, int dir) 879 { 880 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 881 unsigned int fs1_val; 882 unsigned int fs2_val; 883 unsigned int val; 884 int fsindex; 885 886 fsindex = cs35l41_get_fs_mon_config_index(freq); 887 if (fsindex < 0) { 888 dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq); 889 return -EINVAL; 890 } 891 892 dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq); 893 894 if (freq <= 6144000) { 895 /* Use the lookup table */ 896 fs1_val = cs35l41_fs_mon[fsindex].fs1; 897 fs2_val = cs35l41_fs_mon[fsindex].fs2; 898 } else { 899 /* Use hard-coded values */ 900 fs1_val = 0x10; 901 fs2_val = 0x24; 902 } 903 904 val = fs1_val; 905 val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK; 906 regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val); 907 908 return 0; 909 } 910 911 static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) 912 { 913 struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg; 914 int ret; 915 916 if (!hw_cfg->valid) 917 return -EINVAL; 918 919 if (hw_cfg->bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH) 920 return -EINVAL; 921 922 /* Required */ 923 ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg); 924 if (ret) 925 return ret; 926 927 /* Optional */ 928 if (hw_cfg->dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && hw_cfg->dout_hiz >= 0) 929 regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, CS35L41_ASP_DOUT_HIZ_MASK, 930 hw_cfg->dout_hiz); 931 932 return 0; 933 } 934 935 static const struct snd_soc_dapm_route cs35l41_ext_bst_routes[] = { 936 {"Main AMP", NULL, "VSPK"}, 937 }; 938 939 static const struct snd_soc_dapm_widget cs35l41_ext_bst_widget[] = { 940 SND_SOC_DAPM_SUPPLY("VSPK", CS35L41_GPIO1_CTRL1, CS35L41_GPIO_LVL_SHIFT, 0, NULL, 0), 941 }; 942 943 static int cs35l41_component_probe(struct snd_soc_component *component) 944 { 945 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 946 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 947 int ret; 948 949 if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) { 950 ret = snd_soc_dapm_new_controls(dapm, cs35l41_ext_bst_widget, 951 ARRAY_SIZE(cs35l41_ext_bst_widget)); 952 if (ret) 953 return ret; 954 955 ret = snd_soc_dapm_add_routes(dapm, cs35l41_ext_bst_routes, 956 ARRAY_SIZE(cs35l41_ext_bst_routes)); 957 if (ret) 958 return ret; 959 } 960 961 return wm_adsp2_component_probe(&cs35l41->dsp, component); 962 } 963 964 static void cs35l41_component_remove(struct snd_soc_component *component) 965 { 966 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 967 968 wm_adsp2_component_remove(&cs35l41->dsp, component); 969 } 970 971 static const struct snd_soc_dai_ops cs35l41_ops = { 972 .startup = cs35l41_pcm_startup, 973 .set_fmt = cs35l41_set_dai_fmt, 974 .hw_params = cs35l41_pcm_hw_params, 975 .set_sysclk = cs35l41_dai_set_sysclk, 976 .set_channel_map = cs35l41_set_channel_map, 977 }; 978 979 static struct snd_soc_dai_driver cs35l41_dai[] = { 980 { 981 .name = "cs35l41-pcm", 982 .id = 0, 983 .playback = { 984 .stream_name = "AMP Playback", 985 .channels_min = 1, 986 .channels_max = 2, 987 .rates = SNDRV_PCM_RATE_KNOT, 988 .formats = CS35L41_RX_FORMATS, 989 }, 990 .capture = { 991 .stream_name = "AMP Capture", 992 .channels_min = 1, 993 .channels_max = 4, 994 .rates = SNDRV_PCM_RATE_KNOT, 995 .formats = CS35L41_TX_FORMATS, 996 }, 997 .ops = &cs35l41_ops, 998 .symmetric_rate = 1, 999 }, 1000 }; 1001 1002 static const struct snd_soc_component_driver soc_component_dev_cs35l41 = { 1003 .name = "cs35l41-codec", 1004 .probe = cs35l41_component_probe, 1005 .remove = cs35l41_component_remove, 1006 1007 .dapm_widgets = cs35l41_dapm_widgets, 1008 .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets), 1009 .dapm_routes = cs35l41_audio_map, 1010 .num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map), 1011 1012 .controls = cs35l41_aud_controls, 1013 .num_controls = ARRAY_SIZE(cs35l41_aud_controls), 1014 .set_sysclk = cs35l41_component_set_sysclk, 1015 1016 .endianness = 1, 1017 }; 1018 1019 static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cfg) 1020 { 1021 struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1; 1022 struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2; 1023 unsigned int val; 1024 int ret; 1025 1026 /* Some ACPI systems received the Shared Boost feature before the upstream driver, 1027 * leaving those systems with deprecated _DSD properties. 1028 * To correctly configure those systems add shared-boost-active and shared-boost-passive 1029 * properties mapped to the correct value in boost-type. 1030 * These two are not DT properties and should not be used in new systems designs. 1031 */ 1032 if (device_property_read_bool(dev, "cirrus,shared-boost-active")) { 1033 hw_cfg->bst_type = CS35L41_SHD_BOOST_ACTV; 1034 } else if (device_property_read_bool(dev, "cirrus,shared-boost-passive")) { 1035 hw_cfg->bst_type = CS35L41_SHD_BOOST_PASS; 1036 } else { 1037 ret = device_property_read_u32(dev, "cirrus,boost-type", &val); 1038 if (ret >= 0) 1039 hw_cfg->bst_type = val; 1040 } 1041 1042 ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val); 1043 if (ret >= 0) 1044 hw_cfg->bst_ipk = val; 1045 else 1046 hw_cfg->bst_ipk = -1; 1047 1048 ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val); 1049 if (ret >= 0) 1050 hw_cfg->bst_ind = val; 1051 else 1052 hw_cfg->bst_ind = -1; 1053 1054 ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val); 1055 if (ret >= 0) 1056 hw_cfg->bst_cap = val; 1057 else 1058 hw_cfg->bst_cap = -1; 1059 1060 ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val); 1061 if (ret >= 0) 1062 hw_cfg->dout_hiz = val; 1063 else 1064 hw_cfg->dout_hiz = -1; 1065 1066 /* GPIO1 Pin Config */ 1067 gpio1->pol_inv = device_property_read_bool(dev, "cirrus,gpio1-polarity-invert"); 1068 gpio1->out_en = device_property_read_bool(dev, "cirrus,gpio1-output-enable"); 1069 ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", &val); 1070 if (ret >= 0) { 1071 gpio1->func = val; 1072 gpio1->valid = true; 1073 } 1074 1075 /* GPIO2 Pin Config */ 1076 gpio2->pol_inv = device_property_read_bool(dev, "cirrus,gpio2-polarity-invert"); 1077 gpio2->out_en = device_property_read_bool(dev, "cirrus,gpio2-output-enable"); 1078 ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", &val); 1079 if (ret >= 0) { 1080 gpio2->func = val; 1081 gpio2->valid = true; 1082 } 1083 1084 hw_cfg->valid = true; 1085 1086 return 0; 1087 } 1088 1089 static int cs35l41_dsp_init(struct cs35l41_private *cs35l41) 1090 { 1091 struct wm_adsp *dsp; 1092 int ret; 1093 1094 dsp = &cs35l41->dsp; 1095 dsp->part = "cs35l41"; 1096 dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */ 1097 dsp->toggle_preload = true; 1098 1099 cs35l41_configure_cs_dsp(cs35l41->dev, cs35l41->regmap, &dsp->cs_dsp); 1100 1101 ret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap); 1102 if (ret < 0) 1103 return ret; 1104 1105 ret = wm_halo_init(dsp); 1106 if (ret) { 1107 dev_err(cs35l41->dev, "wm_halo_init failed: %d\n", ret); 1108 return ret; 1109 } 1110 1111 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC, 1112 CS35L41_INPUT_SRC_VPMON); 1113 if (ret < 0) { 1114 dev_err(cs35l41->dev, "Write INPUT_SRC_VPMON failed: %d\n", ret); 1115 goto err_dsp; 1116 } 1117 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC, 1118 CS35L41_INPUT_SRC_CLASSH); 1119 if (ret < 0) { 1120 dev_err(cs35l41->dev, "Write INPUT_SRC_CLASSH failed: %d\n", ret); 1121 goto err_dsp; 1122 } 1123 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC, 1124 CS35L41_INPUT_SRC_TEMPMON); 1125 if (ret < 0) { 1126 dev_err(cs35l41->dev, "Write INPUT_SRC_TEMPMON failed: %d\n", ret); 1127 goto err_dsp; 1128 } 1129 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC, 1130 CS35L41_INPUT_SRC_RSVD); 1131 if (ret < 0) { 1132 dev_err(cs35l41->dev, "Write INPUT_SRC_RSVD failed: %d\n", ret); 1133 goto err_dsp; 1134 } 1135 1136 return 0; 1137 1138 err_dsp: 1139 wm_adsp2_remove(dsp); 1140 1141 return ret; 1142 } 1143 1144 static int cs35l41_acpi_get_name(struct cs35l41_private *cs35l41) 1145 { 1146 acpi_handle handle = ACPI_HANDLE(cs35l41->dev); 1147 const char *sub; 1148 1149 /* If there is no ACPI_HANDLE, there is no ACPI for this system, return 0 */ 1150 if (!handle) 1151 return 0; 1152 1153 sub = acpi_get_subsystem_id(handle); 1154 if (IS_ERR(sub)) { 1155 /* If bad ACPI, return 0 and fallback to legacy firmware path, otherwise fail */ 1156 if (PTR_ERR(sub) == -ENODATA) 1157 return 0; 1158 else 1159 return PTR_ERR(sub); 1160 } 1161 1162 cs35l41->dsp.system_name = sub; 1163 dev_dbg(cs35l41->dev, "Subsystem ID: %s\n", cs35l41->dsp.system_name); 1164 1165 return 0; 1166 } 1167 1168 int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg *hw_cfg) 1169 { 1170 u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match; 1171 int irq_pol = 0; 1172 int ret; 1173 1174 if (hw_cfg) { 1175 cs35l41->hw_cfg = *hw_cfg; 1176 } else { 1177 ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->hw_cfg); 1178 if (ret != 0) 1179 return ret; 1180 } 1181 1182 for (i = 0; i < CS35L41_NUM_SUPPLIES; i++) 1183 cs35l41->supplies[i].supply = cs35l41_supplies[i]; 1184 1185 ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES, 1186 cs35l41->supplies); 1187 if (ret != 0) { 1188 dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", ret); 1189 return ret; 1190 } 1191 1192 ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1193 if (ret != 0) { 1194 dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", ret); 1195 return ret; 1196 } 1197 1198 /* returning NULL can be an option if in stereo mode */ 1199 cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset", 1200 GPIOD_OUT_LOW); 1201 if (IS_ERR(cs35l41->reset_gpio)) { 1202 ret = PTR_ERR(cs35l41->reset_gpio); 1203 cs35l41->reset_gpio = NULL; 1204 if (ret == -EBUSY) { 1205 dev_info(cs35l41->dev, 1206 "Reset line busy, assuming shared reset\n"); 1207 } else { 1208 dev_err(cs35l41->dev, 1209 "Failed to get reset GPIO: %d\n", ret); 1210 goto err; 1211 } 1212 } 1213 if (cs35l41->reset_gpio) { 1214 /* satisfy minimum reset pulse width spec */ 1215 usleep_range(2000, 2100); 1216 gpiod_set_value_cansleep(cs35l41->reset_gpio, 1); 1217 } 1218 1219 usleep_range(2000, 2100); 1220 1221 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4, 1222 int_status, int_status & CS35L41_OTP_BOOT_DONE, 1223 1000, 100000); 1224 if (ret) { 1225 dev_err(cs35l41->dev, 1226 "Failed waiting for OTP_BOOT_DONE: %d\n", ret); 1227 goto err; 1228 } 1229 1230 regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status); 1231 if (int_status & CS35L41_OTP_BOOT_ERR) { 1232 dev_err(cs35l41->dev, "OTP Boot error\n"); 1233 ret = -EINVAL; 1234 goto err; 1235 } 1236 1237 ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id); 1238 if (ret < 0) { 1239 dev_err(cs35l41->dev, "Get Device ID failed: %d\n", ret); 1240 goto err; 1241 } 1242 1243 ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid); 1244 if (ret < 0) { 1245 dev_err(cs35l41->dev, "Get Revision ID failed: %d\n", ret); 1246 goto err; 1247 } 1248 1249 mtl_revid = reg_revid & CS35L41_MTLREVID_MASK; 1250 1251 /* CS35L41 will have even MTLREVID 1252 * CS35L41R will have odd MTLREVID 1253 */ 1254 chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID; 1255 if (regid != chipid_match) { 1256 dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n", 1257 regid, chipid_match); 1258 ret = -ENODEV; 1259 goto err; 1260 } 1261 1262 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap); 1263 1264 ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid); 1265 if (ret) 1266 goto err; 1267 1268 ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap); 1269 if (ret < 0) { 1270 dev_err(cs35l41->dev, "OTP Unpack failed: %d\n", ret); 1271 goto err; 1272 } 1273 1274 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); 1275 1276 irq_pol = cs35l41_gpio_config(cs35l41->regmap, &cs35l41->hw_cfg); 1277 1278 /* Set interrupt masks for critical errors */ 1279 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 1280 CS35L41_INT1_MASK_DEFAULT); 1281 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS || 1282 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV) 1283 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK, 1284 0 << CS35L41_INT3_PLL_LOCK_SHIFT); 1285 1286 ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq, 1287 IRQF_ONESHOT | IRQF_SHARED | irq_pol, 1288 "cs35l41", cs35l41); 1289 if (ret != 0) { 1290 dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret); 1291 goto err; 1292 } 1293 1294 ret = cs35l41_set_pdata(cs35l41); 1295 if (ret < 0) { 1296 dev_err(cs35l41->dev, "Set pdata failed: %d\n", ret); 1297 goto err; 1298 } 1299 1300 ret = cs35l41_acpi_get_name(cs35l41); 1301 if (ret < 0) 1302 goto err; 1303 1304 ret = cs35l41_dsp_init(cs35l41); 1305 if (ret < 0) 1306 goto err; 1307 1308 init_completion(&cs35l41->pll_lock); 1309 1310 pm_runtime_set_autosuspend_delay(cs35l41->dev, 3000); 1311 pm_runtime_use_autosuspend(cs35l41->dev); 1312 pm_runtime_mark_last_busy(cs35l41->dev); 1313 pm_runtime_set_active(cs35l41->dev); 1314 pm_runtime_get_noresume(cs35l41->dev); 1315 pm_runtime_enable(cs35l41->dev); 1316 1317 ret = devm_snd_soc_register_component(cs35l41->dev, 1318 &soc_component_dev_cs35l41, 1319 cs35l41_dai, ARRAY_SIZE(cs35l41_dai)); 1320 if (ret < 0) { 1321 dev_err(cs35l41->dev, "Register codec failed: %d\n", ret); 1322 goto err_pm; 1323 } 1324 1325 pm_runtime_put_autosuspend(cs35l41->dev); 1326 1327 dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n", 1328 regid, reg_revid); 1329 1330 return 0; 1331 1332 err_pm: 1333 pm_runtime_disable(cs35l41->dev); 1334 pm_runtime_put_noidle(cs35l41->dev); 1335 1336 wm_adsp2_remove(&cs35l41->dsp); 1337 err: 1338 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1339 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1340 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1341 1342 return ret; 1343 } 1344 EXPORT_SYMBOL_GPL(cs35l41_probe); 1345 1346 void cs35l41_remove(struct cs35l41_private *cs35l41) 1347 { 1348 pm_runtime_get_sync(cs35l41->dev); 1349 pm_runtime_disable(cs35l41->dev); 1350 1351 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF); 1352 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS || 1353 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV) 1354 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK, 1355 1 << CS35L41_INT3_PLL_LOCK_SHIFT); 1356 kfree(cs35l41->dsp.system_name); 1357 wm_adsp2_remove(&cs35l41->dsp); 1358 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1359 1360 pm_runtime_put_noidle(cs35l41->dev); 1361 1362 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1363 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1364 } 1365 EXPORT_SYMBOL_GPL(cs35l41_remove); 1366 1367 static int __maybe_unused cs35l41_runtime_suspend(struct device *dev) 1368 { 1369 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1370 1371 dev_dbg(cs35l41->dev, "Runtime suspend\n"); 1372 1373 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running) 1374 return 0; 1375 1376 cs35l41_enter_hibernate(dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1377 1378 regcache_cache_only(cs35l41->regmap, true); 1379 regcache_mark_dirty(cs35l41->regmap); 1380 1381 return 0; 1382 } 1383 1384 static int __maybe_unused cs35l41_runtime_resume(struct device *dev) 1385 { 1386 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1387 int ret; 1388 1389 dev_dbg(cs35l41->dev, "Runtime resume\n"); 1390 1391 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running) 1392 return 0; 1393 1394 regcache_cache_only(cs35l41->regmap, false); 1395 1396 ret = cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap); 1397 if (ret) 1398 return ret; 1399 1400 /* Test key needs to be unlocked to allow the OTP settings to re-apply */ 1401 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap); 1402 ret = regcache_sync(cs35l41->regmap); 1403 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); 1404 if (ret) { 1405 dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret); 1406 return ret; 1407 } 1408 cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, &cs35l41->hw_cfg); 1409 1410 return 0; 1411 } 1412 1413 static int __maybe_unused cs35l41_sys_suspend(struct device *dev) 1414 { 1415 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1416 1417 dev_dbg(cs35l41->dev, "System suspend, disabling IRQ\n"); 1418 disable_irq(cs35l41->irq); 1419 1420 return 0; 1421 } 1422 1423 static int __maybe_unused cs35l41_sys_suspend_noirq(struct device *dev) 1424 { 1425 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1426 1427 dev_dbg(cs35l41->dev, "Late system suspend, reenabling IRQ\n"); 1428 enable_irq(cs35l41->irq); 1429 1430 return 0; 1431 } 1432 1433 static int __maybe_unused cs35l41_sys_resume_noirq(struct device *dev) 1434 { 1435 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1436 1437 dev_dbg(cs35l41->dev, "Early system resume, disabling IRQ\n"); 1438 disable_irq(cs35l41->irq); 1439 1440 return 0; 1441 } 1442 1443 static int __maybe_unused cs35l41_sys_resume(struct device *dev) 1444 { 1445 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1446 1447 dev_dbg(cs35l41->dev, "System resume, reenabling IRQ\n"); 1448 enable_irq(cs35l41->irq); 1449 1450 return 0; 1451 } 1452 1453 const struct dev_pm_ops cs35l41_pm_ops = { 1454 SET_RUNTIME_PM_OPS(cs35l41_runtime_suspend, cs35l41_runtime_resume, NULL) 1455 1456 SET_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend, cs35l41_sys_resume) 1457 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend_noirq, cs35l41_sys_resume_noirq) 1458 }; 1459 EXPORT_SYMBOL_GPL(cs35l41_pm_ops); 1460 1461 MODULE_DESCRIPTION("ASoC CS35L41 driver"); 1462 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>"); 1463 MODULE_LICENSE("GPL"); 1464