1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/starfive,jh7110-crg.h>
9#include <dt-bindings/power/starfive,jh7110-pmu.h>
10#include <dt-bindings/reset/starfive,jh7110-crg.h>
11#include <dt-bindings/thermal/thermal.h>
12
13/ {
14	compatible = "starfive,jh7110";
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		S7_0: cpu@0 {
23			compatible = "sifive,s7", "riscv";
24			reg = <0>;
25			device_type = "cpu";
26			i-cache-block-size = <64>;
27			i-cache-sets = <64>;
28			i-cache-size = <16384>;
29			next-level-cache = <&ccache>;
30			riscv,isa = "rv64imac_zba_zbb";
31			status = "disabled";
32
33			cpu0_intc: interrupt-controller {
34				compatible = "riscv,cpu-intc";
35				interrupt-controller;
36				#interrupt-cells = <1>;
37			};
38		};
39
40		U74_1: cpu@1 {
41			compatible = "sifive,u74-mc", "riscv";
42			reg = <1>;
43			d-cache-block-size = <64>;
44			d-cache-sets = <64>;
45			d-cache-size = <32768>;
46			d-tlb-sets = <1>;
47			d-tlb-size = <40>;
48			device_type = "cpu";
49			i-cache-block-size = <64>;
50			i-cache-sets = <64>;
51			i-cache-size = <32768>;
52			i-tlb-sets = <1>;
53			i-tlb-size = <40>;
54			mmu-type = "riscv,sv39";
55			next-level-cache = <&ccache>;
56			riscv,isa = "rv64imafdc_zba_zbb";
57			tlb-split;
58			operating-points-v2 = <&cpu_opp>;
59			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
60			clock-names = "cpu";
61			#cooling-cells = <2>;
62
63			cpu1_intc: interrupt-controller {
64				compatible = "riscv,cpu-intc";
65				interrupt-controller;
66				#interrupt-cells = <1>;
67			};
68		};
69
70		U74_2: cpu@2 {
71			compatible = "sifive,u74-mc", "riscv";
72			reg = <2>;
73			d-cache-block-size = <64>;
74			d-cache-sets = <64>;
75			d-cache-size = <32768>;
76			d-tlb-sets = <1>;
77			d-tlb-size = <40>;
78			device_type = "cpu";
79			i-cache-block-size = <64>;
80			i-cache-sets = <64>;
81			i-cache-size = <32768>;
82			i-tlb-sets = <1>;
83			i-tlb-size = <40>;
84			mmu-type = "riscv,sv39";
85			next-level-cache = <&ccache>;
86			riscv,isa = "rv64imafdc_zba_zbb";
87			tlb-split;
88			operating-points-v2 = <&cpu_opp>;
89			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
90			clock-names = "cpu";
91			#cooling-cells = <2>;
92
93			cpu2_intc: interrupt-controller {
94				compatible = "riscv,cpu-intc";
95				interrupt-controller;
96				#interrupt-cells = <1>;
97			};
98		};
99
100		U74_3: cpu@3 {
101			compatible = "sifive,u74-mc", "riscv";
102			reg = <3>;
103			d-cache-block-size = <64>;
104			d-cache-sets = <64>;
105			d-cache-size = <32768>;
106			d-tlb-sets = <1>;
107			d-tlb-size = <40>;
108			device_type = "cpu";
109			i-cache-block-size = <64>;
110			i-cache-sets = <64>;
111			i-cache-size = <32768>;
112			i-tlb-sets = <1>;
113			i-tlb-size = <40>;
114			mmu-type = "riscv,sv39";
115			next-level-cache = <&ccache>;
116			riscv,isa = "rv64imafdc_zba_zbb";
117			tlb-split;
118			operating-points-v2 = <&cpu_opp>;
119			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
120			clock-names = "cpu";
121			#cooling-cells = <2>;
122
123			cpu3_intc: interrupt-controller {
124				compatible = "riscv,cpu-intc";
125				interrupt-controller;
126				#interrupt-cells = <1>;
127			};
128		};
129
130		U74_4: cpu@4 {
131			compatible = "sifive,u74-mc", "riscv";
132			reg = <4>;
133			d-cache-block-size = <64>;
134			d-cache-sets = <64>;
135			d-cache-size = <32768>;
136			d-tlb-sets = <1>;
137			d-tlb-size = <40>;
138			device_type = "cpu";
139			i-cache-block-size = <64>;
140			i-cache-sets = <64>;
141			i-cache-size = <32768>;
142			i-tlb-sets = <1>;
143			i-tlb-size = <40>;
144			mmu-type = "riscv,sv39";
145			next-level-cache = <&ccache>;
146			riscv,isa = "rv64imafdc_zba_zbb";
147			tlb-split;
148			operating-points-v2 = <&cpu_opp>;
149			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
150			clock-names = "cpu";
151			#cooling-cells = <2>;
152
153			cpu4_intc: interrupt-controller {
154				compatible = "riscv,cpu-intc";
155				interrupt-controller;
156				#interrupt-cells = <1>;
157			};
158		};
159
160		cpu-map {
161			cluster0 {
162				core0 {
163					cpu = <&S7_0>;
164				};
165
166				core1 {
167					cpu = <&U74_1>;
168				};
169
170				core2 {
171					cpu = <&U74_2>;
172				};
173
174				core3 {
175					cpu = <&U74_3>;
176				};
177
178				core4 {
179					cpu = <&U74_4>;
180				};
181			};
182		};
183	};
184
185	cpu_opp: opp-table-0 {
186			compatible = "operating-points-v2";
187			opp-shared;
188			opp-375000000 {
189					opp-hz = /bits/ 64 <375000000>;
190					opp-microvolt = <800000>;
191			};
192			opp-500000000 {
193					opp-hz = /bits/ 64 <500000000>;
194					opp-microvolt = <800000>;
195			};
196			opp-750000000 {
197					opp-hz = /bits/ 64 <750000000>;
198					opp-microvolt = <800000>;
199			};
200			opp-1500000000 {
201					opp-hz = /bits/ 64 <1500000000>;
202					opp-microvolt = <1040000>;
203			};
204	};
205
206	thermal-zones {
207		cpu-thermal {
208			polling-delay-passive = <250>;
209			polling-delay = <15000>;
210
211			thermal-sensors = <&sfctemp>;
212
213			cooling-maps {
214				map0 {
215					trip = <&cpu_alert0>;
216					cooling-device =
217						<&U74_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
218						<&U74_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
219						<&U74_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
220						<&U74_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
221				};
222			};
223
224			trips {
225				cpu_alert0: cpu_alert0 {
226					/* milliCelsius */
227					temperature = <85000>;
228					hysteresis = <2000>;
229					type = "passive";
230				};
231
232				cpu_crit {
233					/* milliCelsius */
234					temperature = <100000>;
235					hysteresis = <2000>;
236					type = "critical";
237				};
238			};
239		};
240	};
241
242	dvp_clk: dvp-clock {
243		compatible = "fixed-clock";
244		clock-output-names = "dvp_clk";
245		#clock-cells = <0>;
246	};
247	gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
248		compatible = "fixed-clock";
249		clock-output-names = "gmac0_rgmii_rxin";
250		#clock-cells = <0>;
251	};
252
253	gmac0_rmii_refin: gmac0-rmii-refin-clock {
254		compatible = "fixed-clock";
255		clock-output-names = "gmac0_rmii_refin";
256		#clock-cells = <0>;
257	};
258
259	gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
260		compatible = "fixed-clock";
261		clock-output-names = "gmac1_rgmii_rxin";
262		#clock-cells = <0>;
263	};
264
265	gmac1_rmii_refin: gmac1-rmii-refin-clock {
266		compatible = "fixed-clock";
267		clock-output-names = "gmac1_rmii_refin";
268		#clock-cells = <0>;
269	};
270
271	hdmitx0_pixelclk: hdmitx0-pixel-clock {
272		compatible = "fixed-clock";
273		clock-output-names = "hdmitx0_pixelclk";
274		#clock-cells = <0>;
275	};
276
277	i2srx_bclk_ext: i2srx-bclk-ext-clock {
278		compatible = "fixed-clock";
279		clock-output-names = "i2srx_bclk_ext";
280		#clock-cells = <0>;
281	};
282
283	i2srx_lrck_ext: i2srx-lrck-ext-clock {
284		compatible = "fixed-clock";
285		clock-output-names = "i2srx_lrck_ext";
286		#clock-cells = <0>;
287	};
288
289	i2stx_bclk_ext: i2stx-bclk-ext-clock {
290		compatible = "fixed-clock";
291		clock-output-names = "i2stx_bclk_ext";
292		#clock-cells = <0>;
293	};
294
295	i2stx_lrck_ext: i2stx-lrck-ext-clock {
296		compatible = "fixed-clock";
297		clock-output-names = "i2stx_lrck_ext";
298		#clock-cells = <0>;
299	};
300
301	mclk_ext: mclk-ext-clock {
302		compatible = "fixed-clock";
303		clock-output-names = "mclk_ext";
304		#clock-cells = <0>;
305	};
306
307	osc: oscillator {
308		compatible = "fixed-clock";
309		clock-output-names = "osc";
310		#clock-cells = <0>;
311	};
312
313	rtc_osc: rtc-oscillator {
314		compatible = "fixed-clock";
315		clock-output-names = "rtc_osc";
316		#clock-cells = <0>;
317	};
318
319	stmmac_axi_setup: stmmac-axi-config {
320		snps,lpi_en;
321		snps,wr_osr_lmt = <15>;
322		snps,rd_osr_lmt = <15>;
323		snps,blen = <256 128 64 32 0 0 0>;
324	};
325
326	tdm_ext: tdm-ext-clock {
327		compatible = "fixed-clock";
328		clock-output-names = "tdm_ext";
329		#clock-cells = <0>;
330	};
331
332	soc {
333		compatible = "simple-bus";
334		interrupt-parent = <&plic>;
335		#address-cells = <2>;
336		#size-cells = <2>;
337		ranges;
338
339		clint: timer@2000000 {
340			compatible = "starfive,jh7110-clint", "sifive,clint0";
341			reg = <0x0 0x2000000 0x0 0x10000>;
342			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
343					      <&cpu1_intc 3>, <&cpu1_intc 7>,
344					      <&cpu2_intc 3>, <&cpu2_intc 7>,
345					      <&cpu3_intc 3>, <&cpu3_intc 7>,
346					      <&cpu4_intc 3>, <&cpu4_intc 7>;
347		};
348
349		ccache: cache-controller@2010000 {
350			compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
351			reg = <0x0 0x2010000 0x0 0x4000>;
352			interrupts = <1>, <3>, <4>, <2>;
353			cache-block-size = <64>;
354			cache-level = <2>;
355			cache-sets = <2048>;
356			cache-size = <2097152>;
357			cache-unified;
358		};
359
360		plic: interrupt-controller@c000000 {
361			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
362			reg = <0x0 0xc000000 0x0 0x4000000>;
363			interrupts-extended = <&cpu0_intc 11>,
364					      <&cpu1_intc 11>, <&cpu1_intc 9>,
365					      <&cpu2_intc 11>, <&cpu2_intc 9>,
366					      <&cpu3_intc 11>, <&cpu3_intc 9>,
367					      <&cpu4_intc 11>, <&cpu4_intc 9>;
368			interrupt-controller;
369			#interrupt-cells = <1>;
370			#address-cells = <0>;
371			riscv,ndev = <136>;
372		};
373
374		uart0: serial@10000000 {
375			compatible = "snps,dw-apb-uart";
376			reg = <0x0 0x10000000 0x0 0x10000>;
377			clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
378				 <&syscrg JH7110_SYSCLK_UART0_APB>;
379			clock-names = "baudclk", "apb_pclk";
380			resets = <&syscrg JH7110_SYSRST_UART0_APB>;
381			interrupts = <32>;
382			reg-io-width = <4>;
383			reg-shift = <2>;
384			status = "disabled";
385		};
386
387		uart1: serial@10010000 {
388			compatible = "snps,dw-apb-uart";
389			reg = <0x0 0x10010000 0x0 0x10000>;
390			clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
391				 <&syscrg JH7110_SYSCLK_UART1_APB>;
392			clock-names = "baudclk", "apb_pclk";
393			resets = <&syscrg JH7110_SYSRST_UART1_APB>;
394			interrupts = <33>;
395			reg-io-width = <4>;
396			reg-shift = <2>;
397			status = "disabled";
398		};
399
400		uart2: serial@10020000 {
401			compatible = "snps,dw-apb-uart";
402			reg = <0x0 0x10020000 0x0 0x10000>;
403			clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
404				 <&syscrg JH7110_SYSCLK_UART2_APB>;
405			clock-names = "baudclk", "apb_pclk";
406			resets = <&syscrg JH7110_SYSRST_UART2_APB>;
407			interrupts = <34>;
408			reg-io-width = <4>;
409			reg-shift = <2>;
410			status = "disabled";
411		};
412
413		i2c0: i2c@10030000 {
414			compatible = "snps,designware-i2c";
415			reg = <0x0 0x10030000 0x0 0x10000>;
416			clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
417			clock-names = "ref";
418			resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
419			interrupts = <35>;
420			#address-cells = <1>;
421			#size-cells = <0>;
422			status = "disabled";
423		};
424
425		i2c1: i2c@10040000 {
426			compatible = "snps,designware-i2c";
427			reg = <0x0 0x10040000 0x0 0x10000>;
428			clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
429			clock-names = "ref";
430			resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
431			interrupts = <36>;
432			#address-cells = <1>;
433			#size-cells = <0>;
434			status = "disabled";
435		};
436
437		i2c2: i2c@10050000 {
438			compatible = "snps,designware-i2c";
439			reg = <0x0 0x10050000 0x0 0x10000>;
440			clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
441			clock-names = "ref";
442			resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
443			interrupts = <37>;
444			#address-cells = <1>;
445			#size-cells = <0>;
446			status = "disabled";
447		};
448
449		spi0: spi@10060000 {
450			compatible = "arm,pl022", "arm,primecell";
451			reg = <0x0 0x10060000 0x0 0x10000>;
452			clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>,
453				 <&syscrg JH7110_SYSCLK_SPI0_APB>;
454			clock-names = "sspclk", "apb_pclk";
455			resets = <&syscrg JH7110_SYSRST_SPI0_APB>;
456			interrupts = <38>;
457			arm,primecell-periphid = <0x00041022>;
458			num-cs = <1>;
459			#address-cells = <1>;
460			#size-cells = <0>;
461			status = "disabled";
462		};
463
464		spi1: spi@10070000 {
465			compatible = "arm,pl022", "arm,primecell";
466			reg = <0x0 0x10070000 0x0 0x10000>;
467			clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>,
468				 <&syscrg JH7110_SYSCLK_SPI1_APB>;
469			clock-names = "sspclk", "apb_pclk";
470			resets = <&syscrg JH7110_SYSRST_SPI1_APB>;
471			interrupts = <39>;
472			arm,primecell-periphid = <0x00041022>;
473			num-cs = <1>;
474			#address-cells = <1>;
475			#size-cells = <0>;
476			status = "disabled";
477		};
478
479		spi2: spi@10080000 {
480			compatible = "arm,pl022", "arm,primecell";
481			reg = <0x0 0x10080000 0x0 0x10000>;
482			clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>,
483				 <&syscrg JH7110_SYSCLK_SPI2_APB>;
484			clock-names = "sspclk", "apb_pclk";
485			resets = <&syscrg JH7110_SYSRST_SPI2_APB>;
486			interrupts = <40>;
487			arm,primecell-periphid = <0x00041022>;
488			num-cs = <1>;
489			#address-cells = <1>;
490			#size-cells = <0>;
491			status = "disabled";
492		};
493
494		tdm: tdm@10090000 {
495			compatible = "starfive,jh7110-tdm";
496			reg = <0x0 0x10090000 0x0 0x1000>;
497			clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>,
498				 <&syscrg JH7110_SYSCLK_TDM_APB>,
499				 <&syscrg JH7110_SYSCLK_TDM_INTERNAL>,
500				 <&syscrg JH7110_SYSCLK_TDM_TDM>,
501				 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
502				 <&tdm_ext>;
503			clock-names = "tdm_ahb", "tdm_apb",
504				      "tdm_internal", "tdm",
505				      "mclk_inner", "tdm_ext";
506			resets = <&syscrg JH7110_SYSRST_TDM_AHB>,
507				 <&syscrg JH7110_SYSRST_TDM_APB>,
508				 <&syscrg JH7110_SYSRST_TDM_CORE>;
509			dmas = <&dma 20>, <&dma 21>;
510			dma-names = "rx","tx";
511			#sound-dai-cells = <0>;
512			status = "disabled";
513		};
514
515		usb0: usb@10100000 {
516			compatible = "starfive,jh7110-usb";
517			ranges = <0x0 0x0 0x10100000 0x100000>;
518			#address-cells = <1>;
519			#size-cells = <1>;
520			starfive,stg-syscon = <&stg_syscon 0x4>;
521			clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
522				 <&stgcrg JH7110_STGCLK_USB0_STB>,
523				 <&stgcrg JH7110_STGCLK_USB0_APB>,
524				 <&stgcrg JH7110_STGCLK_USB0_AXI>,
525				 <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
526			clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
527			resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
528				 <&stgcrg JH7110_STGRST_USB0_APB>,
529				 <&stgcrg JH7110_STGRST_USB0_AXI>,
530				 <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
531			reset-names = "pwrup", "apb", "axi", "utmi_apb";
532			status = "disabled";
533
534			usb_cdns3: usb@0 {
535				compatible = "cdns,usb3";
536				reg = <0x0 0x10000>,
537				      <0x10000 0x10000>,
538				      <0x20000 0x10000>;
539				reg-names = "otg", "xhci", "dev";
540				interrupts = <100>, <108>, <110>;
541				interrupt-names = "host", "peripheral", "otg";
542				phys = <&usbphy0>;
543				phy-names = "cdns3,usb2-phy";
544			};
545		};
546
547		usbphy0: phy@10200000 {
548			compatible = "starfive,jh7110-usb-phy";
549			reg = <0x0 0x10200000 0x0 0x10000>;
550			clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
551				 <&stgcrg JH7110_STGCLK_USB0_APP_125>;
552			clock-names = "125m", "app_125m";
553			#phy-cells = <0>;
554		};
555
556		pciephy0: phy@10210000 {
557			compatible = "starfive,jh7110-pcie-phy";
558			reg = <0x0 0x10210000 0x0 0x10000>;
559			#phy-cells = <0>;
560		};
561
562		pciephy1: phy@10220000 {
563			compatible = "starfive,jh7110-pcie-phy";
564			reg = <0x0 0x10220000 0x0 0x10000>;
565			#phy-cells = <0>;
566		};
567
568		stgcrg: clock-controller@10230000 {
569			compatible = "starfive,jh7110-stgcrg";
570			reg = <0x0 0x10230000 0x0 0x10000>;
571			clocks = <&osc>,
572				 <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
573				 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
574				 <&syscrg JH7110_SYSCLK_USB_125M>,
575				 <&syscrg JH7110_SYSCLK_CPU_BUS>,
576				 <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
577				 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
578				 <&syscrg JH7110_SYSCLK_APB_BUS>;
579			clock-names = "osc", "hifi4_core",
580				      "stg_axiahb", "usb_125m",
581				      "cpu_bus", "hifi4_axi",
582				      "nocstg_bus", "apb_bus";
583			#clock-cells = <1>;
584			#reset-cells = <1>;
585		};
586
587		stg_syscon: syscon@10240000 {
588			compatible = "starfive,jh7110-stg-syscon", "syscon";
589			reg = <0x0 0x10240000 0x0 0x1000>;
590		};
591
592		uart3: serial@12000000 {
593			compatible = "snps,dw-apb-uart";
594			reg = <0x0 0x12000000 0x0 0x10000>;
595			clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
596				 <&syscrg JH7110_SYSCLK_UART3_APB>;
597			clock-names = "baudclk", "apb_pclk";
598			resets = <&syscrg JH7110_SYSRST_UART3_APB>;
599			interrupts = <45>;
600			reg-io-width = <4>;
601			reg-shift = <2>;
602			status = "disabled";
603		};
604
605		uart4: serial@12010000 {
606			compatible = "snps,dw-apb-uart";
607			reg = <0x0 0x12010000 0x0 0x10000>;
608			clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
609				 <&syscrg JH7110_SYSCLK_UART4_APB>;
610			clock-names = "baudclk", "apb_pclk";
611			resets = <&syscrg JH7110_SYSRST_UART4_APB>;
612			interrupts = <46>;
613			reg-io-width = <4>;
614			reg-shift = <2>;
615			status = "disabled";
616		};
617
618		uart5: serial@12020000 {
619			compatible = "snps,dw-apb-uart";
620			reg = <0x0 0x12020000 0x0 0x10000>;
621			clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
622				 <&syscrg JH7110_SYSCLK_UART5_APB>;
623			clock-names = "baudclk", "apb_pclk";
624			resets = <&syscrg JH7110_SYSRST_UART5_APB>;
625			interrupts = <47>;
626			reg-io-width = <4>;
627			reg-shift = <2>;
628			status = "disabled";
629		};
630
631		i2c3: i2c@12030000 {
632			compatible = "snps,designware-i2c";
633			reg = <0x0 0x12030000 0x0 0x10000>;
634			clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
635			clock-names = "ref";
636			resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
637			interrupts = <48>;
638			#address-cells = <1>;
639			#size-cells = <0>;
640			status = "disabled";
641		};
642
643		i2c4: i2c@12040000 {
644			compatible = "snps,designware-i2c";
645			reg = <0x0 0x12040000 0x0 0x10000>;
646			clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
647			clock-names = "ref";
648			resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
649			interrupts = <49>;
650			#address-cells = <1>;
651			#size-cells = <0>;
652			status = "disabled";
653		};
654
655		i2c5: i2c@12050000 {
656			compatible = "snps,designware-i2c";
657			reg = <0x0 0x12050000 0x0 0x10000>;
658			clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
659			clock-names = "ref";
660			resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
661			interrupts = <50>;
662			#address-cells = <1>;
663			#size-cells = <0>;
664			status = "disabled";
665		};
666
667		i2c6: i2c@12060000 {
668			compatible = "snps,designware-i2c";
669			reg = <0x0 0x12060000 0x0 0x10000>;
670			clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
671			clock-names = "ref";
672			resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
673			interrupts = <51>;
674			#address-cells = <1>;
675			#size-cells = <0>;
676			status = "disabled";
677		};
678
679		spi3: spi@12070000 {
680			compatible = "arm,pl022", "arm,primecell";
681			reg = <0x0 0x12070000 0x0 0x10000>;
682			clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>,
683				 <&syscrg JH7110_SYSCLK_SPI3_APB>;
684			clock-names = "sspclk", "apb_pclk";
685			resets = <&syscrg JH7110_SYSRST_SPI3_APB>;
686			interrupts = <52>;
687			arm,primecell-periphid = <0x00041022>;
688			num-cs = <1>;
689			#address-cells = <1>;
690			#size-cells = <0>;
691			status = "disabled";
692		};
693
694		spi4: spi@12080000 {
695			compatible = "arm,pl022", "arm,primecell";
696			reg = <0x0 0x12080000 0x0 0x10000>;
697			clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>,
698				 <&syscrg JH7110_SYSCLK_SPI4_APB>;
699			clock-names = "sspclk", "apb_pclk";
700			resets = <&syscrg JH7110_SYSRST_SPI4_APB>;
701			interrupts = <53>;
702			arm,primecell-periphid = <0x00041022>;
703			num-cs = <1>;
704			#address-cells = <1>;
705			#size-cells = <0>;
706			status = "disabled";
707		};
708
709		spi5: spi@12090000 {
710			compatible = "arm,pl022", "arm,primecell";
711			reg = <0x0 0x12090000 0x0 0x10000>;
712			clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>,
713				 <&syscrg JH7110_SYSCLK_SPI5_APB>;
714			clock-names = "sspclk", "apb_pclk";
715			resets = <&syscrg JH7110_SYSRST_SPI5_APB>;
716			interrupts = <54>;
717			arm,primecell-periphid = <0x00041022>;
718			num-cs = <1>;
719			#address-cells = <1>;
720			#size-cells = <0>;
721			status = "disabled";
722		};
723
724		spi6: spi@120a0000 {
725			compatible = "arm,pl022", "arm,primecell";
726			reg = <0x0 0x120A0000 0x0 0x10000>;
727			clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>,
728				 <&syscrg JH7110_SYSCLK_SPI6_APB>;
729			clock-names = "sspclk", "apb_pclk";
730			resets = <&syscrg JH7110_SYSRST_SPI6_APB>;
731			interrupts = <55>;
732			arm,primecell-periphid = <0x00041022>;
733			num-cs = <1>;
734			#address-cells = <1>;
735			#size-cells = <0>;
736			status = "disabled";
737		};
738
739		sfctemp: temperature-sensor@120e0000 {
740			compatible = "starfive,jh7110-temp";
741			reg = <0x0 0x120e0000 0x0 0x10000>;
742			clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
743				 <&syscrg JH7110_SYSCLK_TEMP_APB>;
744			clock-names = "sense", "bus";
745			resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
746				 <&syscrg JH7110_SYSRST_TEMP_APB>;
747			reset-names = "sense", "bus";
748			#thermal-sensor-cells = <0>;
749		};
750
751		qspi: spi@13010000 {
752			compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
753			reg = <0x0 0x13010000 0x0 0x10000>,
754			      <0x0 0x21000000 0x0 0x400000>;
755			interrupts = <25>;
756			clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
757				 <&syscrg JH7110_SYSCLK_QSPI_AHB>,
758				 <&syscrg JH7110_SYSCLK_QSPI_APB>;
759			clock-names = "ref", "ahb", "apb";
760			resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
761				 <&syscrg JH7110_SYSRST_QSPI_AHB>,
762				 <&syscrg JH7110_SYSRST_QSPI_REF>;
763			reset-names = "qspi", "qspi-ocp", "rstc_ref";
764			cdns,fifo-depth = <256>;
765			cdns,fifo-width = <4>;
766			cdns,trigger-address = <0x0>;
767			status = "disabled";
768		};
769
770		syscrg: clock-controller@13020000 {
771			compatible = "starfive,jh7110-syscrg";
772			reg = <0x0 0x13020000 0x0 0x10000>;
773			clocks = <&osc>, <&gmac1_rmii_refin>,
774				 <&gmac1_rgmii_rxin>,
775				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
776				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
777				 <&tdm_ext>, <&mclk_ext>,
778				 <&pllclk JH7110_PLLCLK_PLL0_OUT>,
779				 <&pllclk JH7110_PLLCLK_PLL1_OUT>,
780				 <&pllclk JH7110_PLLCLK_PLL2_OUT>;
781			clock-names = "osc", "gmac1_rmii_refin",
782				      "gmac1_rgmii_rxin",
783				      "i2stx_bclk_ext", "i2stx_lrck_ext",
784				      "i2srx_bclk_ext", "i2srx_lrck_ext",
785				      "tdm_ext", "mclk_ext",
786				      "pll0_out", "pll1_out", "pll2_out";
787			#clock-cells = <1>;
788			#reset-cells = <1>;
789		};
790
791		sys_syscon: syscon@13030000 {
792			compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
793			reg = <0x0 0x13030000 0x0 0x1000>;
794
795			pllclk: clock-controller {
796				compatible = "starfive,jh7110-pll";
797				clocks = <&osc>;
798				#clock-cells = <1>;
799			};
800		};
801
802		sysgpio: pinctrl@13040000 {
803			compatible = "starfive,jh7110-sys-pinctrl";
804			reg = <0x0 0x13040000 0x0 0x10000>;
805			clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
806			resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
807			interrupts = <86>;
808			interrupt-controller;
809			#interrupt-cells = <2>;
810			gpio-controller;
811			#gpio-cells = <2>;
812		};
813
814		watchdog@13070000 {
815			compatible = "starfive,jh7110-wdt";
816			reg = <0x0 0x13070000 0x0 0x10000>;
817			clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
818				 <&syscrg JH7110_SYSCLK_WDT_CORE>;
819			clock-names = "apb", "core";
820			resets = <&syscrg JH7110_SYSRST_WDT_APB>,
821				 <&syscrg JH7110_SYSRST_WDT_CORE>;
822		};
823
824		crypto: crypto@16000000 {
825			compatible = "starfive,jh7110-crypto";
826			reg = <0x0 0x16000000 0x0 0x4000>;
827			clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
828				 <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
829			clock-names = "hclk", "ahb";
830			interrupts = <28>;
831			resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
832			dmas = <&sdma 1 2>, <&sdma 0 2>;
833			dma-names = "tx", "rx";
834		};
835
836		sdma: dma-controller@16008000 {
837			compatible = "arm,pl080", "arm,primecell";
838			arm,primecell-periphid = <0x00041080>;
839			reg = <0x0 0x16008000 0x0 0x4000>;
840			interrupts = <29>;
841			clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>;
842			clock-names = "apb_pclk";
843			resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
844			lli-bus-interface-ahb1;
845			mem-bus-interface-ahb1;
846			memcpy-burst-size = <256>;
847			memcpy-bus-width = <32>;
848			#dma-cells = <2>;
849		};
850
851		rng: rng@1600c000 {
852			compatible = "starfive,jh7110-trng";
853			reg = <0x0 0x1600C000 0x0 0x4000>;
854			clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
855				 <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
856			clock-names = "hclk", "ahb";
857			resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
858			interrupts = <30>;
859		};
860
861		mmc0: mmc@16010000 {
862			compatible = "starfive,jh7110-mmc";
863			reg = <0x0 0x16010000 0x0 0x10000>;
864			clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
865				 <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
866			clock-names = "biu","ciu";
867			resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
868			reset-names = "reset";
869			interrupts = <74>;
870			fifo-depth = <32>;
871			fifo-watermark-aligned;
872			data-addr = <0>;
873			starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
874			status = "disabled";
875		};
876
877		mmc1: mmc@16020000 {
878			compatible = "starfive,jh7110-mmc";
879			reg = <0x0 0x16020000 0x0 0x10000>;
880			clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
881				 <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
882			clock-names = "biu","ciu";
883			resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
884			reset-names = "reset";
885			interrupts = <75>;
886			fifo-depth = <32>;
887			fifo-watermark-aligned;
888			data-addr = <0>;
889			starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
890			status = "disabled";
891		};
892
893		gmac0: ethernet@16030000 {
894			compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
895			reg = <0x0 0x16030000 0x0 0x10000>;
896			clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
897				 <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
898				 <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
899				 <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
900				 <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
901			clock-names = "stmmaceth", "pclk", "ptp_ref",
902				      "tx", "gtx";
903			resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
904				 <&aoncrg JH7110_AONRST_GMAC0_AHB>;
905			reset-names = "stmmaceth", "ahb";
906			interrupts = <7>, <6>, <5>;
907			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
908			rx-fifo-depth = <2048>;
909			tx-fifo-depth = <2048>;
910			snps,multicast-filter-bins = <64>;
911			snps,perfect-filter-entries = <256>;
912			snps,fixed-burst;
913			snps,no-pbl-x8;
914			snps,force_thresh_dma_mode;
915			snps,axi-config = <&stmmac_axi_setup>;
916			snps,tso;
917			snps,en-tx-lpi-clockgating;
918			snps,txpbl = <16>;
919			snps,rxpbl = <16>;
920			starfive,syscon = <&aon_syscon 0xc 0x12>;
921			status = "disabled";
922		};
923
924		gmac1: ethernet@16040000 {
925			compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
926			reg = <0x0 0x16040000 0x0 0x10000>;
927			clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
928				 <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
929				 <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
930				 <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
931				 <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
932			clock-names = "stmmaceth", "pclk", "ptp_ref",
933				      "tx", "gtx";
934			resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
935				 <&syscrg JH7110_SYSRST_GMAC1_AHB>;
936			reset-names = "stmmaceth", "ahb";
937			interrupts = <78>, <77>, <76>;
938			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
939			rx-fifo-depth = <2048>;
940			tx-fifo-depth = <2048>;
941			snps,multicast-filter-bins = <64>;
942			snps,perfect-filter-entries = <256>;
943			snps,fixed-burst;
944			snps,no-pbl-x8;
945			snps,force_thresh_dma_mode;
946			snps,axi-config = <&stmmac_axi_setup>;
947			snps,tso;
948			snps,en-tx-lpi-clockgating;
949			snps,txpbl = <16>;
950			snps,rxpbl = <16>;
951			starfive,syscon = <&sys_syscon 0x90 0x2>;
952			status = "disabled";
953		};
954
955		dma: dma-controller@16050000 {
956			compatible = "starfive,jh7110-axi-dma";
957			reg = <0x0 0x16050000 0x0 0x10000>;
958			clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
959				 <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
960			clock-names = "core-clk", "cfgr-clk";
961			resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
962				 <&stgcrg JH7110_STGRST_DMA1P_AHB>;
963			interrupts = <73>;
964			#dma-cells = <1>;
965			dma-channels = <4>;
966			snps,dma-masters = <1>;
967			snps,data-width = <3>;
968			snps,block-size = <65536 65536 65536 65536>;
969			snps,priority = <0 1 2 3>;
970			snps,axi-max-burst-len = <16>;
971		};
972
973		aoncrg: clock-controller@17000000 {
974			compatible = "starfive,jh7110-aoncrg";
975			reg = <0x0 0x17000000 0x0 0x10000>;
976			clocks = <&osc>, <&gmac0_rmii_refin>,
977				 <&gmac0_rgmii_rxin>,
978				 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
979				 <&syscrg JH7110_SYSCLK_APB_BUS>,
980				 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
981				 <&rtc_osc>;
982			clock-names = "osc", "gmac0_rmii_refin",
983				      "gmac0_rgmii_rxin", "stg_axiahb",
984				      "apb_bus", "gmac0_gtxclk",
985				      "rtc_osc";
986			#clock-cells = <1>;
987			#reset-cells = <1>;
988		};
989
990		aon_syscon: syscon@17010000 {
991			compatible = "starfive,jh7110-aon-syscon", "syscon";
992			reg = <0x0 0x17010000 0x0 0x1000>;
993			#power-domain-cells = <1>;
994		};
995
996		aongpio: pinctrl@17020000 {
997			compatible = "starfive,jh7110-aon-pinctrl";
998			reg = <0x0 0x17020000 0x0 0x10000>;
999			resets = <&aoncrg JH7110_AONRST_IOMUX>;
1000			interrupts = <85>;
1001			interrupt-controller;
1002			#interrupt-cells = <2>;
1003			gpio-controller;
1004			#gpio-cells = <2>;
1005		};
1006
1007		pwrc: power-controller@17030000 {
1008			compatible = "starfive,jh7110-pmu";
1009			reg = <0x0 0x17030000 0x0 0x10000>;
1010			interrupts = <111>;
1011			#power-domain-cells = <1>;
1012		};
1013
1014		ispcrg: clock-controller@19810000 {
1015			compatible = "starfive,jh7110-ispcrg";
1016			reg = <0x0 0x19810000 0x0 0x10000>;
1017			clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
1018				 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
1019				 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
1020				 <&dvp_clk>;
1021			clock-names = "isp_top_core", "isp_top_axi",
1022				      "noc_bus_isp_axi", "dvp_clk";
1023			resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
1024				 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
1025				 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
1026			#clock-cells = <1>;
1027			#reset-cells = <1>;
1028			power-domains = <&pwrc JH7110_PD_ISP>;
1029		};
1030
1031		voutcrg: clock-controller@295c0000 {
1032			compatible = "starfive,jh7110-voutcrg";
1033			reg = <0x0 0x295c0000 0x0 0x10000>;
1034			clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
1035				 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
1036				 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
1037				 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
1038				 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
1039				 <&hdmitx0_pixelclk>;
1040			clock-names = "vout_src", "vout_top_ahb",
1041				      "vout_top_axi", "vout_top_hdmitx0_mclk",
1042				      "i2stx0_bclk", "hdmitx0_pixelclk";
1043			resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
1044			#clock-cells = <1>;
1045			#reset-cells = <1>;
1046			power-domains = <&pwrc JH7110_PD_VOUT>;
1047		};
1048	};
1049};
1050