1a4095516SStefan Roese/* 2a4095516SStefan Roese * Device Tree Source for AMCC Haleakala (405EXr) 3a4095516SStefan Roese * 4a4095516SStefan Roese * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> 5a4095516SStefan Roese * 6a4095516SStefan Roese * This file is licensed under the terms of the GNU General Public 7a4095516SStefan Roese * License version 2. This program is licensed "as is" without 8a4095516SStefan Roese * any warranty of any kind, whether express or implied. 9a4095516SStefan Roese */ 10a4095516SStefan Roese 11a4095516SStefan Roese/ { 12a4095516SStefan Roese #address-cells = <1>; 13a4095516SStefan Roese #size-cells = <1>; 14a4095516SStefan Roese model = "amcc,haleakala"; 15a4095516SStefan Roese compatible = "amcc,kilauea"; 16a4095516SStefan Roese dcr-parent = <&/cpus/cpu@0>; 17a4095516SStefan Roese 18a4095516SStefan Roese aliases { 19a4095516SStefan Roese ethernet0 = &EMAC0; 20a4095516SStefan Roese serial0 = &UART0; 21a4095516SStefan Roese serial1 = &UART1; 22a4095516SStefan Roese }; 23a4095516SStefan Roese 24a4095516SStefan Roese cpus { 25a4095516SStefan Roese #address-cells = <1>; 26a4095516SStefan Roese #size-cells = <0>; 27a4095516SStefan Roese 28a4095516SStefan Roese cpu@0 { 29a4095516SStefan Roese device_type = "cpu"; 30a4095516SStefan Roese model = "PowerPC,405EXr"; 31a4095516SStefan Roese reg = <0>; 32a4095516SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 33a4095516SStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 34a4095516SStefan Roese i-cache-line-size = <20>; 35a4095516SStefan Roese d-cache-line-size = <20>; 36a4095516SStefan Roese i-cache-size = <4000>; /* 16 kB */ 37a4095516SStefan Roese d-cache-size = <4000>; /* 16 kB */ 38a4095516SStefan Roese dcr-controller; 39a4095516SStefan Roese dcr-access-method = "native"; 40a4095516SStefan Roese }; 41a4095516SStefan Roese }; 42a4095516SStefan Roese 43a4095516SStefan Roese memory { 44a4095516SStefan Roese device_type = "memory"; 45a4095516SStefan Roese reg = <0 0>; /* Filled in by U-Boot */ 46a4095516SStefan Roese }; 47a4095516SStefan Roese 48a4095516SStefan Roese UIC0: interrupt-controller { 49a4095516SStefan Roese compatible = "ibm,uic-405exr", "ibm,uic"; 50a4095516SStefan Roese interrupt-controller; 51a4095516SStefan Roese cell-index = <0>; 52a4095516SStefan Roese dcr-reg = <0c0 009>; 53a4095516SStefan Roese #address-cells = <0>; 54a4095516SStefan Roese #size-cells = <0>; 55a4095516SStefan Roese #interrupt-cells = <2>; 56a4095516SStefan Roese }; 57a4095516SStefan Roese 58a4095516SStefan Roese UIC1: interrupt-controller1 { 59a4095516SStefan Roese compatible = "ibm,uic-405exr","ibm,uic"; 60a4095516SStefan Roese interrupt-controller; 61a4095516SStefan Roese cell-index = <1>; 62a4095516SStefan Roese dcr-reg = <0d0 009>; 63a4095516SStefan Roese #address-cells = <0>; 64a4095516SStefan Roese #size-cells = <0>; 65a4095516SStefan Roese #interrupt-cells = <2>; 66a4095516SStefan Roese interrupts = <1e 4 1f 4>; /* cascade */ 67a4095516SStefan Roese interrupt-parent = <&UIC0>; 68a4095516SStefan Roese }; 69a4095516SStefan Roese 70a4095516SStefan Roese UIC2: interrupt-controller2 { 71a4095516SStefan Roese compatible = "ibm,uic-405exr","ibm,uic"; 72a4095516SStefan Roese interrupt-controller; 73a4095516SStefan Roese cell-index = <2>; 74a4095516SStefan Roese dcr-reg = <0e0 009>; 75a4095516SStefan Roese #address-cells = <0>; 76a4095516SStefan Roese #size-cells = <0>; 77a4095516SStefan Roese #interrupt-cells = <2>; 78a4095516SStefan Roese interrupts = <1c 4 1d 4>; /* cascade */ 79a4095516SStefan Roese interrupt-parent = <&UIC0>; 80a4095516SStefan Roese }; 81a4095516SStefan Roese 82a4095516SStefan Roese plb { 83a4095516SStefan Roese compatible = "ibm,plb-405exr", "ibm,plb4"; 84a4095516SStefan Roese #address-cells = <1>; 85a4095516SStefan Roese #size-cells = <1>; 86a4095516SStefan Roese ranges; 87a4095516SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 88a4095516SStefan Roese 89a4095516SStefan Roese SDRAM0: memory-controller { 90a4095516SStefan Roese compatible = "ibm,sdram-405exr"; 91a4095516SStefan Roese dcr-reg = <010 2>; 92a4095516SStefan Roese }; 93a4095516SStefan Roese 94a4095516SStefan Roese MAL0: mcmal { 95a4095516SStefan Roese compatible = "ibm,mcmal-405exr", "ibm,mcmal2"; 96a4095516SStefan Roese dcr-reg = <180 62>; 97a4095516SStefan Roese num-tx-chans = <2>; 98a4095516SStefan Roese num-rx-chans = <2>; 99a4095516SStefan Roese interrupt-parent = <&MAL0>; 100a4095516SStefan Roese interrupts = <0 1 2 3 4>; 101a4095516SStefan Roese #interrupt-cells = <1>; 102a4095516SStefan Roese #address-cells = <0>; 103a4095516SStefan Roese #size-cells = <0>; 104a4095516SStefan Roese interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 105a4095516SStefan Roese /*RXEOB*/ 1 &UIC0 b 4 106a4095516SStefan Roese /*SERR*/ 2 &UIC1 0 4 107a4095516SStefan Roese /*TXDE*/ 3 &UIC1 1 4 108a4095516SStefan Roese /*RXDE*/ 4 &UIC1 2 4>; 109a4095516SStefan Roese interrupt-map-mask = <ffffffff>; 110a4095516SStefan Roese }; 111a4095516SStefan Roese 112a4095516SStefan Roese POB0: opb { 113a4095516SStefan Roese compatible = "ibm,opb-405exr", "ibm,opb"; 114a4095516SStefan Roese #address-cells = <1>; 115a4095516SStefan Roese #size-cells = <1>; 116a4095516SStefan Roese ranges = <80000000 80000000 10000000 117a4095516SStefan Roese ef600000 ef600000 a00000 118a4095516SStefan Roese f0000000 f0000000 10000000>; 119a4095516SStefan Roese dcr-reg = <0a0 5>; 120a4095516SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 121a4095516SStefan Roese 122a4095516SStefan Roese EBC0: ebc { 123a4095516SStefan Roese compatible = "ibm,ebc-405exr", "ibm,ebc"; 124a4095516SStefan Roese dcr-reg = <012 2>; 125a4095516SStefan Roese #address-cells = <2>; 126a4095516SStefan Roese #size-cells = <1>; 127a4095516SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 128a4095516SStefan Roese /* ranges property is supplied by U-Boot */ 129a4095516SStefan Roese interrupts = <5 1>; 130a4095516SStefan Roese interrupt-parent = <&UIC1>; 131a4095516SStefan Roese 132a4095516SStefan Roese nor_flash@0,0 { 133a4095516SStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 134a4095516SStefan Roese bank-width = <2>; 135a4095516SStefan Roese reg = <0 000000 4000000>; 136a4095516SStefan Roese #address-cells = <1>; 137a4095516SStefan Roese #size-cells = <1>; 138a4095516SStefan Roese partition@0 { 139a4095516SStefan Roese label = "kernel"; 140a4095516SStefan Roese reg = <0 200000>; 141a4095516SStefan Roese }; 142a4095516SStefan Roese partition@200000 { 143a4095516SStefan Roese label = "root"; 144a4095516SStefan Roese reg = <200000 200000>; 145a4095516SStefan Roese }; 146a4095516SStefan Roese partition@400000 { 147a4095516SStefan Roese label = "user"; 148a4095516SStefan Roese reg = <400000 3b60000>; 149a4095516SStefan Roese }; 150a4095516SStefan Roese partition@3f60000 { 151a4095516SStefan Roese label = "env"; 152a4095516SStefan Roese reg = <3f60000 40000>; 153a4095516SStefan Roese }; 154a4095516SStefan Roese partition@3fa0000 { 155a4095516SStefan Roese label = "u-boot"; 156a4095516SStefan Roese reg = <3fa0000 60000>; 157a4095516SStefan Roese }; 158a4095516SStefan Roese }; 159a4095516SStefan Roese }; 160a4095516SStefan Roese 161a4095516SStefan Roese UART0: serial@ef600200 { 162a4095516SStefan Roese device_type = "serial"; 163a4095516SStefan Roese compatible = "ns16550"; 164a4095516SStefan Roese reg = <ef600200 8>; 165a4095516SStefan Roese virtual-reg = <ef600200>; 166a4095516SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 167a4095516SStefan Roese current-speed = <0>; 168a4095516SStefan Roese interrupt-parent = <&UIC0>; 169a4095516SStefan Roese interrupts = <1a 4>; 170a4095516SStefan Roese }; 171a4095516SStefan Roese 172a4095516SStefan Roese UART1: serial@ef600300 { 173a4095516SStefan Roese device_type = "serial"; 174a4095516SStefan Roese compatible = "ns16550"; 175a4095516SStefan Roese reg = <ef600300 8>; 176a4095516SStefan Roese virtual-reg = <ef600300>; 177a4095516SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 178a4095516SStefan Roese current-speed = <0>; 179a4095516SStefan Roese interrupt-parent = <&UIC0>; 180a4095516SStefan Roese interrupts = <1 4>; 181a4095516SStefan Roese }; 182a4095516SStefan Roese 183a4095516SStefan Roese IIC0: i2c@ef600400 { 184a4095516SStefan Roese compatible = "ibm,iic-405exr", "ibm,iic"; 185a4095516SStefan Roese reg = <ef600400 14>; 186a4095516SStefan Roese interrupt-parent = <&UIC0>; 187a4095516SStefan Roese interrupts = <2 4>; 188a4095516SStefan Roese }; 189a4095516SStefan Roese 190a4095516SStefan Roese IIC1: i2c@ef600500 { 191a4095516SStefan Roese compatible = "ibm,iic-405exr", "ibm,iic"; 192a4095516SStefan Roese reg = <ef600500 14>; 193a4095516SStefan Roese interrupt-parent = <&UIC0>; 194a4095516SStefan Roese interrupts = <7 4>; 195a4095516SStefan Roese }; 196a4095516SStefan Roese 197a4095516SStefan Roese 198a4095516SStefan Roese RGMII0: emac-rgmii@ef600b00 { 199a4095516SStefan Roese compatible = "ibm,rgmii-405exr", "ibm,rgmii"; 200a4095516SStefan Roese reg = <ef600b00 104>; 201a4095516SStefan Roese has-mdio; 202a4095516SStefan Roese }; 203a4095516SStefan Roese 204a4095516SStefan Roese EMAC0: ethernet@ef600900 { 205a4095516SStefan Roese linux,network-index = <0>; 206a4095516SStefan Roese device_type = "network"; 207a4095516SStefan Roese compatible = "ibm,emac-405exr", "ibm,emac4"; 208a4095516SStefan Roese interrupt-parent = <&EMAC0>; 209a4095516SStefan Roese interrupts = <0 1>; 210a4095516SStefan Roese #interrupt-cells = <1>; 211a4095516SStefan Roese #address-cells = <0>; 212a4095516SStefan Roese #size-cells = <0>; 213a4095516SStefan Roese interrupt-map = </*Status*/ 0 &UIC0 18 4 214a4095516SStefan Roese /*Wake*/ 1 &UIC1 1d 4>; 215a4095516SStefan Roese reg = <ef600900 70>; 216a4095516SStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 217a4095516SStefan Roese mal-device = <&MAL0>; 218a4095516SStefan Roese mal-tx-channel = <0>; 219a4095516SStefan Roese mal-rx-channel = <0>; 220a4095516SStefan Roese cell-index = <0>; 221a4095516SStefan Roese max-frame-size = <5dc>; 222a4095516SStefan Roese rx-fifo-size = <1000>; 223a4095516SStefan Roese tx-fifo-size = <800>; 224a4095516SStefan Roese phy-mode = "rgmii"; 225a4095516SStefan Roese phy-map = <00000000>; 226a4095516SStefan Roese rgmii-device = <&RGMII0>; 227a4095516SStefan Roese rgmii-channel = <0>; 228a4095516SStefan Roese has-inverted-stacr-oc; 229a4095516SStefan Roese has-new-stacr-staopc; 230a4095516SStefan Roese }; 231a4095516SStefan Roese }; 232a4095516SStefan Roese 233a4095516SStefan Roese PCIE0: pciex@0a0000000 { 234a4095516SStefan Roese device_type = "pci"; 235a4095516SStefan Roese #interrupt-cells = <1>; 236a4095516SStefan Roese #size-cells = <2>; 237a4095516SStefan Roese #address-cells = <3>; 238e33eb074SStefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 239a4095516SStefan Roese primary; 240a4095516SStefan Roese port = <0>; /* port number */ 241a4095516SStefan Roese reg = <a0000000 20000000 /* Config space access */ 242a4095516SStefan Roese ef000000 00001000>; /* Registers */ 243a4095516SStefan Roese dcr-reg = <040 020>; 244a4095516SStefan Roese sdr-base = <400>; 245a4095516SStefan Roese 246a4095516SStefan Roese /* Outbound ranges, one memory and one IO, 247a4095516SStefan Roese * later cannot be changed 248a4095516SStefan Roese */ 249a4095516SStefan Roese ranges = <02000000 0 80000000 90000000 0 08000000 250a4095516SStefan Roese 01000000 0 00000000 e0000000 0 00010000>; 251a4095516SStefan Roese 252a4095516SStefan Roese /* Inbound 2GB range starting at 0 */ 253a4095516SStefan Roese dma-ranges = <42000000 0 0 0 0 80000000>; 254a4095516SStefan Roese 255a4095516SStefan Roese /* This drives busses 0x00 to 0x3f */ 256a4095516SStefan Roese bus-range = <00 3f>; 257a4095516SStefan Roese 258a4095516SStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 259a4095516SStefan Roese * to invert PCIe legacy interrupts). 260a4095516SStefan Roese * We are de-swizzling here because the numbers are actually for 261a4095516SStefan Roese * port of the root complex virtual P2P bridge. But I want 262a4095516SStefan Roese * to avoid putting a node for it in the tree, so the numbers 263a4095516SStefan Roese * below are basically de-swizzled numbers. 264a4095516SStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 265a4095516SStefan Roese */ 266a4095516SStefan Roese interrupt-map-mask = <0000 0 0 7>; 267a4095516SStefan Roese interrupt-map = < 268a4095516SStefan Roese 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ 269a4095516SStefan Roese 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ 270a4095516SStefan Roese 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ 271a4095516SStefan Roese 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; 272a4095516SStefan Roese }; 273a4095516SStefan Roese }; 274a4095516SStefan Roese}; 275