1a4095516SStefan Roese/* 2a4095516SStefan Roese * Device Tree Source for AMCC Haleakala (405EXr) 3a4095516SStefan Roese * 4a4095516SStefan Roese * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> 5a4095516SStefan Roese * 6a4095516SStefan Roese * This file is licensed under the terms of the GNU General Public 7a4095516SStefan Roese * License version 2. This program is licensed "as is" without 8a4095516SStefan Roese * any warranty of any kind, whether express or implied. 9a4095516SStefan Roese */ 10a4095516SStefan Roese 1171f34979SDavid Gibson/dts-v1/; 1271f34979SDavid Gibson 13a4095516SStefan Roese/ { 14a4095516SStefan Roese #address-cells = <1>; 15a4095516SStefan Roese #size-cells = <1>; 16a4095516SStefan Roese model = "amcc,haleakala"; 17145692a7SStefan Roese compatible = "amcc,haleakala", "amcc,kilauea"; 1871f34979SDavid Gibson dcr-parent = <&{/cpus/cpu@0}>; 19a4095516SStefan Roese 20a4095516SStefan Roese aliases { 21a4095516SStefan Roese ethernet0 = &EMAC0; 22a4095516SStefan Roese serial0 = &UART0; 23a4095516SStefan Roese serial1 = &UART1; 24a4095516SStefan Roese }; 25a4095516SStefan Roese 26a4095516SStefan Roese cpus { 27a4095516SStefan Roese #address-cells = <1>; 28a4095516SStefan Roese #size-cells = <0>; 29a4095516SStefan Roese 30a4095516SStefan Roese cpu@0 { 31a4095516SStefan Roese device_type = "cpu"; 32a4095516SStefan Roese model = "PowerPC,405EXr"; 3371f34979SDavid Gibson reg = <0x00000000>; 34a4095516SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 35a4095516SStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 3671f34979SDavid Gibson i-cache-line-size = <32>; 3771f34979SDavid Gibson d-cache-line-size = <32>; 3871f34979SDavid Gibson i-cache-size = <16384>; /* 16 kB */ 3971f34979SDavid Gibson d-cache-size = <16384>; /* 16 kB */ 40a4095516SStefan Roese dcr-controller; 41a4095516SStefan Roese dcr-access-method = "native"; 42a4095516SStefan Roese }; 43a4095516SStefan Roese }; 44a4095516SStefan Roese 45a4095516SStefan Roese memory { 46a4095516SStefan Roese device_type = "memory"; 4771f34979SDavid Gibson reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ 48a4095516SStefan Roese }; 49a4095516SStefan Roese 50a4095516SStefan Roese UIC0: interrupt-controller { 51a4095516SStefan Roese compatible = "ibm,uic-405exr", "ibm,uic"; 52a4095516SStefan Roese interrupt-controller; 53a4095516SStefan Roese cell-index = <0>; 5471f34979SDavid Gibson dcr-reg = <0x0c0 0x009>; 55a4095516SStefan Roese #address-cells = <0>; 56a4095516SStefan Roese #size-cells = <0>; 57a4095516SStefan Roese #interrupt-cells = <2>; 58a4095516SStefan Roese }; 59a4095516SStefan Roese 60a4095516SStefan Roese UIC1: interrupt-controller1 { 61a4095516SStefan Roese compatible = "ibm,uic-405exr","ibm,uic"; 62a4095516SStefan Roese interrupt-controller; 63a4095516SStefan Roese cell-index = <1>; 6471f34979SDavid Gibson dcr-reg = <0x0d0 0x009>; 65a4095516SStefan Roese #address-cells = <0>; 66a4095516SStefan Roese #size-cells = <0>; 67a4095516SStefan Roese #interrupt-cells = <2>; 6871f34979SDavid Gibson interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 69a4095516SStefan Roese interrupt-parent = <&UIC0>; 70a4095516SStefan Roese }; 71a4095516SStefan Roese 72a4095516SStefan Roese UIC2: interrupt-controller2 { 73a4095516SStefan Roese compatible = "ibm,uic-405exr","ibm,uic"; 74a4095516SStefan Roese interrupt-controller; 75a4095516SStefan Roese cell-index = <2>; 7671f34979SDavid Gibson dcr-reg = <0x0e0 0x009>; 77a4095516SStefan Roese #address-cells = <0>; 78a4095516SStefan Roese #size-cells = <0>; 79a4095516SStefan Roese #interrupt-cells = <2>; 8071f34979SDavid Gibson interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ 81a4095516SStefan Roese interrupt-parent = <&UIC0>; 82a4095516SStefan Roese }; 83a4095516SStefan Roese 84a4095516SStefan Roese plb { 85a4095516SStefan Roese compatible = "ibm,plb-405exr", "ibm,plb4"; 86a4095516SStefan Roese #address-cells = <1>; 87a4095516SStefan Roese #size-cells = <1>; 88a4095516SStefan Roese ranges; 89a4095516SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 90a4095516SStefan Roese 91a4095516SStefan Roese SDRAM0: memory-controller { 9294ce1c58SGrant Erickson compatible = "ibm,sdram-405exr", "ibm,sdram-4xx-ddr2"; 9371f34979SDavid Gibson dcr-reg = <0x010 0x002>; 9494ce1c58SGrant Erickson interrupt-parent = <&UIC2>; 9594ce1c58SGrant Erickson interrupts = <0x5 0x4 /* ECC DED Error */ 9694ce1c58SGrant Erickson 0x6 0x4>; /* ECC SEC Error */ 97a4095516SStefan Roese }; 98a4095516SStefan Roese 99a4095516SStefan Roese MAL0: mcmal { 100a4095516SStefan Roese compatible = "ibm,mcmal-405exr", "ibm,mcmal2"; 10171f34979SDavid Gibson dcr-reg = <0x180 0x062>; 102a4095516SStefan Roese num-tx-chans = <2>; 103a4095516SStefan Roese num-rx-chans = <2>; 104a4095516SStefan Roese interrupt-parent = <&MAL0>; 10571f34979SDavid Gibson interrupts = <0x0 0x1 0x2 0x3 0x4>; 106a4095516SStefan Roese #interrupt-cells = <1>; 107a4095516SStefan Roese #address-cells = <0>; 108a4095516SStefan Roese #size-cells = <0>; 10971f34979SDavid Gibson interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 11071f34979SDavid Gibson /*RXEOB*/ 0x1 &UIC0 0xb 0x4 11171f34979SDavid Gibson /*SERR*/ 0x2 &UIC1 0x0 0x4 11271f34979SDavid Gibson /*TXDE*/ 0x3 &UIC1 0x1 0x4 11371f34979SDavid Gibson /*RXDE*/ 0x4 &UIC1 0x2 0x4>; 11471f34979SDavid Gibson interrupt-map-mask = <0xffffffff>; 115a4095516SStefan Roese }; 116a4095516SStefan Roese 117a4095516SStefan Roese POB0: opb { 118a4095516SStefan Roese compatible = "ibm,opb-405exr", "ibm,opb"; 119a4095516SStefan Roese #address-cells = <1>; 120a4095516SStefan Roese #size-cells = <1>; 12171f34979SDavid Gibson ranges = <0x80000000 0x80000000 0x10000000 12271f34979SDavid Gibson 0xef600000 0xef600000 0x00a00000 12371f34979SDavid Gibson 0xf0000000 0xf0000000 0x10000000>; 12471f34979SDavid Gibson dcr-reg = <0x0a0 0x005>; 125a4095516SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 126a4095516SStefan Roese 127a4095516SStefan Roese EBC0: ebc { 128a4095516SStefan Roese compatible = "ibm,ebc-405exr", "ibm,ebc"; 12971f34979SDavid Gibson dcr-reg = <0x012 0x002>; 130a4095516SStefan Roese #address-cells = <2>; 131a4095516SStefan Roese #size-cells = <1>; 132a4095516SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 133a4095516SStefan Roese /* ranges property is supplied by U-Boot */ 13471f34979SDavid Gibson interrupts = <0x5 0x1>; 135a4095516SStefan Roese interrupt-parent = <&UIC1>; 136a4095516SStefan Roese 137a4095516SStefan Roese nor_flash@0,0 { 138a4095516SStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 139a4095516SStefan Roese bank-width = <2>; 14071f34979SDavid Gibson reg = <0x00000000 0x00000000 0x04000000>; 141a4095516SStefan Roese #address-cells = <1>; 142a4095516SStefan Roese #size-cells = <1>; 143a4095516SStefan Roese partition@0 { 144a4095516SStefan Roese label = "kernel"; 14571f34979SDavid Gibson reg = <0x00000000 0x00200000>; 146a4095516SStefan Roese }; 147a4095516SStefan Roese partition@200000 { 148a4095516SStefan Roese label = "root"; 14971f34979SDavid Gibson reg = <0x00200000 0x00200000>; 150a4095516SStefan Roese }; 151a4095516SStefan Roese partition@400000 { 152a4095516SStefan Roese label = "user"; 15371f34979SDavid Gibson reg = <0x00400000 0x03b60000>; 154a4095516SStefan Roese }; 155a4095516SStefan Roese partition@3f60000 { 156a4095516SStefan Roese label = "env"; 15771f34979SDavid Gibson reg = <0x03f60000 0x00040000>; 158a4095516SStefan Roese }; 159a4095516SStefan Roese partition@3fa0000 { 160a4095516SStefan Roese label = "u-boot"; 16171f34979SDavid Gibson reg = <0x03fa0000 0x00060000>; 162a4095516SStefan Roese }; 163a4095516SStefan Roese }; 164a4095516SStefan Roese }; 165a4095516SStefan Roese 166a4095516SStefan Roese UART0: serial@ef600200 { 167a4095516SStefan Roese device_type = "serial"; 168a4095516SStefan Roese compatible = "ns16550"; 16971f34979SDavid Gibson reg = <0xef600200 0x00000008>; 17071f34979SDavid Gibson virtual-reg = <0xef600200>; 171a4095516SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 172a4095516SStefan Roese current-speed = <0>; 173a4095516SStefan Roese interrupt-parent = <&UIC0>; 17471f34979SDavid Gibson interrupts = <0x1a 0x4>; 175a4095516SStefan Roese }; 176a4095516SStefan Roese 177a4095516SStefan Roese UART1: serial@ef600300 { 178a4095516SStefan Roese device_type = "serial"; 179a4095516SStefan Roese compatible = "ns16550"; 18071f34979SDavid Gibson reg = <0xef600300 0x00000008>; 18171f34979SDavid Gibson virtual-reg = <0xef600300>; 182a4095516SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 183a4095516SStefan Roese current-speed = <0>; 184a4095516SStefan Roese interrupt-parent = <&UIC0>; 18571f34979SDavid Gibson interrupts = <0x1 0x4>; 186a4095516SStefan Roese }; 187a4095516SStefan Roese 188a4095516SStefan Roese IIC0: i2c@ef600400 { 189a4095516SStefan Roese compatible = "ibm,iic-405exr", "ibm,iic"; 19071f34979SDavid Gibson reg = <0xef600400 0x00000014>; 191a4095516SStefan Roese interrupt-parent = <&UIC0>; 19271f34979SDavid Gibson interrupts = <0x2 0x4>; 193a4095516SStefan Roese }; 194a4095516SStefan Roese 195a4095516SStefan Roese IIC1: i2c@ef600500 { 196a4095516SStefan Roese compatible = "ibm,iic-405exr", "ibm,iic"; 19771f34979SDavid Gibson reg = <0xef600500 0x00000014>; 198a4095516SStefan Roese interrupt-parent = <&UIC0>; 19971f34979SDavid Gibson interrupts = <0x7 0x4>; 200a4095516SStefan Roese }; 201a4095516SStefan Roese 202a4095516SStefan Roese 203a4095516SStefan Roese RGMII0: emac-rgmii@ef600b00 { 204a4095516SStefan Roese compatible = "ibm,rgmii-405exr", "ibm,rgmii"; 20571f34979SDavid Gibson reg = <0xef600b00 0x00000104>; 206a4095516SStefan Roese has-mdio; 207a4095516SStefan Roese }; 208a4095516SStefan Roese 209a4095516SStefan Roese EMAC0: ethernet@ef600900 { 21071f34979SDavid Gibson linux,network-index = <0x0>; 211a4095516SStefan Roese device_type = "network"; 21205781ccdSGrant Erickson compatible = "ibm,emac-405exr", "ibm,emac4sync"; 213a4095516SStefan Roese interrupt-parent = <&EMAC0>; 21471f34979SDavid Gibson interrupts = <0x0 0x1>; 215a4095516SStefan Roese #interrupt-cells = <1>; 216a4095516SStefan Roese #address-cells = <0>; 217a4095516SStefan Roese #size-cells = <0>; 21871f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4 21971f34979SDavid Gibson /*Wake*/ 0x1 &UIC1 0x1d 0x4>; 22005781ccdSGrant Erickson reg = <0xef600900 0x000000c4>; 221a4095516SStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 222a4095516SStefan Roese mal-device = <&MAL0>; 223a4095516SStefan Roese mal-tx-channel = <0>; 224a4095516SStefan Roese mal-rx-channel = <0>; 225a4095516SStefan Roese cell-index = <0>; 22671f34979SDavid Gibson max-frame-size = <9000>; 22771f34979SDavid Gibson rx-fifo-size = <4096>; 22871f34979SDavid Gibson tx-fifo-size = <2048>; 229835ad8e7SDave Mitchell rx-fifo-size-gige = <16384>; 230835ad8e7SDave Mitchell tx-fifo-size-gige = <16384>; 231a4095516SStefan Roese phy-mode = "rgmii"; 23271f34979SDavid Gibson phy-map = <0x00000000>; 233a4095516SStefan Roese rgmii-device = <&RGMII0>; 234a4095516SStefan Roese rgmii-channel = <0>; 235a4095516SStefan Roese has-inverted-stacr-oc; 236a4095516SStefan Roese has-new-stacr-staopc; 237a4095516SStefan Roese }; 238a4095516SStefan Roese }; 239a4095516SStefan Roese 24086bc917dSMichael Ellerman PCIE0: pcie@a0000000 { 241a4095516SStefan Roese device_type = "pci"; 242a4095516SStefan Roese #interrupt-cells = <1>; 243a4095516SStefan Roese #size-cells = <2>; 244a4095516SStefan Roese #address-cells = <3>; 245e33eb074SStefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 246a4095516SStefan Roese primary; 24771f34979SDavid Gibson port = <0x0>; /* port number */ 24871f34979SDavid Gibson reg = <0xa0000000 0x20000000 /* Config space access */ 24971f34979SDavid Gibson 0xef000000 0x00001000>; /* Registers */ 25071f34979SDavid Gibson dcr-reg = <0x040 0x020>; 25171f34979SDavid Gibson sdr-base = <0x400>; 252a4095516SStefan Roese 253a4095516SStefan Roese /* Outbound ranges, one memory and one IO, 254a4095516SStefan Roese * later cannot be changed 255a4095516SStefan Roese */ 25671f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 25771f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; 258a4095516SStefan Roese 259a4095516SStefan Roese /* Inbound 2GB range starting at 0 */ 26071f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; 261a4095516SStefan Roese 262a4095516SStefan Roese /* This drives busses 0x00 to 0x3f */ 26371f34979SDavid Gibson bus-range = <0x0 0x3f>; 264a4095516SStefan Roese 265a4095516SStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 266a4095516SStefan Roese * to invert PCIe legacy interrupts). 267a4095516SStefan Roese * We are de-swizzling here because the numbers are actually for 268a4095516SStefan Roese * port of the root complex virtual P2P bridge. But I want 269a4095516SStefan Roese * to avoid putting a node for it in the tree, so the numbers 270a4095516SStefan Roese * below are basically de-swizzled numbers. 271a4095516SStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 272a4095516SStefan Roese */ 27371f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 274a4095516SStefan Roese interrupt-map = < 27571f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ 27671f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ 27771f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ 27871f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; 279a4095516SStefan Roese }; 280a4095516SStefan Roese }; 281a4095516SStefan Roese}; 282