1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/gpio/gpio.h> 12#include "k3-j784s4.dtsi" 13 14/ { 15 compatible = "ti,j784s4-evm", "ti,j784s4"; 16 model = "Texas Instruments J784S4 EVM"; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 }; 21 22 aliases { 23 serial2 = &main_uart8; 24 mmc0 = &main_sdhci0; 25 mmc1 = &main_sdhci1; 26 i2c0 = &main_i2c0; 27 }; 28 29 memory@80000000 { 30 device_type = "memory"; 31 /* 32G RAM */ 32 reg = <0x00 0x80000000 0x00 0x80000000>, 33 <0x08 0x80000000 0x07 0x80000000>; 34 }; 35 36 reserved_memory: reserved-memory { 37 #address-cells = <2>; 38 #size-cells = <2>; 39 ranges; 40 41 secure_ddr: optee@9e800000 { 42 reg = <0x00 0x9e800000 0x00 0x01800000>; 43 no-map; 44 }; 45 46 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 47 compatible = "shared-dma-pool"; 48 reg = <0x00 0xa0000000 0x00 0x100000>; 49 no-map; 50 }; 51 52 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 53 compatible = "shared-dma-pool"; 54 reg = <0x00 0xa0100000 0x00 0xf00000>; 55 no-map; 56 }; 57 58 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 59 compatible = "shared-dma-pool"; 60 reg = <0x00 0xa1000000 0x00 0x100000>; 61 no-map; 62 }; 63 64 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 65 compatible = "shared-dma-pool"; 66 reg = <0x00 0xa1100000 0x00 0xf00000>; 67 no-map; 68 }; 69 70 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 71 compatible = "shared-dma-pool"; 72 reg = <0x00 0xa2000000 0x00 0x100000>; 73 no-map; 74 }; 75 76 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 77 compatible = "shared-dma-pool"; 78 reg = <0x00 0xa2100000 0x00 0xf00000>; 79 no-map; 80 }; 81 82 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 83 compatible = "shared-dma-pool"; 84 reg = <0x00 0xa3000000 0x00 0x100000>; 85 no-map; 86 }; 87 88 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 89 compatible = "shared-dma-pool"; 90 reg = <0x00 0xa3100000 0x00 0xf00000>; 91 no-map; 92 }; 93 94 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 95 compatible = "shared-dma-pool"; 96 reg = <0x00 0xa4000000 0x00 0x100000>; 97 no-map; 98 }; 99 100 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 101 compatible = "shared-dma-pool"; 102 reg = <0x00 0xa4100000 0x00 0xf00000>; 103 no-map; 104 }; 105 106 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 107 compatible = "shared-dma-pool"; 108 reg = <0x00 0xa5000000 0x00 0x100000>; 109 no-map; 110 }; 111 112 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 113 compatible = "shared-dma-pool"; 114 reg = <0x00 0xa5100000 0x00 0xf00000>; 115 no-map; 116 }; 117 118 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { 119 compatible = "shared-dma-pool"; 120 reg = <0x00 0xa6000000 0x00 0x100000>; 121 no-map; 122 }; 123 124 main_r5fss2_core0_memory_region: r5f-memory@a6100000 { 125 compatible = "shared-dma-pool"; 126 reg = <0x00 0xa6100000 0x00 0xf00000>; 127 no-map; 128 }; 129 130 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { 131 compatible = "shared-dma-pool"; 132 reg = <0x00 0xa7000000 0x00 0x100000>; 133 no-map; 134 }; 135 136 main_r5fss2_core1_memory_region: r5f-memory@a7100000 { 137 compatible = "shared-dma-pool"; 138 reg = <0x00 0xa7100000 0x00 0xf00000>; 139 no-map; 140 }; 141 142 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 143 compatible = "shared-dma-pool"; 144 reg = <0x00 0xa8000000 0x00 0x100000>; 145 no-map; 146 }; 147 148 c71_0_memory_region: c71-memory@a8100000 { 149 compatible = "shared-dma-pool"; 150 reg = <0x00 0xa8100000 0x00 0xf00000>; 151 no-map; 152 }; 153 154 c71_1_dma_memory_region: c71-dma-memory@a9000000 { 155 compatible = "shared-dma-pool"; 156 reg = <0x00 0xa9000000 0x00 0x100000>; 157 no-map; 158 }; 159 160 c71_1_memory_region: c71-memory@a9100000 { 161 compatible = "shared-dma-pool"; 162 reg = <0x00 0xa9100000 0x00 0xf00000>; 163 no-map; 164 }; 165 166 c71_2_dma_memory_region: c71-dma-memory@aa000000 { 167 compatible = "shared-dma-pool"; 168 reg = <0x00 0xaa000000 0x00 0x100000>; 169 no-map; 170 }; 171 172 c71_2_memory_region: c71-memory@aa100000 { 173 compatible = "shared-dma-pool"; 174 reg = <0x00 0xaa100000 0x00 0xf00000>; 175 no-map; 176 }; 177 178 c71_3_dma_memory_region: c71-dma-memory@ab000000 { 179 compatible = "shared-dma-pool"; 180 reg = <0x00 0xab000000 0x00 0x100000>; 181 no-map; 182 }; 183 184 c71_3_memory_region: c71-memory@ab100000 { 185 compatible = "shared-dma-pool"; 186 reg = <0x00 0xab100000 0x00 0xf00000>; 187 no-map; 188 }; 189 }; 190 191 evm_12v0: regulator-evm12v0 { 192 /* main supply */ 193 compatible = "regulator-fixed"; 194 regulator-name = "evm_12v0"; 195 regulator-min-microvolt = <12000000>; 196 regulator-max-microvolt = <12000000>; 197 regulator-always-on; 198 regulator-boot-on; 199 }; 200 201 vsys_3v3: regulator-vsys3v3 { 202 /* Output of LM5140 */ 203 compatible = "regulator-fixed"; 204 regulator-name = "vsys_3v3"; 205 regulator-min-microvolt = <3300000>; 206 regulator-max-microvolt = <3300000>; 207 vin-supply = <&evm_12v0>; 208 regulator-always-on; 209 regulator-boot-on; 210 }; 211 212 vsys_5v0: regulator-vsys5v0 { 213 /* Output of LM5140 */ 214 compatible = "regulator-fixed"; 215 regulator-name = "vsys_5v0"; 216 regulator-min-microvolt = <5000000>; 217 regulator-max-microvolt = <5000000>; 218 vin-supply = <&evm_12v0>; 219 regulator-always-on; 220 regulator-boot-on; 221 }; 222 223 vdd_mmc1: regulator-sd { 224 /* Output of TPS22918 */ 225 compatible = "regulator-fixed"; 226 regulator-name = "vdd_mmc1"; 227 regulator-min-microvolt = <3300000>; 228 regulator-max-microvolt = <3300000>; 229 regulator-boot-on; 230 enable-active-high; 231 vin-supply = <&vsys_3v3>; 232 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 233 }; 234 235 vdd_sd_dv: regulator-TLV71033 { 236 /* Output of TLV71033 */ 237 compatible = "regulator-gpio"; 238 regulator-name = "tlv71033"; 239 pinctrl-names = "default"; 240 pinctrl-0 = <&vdd_sd_dv_pins_default>; 241 regulator-min-microvolt = <1800000>; 242 regulator-max-microvolt = <3300000>; 243 regulator-boot-on; 244 vin-supply = <&vsys_5v0>; 245 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; 246 states = <1800000 0x0>, 247 <3300000 0x1>; 248 }; 249}; 250 251&main_pmx0 { 252 main_uart8_pins_default: main-uart8-pins-default { 253 pinctrl-single,pins = < 254 J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ 255 J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ 256 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 257 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ 258 >; 259 }; 260 261 main_i2c0_pins_default: main-i2c0-pins-default { 262 pinctrl-single,pins = < 263 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ 264 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ 265 >; 266 }; 267 268 main_mmc1_pins_default: main-mmc1-pins-default { 269 pinctrl-single,pins = < 270 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 271 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ 272 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ 273 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ 274 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ 275 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ 276 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ 277 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ 278 >; 279 }; 280 281 vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { 282 pinctrl-single,pins = < 283 J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ 284 >; 285 }; 286}; 287 288&wkup_pmx0 { 289 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 290 pinctrl-single,pins = < 291 J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 292 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 293 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 294 J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 295 J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 296 J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 297 J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 298 J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 299 J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 300 J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 301 J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 302 J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 303 >; 304 }; 305 306 mcu_mdio_pins_default: mcu-mdio-pins-default { 307 pinctrl-single,pins = < 308 J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 309 J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 310 >; 311 }; 312}; 313 314&main_uart8 { 315 status = "okay"; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&main_uart8_pins_default>; 318}; 319 320&main_i2c0 { 321 status = "okay"; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&main_i2c0_pins_default>; 324 325 clock-frequency = <400000>; 326 327 exp1: gpio@20 { 328 compatible = "ti,tca6416"; 329 reg = <0x20>; 330 gpio-controller; 331 #gpio-cells = <2>; 332 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ", 333 "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", 334 "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", 335 "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", 336 "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; 337 }; 338 339 exp2: gpio@22 { 340 compatible = "ti,tca6424"; 341 reg = <0x22>; 342 gpio-controller; 343 #gpio-cells = <2>; 344 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN", 345 "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", 346 "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", 347 "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", 348 "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", 349 "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", 350 "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", 351 "USER_INPUT1", "USER_LED1", "USER_LED2"; 352 }; 353}; 354 355&main_sdhci0 { 356 /* eMMC */ 357 status = "okay"; 358 non-removable; 359 ti,driver-strength-ohm = <50>; 360 disable-wp; 361}; 362 363&main_sdhci1 { 364 /* SD card */ 365 status = "okay"; 366 pinctrl-0 = <&main_mmc1_pins_default>; 367 pinctrl-names = "default"; 368 disable-wp; 369 vmmc-supply = <&vdd_mmc1>; 370 vqmmc-supply = <&vdd_sd_dv>; 371}; 372 373&main_gpio0 { 374 status = "okay"; 375}; 376 377&mcu_cpsw { 378 status = "okay"; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&mcu_cpsw_pins_default>; 381}; 382 383&davinci_mdio { 384 pinctrl-names = "default"; 385 pinctrl-0 = <&mcu_mdio_pins_default>; 386 387 mcu_phy0: ethernet-phy@0 { 388 reg = <0>; 389 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 390 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 391 ti,min-output-impedance; 392 }; 393}; 394 395&mcu_cpsw_port1 { 396 status = "okay"; 397 phy-mode = "rgmii-rxid"; 398 phy-handle = <&mcu_phy0>; 399}; 400 401&mailbox0_cluster0 { 402 status = "okay"; 403 interrupts = <436>; 404 405 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 406 ti,mbox-rx = <0 0 0>; 407 ti,mbox-tx = <1 0 0>; 408 }; 409 410 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 411 ti,mbox-rx = <2 0 0>; 412 ti,mbox-tx = <3 0 0>; 413 }; 414}; 415 416&mailbox0_cluster1 { 417 status = "okay"; 418 interrupts = <432>; 419 420 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 421 ti,mbox-rx = <0 0 0>; 422 ti,mbox-tx = <1 0 0>; 423 }; 424 425 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 426 ti,mbox-rx = <2 0 0>; 427 ti,mbox-tx = <3 0 0>; 428 }; 429}; 430 431&mailbox0_cluster2 { 432 status = "okay"; 433 interrupts = <428>; 434 435 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 436 ti,mbox-rx = <0 0 0>; 437 ti,mbox-tx = <1 0 0>; 438 }; 439 440 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 441 ti,mbox-rx = <2 0 0>; 442 ti,mbox-tx = <3 0 0>; 443 }; 444}; 445 446&mailbox0_cluster3 { 447 status = "okay"; 448 interrupts = <424>; 449 450 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { 451 ti,mbox-rx = <0 0 0>; 452 ti,mbox-tx = <1 0 0>; 453 }; 454 455 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { 456 ti,mbox-rx = <2 0 0>; 457 ti,mbox-tx = <3 0 0>; 458 }; 459}; 460 461&mailbox0_cluster4 { 462 status = "okay"; 463 interrupts = <420>; 464 465 mbox_c71_0: mbox-c71-0 { 466 ti,mbox-rx = <0 0 0>; 467 ti,mbox-tx = <1 0 0>; 468 }; 469 470 mbox_c71_1: mbox-c71-1 { 471 ti,mbox-rx = <2 0 0>; 472 ti,mbox-tx = <3 0 0>; 473 }; 474}; 475 476&mailbox0_cluster5 { 477 status = "okay"; 478 interrupts = <416>; 479 480 mbox_c71_2: mbox-c71-2 { 481 ti,mbox-rx = <0 0 0>; 482 ti,mbox-tx = <1 0 0>; 483 }; 484 485 mbox_c71_3: mbox-c71-3 { 486 ti,mbox-rx = <2 0 0>; 487 ti,mbox-tx = <3 0 0>; 488 }; 489}; 490 491&mcu_r5fss0_core0 { 492 status = "okay"; 493 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 494 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 495 <&mcu_r5fss0_core0_memory_region>; 496}; 497 498&mcu_r5fss0_core1 { 499 status = "okay"; 500 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 501 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 502 <&mcu_r5fss0_core1_memory_region>; 503}; 504 505&main_r5fss0_core0 { 506 status = "okay"; 507 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 508 memory-region = <&main_r5fss0_core0_dma_memory_region>, 509 <&main_r5fss0_core0_memory_region>; 510}; 511 512&main_r5fss0_core1 { 513 status = "okay"; 514 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 515 memory-region = <&main_r5fss0_core1_dma_memory_region>, 516 <&main_r5fss0_core1_memory_region>; 517}; 518 519&main_r5fss1_core0 { 520 status = "okay"; 521 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 522 memory-region = <&main_r5fss1_core0_dma_memory_region>, 523 <&main_r5fss1_core0_memory_region>; 524}; 525 526&main_r5fss1_core1 { 527 status = "okay"; 528 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 529 memory-region = <&main_r5fss1_core1_dma_memory_region>, 530 <&main_r5fss1_core1_memory_region>; 531}; 532 533&main_r5fss2_core0 { 534 status = "okay"; 535 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; 536 memory-region = <&main_r5fss2_core0_dma_memory_region>, 537 <&main_r5fss2_core0_memory_region>; 538}; 539 540&main_r5fss2_core1 { 541 status = "okay"; 542 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; 543 memory-region = <&main_r5fss2_core1_dma_memory_region>, 544 <&main_r5fss2_core1_memory_region>; 545}; 546 547&c71_0 { 548 status = "okay"; 549 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 550 memory-region = <&c71_0_dma_memory_region>, 551 <&c71_0_memory_region>; 552}; 553 554&c71_1 { 555 status = "okay"; 556 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 557 memory-region = <&c71_1_dma_memory_region>, 558 <&c71_1_memory_region>; 559}; 560 561&c71_2 { 562 status = "okay"; 563 mboxes = <&mailbox0_cluster5 &mbox_c71_2>; 564 memory-region = <&c71_2_dma_memory_region>, 565 <&c71_2_memory_region>; 566}; 567 568&c71_3 { 569 status = "okay"; 570 mboxes = <&mailbox0_cluster5 &mbox_c71_3>; 571 memory-region = <&c71_3_dma_memory_region>, 572 <&c71_3_memory_region>; 573}; 574