1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/gpio/gpio.h> 12#include "k3-j784s4.dtsi" 13 14/ { 15 compatible = "ti,j784s4-evm", "ti,j784s4"; 16 model = "Texas Instruments J784S4 EVM"; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 }; 21 22 aliases { 23 serial0 = &wkup_uart0; 24 serial1 = &mcu_uart0; 25 serial2 = &main_uart8; 26 mmc0 = &main_sdhci0; 27 mmc1 = &main_sdhci1; 28 i2c0 = &wkup_i2c0; 29 i2c3 = &main_i2c0; 30 }; 31 32 memory@80000000 { 33 device_type = "memory"; 34 /* 32G RAM */ 35 reg = <0x00 0x80000000 0x00 0x80000000>, 36 <0x08 0x80000000 0x07 0x80000000>; 37 }; 38 39 reserved_memory: reserved-memory { 40 #address-cells = <2>; 41 #size-cells = <2>; 42 ranges; 43 44 secure_ddr: optee@9e800000 { 45 reg = <0x00 0x9e800000 0x00 0x01800000>; 46 no-map; 47 }; 48 49 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 50 compatible = "shared-dma-pool"; 51 reg = <0x00 0xa0000000 0x00 0x100000>; 52 no-map; 53 }; 54 55 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 56 compatible = "shared-dma-pool"; 57 reg = <0x00 0xa0100000 0x00 0xf00000>; 58 no-map; 59 }; 60 61 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 62 compatible = "shared-dma-pool"; 63 reg = <0x00 0xa1000000 0x00 0x100000>; 64 no-map; 65 }; 66 67 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 68 compatible = "shared-dma-pool"; 69 reg = <0x00 0xa1100000 0x00 0xf00000>; 70 no-map; 71 }; 72 73 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 74 compatible = "shared-dma-pool"; 75 reg = <0x00 0xa2000000 0x00 0x100000>; 76 no-map; 77 }; 78 79 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 80 compatible = "shared-dma-pool"; 81 reg = <0x00 0xa2100000 0x00 0xf00000>; 82 no-map; 83 }; 84 85 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 86 compatible = "shared-dma-pool"; 87 reg = <0x00 0xa3000000 0x00 0x100000>; 88 no-map; 89 }; 90 91 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 92 compatible = "shared-dma-pool"; 93 reg = <0x00 0xa3100000 0x00 0xf00000>; 94 no-map; 95 }; 96 97 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 98 compatible = "shared-dma-pool"; 99 reg = <0x00 0xa4000000 0x00 0x100000>; 100 no-map; 101 }; 102 103 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 104 compatible = "shared-dma-pool"; 105 reg = <0x00 0xa4100000 0x00 0xf00000>; 106 no-map; 107 }; 108 109 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 110 compatible = "shared-dma-pool"; 111 reg = <0x00 0xa5000000 0x00 0x100000>; 112 no-map; 113 }; 114 115 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 116 compatible = "shared-dma-pool"; 117 reg = <0x00 0xa5100000 0x00 0xf00000>; 118 no-map; 119 }; 120 121 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { 122 compatible = "shared-dma-pool"; 123 reg = <0x00 0xa6000000 0x00 0x100000>; 124 no-map; 125 }; 126 127 main_r5fss2_core0_memory_region: r5f-memory@a6100000 { 128 compatible = "shared-dma-pool"; 129 reg = <0x00 0xa6100000 0x00 0xf00000>; 130 no-map; 131 }; 132 133 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { 134 compatible = "shared-dma-pool"; 135 reg = <0x00 0xa7000000 0x00 0x100000>; 136 no-map; 137 }; 138 139 main_r5fss2_core1_memory_region: r5f-memory@a7100000 { 140 compatible = "shared-dma-pool"; 141 reg = <0x00 0xa7100000 0x00 0xf00000>; 142 no-map; 143 }; 144 145 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 146 compatible = "shared-dma-pool"; 147 reg = <0x00 0xa8000000 0x00 0x100000>; 148 no-map; 149 }; 150 151 c71_0_memory_region: c71-memory@a8100000 { 152 compatible = "shared-dma-pool"; 153 reg = <0x00 0xa8100000 0x00 0xf00000>; 154 no-map; 155 }; 156 157 c71_1_dma_memory_region: c71-dma-memory@a9000000 { 158 compatible = "shared-dma-pool"; 159 reg = <0x00 0xa9000000 0x00 0x100000>; 160 no-map; 161 }; 162 163 c71_1_memory_region: c71-memory@a9100000 { 164 compatible = "shared-dma-pool"; 165 reg = <0x00 0xa9100000 0x00 0xf00000>; 166 no-map; 167 }; 168 169 c71_2_dma_memory_region: c71-dma-memory@aa000000 { 170 compatible = "shared-dma-pool"; 171 reg = <0x00 0xaa000000 0x00 0x100000>; 172 no-map; 173 }; 174 175 c71_2_memory_region: c71-memory@aa100000 { 176 compatible = "shared-dma-pool"; 177 reg = <0x00 0xaa100000 0x00 0xf00000>; 178 no-map; 179 }; 180 181 c71_3_dma_memory_region: c71-dma-memory@ab000000 { 182 compatible = "shared-dma-pool"; 183 reg = <0x00 0xab000000 0x00 0x100000>; 184 no-map; 185 }; 186 187 c71_3_memory_region: c71-memory@ab100000 { 188 compatible = "shared-dma-pool"; 189 reg = <0x00 0xab100000 0x00 0xf00000>; 190 no-map; 191 }; 192 }; 193 194 evm_12v0: regulator-evm12v0 { 195 /* main supply */ 196 compatible = "regulator-fixed"; 197 regulator-name = "evm_12v0"; 198 regulator-min-microvolt = <12000000>; 199 regulator-max-microvolt = <12000000>; 200 regulator-always-on; 201 regulator-boot-on; 202 }; 203 204 vsys_3v3: regulator-vsys3v3 { 205 /* Output of LM5140 */ 206 compatible = "regulator-fixed"; 207 regulator-name = "vsys_3v3"; 208 regulator-min-microvolt = <3300000>; 209 regulator-max-microvolt = <3300000>; 210 vin-supply = <&evm_12v0>; 211 regulator-always-on; 212 regulator-boot-on; 213 }; 214 215 vsys_5v0: regulator-vsys5v0 { 216 /* Output of LM5140 */ 217 compatible = "regulator-fixed"; 218 regulator-name = "vsys_5v0"; 219 regulator-min-microvolt = <5000000>; 220 regulator-max-microvolt = <5000000>; 221 vin-supply = <&evm_12v0>; 222 regulator-always-on; 223 regulator-boot-on; 224 }; 225 226 vdd_mmc1: regulator-sd { 227 /* Output of TPS22918 */ 228 compatible = "regulator-fixed"; 229 regulator-name = "vdd_mmc1"; 230 regulator-min-microvolt = <3300000>; 231 regulator-max-microvolt = <3300000>; 232 regulator-boot-on; 233 enable-active-high; 234 vin-supply = <&vsys_3v3>; 235 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 236 }; 237 238 vdd_sd_dv: regulator-TLV71033 { 239 /* Output of TLV71033 */ 240 compatible = "regulator-gpio"; 241 regulator-name = "tlv71033"; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&vdd_sd_dv_pins_default>; 244 regulator-min-microvolt = <1800000>; 245 regulator-max-microvolt = <3300000>; 246 regulator-boot-on; 247 vin-supply = <&vsys_5v0>; 248 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; 249 states = <1800000 0x0>, 250 <3300000 0x1>; 251 }; 252}; 253 254&main_pmx0 { 255 main_uart8_pins_default: main-uart8-default-pins { 256 pinctrl-single,pins = < 257 J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ 258 J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ 259 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 260 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ 261 >; 262 }; 263 264 main_i2c0_pins_default: main-i2c0-default-pins { 265 pinctrl-single,pins = < 266 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ 267 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ 268 >; 269 }; 270 271 main_mmc1_pins_default: main-mmc1-default-pins { 272 pinctrl-single,pins = < 273 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 274 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ 275 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ 276 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ 277 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ 278 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ 279 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ 280 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ 281 >; 282 }; 283 284 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 285 pinctrl-single,pins = < 286 J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ 287 >; 288 }; 289}; 290 291&wkup_pmx2 { 292 wkup_uart0_pins_default: wkup-uart0-default-pins { 293 pinctrl-single,pins = < 294 J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ 295 J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ 296 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ 297 J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ 298 >; 299 }; 300 301 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 302 pinctrl-single,pins = < 303 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ 304 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ 305 >; 306 }; 307 308 mcu_uart0_pins_default: mcu-uart0-default-pins { 309 pinctrl-single,pins = < 310 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ 311 J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ 312 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ 313 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ 314 >; 315 }; 316 317 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 318 pinctrl-single,pins = < 319 J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 320 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 321 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 322 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 323 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 324 J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 325 J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 326 J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 327 J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 328 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 329 J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 330 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 331 >; 332 }; 333 334 mcu_mdio_pins_default: mcu-mdio-default-pins { 335 pinctrl-single,pins = < 336 J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 337 J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 338 >; 339 }; 340 341 mcu_adc0_pins_default: mcu-adc0-default-pins { 342 pinctrl-single,pins = < 343 J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ 344 J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ 345 J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ 346 J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ 347 J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ 348 J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ 349 J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ 350 J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ 351 >; 352 }; 353 354 mcu_adc1_pins_default: mcu-adc1-default-pins { 355 pinctrl-single,pins = < 356 J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ 357 J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ 358 J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ 359 J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ 360 J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ 361 J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ 362 J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ 363 J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ 364 >; 365 }; 366}; 367 368&wkup_pmx0 { 369 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 370 pinctrl-single,pins = < 371 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ 372 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ 373 J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ 374 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ 375 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ 376 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ 377 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ 378 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ 379 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ 380 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ 381 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ 382 >; 383 }; 384}; 385 386&wkup_pmx1 { 387 mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { 388 pinctrl-single,pins = < 389 J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ 390 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ 391 >; 392 }; 393 394 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 395 pinctrl-single,pins = < 396 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ 397 J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ 398 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ 399 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ 400 J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ 401 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ 402 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ 403 J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ 404 >; 405 }; 406}; 407 408&wkup_uart0 { 409 /* Firmware usage */ 410 status = "reserved"; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&wkup_uart0_pins_default>; 413}; 414 415&wkup_i2c0 { 416 status = "okay"; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&wkup_i2c0_pins_default>; 419 clock-frequency = <400000>; 420 421 eeprom@50 { 422 /* CAV24C256WE-GT3 */ 423 compatible = "atmel,24c256"; 424 reg = <0x50>; 425 }; 426}; 427 428&mcu_uart0 { 429 status = "okay"; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&mcu_uart0_pins_default>; 432}; 433 434&main_uart8 { 435 status = "okay"; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&main_uart8_pins_default>; 438}; 439 440&ufs_wrapper { 441 status = "okay"; 442}; 443 444&fss { 445 status = "okay"; 446}; 447 448&ospi0 { 449 status = "okay"; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; 452 453 flash@0 { 454 compatible = "jedec,spi-nor"; 455 reg = <0x0>; 456 spi-tx-bus-width = <8>; 457 spi-rx-bus-width = <8>; 458 spi-max-frequency = <25000000>; 459 cdns,tshsl-ns = <60>; 460 cdns,tsd2d-ns = <60>; 461 cdns,tchsh-ns = <60>; 462 cdns,tslch-ns = <60>; 463 cdns,read-delay = <4>; 464 465 partitions { 466 compatible = "fixed-partitions"; 467 #address-cells = <1>; 468 #size-cells = <1>; 469 470 partition@0 { 471 label = "ospi.tiboot3"; 472 reg = <0x0 0x80000>; 473 }; 474 475 partition@80000 { 476 label = "ospi.tispl"; 477 reg = <0x80000 0x200000>; 478 }; 479 480 partition@280000 { 481 label = "ospi.u-boot"; 482 reg = <0x280000 0x400000>; 483 }; 484 485 partition@680000 { 486 label = "ospi.env"; 487 reg = <0x680000 0x40000>; 488 }; 489 490 partition@6c0000 { 491 label = "ospi.env.backup"; 492 reg = <0x6c0000 0x40000>; 493 }; 494 495 partition@800000 { 496 label = "ospi.rootfs"; 497 reg = <0x800000 0x37c0000>; 498 }; 499 500 partition@3fc0000 { 501 label = "ospi.phypattern"; 502 reg = <0x3fc0000 0x40000>; 503 }; 504 }; 505 }; 506}; 507 508&ospi1 { 509 status = "okay"; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 512 513 flash@0 { 514 compatible = "jedec,spi-nor"; 515 reg = <0x0>; 516 spi-tx-bus-width = <1>; 517 spi-rx-bus-width = <4>; 518 spi-max-frequency = <40000000>; 519 cdns,tshsl-ns = <60>; 520 cdns,tsd2d-ns = <60>; 521 cdns,tchsh-ns = <60>; 522 cdns,tslch-ns = <60>; 523 cdns,read-delay = <2>; 524 525 partitions { 526 compatible = "fixed-partitions"; 527 #address-cells = <1>; 528 #size-cells = <1>; 529 530 partition@0 { 531 label = "qspi.tiboot3"; 532 reg = <0x0 0x80000>; 533 }; 534 535 partition@80000 { 536 label = "qspi.tispl"; 537 reg = <0x80000 0x200000>; 538 }; 539 540 partition@280000 { 541 label = "qspi.u-boot"; 542 reg = <0x280000 0x400000>; 543 }; 544 545 partition@680000 { 546 label = "qspi.env"; 547 reg = <0x680000 0x40000>; 548 }; 549 550 partition@6c0000 { 551 label = "qspi.env.backup"; 552 reg = <0x6c0000 0x40000>; 553 }; 554 555 partition@800000 { 556 label = "qspi.rootfs"; 557 reg = <0x800000 0x37c0000>; 558 }; 559 560 partition@3fc0000 { 561 label = "qspi.phypattern"; 562 reg = <0x3fc0000 0x40000>; 563 }; 564 }; 565 566 }; 567}; 568 569&main_i2c0 { 570 status = "okay"; 571 pinctrl-names = "default"; 572 pinctrl-0 = <&main_i2c0_pins_default>; 573 574 clock-frequency = <400000>; 575 576 exp1: gpio@20 { 577 compatible = "ti,tca6416"; 578 reg = <0x20>; 579 gpio-controller; 580 #gpio-cells = <2>; 581 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ", 582 "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", 583 "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", 584 "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", 585 "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; 586 }; 587 588 exp2: gpio@22 { 589 compatible = "ti,tca6424"; 590 reg = <0x22>; 591 gpio-controller; 592 #gpio-cells = <2>; 593 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN", 594 "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", 595 "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", 596 "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", 597 "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", 598 "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", 599 "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", 600 "USER_INPUT1", "USER_LED1", "USER_LED2"; 601 }; 602}; 603 604&main_sdhci0 { 605 /* eMMC */ 606 status = "okay"; 607 non-removable; 608 ti,driver-strength-ohm = <50>; 609 disable-wp; 610}; 611 612&main_sdhci1 { 613 /* SD card */ 614 status = "okay"; 615 pinctrl-0 = <&main_mmc1_pins_default>; 616 pinctrl-names = "default"; 617 disable-wp; 618 vmmc-supply = <&vdd_mmc1>; 619 vqmmc-supply = <&vdd_sd_dv>; 620}; 621 622&main_gpio0 { 623 status = "okay"; 624}; 625 626&mcu_cpsw { 627 status = "okay"; 628 pinctrl-names = "default"; 629 pinctrl-0 = <&mcu_cpsw_pins_default>; 630}; 631 632&davinci_mdio { 633 pinctrl-names = "default"; 634 pinctrl-0 = <&mcu_mdio_pins_default>; 635 636 mcu_phy0: ethernet-phy@0 { 637 reg = <0>; 638 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 639 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 640 ti,min-output-impedance; 641 }; 642}; 643 644&mcu_cpsw_port1 { 645 status = "okay"; 646 phy-mode = "rgmii-rxid"; 647 phy-handle = <&mcu_phy0>; 648}; 649 650&mailbox0_cluster0 { 651 status = "okay"; 652 interrupts = <436>; 653 654 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 655 ti,mbox-rx = <0 0 0>; 656 ti,mbox-tx = <1 0 0>; 657 }; 658 659 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 660 ti,mbox-rx = <2 0 0>; 661 ti,mbox-tx = <3 0 0>; 662 }; 663}; 664 665&mailbox0_cluster1 { 666 status = "okay"; 667 interrupts = <432>; 668 669 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 670 ti,mbox-rx = <0 0 0>; 671 ti,mbox-tx = <1 0 0>; 672 }; 673 674 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 675 ti,mbox-rx = <2 0 0>; 676 ti,mbox-tx = <3 0 0>; 677 }; 678}; 679 680&mailbox0_cluster2 { 681 status = "okay"; 682 interrupts = <428>; 683 684 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 685 ti,mbox-rx = <0 0 0>; 686 ti,mbox-tx = <1 0 0>; 687 }; 688 689 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 690 ti,mbox-rx = <2 0 0>; 691 ti,mbox-tx = <3 0 0>; 692 }; 693}; 694 695&mailbox0_cluster3 { 696 status = "okay"; 697 interrupts = <424>; 698 699 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { 700 ti,mbox-rx = <0 0 0>; 701 ti,mbox-tx = <1 0 0>; 702 }; 703 704 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { 705 ti,mbox-rx = <2 0 0>; 706 ti,mbox-tx = <3 0 0>; 707 }; 708}; 709 710&mailbox0_cluster4 { 711 status = "okay"; 712 interrupts = <420>; 713 714 mbox_c71_0: mbox-c71-0 { 715 ti,mbox-rx = <0 0 0>; 716 ti,mbox-tx = <1 0 0>; 717 }; 718 719 mbox_c71_1: mbox-c71-1 { 720 ti,mbox-rx = <2 0 0>; 721 ti,mbox-tx = <3 0 0>; 722 }; 723}; 724 725&mailbox0_cluster5 { 726 status = "okay"; 727 interrupts = <416>; 728 729 mbox_c71_2: mbox-c71-2 { 730 ti,mbox-rx = <0 0 0>; 731 ti,mbox-tx = <1 0 0>; 732 }; 733 734 mbox_c71_3: mbox-c71-3 { 735 ti,mbox-rx = <2 0 0>; 736 ti,mbox-tx = <3 0 0>; 737 }; 738}; 739 740&mcu_r5fss0_core0 { 741 status = "okay"; 742 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 743 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 744 <&mcu_r5fss0_core0_memory_region>; 745}; 746 747&mcu_r5fss0_core1 { 748 status = "okay"; 749 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 750 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 751 <&mcu_r5fss0_core1_memory_region>; 752}; 753 754&main_r5fss0_core0 { 755 status = "okay"; 756 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 757 memory-region = <&main_r5fss0_core0_dma_memory_region>, 758 <&main_r5fss0_core0_memory_region>; 759}; 760 761&main_r5fss0_core1 { 762 status = "okay"; 763 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 764 memory-region = <&main_r5fss0_core1_dma_memory_region>, 765 <&main_r5fss0_core1_memory_region>; 766}; 767 768&main_r5fss1_core0 { 769 status = "okay"; 770 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 771 memory-region = <&main_r5fss1_core0_dma_memory_region>, 772 <&main_r5fss1_core0_memory_region>; 773}; 774 775&main_r5fss1_core1 { 776 status = "okay"; 777 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 778 memory-region = <&main_r5fss1_core1_dma_memory_region>, 779 <&main_r5fss1_core1_memory_region>; 780}; 781 782&main_r5fss2_core0 { 783 status = "okay"; 784 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; 785 memory-region = <&main_r5fss2_core0_dma_memory_region>, 786 <&main_r5fss2_core0_memory_region>; 787}; 788 789&main_r5fss2_core1 { 790 status = "okay"; 791 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; 792 memory-region = <&main_r5fss2_core1_dma_memory_region>, 793 <&main_r5fss2_core1_memory_region>; 794}; 795 796&c71_0 { 797 status = "okay"; 798 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 799 memory-region = <&c71_0_dma_memory_region>, 800 <&c71_0_memory_region>; 801}; 802 803&c71_1 { 804 status = "okay"; 805 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 806 memory-region = <&c71_1_dma_memory_region>, 807 <&c71_1_memory_region>; 808}; 809 810&c71_2 { 811 status = "okay"; 812 mboxes = <&mailbox0_cluster5 &mbox_c71_2>; 813 memory-region = <&c71_2_dma_memory_region>, 814 <&c71_2_memory_region>; 815}; 816 817&c71_3 { 818 status = "okay"; 819 mboxes = <&mailbox0_cluster5 &mbox_c71_3>; 820 memory-region = <&c71_3_dma_memory_region>, 821 <&c71_3_memory_region>; 822}; 823 824&tscadc0 { 825 pinctrl-0 = <&mcu_adc0_pins_default>; 826 pinctrl-names = "default"; 827 status = "okay"; 828 adc { 829 ti,adc-channels = <0 1 2 3 4 5 6 7>; 830 }; 831}; 832 833&tscadc1 { 834 pinctrl-0 = <&mcu_adc1_pins_default>; 835 pinctrl-names = "default"; 836 status = "okay"; 837 adc { 838 ti,adc-channels = <0 1 2 3 4 5 6 7>; 839 }; 840}; 841