1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/gpio/gpio.h> 12#include "k3-j784s4.dtsi" 13 14/ { 15 compatible = "ti,j784s4-evm", "ti,j784s4"; 16 model = "Texas Instruments J784S4 EVM"; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 }; 21 22 aliases { 23 serial2 = &main_uart8; 24 mmc0 = &main_sdhci0; 25 mmc1 = &main_sdhci1; 26 i2c0 = &main_i2c0; 27 }; 28 29 memory@80000000 { 30 device_type = "memory"; 31 /* 32G RAM */ 32 reg = <0x00 0x80000000 0x00 0x80000000>, 33 <0x08 0x80000000 0x07 0x80000000>; 34 }; 35 36 reserved_memory: reserved-memory { 37 #address-cells = <2>; 38 #size-cells = <2>; 39 ranges; 40 41 secure_ddr: optee@9e800000 { 42 reg = <0x00 0x9e800000 0x00 0x01800000>; 43 no-map; 44 }; 45 46 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 47 compatible = "shared-dma-pool"; 48 reg = <0x00 0xa0000000 0x00 0x100000>; 49 no-map; 50 }; 51 52 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 53 compatible = "shared-dma-pool"; 54 reg = <0x00 0xa0100000 0x00 0xf00000>; 55 no-map; 56 }; 57 58 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 59 compatible = "shared-dma-pool"; 60 reg = <0x00 0xa1000000 0x00 0x100000>; 61 no-map; 62 }; 63 64 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 65 compatible = "shared-dma-pool"; 66 reg = <0x00 0xa1100000 0x00 0xf00000>; 67 no-map; 68 }; 69 70 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 71 compatible = "shared-dma-pool"; 72 reg = <0x00 0xa2000000 0x00 0x100000>; 73 no-map; 74 }; 75 76 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 77 compatible = "shared-dma-pool"; 78 reg = <0x00 0xa2100000 0x00 0xf00000>; 79 no-map; 80 }; 81 82 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 83 compatible = "shared-dma-pool"; 84 reg = <0x00 0xa3000000 0x00 0x100000>; 85 no-map; 86 }; 87 88 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 89 compatible = "shared-dma-pool"; 90 reg = <0x00 0xa3100000 0x00 0xf00000>; 91 no-map; 92 }; 93 94 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 95 compatible = "shared-dma-pool"; 96 reg = <0x00 0xa4000000 0x00 0x100000>; 97 no-map; 98 }; 99 100 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 101 compatible = "shared-dma-pool"; 102 reg = <0x00 0xa4100000 0x00 0xf00000>; 103 no-map; 104 }; 105 106 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 107 compatible = "shared-dma-pool"; 108 reg = <0x00 0xa5000000 0x00 0x100000>; 109 no-map; 110 }; 111 112 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 113 compatible = "shared-dma-pool"; 114 reg = <0x00 0xa5100000 0x00 0xf00000>; 115 no-map; 116 }; 117 118 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { 119 compatible = "shared-dma-pool"; 120 reg = <0x00 0xa6000000 0x00 0x100000>; 121 no-map; 122 }; 123 124 main_r5fss2_core0_memory_region: r5f-memory@a6100000 { 125 compatible = "shared-dma-pool"; 126 reg = <0x00 0xa6100000 0x00 0xf00000>; 127 no-map; 128 }; 129 130 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { 131 compatible = "shared-dma-pool"; 132 reg = <0x00 0xa7000000 0x00 0x100000>; 133 no-map; 134 }; 135 136 main_r5fss2_core1_memory_region: r5f-memory@a7100000 { 137 compatible = "shared-dma-pool"; 138 reg = <0x00 0xa7100000 0x00 0xf00000>; 139 no-map; 140 }; 141 142 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 143 compatible = "shared-dma-pool"; 144 reg = <0x00 0xa8000000 0x00 0x100000>; 145 no-map; 146 }; 147 148 c71_0_memory_region: c71-memory@a8100000 { 149 compatible = "shared-dma-pool"; 150 reg = <0x00 0xa8100000 0x00 0xf00000>; 151 no-map; 152 }; 153 154 c71_1_dma_memory_region: c71-dma-memory@a9000000 { 155 compatible = "shared-dma-pool"; 156 reg = <0x00 0xa9000000 0x00 0x100000>; 157 no-map; 158 }; 159 160 c71_1_memory_region: c71-memory@a9100000 { 161 compatible = "shared-dma-pool"; 162 reg = <0x00 0xa9100000 0x00 0xf00000>; 163 no-map; 164 }; 165 166 c71_2_dma_memory_region: c71-dma-memory@aa000000 { 167 compatible = "shared-dma-pool"; 168 reg = <0x00 0xaa000000 0x00 0x100000>; 169 no-map; 170 }; 171 172 c71_2_memory_region: c71-memory@aa100000 { 173 compatible = "shared-dma-pool"; 174 reg = <0x00 0xaa100000 0x00 0xf00000>; 175 no-map; 176 }; 177 178 c71_3_dma_memory_region: c71-dma-memory@ab000000 { 179 compatible = "shared-dma-pool"; 180 reg = <0x00 0xab000000 0x00 0x100000>; 181 no-map; 182 }; 183 184 c71_3_memory_region: c71-memory@ab100000 { 185 compatible = "shared-dma-pool"; 186 reg = <0x00 0xab100000 0x00 0xf00000>; 187 no-map; 188 }; 189 }; 190 191 evm_12v0: regulator-evm12v0 { 192 /* main supply */ 193 compatible = "regulator-fixed"; 194 regulator-name = "evm_12v0"; 195 regulator-min-microvolt = <12000000>; 196 regulator-max-microvolt = <12000000>; 197 regulator-always-on; 198 regulator-boot-on; 199 }; 200 201 vsys_3v3: regulator-vsys3v3 { 202 /* Output of LM5140 */ 203 compatible = "regulator-fixed"; 204 regulator-name = "vsys_3v3"; 205 regulator-min-microvolt = <3300000>; 206 regulator-max-microvolt = <3300000>; 207 vin-supply = <&evm_12v0>; 208 regulator-always-on; 209 regulator-boot-on; 210 }; 211 212 vsys_5v0: regulator-vsys5v0 { 213 /* Output of LM5140 */ 214 compatible = "regulator-fixed"; 215 regulator-name = "vsys_5v0"; 216 regulator-min-microvolt = <5000000>; 217 regulator-max-microvolt = <5000000>; 218 vin-supply = <&evm_12v0>; 219 regulator-always-on; 220 regulator-boot-on; 221 }; 222 223 vdd_mmc1: regulator-sd { 224 /* Output of TPS22918 */ 225 compatible = "regulator-fixed"; 226 regulator-name = "vdd_mmc1"; 227 regulator-min-microvolt = <3300000>; 228 regulator-max-microvolt = <3300000>; 229 regulator-boot-on; 230 enable-active-high; 231 vin-supply = <&vsys_3v3>; 232 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 233 }; 234 235 vdd_sd_dv: regulator-TLV71033 { 236 /* Output of TLV71033 */ 237 compatible = "regulator-gpio"; 238 regulator-name = "tlv71033"; 239 pinctrl-names = "default"; 240 pinctrl-0 = <&vdd_sd_dv_pins_default>; 241 regulator-min-microvolt = <1800000>; 242 regulator-max-microvolt = <3300000>; 243 regulator-boot-on; 244 vin-supply = <&vsys_5v0>; 245 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; 246 states = <1800000 0x0>, 247 <3300000 0x1>; 248 }; 249}; 250 251&main_pmx0 { 252 main_uart8_pins_default: main-uart8-pins-default { 253 pinctrl-single,pins = < 254 J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ 255 J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ 256 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 257 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ 258 >; 259 }; 260 261 main_i2c0_pins_default: main-i2c0-pins-default { 262 pinctrl-single,pins = < 263 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ 264 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ 265 >; 266 }; 267 268 main_mmc1_pins_default: main-mmc1-pins-default { 269 pinctrl-single,pins = < 270 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 271 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ 272 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ 273 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ 274 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ 275 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ 276 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ 277 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ 278 >; 279 }; 280 281 vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { 282 pinctrl-single,pins = < 283 J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ 284 >; 285 }; 286}; 287 288&wkup_pmx0 { 289 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 290 pinctrl-single,pins = < 291 J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 292 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 293 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 294 J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 295 J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 296 J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 297 J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 298 J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 299 J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 300 J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 301 J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 302 J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 303 >; 304 }; 305 306 mcu_mdio_pins_default: mcu-mdio-pins-default { 307 pinctrl-single,pins = < 308 J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 309 J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 310 >; 311 }; 312 313 mcu_adc0_pins_default: mcu-adc0-pins-default { 314 pinctrl-single,pins = < 315 J784S4_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ 316 J784S4_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ 317 J784S4_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ 318 J784S4_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ 319 J784S4_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ 320 J784S4_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ 321 J784S4_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ 322 J784S4_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ 323 >; 324 }; 325 326 mcu_adc1_pins_default: mcu-adc1-pins-default { 327 pinctrl-single,pins = < 328 J784S4_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ 329 J784S4_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ 330 J784S4_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ 331 J784S4_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ 332 J784S4_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ 333 J784S4_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ 334 J784S4_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ 335 J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ 336 >; 337 }; 338}; 339 340&wkup_pmx0 { 341 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { 342 pinctrl-single,pins = < 343 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ 344 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ 345 J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ 346 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ 347 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ 348 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ 349 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ 350 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ 351 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ 352 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ 353 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ 354 J784S4_WKUP_IOPAD(0x03c, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_CSn3.MCU_OSPI0_ECC_FAIL */ 355 J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_CSn2.MCU_OSPI0_RESET_OUT0 */ 356 >; 357 }; 358 359 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { 360 pinctrl-single,pins = < 361 J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ 362 J784S4_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ 363 J784S4_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ 364 J784S4_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ 365 J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ 366 J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ 367 J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ 368 J784S4_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ 369 >; 370 }; 371}; 372 373&main_uart8 { 374 status = "okay"; 375 pinctrl-names = "default"; 376 pinctrl-0 = <&main_uart8_pins_default>; 377}; 378 379&fss { 380 status = "okay"; 381}; 382 383&ospi0 { 384 status = "okay"; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 387 388 flash@0 { 389 compatible = "jedec,spi-nor"; 390 reg = <0x0>; 391 spi-tx-bus-width = <8>; 392 spi-rx-bus-width = <8>; 393 spi-max-frequency = <25000000>; 394 cdns,tshsl-ns = <60>; 395 cdns,tsd2d-ns = <60>; 396 cdns,tchsh-ns = <60>; 397 cdns,tslch-ns = <60>; 398 cdns,read-delay = <4>; 399 400 partitions { 401 compatible = "fixed-partitions"; 402 #address-cells = <1>; 403 #size-cells = <1>; 404 405 partition@0 { 406 label = "ospi.tiboot3"; 407 reg = <0x0 0x80000>; 408 }; 409 410 partition@80000 { 411 label = "ospi.tispl"; 412 reg = <0x80000 0x200000>; 413 }; 414 415 partition@280000 { 416 label = "ospi.u-boot"; 417 reg = <0x280000 0x400000>; 418 }; 419 420 partition@680000 { 421 label = "ospi.env"; 422 reg = <0x680000 0x40000>; 423 }; 424 425 partition@6c0000 { 426 label = "ospi.env.backup"; 427 reg = <0x6c0000 0x40000>; 428 }; 429 430 partition@800000 { 431 label = "ospi.rootfs"; 432 reg = <0x800000 0x37c0000>; 433 }; 434 435 partition@3fc0000 { 436 label = "ospi.phypattern"; 437 reg = <0x3fc0000 0x40000>; 438 }; 439 }; 440 }; 441}; 442 443&ospi1 { 444 status = "okay"; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 447 448 flash@0{ 449 compatible = "jedec,spi-nor"; 450 reg = <0x0>; 451 spi-tx-bus-width = <1>; 452 spi-rx-bus-width = <4>; 453 spi-max-frequency = <40000000>; 454 cdns,tshsl-ns = <60>; 455 cdns,tsd2d-ns = <60>; 456 cdns,tchsh-ns = <60>; 457 cdns,tslch-ns = <60>; 458 cdns,read-delay = <2>; 459 460 partitions { 461 compatible = "fixed-partitions"; 462 #address-cells = <1>; 463 #size-cells = <1>; 464 465 partition@0 { 466 label = "qspi.tiboot3"; 467 reg = <0x0 0x80000>; 468 }; 469 470 partition@80000 { 471 label = "qspi.tispl"; 472 reg = <0x80000 0x200000>; 473 }; 474 475 partition@280000 { 476 label = "qspi.u-boot"; 477 reg = <0x280000 0x400000>; 478 }; 479 480 partition@680000 { 481 label = "qspi.env"; 482 reg = <0x680000 0x40000>; 483 }; 484 485 partition@6c0000 { 486 label = "qspi.env.backup"; 487 reg = <0x6c0000 0x40000>; 488 }; 489 490 partition@800000 { 491 label = "qspi.rootfs"; 492 reg = <0x800000 0x37c0000>; 493 }; 494 495 partition@3fc0000 { 496 label = "qspi.phypattern"; 497 reg = <0x3fc0000 0x40000>; 498 }; 499 }; 500 501 }; 502}; 503 504&main_i2c0 { 505 status = "okay"; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&main_i2c0_pins_default>; 508 509 clock-frequency = <400000>; 510 511 exp1: gpio@20 { 512 compatible = "ti,tca6416"; 513 reg = <0x20>; 514 gpio-controller; 515 #gpio-cells = <2>; 516 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ", 517 "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", 518 "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", 519 "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", 520 "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; 521 }; 522 523 exp2: gpio@22 { 524 compatible = "ti,tca6424"; 525 reg = <0x22>; 526 gpio-controller; 527 #gpio-cells = <2>; 528 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN", 529 "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", 530 "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", 531 "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", 532 "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", 533 "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", 534 "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", 535 "USER_INPUT1", "USER_LED1", "USER_LED2"; 536 }; 537}; 538 539&main_sdhci0 { 540 /* eMMC */ 541 status = "okay"; 542 non-removable; 543 ti,driver-strength-ohm = <50>; 544 disable-wp; 545}; 546 547&main_sdhci1 { 548 /* SD card */ 549 status = "okay"; 550 pinctrl-0 = <&main_mmc1_pins_default>; 551 pinctrl-names = "default"; 552 disable-wp; 553 vmmc-supply = <&vdd_mmc1>; 554 vqmmc-supply = <&vdd_sd_dv>; 555}; 556 557&main_gpio0 { 558 status = "okay"; 559}; 560 561&mcu_cpsw { 562 status = "okay"; 563 pinctrl-names = "default"; 564 pinctrl-0 = <&mcu_cpsw_pins_default>; 565}; 566 567&davinci_mdio { 568 pinctrl-names = "default"; 569 pinctrl-0 = <&mcu_mdio_pins_default>; 570 571 mcu_phy0: ethernet-phy@0 { 572 reg = <0>; 573 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 574 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 575 ti,min-output-impedance; 576 }; 577}; 578 579&mcu_cpsw_port1 { 580 status = "okay"; 581 phy-mode = "rgmii-rxid"; 582 phy-handle = <&mcu_phy0>; 583}; 584 585&mailbox0_cluster0 { 586 status = "okay"; 587 interrupts = <436>; 588 589 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 590 ti,mbox-rx = <0 0 0>; 591 ti,mbox-tx = <1 0 0>; 592 }; 593 594 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 595 ti,mbox-rx = <2 0 0>; 596 ti,mbox-tx = <3 0 0>; 597 }; 598}; 599 600&mailbox0_cluster1 { 601 status = "okay"; 602 interrupts = <432>; 603 604 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 605 ti,mbox-rx = <0 0 0>; 606 ti,mbox-tx = <1 0 0>; 607 }; 608 609 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 610 ti,mbox-rx = <2 0 0>; 611 ti,mbox-tx = <3 0 0>; 612 }; 613}; 614 615&mailbox0_cluster2 { 616 status = "okay"; 617 interrupts = <428>; 618 619 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 620 ti,mbox-rx = <0 0 0>; 621 ti,mbox-tx = <1 0 0>; 622 }; 623 624 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 625 ti,mbox-rx = <2 0 0>; 626 ti,mbox-tx = <3 0 0>; 627 }; 628}; 629 630&mailbox0_cluster3 { 631 status = "okay"; 632 interrupts = <424>; 633 634 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { 635 ti,mbox-rx = <0 0 0>; 636 ti,mbox-tx = <1 0 0>; 637 }; 638 639 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { 640 ti,mbox-rx = <2 0 0>; 641 ti,mbox-tx = <3 0 0>; 642 }; 643}; 644 645&mailbox0_cluster4 { 646 status = "okay"; 647 interrupts = <420>; 648 649 mbox_c71_0: mbox-c71-0 { 650 ti,mbox-rx = <0 0 0>; 651 ti,mbox-tx = <1 0 0>; 652 }; 653 654 mbox_c71_1: mbox-c71-1 { 655 ti,mbox-rx = <2 0 0>; 656 ti,mbox-tx = <3 0 0>; 657 }; 658}; 659 660&mailbox0_cluster5 { 661 status = "okay"; 662 interrupts = <416>; 663 664 mbox_c71_2: mbox-c71-2 { 665 ti,mbox-rx = <0 0 0>; 666 ti,mbox-tx = <1 0 0>; 667 }; 668 669 mbox_c71_3: mbox-c71-3 { 670 ti,mbox-rx = <2 0 0>; 671 ti,mbox-tx = <3 0 0>; 672 }; 673}; 674 675&mcu_r5fss0_core0 { 676 status = "okay"; 677 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 678 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 679 <&mcu_r5fss0_core0_memory_region>; 680}; 681 682&mcu_r5fss0_core1 { 683 status = "okay"; 684 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 685 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 686 <&mcu_r5fss0_core1_memory_region>; 687}; 688 689&main_r5fss0_core0 { 690 status = "okay"; 691 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 692 memory-region = <&main_r5fss0_core0_dma_memory_region>, 693 <&main_r5fss0_core0_memory_region>; 694}; 695 696&main_r5fss0_core1 { 697 status = "okay"; 698 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 699 memory-region = <&main_r5fss0_core1_dma_memory_region>, 700 <&main_r5fss0_core1_memory_region>; 701}; 702 703&main_r5fss1_core0 { 704 status = "okay"; 705 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 706 memory-region = <&main_r5fss1_core0_dma_memory_region>, 707 <&main_r5fss1_core0_memory_region>; 708}; 709 710&main_r5fss1_core1 { 711 status = "okay"; 712 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 713 memory-region = <&main_r5fss1_core1_dma_memory_region>, 714 <&main_r5fss1_core1_memory_region>; 715}; 716 717&main_r5fss2_core0 { 718 status = "okay"; 719 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; 720 memory-region = <&main_r5fss2_core0_dma_memory_region>, 721 <&main_r5fss2_core0_memory_region>; 722}; 723 724&main_r5fss2_core1 { 725 status = "okay"; 726 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; 727 memory-region = <&main_r5fss2_core1_dma_memory_region>, 728 <&main_r5fss2_core1_memory_region>; 729}; 730 731&c71_0 { 732 status = "okay"; 733 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 734 memory-region = <&c71_0_dma_memory_region>, 735 <&c71_0_memory_region>; 736}; 737 738&c71_1 { 739 status = "okay"; 740 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 741 memory-region = <&c71_1_dma_memory_region>, 742 <&c71_1_memory_region>; 743}; 744 745&c71_2 { 746 status = "okay"; 747 mboxes = <&mailbox0_cluster5 &mbox_c71_2>; 748 memory-region = <&c71_2_dma_memory_region>, 749 <&c71_2_memory_region>; 750}; 751 752&c71_3 { 753 status = "okay"; 754 mboxes = <&mailbox0_cluster5 &mbox_c71_3>; 755 memory-region = <&c71_3_dma_memory_region>, 756 <&c71_3_memory_region>; 757}; 758 759&tscadc0 { 760 pinctrl-0 = <&mcu_adc0_pins_default>; 761 pinctrl-names = "default"; 762 status = "okay"; 763 adc { 764 ti,adc-channels = <0 1 2 3 4 5 6 7>; 765 }; 766}; 767 768&tscadc1 { 769 pinctrl-0 = <&mcu_adc1_pins_default>; 770 pinctrl-names = "default"; 771 status = "okay"; 772 adc { 773 ti,adc-channels = <0 1 2 3 4 5 6 7>; 774 }; 775}; 776