1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/phy/phy-ti.h> 9#include <dt-bindings/mux/mux.h> 10#include <dt-bindings/mux/ti-serdes.h> 11 12/ { 13 cmn_refclk: clock-cmnrefclk { 14 #clock-cells = <0>; 15 compatible = "fixed-clock"; 16 clock-frequency = <0>; 17 }; 18 19 cmn_refclk1: clock-cmnrefclk1 { 20 #clock-cells = <0>; 21 compatible = "fixed-clock"; 22 clock-frequency = <0>; 23 }; 24}; 25 26&cbass_main { 27 msmc_ram: sram@70000000 { 28 compatible = "mmio-sram"; 29 reg = <0x0 0x70000000 0x0 0x800000>; 30 #address-cells = <1>; 31 #size-cells = <1>; 32 ranges = <0x0 0x0 0x70000000 0x800000>; 33 34 atf-sram@0 { 35 reg = <0x0 0x20000>; 36 }; 37 }; 38 39 scm_conf: scm-conf@100000 { 40 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 41 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 42 #address-cells = <1>; 43 #size-cells = <1>; 44 ranges = <0x0 0x0 0x00100000 0x1c000>; 45 46 serdes_ln_ctrl: mux-controller@4080 { 47 compatible = "mmio-mux"; 48 reg = <0x00004080 0x50>; 49 #mux-control-cells = <1>; 50 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 51 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 52 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 53 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 54 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 55 /* SERDES4 lane0/1/2/3 select */ 56 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 57 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 58 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 59 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 60 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 61 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 62 }; 63 64 cpsw0_phy_gmii_sel: phy@4044 { 65 compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; 66 ti,qsgmii-main-ports = <2>, <2>; 67 reg = <0x4044 0x20>; 68 #phy-cells = <1>; 69 }; 70 71 usb_serdes_mux: mux-controller@4000 { 72 compatible = "mmio-mux"; 73 #mux-control-cells = <1>; 74 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 75 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 76 }; 77 78 ehrpwm_tbclk: clock-controller@4140 { 79 compatible = "ti,am654-ehrpwm-tbclk", "syscon"; 80 reg = <0x4140 0x18>; 81 #clock-cells = <1>; 82 }; 83 }; 84 85 main_ehrpwm0: pwm@3000000 { 86 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 87 #pwm-cells = <3>; 88 reg = <0x00 0x3000000 0x00 0x100>; 89 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; 90 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; 91 clock-names = "tbclk", "fck"; 92 status = "disabled"; 93 }; 94 95 main_ehrpwm1: pwm@3010000 { 96 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 97 #pwm-cells = <3>; 98 reg = <0x00 0x3010000 0x00 0x100>; 99 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 100 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; 101 clock-names = "tbclk", "fck"; 102 status = "disabled"; 103 }; 104 105 main_ehrpwm2: pwm@3020000 { 106 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 107 #pwm-cells = <3>; 108 reg = <0x00 0x3020000 0x00 0x100>; 109 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; 110 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; 111 clock-names = "tbclk", "fck"; 112 status = "disabled"; 113 }; 114 115 main_ehrpwm3: pwm@3030000 { 116 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 117 #pwm-cells = <3>; 118 reg = <0x00 0x3030000 0x00 0x100>; 119 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 120 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; 121 clock-names = "tbclk", "fck"; 122 status = "disabled"; 123 }; 124 125 main_ehrpwm4: pwm@3040000 { 126 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 127 #pwm-cells = <3>; 128 reg = <0x00 0x3040000 0x00 0x100>; 129 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 130 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; 131 clock-names = "tbclk", "fck"; 132 status = "disabled"; 133 }; 134 135 main_ehrpwm5: pwm@3050000 { 136 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 137 #pwm-cells = <3>; 138 reg = <0x00 0x3050000 0x00 0x100>; 139 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 140 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; 141 clock-names = "tbclk", "fck"; 142 status = "disabled"; 143 }; 144 145 gic500: interrupt-controller@1800000 { 146 compatible = "arm,gic-v3"; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 ranges; 150 #interrupt-cells = <3>; 151 interrupt-controller; 152 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 153 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 154 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 155 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 156 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 157 158 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 159 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 160 161 gic_its: msi-controller@1820000 { 162 compatible = "arm,gic-v3-its"; 163 reg = <0x00 0x01820000 0x00 0x10000>; 164 socionext,synquacer-pre-its = <0x1000000 0x400000>; 165 msi-controller; 166 #msi-cells = <1>; 167 }; 168 }; 169 170 main_gpio_intr: interrupt-controller@a00000 { 171 compatible = "ti,sci-intr"; 172 reg = <0x00 0x00a00000 0x00 0x800>; 173 ti,intr-trigger-type = <1>; 174 interrupt-controller; 175 interrupt-parent = <&gic500>; 176 #interrupt-cells = <1>; 177 ti,sci = <&dmsc>; 178 ti,sci-dev-id = <131>; 179 ti,interrupt-ranges = <8 392 56>; 180 }; 181 182 main_navss: bus@30000000 { 183 compatible = "simple-mfd"; 184 #address-cells = <2>; 185 #size-cells = <2>; 186 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 187 dma-coherent; 188 dma-ranges; 189 190 ti,sci-dev-id = <199>; 191 192 main_navss_intr: interrupt-controller@310e0000 { 193 compatible = "ti,sci-intr"; 194 reg = <0x0 0x310e0000 0x0 0x4000>; 195 ti,intr-trigger-type = <4>; 196 interrupt-controller; 197 interrupt-parent = <&gic500>; 198 #interrupt-cells = <1>; 199 ti,sci = <&dmsc>; 200 ti,sci-dev-id = <213>; 201 ti,interrupt-ranges = <0 64 64>, 202 <64 448 64>, 203 <128 672 64>; 204 }; 205 206 main_udmass_inta: interrupt-controller@33d00000 { 207 compatible = "ti,sci-inta"; 208 reg = <0x0 0x33d00000 0x0 0x100000>; 209 interrupt-controller; 210 interrupt-parent = <&main_navss_intr>; 211 msi-controller; 212 #interrupt-cells = <0>; 213 ti,sci = <&dmsc>; 214 ti,sci-dev-id = <209>; 215 ti,interrupt-ranges = <0 0 256>; 216 }; 217 218 secure_proxy_main: mailbox@32c00000 { 219 compatible = "ti,am654-secure-proxy"; 220 #mbox-cells = <1>; 221 reg-names = "target_data", "rt", "scfg"; 222 reg = <0x00 0x32c00000 0x00 0x100000>, 223 <0x00 0x32400000 0x00 0x100000>, 224 <0x00 0x32800000 0x00 0x100000>; 225 interrupt-names = "rx_011"; 226 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 227 }; 228 229 smmu0: iommu@36600000 { 230 compatible = "arm,smmu-v3"; 231 reg = <0x0 0x36600000 0x0 0x100000>; 232 interrupt-parent = <&gic500>; 233 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 234 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 235 interrupt-names = "eventq", "gerror"; 236 #iommu-cells = <1>; 237 }; 238 239 hwspinlock: spinlock@30e00000 { 240 compatible = "ti,am654-hwspinlock"; 241 reg = <0x00 0x30e00000 0x00 0x1000>; 242 #hwlock-cells = <1>; 243 }; 244 245 mailbox0_cluster0: mailbox@31f80000 { 246 compatible = "ti,am654-mailbox"; 247 reg = <0x00 0x31f80000 0x00 0x200>; 248 #mbox-cells = <1>; 249 ti,mbox-num-users = <4>; 250 ti,mbox-num-fifos = <16>; 251 interrupt-parent = <&main_navss_intr>; 252 status = "disabled"; 253 }; 254 255 mailbox0_cluster1: mailbox@31f81000 { 256 compatible = "ti,am654-mailbox"; 257 reg = <0x00 0x31f81000 0x00 0x200>; 258 #mbox-cells = <1>; 259 ti,mbox-num-users = <4>; 260 ti,mbox-num-fifos = <16>; 261 interrupt-parent = <&main_navss_intr>; 262 status = "disabled"; 263 }; 264 265 mailbox0_cluster2: mailbox@31f82000 { 266 compatible = "ti,am654-mailbox"; 267 reg = <0x00 0x31f82000 0x00 0x200>; 268 #mbox-cells = <1>; 269 ti,mbox-num-users = <4>; 270 ti,mbox-num-fifos = <16>; 271 interrupt-parent = <&main_navss_intr>; 272 status = "disabled"; 273 }; 274 275 mailbox0_cluster3: mailbox@31f83000 { 276 compatible = "ti,am654-mailbox"; 277 reg = <0x00 0x31f83000 0x00 0x200>; 278 #mbox-cells = <1>; 279 ti,mbox-num-users = <4>; 280 ti,mbox-num-fifos = <16>; 281 interrupt-parent = <&main_navss_intr>; 282 status = "disabled"; 283 }; 284 285 mailbox0_cluster4: mailbox@31f84000 { 286 compatible = "ti,am654-mailbox"; 287 reg = <0x00 0x31f84000 0x00 0x200>; 288 #mbox-cells = <1>; 289 ti,mbox-num-users = <4>; 290 ti,mbox-num-fifos = <16>; 291 interrupt-parent = <&main_navss_intr>; 292 status = "disabled"; 293 }; 294 295 mailbox0_cluster5: mailbox@31f85000 { 296 compatible = "ti,am654-mailbox"; 297 reg = <0x00 0x31f85000 0x00 0x200>; 298 #mbox-cells = <1>; 299 ti,mbox-num-users = <4>; 300 ti,mbox-num-fifos = <16>; 301 interrupt-parent = <&main_navss_intr>; 302 status = "disabled"; 303 }; 304 305 mailbox0_cluster6: mailbox@31f86000 { 306 compatible = "ti,am654-mailbox"; 307 reg = <0x00 0x31f86000 0x00 0x200>; 308 #mbox-cells = <1>; 309 ti,mbox-num-users = <4>; 310 ti,mbox-num-fifos = <16>; 311 interrupt-parent = <&main_navss_intr>; 312 status = "disabled"; 313 }; 314 315 mailbox0_cluster7: mailbox@31f87000 { 316 compatible = "ti,am654-mailbox"; 317 reg = <0x00 0x31f87000 0x00 0x200>; 318 #mbox-cells = <1>; 319 ti,mbox-num-users = <4>; 320 ti,mbox-num-fifos = <16>; 321 interrupt-parent = <&main_navss_intr>; 322 status = "disabled"; 323 }; 324 325 mailbox0_cluster8: mailbox@31f88000 { 326 compatible = "ti,am654-mailbox"; 327 reg = <0x00 0x31f88000 0x00 0x200>; 328 #mbox-cells = <1>; 329 ti,mbox-num-users = <4>; 330 ti,mbox-num-fifos = <16>; 331 interrupt-parent = <&main_navss_intr>; 332 status = "disabled"; 333 }; 334 335 mailbox0_cluster9: mailbox@31f89000 { 336 compatible = "ti,am654-mailbox"; 337 reg = <0x00 0x31f89000 0x00 0x200>; 338 #mbox-cells = <1>; 339 ti,mbox-num-users = <4>; 340 ti,mbox-num-fifos = <16>; 341 interrupt-parent = <&main_navss_intr>; 342 status = "disabled"; 343 }; 344 345 mailbox0_cluster10: mailbox@31f8a000 { 346 compatible = "ti,am654-mailbox"; 347 reg = <0x00 0x31f8a000 0x00 0x200>; 348 #mbox-cells = <1>; 349 ti,mbox-num-users = <4>; 350 ti,mbox-num-fifos = <16>; 351 interrupt-parent = <&main_navss_intr>; 352 status = "disabled"; 353 }; 354 355 mailbox0_cluster11: mailbox@31f8b000 { 356 compatible = "ti,am654-mailbox"; 357 reg = <0x00 0x31f8b000 0x00 0x200>; 358 #mbox-cells = <1>; 359 ti,mbox-num-users = <4>; 360 ti,mbox-num-fifos = <16>; 361 interrupt-parent = <&main_navss_intr>; 362 status = "disabled"; 363 }; 364 365 main_ringacc: ringacc@3c000000 { 366 compatible = "ti,am654-navss-ringacc"; 367 reg = <0x0 0x3c000000 0x0 0x400000>, 368 <0x0 0x38000000 0x0 0x400000>, 369 <0x0 0x31120000 0x0 0x100>, 370 <0x0 0x33000000 0x0 0x40000>; 371 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 372 ti,num-rings = <1024>; 373 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 374 ti,sci = <&dmsc>; 375 ti,sci-dev-id = <211>; 376 msi-parent = <&main_udmass_inta>; 377 }; 378 379 main_udmap: dma-controller@31150000 { 380 compatible = "ti,j721e-navss-main-udmap"; 381 reg = <0x0 0x31150000 0x0 0x100>, 382 <0x0 0x34000000 0x0 0x100000>, 383 <0x0 0x35000000 0x0 0x100000>; 384 reg-names = "gcfg", "rchanrt", "tchanrt"; 385 msi-parent = <&main_udmass_inta>; 386 #dma-cells = <1>; 387 388 ti,sci = <&dmsc>; 389 ti,sci-dev-id = <212>; 390 ti,ringacc = <&main_ringacc>; 391 392 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 393 <0x0f>, /* TX_HCHAN */ 394 <0x10>; /* TX_UHCHAN */ 395 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 396 <0x0b>, /* RX_HCHAN */ 397 <0x0c>; /* RX_UHCHAN */ 398 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 399 }; 400 401 cpts@310d0000 { 402 compatible = "ti,j721e-cpts"; 403 reg = <0x0 0x310d0000 0x0 0x400>; 404 reg-names = "cpts"; 405 clocks = <&k3_clks 201 1>; 406 clock-names = "cpts"; 407 interrupts-extended = <&main_navss_intr 391>; 408 interrupt-names = "cpts"; 409 ti,cpts-periodic-outputs = <6>; 410 ti,cpts-ext-ts-inputs = <8>; 411 }; 412 }; 413 414 cpsw0: ethernet@c000000 { 415 compatible = "ti,j721e-cpswxg-nuss"; 416 #address-cells = <2>; 417 #size-cells = <2>; 418 reg = <0x0 0xc000000 0x0 0x200000>; 419 reg-names = "cpsw_nuss"; 420 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; 421 clocks = <&k3_clks 19 89>; 422 clock-names = "fck"; 423 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 424 425 dmas = <&main_udmap 0xca00>, 426 <&main_udmap 0xca01>, 427 <&main_udmap 0xca02>, 428 <&main_udmap 0xca03>, 429 <&main_udmap 0xca04>, 430 <&main_udmap 0xca05>, 431 <&main_udmap 0xca06>, 432 <&main_udmap 0xca07>, 433 <&main_udmap 0x4a00>; 434 dma-names = "tx0", "tx1", "tx2", "tx3", 435 "tx4", "tx5", "tx6", "tx7", 436 "rx"; 437 438 status = "disabled"; 439 440 ethernet-ports { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 cpsw0_port1: port@1 { 444 reg = <1>; 445 ti,mac-only; 446 label = "port1"; 447 status = "disabled"; 448 }; 449 450 cpsw0_port2: port@2 { 451 reg = <2>; 452 ti,mac-only; 453 label = "port2"; 454 status = "disabled"; 455 }; 456 457 cpsw0_port3: port@3 { 458 reg = <3>; 459 ti,mac-only; 460 label = "port3"; 461 status = "disabled"; 462 }; 463 464 cpsw0_port4: port@4 { 465 reg = <4>; 466 ti,mac-only; 467 label = "port4"; 468 status = "disabled"; 469 }; 470 471 cpsw0_port5: port@5 { 472 reg = <5>; 473 ti,mac-only; 474 label = "port5"; 475 status = "disabled"; 476 }; 477 478 cpsw0_port6: port@6 { 479 reg = <6>; 480 ti,mac-only; 481 label = "port6"; 482 status = "disabled"; 483 }; 484 485 cpsw0_port7: port@7 { 486 reg = <7>; 487 ti,mac-only; 488 label = "port7"; 489 status = "disabled"; 490 }; 491 492 cpsw0_port8: port@8 { 493 reg = <8>; 494 ti,mac-only; 495 label = "port8"; 496 status = "disabled"; 497 }; 498 }; 499 500 cpsw9g_mdio: mdio@f00 { 501 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 502 reg = <0x0 0xf00 0x0 0x100>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 clocks = <&k3_clks 19 89>; 506 clock-names = "fck"; 507 bus_freq = <1000000>; 508 status = "disabled"; 509 }; 510 511 cpts@3d000 { 512 compatible = "ti,j721e-cpts"; 513 reg = <0x0 0x3d000 0x0 0x400>; 514 clocks = <&k3_clks 19 16>; 515 clock-names = "cpts"; 516 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 517 interrupt-names = "cpts"; 518 ti,cpts-ext-ts-inputs = <4>; 519 ti,cpts-periodic-outputs = <2>; 520 }; 521 }; 522 523 main_crypto: crypto@4e00000 { 524 compatible = "ti,j721e-sa2ul"; 525 reg = <0x0 0x4e00000 0x0 0x1200>; 526 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 527 #address-cells = <2>; 528 #size-cells = <2>; 529 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 530 531 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 532 <&main_udmap 0x4001>; 533 dma-names = "tx", "rx1", "rx2"; 534 535 rng: rng@4e10000 { 536 compatible = "inside-secure,safexcel-eip76"; 537 reg = <0x0 0x4e10000 0x0 0x7d>; 538 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 539 }; 540 }; 541 542 main_pmx0: pinctrl@11c000 { 543 compatible = "pinctrl-single"; 544 /* Proxy 0 addressing */ 545 reg = <0x0 0x11c000 0x0 0x2b4>; 546 #pinctrl-cells = <1>; 547 pinctrl-single,register-width = <32>; 548 pinctrl-single,function-mask = <0xffffffff>; 549 }; 550 551 serdes_wiz0: wiz@5000000 { 552 compatible = "ti,j721e-wiz-16g"; 553 #address-cells = <1>; 554 #size-cells = <1>; 555 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 556 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; 557 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 558 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 559 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 560 num-lanes = <2>; 561 #reset-cells = <1>; 562 ranges = <0x5000000 0x0 0x5000000 0x10000>; 563 564 wiz0_pll0_refclk: pll0-refclk { 565 clocks = <&k3_clks 292 11>, <&cmn_refclk>; 566 #clock-cells = <0>; 567 assigned-clocks = <&wiz0_pll0_refclk>; 568 assigned-clock-parents = <&k3_clks 292 11>; 569 }; 570 571 wiz0_pll1_refclk: pll1-refclk { 572 clocks = <&k3_clks 292 0>, <&cmn_refclk1>; 573 #clock-cells = <0>; 574 assigned-clocks = <&wiz0_pll1_refclk>; 575 assigned-clock-parents = <&k3_clks 292 0>; 576 }; 577 578 wiz0_refclk_dig: refclk-dig { 579 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; 580 #clock-cells = <0>; 581 assigned-clocks = <&wiz0_refclk_dig>; 582 assigned-clock-parents = <&k3_clks 292 11>; 583 }; 584 585 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 586 clocks = <&wiz0_refclk_dig>; 587 #clock-cells = <0>; 588 }; 589 590 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 591 clocks = <&wiz0_pll1_refclk>; 592 #clock-cells = <0>; 593 }; 594 595 serdes0: serdes@5000000 { 596 compatible = "ti,sierra-phy-t0"; 597 reg-names = "serdes"; 598 reg = <0x5000000 0x10000>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 #clock-cells = <1>; 602 resets = <&serdes_wiz0 0>; 603 reset-names = "sierra_reset"; 604 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, 605 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; 606 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 607 "pll0_refclk", "pll1_refclk"; 608 }; 609 }; 610 611 serdes_wiz1: wiz@5010000 { 612 compatible = "ti,j721e-wiz-16g"; 613 #address-cells = <1>; 614 #size-cells = <1>; 615 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 616 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; 617 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 618 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 619 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 620 num-lanes = <2>; 621 #reset-cells = <1>; 622 ranges = <0x5010000 0x0 0x5010000 0x10000>; 623 624 wiz1_pll0_refclk: pll0-refclk { 625 clocks = <&k3_clks 293 13>, <&cmn_refclk>; 626 #clock-cells = <0>; 627 assigned-clocks = <&wiz1_pll0_refclk>; 628 assigned-clock-parents = <&k3_clks 293 13>; 629 }; 630 631 wiz1_pll1_refclk: pll1-refclk { 632 clocks = <&k3_clks 293 0>, <&cmn_refclk1>; 633 #clock-cells = <0>; 634 assigned-clocks = <&wiz1_pll1_refclk>; 635 assigned-clock-parents = <&k3_clks 293 0>; 636 }; 637 638 wiz1_refclk_dig: refclk-dig { 639 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; 640 #clock-cells = <0>; 641 assigned-clocks = <&wiz1_refclk_dig>; 642 assigned-clock-parents = <&k3_clks 293 13>; 643 }; 644 645 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 646 clocks = <&wiz1_refclk_dig>; 647 #clock-cells = <0>; 648 }; 649 650 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 651 clocks = <&wiz1_pll1_refclk>; 652 #clock-cells = <0>; 653 }; 654 655 serdes1: serdes@5010000 { 656 compatible = "ti,sierra-phy-t0"; 657 reg-names = "serdes"; 658 reg = <0x5010000 0x10000>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 #clock-cells = <1>; 662 resets = <&serdes_wiz1 0>; 663 reset-names = "sierra_reset"; 664 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, 665 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; 666 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 667 "pll0_refclk", "pll1_refclk"; 668 }; 669 }; 670 671 serdes_wiz2: wiz@5020000 { 672 compatible = "ti,j721e-wiz-16g"; 673 #address-cells = <1>; 674 #size-cells = <1>; 675 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 676 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; 677 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 678 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 679 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 680 num-lanes = <2>; 681 #reset-cells = <1>; 682 ranges = <0x5020000 0x0 0x5020000 0x10000>; 683 684 wiz2_pll0_refclk: pll0-refclk { 685 clocks = <&k3_clks 294 11>, <&cmn_refclk>; 686 #clock-cells = <0>; 687 assigned-clocks = <&wiz2_pll0_refclk>; 688 assigned-clock-parents = <&k3_clks 294 11>; 689 }; 690 691 wiz2_pll1_refclk: pll1-refclk { 692 clocks = <&k3_clks 294 0>, <&cmn_refclk1>; 693 #clock-cells = <0>; 694 assigned-clocks = <&wiz2_pll1_refclk>; 695 assigned-clock-parents = <&k3_clks 294 0>; 696 }; 697 698 wiz2_refclk_dig: refclk-dig { 699 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; 700 #clock-cells = <0>; 701 assigned-clocks = <&wiz2_refclk_dig>; 702 assigned-clock-parents = <&k3_clks 294 11>; 703 }; 704 705 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 706 clocks = <&wiz2_refclk_dig>; 707 #clock-cells = <0>; 708 }; 709 710 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 711 clocks = <&wiz2_pll1_refclk>; 712 #clock-cells = <0>; 713 }; 714 715 serdes2: serdes@5020000 { 716 compatible = "ti,sierra-phy-t0"; 717 reg-names = "serdes"; 718 reg = <0x5020000 0x10000>; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 #clock-cells = <1>; 722 resets = <&serdes_wiz2 0>; 723 reset-names = "sierra_reset"; 724 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, 725 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; 726 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 727 "pll0_refclk", "pll1_refclk"; 728 }; 729 }; 730 731 serdes_wiz3: wiz@5030000 { 732 compatible = "ti,j721e-wiz-16g"; 733 #address-cells = <1>; 734 #size-cells = <1>; 735 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 736 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; 737 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 738 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 739 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 740 num-lanes = <2>; 741 #reset-cells = <1>; 742 ranges = <0x5030000 0x0 0x5030000 0x10000>; 743 744 wiz3_pll0_refclk: pll0-refclk { 745 clocks = <&k3_clks 295 9>, <&cmn_refclk>; 746 #clock-cells = <0>; 747 assigned-clocks = <&wiz3_pll0_refclk>; 748 assigned-clock-parents = <&k3_clks 295 9>; 749 }; 750 751 wiz3_pll1_refclk: pll1-refclk { 752 clocks = <&k3_clks 295 0>, <&cmn_refclk1>; 753 #clock-cells = <0>; 754 assigned-clocks = <&wiz3_pll1_refclk>; 755 assigned-clock-parents = <&k3_clks 295 0>; 756 }; 757 758 wiz3_refclk_dig: refclk-dig { 759 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; 760 #clock-cells = <0>; 761 assigned-clocks = <&wiz3_refclk_dig>; 762 assigned-clock-parents = <&k3_clks 295 9>; 763 }; 764 765 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 766 clocks = <&wiz3_refclk_dig>; 767 #clock-cells = <0>; 768 }; 769 770 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 771 clocks = <&wiz3_pll1_refclk>; 772 #clock-cells = <0>; 773 }; 774 775 serdes3: serdes@5030000 { 776 compatible = "ti,sierra-phy-t0"; 777 reg-names = "serdes"; 778 reg = <0x5030000 0x10000>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 #clock-cells = <1>; 782 resets = <&serdes_wiz3 0>; 783 reset-names = "sierra_reset"; 784 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, 785 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; 786 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 787 "pll0_refclk", "pll1_refclk"; 788 }; 789 }; 790 791 pcie0_rc: pcie@2900000 { 792 compatible = "ti,j721e-pcie-host"; 793 reg = <0x00 0x02900000 0x00 0x1000>, 794 <0x00 0x02907000 0x00 0x400>, 795 <0x00 0x0d000000 0x00 0x00800000>, 796 <0x00 0x10000000 0x00 0x00001000>; 797 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 798 interrupt-names = "link_state"; 799 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 800 device_type = "pci"; 801 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 802 max-link-speed = <3>; 803 num-lanes = <2>; 804 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 805 clocks = <&k3_clks 239 1>; 806 clock-names = "fck"; 807 #address-cells = <3>; 808 #size-cells = <2>; 809 bus-range = <0x0 0xff>; 810 vendor-id = <0x104c>; 811 device-id = <0xb00d>; 812 msi-map = <0x0 &gic_its 0x0 0x10000>; 813 dma-coherent; 814 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 815 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 816 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 817 }; 818 819 pcie1_rc: pcie@2910000 { 820 compatible = "ti,j721e-pcie-host"; 821 reg = <0x00 0x02910000 0x00 0x1000>, 822 <0x00 0x02917000 0x00 0x400>, 823 <0x00 0x0d800000 0x00 0x00800000>, 824 <0x00 0x18000000 0x00 0x00001000>; 825 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 826 interrupt-names = "link_state"; 827 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 828 device_type = "pci"; 829 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 830 max-link-speed = <3>; 831 num-lanes = <2>; 832 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 833 clocks = <&k3_clks 240 1>; 834 clock-names = "fck"; 835 #address-cells = <3>; 836 #size-cells = <2>; 837 bus-range = <0x0 0xff>; 838 vendor-id = <0x104c>; 839 device-id = <0xb00d>; 840 msi-map = <0x0 &gic_its 0x10000 0x10000>; 841 dma-coherent; 842 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 843 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 844 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 845 }; 846 847 pcie2_rc: pcie@2920000 { 848 compatible = "ti,j721e-pcie-host"; 849 reg = <0x00 0x02920000 0x00 0x1000>, 850 <0x00 0x02927000 0x00 0x400>, 851 <0x00 0x0e000000 0x00 0x00800000>, 852 <0x44 0x00000000 0x00 0x00001000>; 853 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 854 interrupt-names = "link_state"; 855 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 856 device_type = "pci"; 857 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 858 max-link-speed = <3>; 859 num-lanes = <2>; 860 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 861 clocks = <&k3_clks 241 1>; 862 clock-names = "fck"; 863 #address-cells = <3>; 864 #size-cells = <2>; 865 bus-range = <0x0 0xff>; 866 vendor-id = <0x104c>; 867 device-id = <0xb00d>; 868 msi-map = <0x0 &gic_its 0x20000 0x10000>; 869 dma-coherent; 870 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 871 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 872 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 873 }; 874 875 pcie3_rc: pcie@2930000 { 876 compatible = "ti,j721e-pcie-host"; 877 reg = <0x00 0x02930000 0x00 0x1000>, 878 <0x00 0x02937000 0x00 0x400>, 879 <0x00 0x0e800000 0x00 0x00800000>, 880 <0x44 0x10000000 0x00 0x00001000>; 881 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 882 interrupt-names = "link_state"; 883 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 884 device_type = "pci"; 885 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 886 max-link-speed = <3>; 887 num-lanes = <2>; 888 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 889 clocks = <&k3_clks 242 1>; 890 clock-names = "fck"; 891 #address-cells = <3>; 892 #size-cells = <2>; 893 bus-range = <0x0 0xff>; 894 vendor-id = <0x104c>; 895 device-id = <0xb00d>; 896 msi-map = <0x0 &gic_its 0x30000 0x10000>; 897 dma-coherent; 898 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 899 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 900 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 901 }; 902 903 serdes_wiz4: wiz@5050000 { 904 compatible = "ti,am64-wiz-10g"; 905 #address-cells = <1>; 906 #size-cells = <1>; 907 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 908 clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; 909 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 910 assigned-clocks = <&k3_clks 297 9>; 911 assigned-clock-parents = <&k3_clks 297 10>; 912 assigned-clock-rates = <19200000>; 913 num-lanes = <4>; 914 #reset-cells = <1>; 915 #clock-cells = <1>; 916 ranges = <0x05050000 0x00 0x05050000 0x010000>, 917 <0x0a030a00 0x00 0x0a030a00 0x40>; 918 919 serdes4: serdes@5050000 { 920 /* 921 * Note: we also map DPTX PHY registers as the Torrent 922 * needs to manage those. 923 */ 924 compatible = "ti,j721e-serdes-10g"; 925 reg = <0x05050000 0x010000>, 926 <0x0a030a00 0x40>; /* DPTX PHY */ 927 reg-names = "torrent_phy", "dptx_phy"; 928 929 resets = <&serdes_wiz4 0>; 930 reset-names = "torrent_reset"; 931 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; 932 clock-names = "refclk"; 933 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 934 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 935 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 936 assigned-clock-parents = <&k3_clks 297 9>, 937 <&k3_clks 297 9>, 938 <&k3_clks 297 9>; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 }; 942 }; 943 944 main_uart0: serial@2800000 { 945 compatible = "ti,j721e-uart", "ti,am654-uart"; 946 reg = <0x00 0x02800000 0x00 0x100>; 947 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 948 clock-frequency = <48000000>; 949 current-speed = <115200>; 950 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 951 clocks = <&k3_clks 146 0>; 952 clock-names = "fclk"; 953 status = "disabled"; 954 }; 955 956 main_uart1: serial@2810000 { 957 compatible = "ti,j721e-uart", "ti,am654-uart"; 958 reg = <0x00 0x02810000 0x00 0x100>; 959 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 960 clock-frequency = <48000000>; 961 current-speed = <115200>; 962 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 963 clocks = <&k3_clks 278 0>; 964 clock-names = "fclk"; 965 status = "disabled"; 966 }; 967 968 main_uart2: serial@2820000 { 969 compatible = "ti,j721e-uart", "ti,am654-uart"; 970 reg = <0x00 0x02820000 0x00 0x100>; 971 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 972 clock-frequency = <48000000>; 973 current-speed = <115200>; 974 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 975 clocks = <&k3_clks 279 0>; 976 clock-names = "fclk"; 977 status = "disabled"; 978 }; 979 980 main_uart3: serial@2830000 { 981 compatible = "ti,j721e-uart", "ti,am654-uart"; 982 reg = <0x00 0x02830000 0x00 0x100>; 983 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 984 clock-frequency = <48000000>; 985 current-speed = <115200>; 986 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 987 clocks = <&k3_clks 280 0>; 988 clock-names = "fclk"; 989 status = "disabled"; 990 }; 991 992 main_uart4: serial@2840000 { 993 compatible = "ti,j721e-uart", "ti,am654-uart"; 994 reg = <0x00 0x02840000 0x00 0x100>; 995 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 996 clock-frequency = <48000000>; 997 current-speed = <115200>; 998 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 999 clocks = <&k3_clks 281 0>; 1000 clock-names = "fclk"; 1001 status = "disabled"; 1002 }; 1003 1004 main_uart5: serial@2850000 { 1005 compatible = "ti,j721e-uart", "ti,am654-uart"; 1006 reg = <0x00 0x02850000 0x00 0x100>; 1007 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1008 clock-frequency = <48000000>; 1009 current-speed = <115200>; 1010 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 1011 clocks = <&k3_clks 282 0>; 1012 clock-names = "fclk"; 1013 status = "disabled"; 1014 }; 1015 1016 main_uart6: serial@2860000 { 1017 compatible = "ti,j721e-uart", "ti,am654-uart"; 1018 reg = <0x00 0x02860000 0x00 0x100>; 1019 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 1020 clock-frequency = <48000000>; 1021 current-speed = <115200>; 1022 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 1023 clocks = <&k3_clks 283 0>; 1024 clock-names = "fclk"; 1025 status = "disabled"; 1026 }; 1027 1028 main_uart7: serial@2870000 { 1029 compatible = "ti,j721e-uart", "ti,am654-uart"; 1030 reg = <0x00 0x02870000 0x00 0x100>; 1031 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1032 clock-frequency = <48000000>; 1033 current-speed = <115200>; 1034 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 1035 clocks = <&k3_clks 284 0>; 1036 clock-names = "fclk"; 1037 status = "disabled"; 1038 }; 1039 1040 main_uart8: serial@2880000 { 1041 compatible = "ti,j721e-uart", "ti,am654-uart"; 1042 reg = <0x00 0x02880000 0x00 0x100>; 1043 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 1044 clock-frequency = <48000000>; 1045 current-speed = <115200>; 1046 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 1047 clocks = <&k3_clks 285 0>; 1048 clock-names = "fclk"; 1049 status = "disabled"; 1050 }; 1051 1052 main_uart9: serial@2890000 { 1053 compatible = "ti,j721e-uart", "ti,am654-uart"; 1054 reg = <0x00 0x02890000 0x00 0x100>; 1055 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 1056 clock-frequency = <48000000>; 1057 current-speed = <115200>; 1058 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 1059 clocks = <&k3_clks 286 0>; 1060 clock-names = "fclk"; 1061 status = "disabled"; 1062 }; 1063 1064 main_gpio0: gpio@600000 { 1065 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1066 reg = <0x0 0x00600000 0x0 0x100>; 1067 gpio-controller; 1068 #gpio-cells = <2>; 1069 interrupt-parent = <&main_gpio_intr>; 1070 interrupts = <256>, <257>, <258>, <259>, 1071 <260>, <261>, <262>, <263>; 1072 interrupt-controller; 1073 #interrupt-cells = <2>; 1074 ti,ngpio = <128>; 1075 ti,davinci-gpio-unbanked = <0>; 1076 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 1077 clocks = <&k3_clks 105 0>; 1078 clock-names = "gpio"; 1079 }; 1080 1081 main_gpio1: gpio@601000 { 1082 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1083 reg = <0x0 0x00601000 0x0 0x100>; 1084 gpio-controller; 1085 #gpio-cells = <2>; 1086 interrupt-parent = <&main_gpio_intr>; 1087 interrupts = <288>, <289>, <290>; 1088 interrupt-controller; 1089 #interrupt-cells = <2>; 1090 ti,ngpio = <36>; 1091 ti,davinci-gpio-unbanked = <0>; 1092 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 1093 clocks = <&k3_clks 106 0>; 1094 clock-names = "gpio"; 1095 }; 1096 1097 main_gpio2: gpio@610000 { 1098 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1099 reg = <0x0 0x00610000 0x0 0x100>; 1100 gpio-controller; 1101 #gpio-cells = <2>; 1102 interrupt-parent = <&main_gpio_intr>; 1103 interrupts = <264>, <265>, <266>, <267>, 1104 <268>, <269>, <270>, <271>; 1105 interrupt-controller; 1106 #interrupt-cells = <2>; 1107 ti,ngpio = <128>; 1108 ti,davinci-gpio-unbanked = <0>; 1109 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 1110 clocks = <&k3_clks 107 0>; 1111 clock-names = "gpio"; 1112 }; 1113 1114 main_gpio3: gpio@611000 { 1115 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1116 reg = <0x0 0x00611000 0x0 0x100>; 1117 gpio-controller; 1118 #gpio-cells = <2>; 1119 interrupt-parent = <&main_gpio_intr>; 1120 interrupts = <292>, <293>, <294>; 1121 interrupt-controller; 1122 #interrupt-cells = <2>; 1123 ti,ngpio = <36>; 1124 ti,davinci-gpio-unbanked = <0>; 1125 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 1126 clocks = <&k3_clks 108 0>; 1127 clock-names = "gpio"; 1128 }; 1129 1130 main_gpio4: gpio@620000 { 1131 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1132 reg = <0x0 0x00620000 0x0 0x100>; 1133 gpio-controller; 1134 #gpio-cells = <2>; 1135 interrupt-parent = <&main_gpio_intr>; 1136 interrupts = <272>, <273>, <274>, <275>, 1137 <276>, <277>, <278>, <279>; 1138 interrupt-controller; 1139 #interrupt-cells = <2>; 1140 ti,ngpio = <128>; 1141 ti,davinci-gpio-unbanked = <0>; 1142 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 1143 clocks = <&k3_clks 109 0>; 1144 clock-names = "gpio"; 1145 }; 1146 1147 main_gpio5: gpio@621000 { 1148 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1149 reg = <0x0 0x00621000 0x0 0x100>; 1150 gpio-controller; 1151 #gpio-cells = <2>; 1152 interrupt-parent = <&main_gpio_intr>; 1153 interrupts = <296>, <297>, <298>; 1154 interrupt-controller; 1155 #interrupt-cells = <2>; 1156 ti,ngpio = <36>; 1157 ti,davinci-gpio-unbanked = <0>; 1158 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 1159 clocks = <&k3_clks 110 0>; 1160 clock-names = "gpio"; 1161 }; 1162 1163 main_gpio6: gpio@630000 { 1164 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1165 reg = <0x0 0x00630000 0x0 0x100>; 1166 gpio-controller; 1167 #gpio-cells = <2>; 1168 interrupt-parent = <&main_gpio_intr>; 1169 interrupts = <280>, <281>, <282>, <283>, 1170 <284>, <285>, <286>, <287>; 1171 interrupt-controller; 1172 #interrupt-cells = <2>; 1173 ti,ngpio = <128>; 1174 ti,davinci-gpio-unbanked = <0>; 1175 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1176 clocks = <&k3_clks 111 0>; 1177 clock-names = "gpio"; 1178 }; 1179 1180 main_gpio7: gpio@631000 { 1181 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1182 reg = <0x0 0x00631000 0x0 0x100>; 1183 gpio-controller; 1184 #gpio-cells = <2>; 1185 interrupt-parent = <&main_gpio_intr>; 1186 interrupts = <300>, <301>, <302>; 1187 interrupt-controller; 1188 #interrupt-cells = <2>; 1189 ti,ngpio = <36>; 1190 ti,davinci-gpio-unbanked = <0>; 1191 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1192 clocks = <&k3_clks 112 0>; 1193 clock-names = "gpio"; 1194 }; 1195 1196 main_sdhci0: mmc@4f80000 { 1197 compatible = "ti,j721e-sdhci-8bit"; 1198 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1199 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1200 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1201 clock-names = "clk_ahb", "clk_xin"; 1202 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; 1203 assigned-clocks = <&k3_clks 91 1>; 1204 assigned-clock-parents = <&k3_clks 91 2>; 1205 bus-width = <8>; 1206 mmc-hs200-1_8v; 1207 mmc-ddr-1_8v; 1208 ti,otap-del-sel-legacy = <0x0>; 1209 ti,otap-del-sel-mmc-hs = <0x0>; 1210 ti,otap-del-sel-ddr52 = <0x5>; 1211 ti,otap-del-sel-hs200 = <0x6>; 1212 ti,otap-del-sel-hs400 = <0x0>; 1213 ti,itap-del-sel-legacy = <0x10>; 1214 ti,itap-del-sel-mmc-hs = <0xa>; 1215 ti,itap-del-sel-ddr52 = <0x3>; 1216 ti,trm-icp = <0x8>; 1217 dma-coherent; 1218 }; 1219 1220 main_sdhci1: mmc@4fb0000 { 1221 compatible = "ti,j721e-sdhci-4bit"; 1222 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1223 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1224 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1225 clock-names = "clk_ahb", "clk_xin"; 1226 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; 1227 assigned-clocks = <&k3_clks 92 0>; 1228 assigned-clock-parents = <&k3_clks 92 1>; 1229 ti,otap-del-sel-legacy = <0x0>; 1230 ti,otap-del-sel-sd-hs = <0x0>; 1231 ti,otap-del-sel-sdr12 = <0xf>; 1232 ti,otap-del-sel-sdr25 = <0xf>; 1233 ti,otap-del-sel-sdr50 = <0xc>; 1234 ti,otap-del-sel-ddr50 = <0xc>; 1235 ti,otap-del-sel-sdr104 = <0x5>; 1236 ti,itap-del-sel-legacy = <0x0>; 1237 ti,itap-del-sel-sd-hs = <0x0>; 1238 ti,itap-del-sel-sdr12 = <0x0>; 1239 ti,itap-del-sel-sdr25 = <0x0>; 1240 ti,itap-del-sel-ddr50 = <0x2>; 1241 ti,trm-icp = <0x8>; 1242 ti,clkbuf-sel = <0x7>; 1243 dma-coherent; 1244 sdhci-caps-mask = <0x2 0x0>; 1245 }; 1246 1247 main_sdhci2: mmc@4f98000 { 1248 compatible = "ti,j721e-sdhci-4bit"; 1249 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1250 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1251 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1252 clock-names = "clk_ahb", "clk_xin"; 1253 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; 1254 assigned-clocks = <&k3_clks 93 0>; 1255 assigned-clock-parents = <&k3_clks 93 1>; 1256 ti,otap-del-sel-legacy = <0x0>; 1257 ti,otap-del-sel-sd-hs = <0x0>; 1258 ti,otap-del-sel-sdr12 = <0xf>; 1259 ti,otap-del-sel-sdr25 = <0xf>; 1260 ti,otap-del-sel-sdr50 = <0xc>; 1261 ti,otap-del-sel-ddr50 = <0xc>; 1262 ti,otap-del-sel-sdr104 = <0x5>; 1263 ti,itap-del-sel-legacy = <0x0>; 1264 ti,itap-del-sel-sd-hs = <0x0>; 1265 ti,itap-del-sel-sdr12 = <0x0>; 1266 ti,itap-del-sel-sdr25 = <0x0>; 1267 ti,itap-del-sel-ddr50 = <0x2>; 1268 ti,trm-icp = <0x8>; 1269 ti,clkbuf-sel = <0x7>; 1270 dma-coherent; 1271 sdhci-caps-mask = <0x2 0x0>; 1272 }; 1273 1274 usbss0: cdns-usb@4104000 { 1275 compatible = "ti,j721e-usb"; 1276 reg = <0x00 0x4104000 0x00 0x100>; 1277 dma-coherent; 1278 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1279 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1280 clock-names = "ref", "lpm"; 1281 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1282 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1283 #address-cells = <2>; 1284 #size-cells = <2>; 1285 ranges; 1286 1287 usb0: usb@6000000 { 1288 compatible = "cdns,usb3"; 1289 reg = <0x00 0x6000000 0x00 0x10000>, 1290 <0x00 0x6010000 0x00 0x10000>, 1291 <0x00 0x6020000 0x00 0x10000>; 1292 reg-names = "otg", "xhci", "dev"; 1293 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1294 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1295 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1296 interrupt-names = "host", 1297 "peripheral", 1298 "otg"; 1299 maximum-speed = "super-speed"; 1300 dr_mode = "otg"; 1301 }; 1302 }; 1303 1304 usbss1: cdns-usb@4114000 { 1305 compatible = "ti,j721e-usb"; 1306 reg = <0x00 0x4114000 0x00 0x100>; 1307 dma-coherent; 1308 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1309 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1310 clock-names = "ref", "lpm"; 1311 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1312 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1313 #address-cells = <2>; 1314 #size-cells = <2>; 1315 ranges; 1316 1317 usb1: usb@6400000 { 1318 compatible = "cdns,usb3"; 1319 reg = <0x00 0x6400000 0x00 0x10000>, 1320 <0x00 0x6410000 0x00 0x10000>, 1321 <0x00 0x6420000 0x00 0x10000>; 1322 reg-names = "otg", "xhci", "dev"; 1323 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1324 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1325 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1326 interrupt-names = "host", 1327 "peripheral", 1328 "otg"; 1329 maximum-speed = "super-speed"; 1330 dr_mode = "otg"; 1331 }; 1332 }; 1333 1334 main_i2c0: i2c@2000000 { 1335 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1336 reg = <0x0 0x2000000 0x0 0x100>; 1337 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 clock-names = "fck"; 1341 clocks = <&k3_clks 187 0>; 1342 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1343 status = "disabled"; 1344 }; 1345 1346 main_i2c1: i2c@2010000 { 1347 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1348 reg = <0x0 0x2010000 0x0 0x100>; 1349 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 clock-names = "fck"; 1353 clocks = <&k3_clks 188 0>; 1354 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1355 status = "disabled"; 1356 }; 1357 1358 main_i2c2: i2c@2020000 { 1359 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1360 reg = <0x0 0x2020000 0x0 0x100>; 1361 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 clock-names = "fck"; 1365 clocks = <&k3_clks 189 0>; 1366 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1367 status = "disabled"; 1368 }; 1369 1370 main_i2c3: i2c@2030000 { 1371 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1372 reg = <0x0 0x2030000 0x0 0x100>; 1373 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1374 #address-cells = <1>; 1375 #size-cells = <0>; 1376 clock-names = "fck"; 1377 clocks = <&k3_clks 190 0>; 1378 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1379 status = "disabled"; 1380 }; 1381 1382 main_i2c4: i2c@2040000 { 1383 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1384 reg = <0x0 0x2040000 0x0 0x100>; 1385 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 clock-names = "fck"; 1389 clocks = <&k3_clks 191 0>; 1390 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1391 status = "disabled"; 1392 }; 1393 1394 main_i2c5: i2c@2050000 { 1395 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1396 reg = <0x0 0x2050000 0x0 0x100>; 1397 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 clock-names = "fck"; 1401 clocks = <&k3_clks 192 0>; 1402 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1403 status = "disabled"; 1404 }; 1405 1406 main_i2c6: i2c@2060000 { 1407 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1408 reg = <0x0 0x2060000 0x0 0x100>; 1409 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 clock-names = "fck"; 1413 clocks = <&k3_clks 193 0>; 1414 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1415 status = "disabled"; 1416 }; 1417 1418 ufs_wrapper: ufs-wrapper@4e80000 { 1419 compatible = "ti,j721e-ufs"; 1420 reg = <0x0 0x4e80000 0x0 0x100>; 1421 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1422 clocks = <&k3_clks 277 1>; 1423 assigned-clocks = <&k3_clks 277 1>; 1424 assigned-clock-parents = <&k3_clks 277 4>; 1425 ranges; 1426 #address-cells = <2>; 1427 #size-cells = <2>; 1428 1429 ufs@4e84000 { 1430 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1431 reg = <0x0 0x4e84000 0x0 0x10000>; 1432 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1433 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1434 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1435 clock-names = "core_clk", "phy_clk", "ref_clk"; 1436 dma-coherent; 1437 }; 1438 }; 1439 1440 mhdp: dp-bridge@a000000 { 1441 compatible = "ti,j721e-mhdp8546"; 1442 /* 1443 * Note: we do not map DPTX PHY area, as that is handled by 1444 * the PHY driver. 1445 */ 1446 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ 1447 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ 1448 reg-names = "mhdptx", "j721e-intg"; 1449 1450 clocks = <&k3_clks 151 36>; 1451 1452 interrupt-parent = <&gic500>; 1453 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 1454 1455 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 1456 1457 dp0_ports: ports { 1458 #address-cells = <1>; 1459 #size-cells = <0>; 1460 1461 port@0 { 1462 reg = <0>; 1463 }; 1464 1465 port@4 { 1466 reg = <4>; 1467 }; 1468 }; 1469 }; 1470 1471 dss: dss@4a00000 { 1472 compatible = "ti,j721e-dss"; 1473 reg = 1474 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1475 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1476 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1477 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1478 1479 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1480 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1481 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1482 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1483 1484 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1485 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1486 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1487 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1488 1489 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1490 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1491 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1492 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1493 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1494 1495 reg-names = "common_m", "common_s0", 1496 "common_s1", "common_s2", 1497 "vidl1", "vidl2","vid1","vid2", 1498 "ovr1", "ovr2", "ovr3", "ovr4", 1499 "vp1", "vp2", "vp3", "vp4", 1500 "wb"; 1501 1502 clocks = <&k3_clks 152 0>, 1503 <&k3_clks 152 1>, 1504 <&k3_clks 152 4>, 1505 <&k3_clks 152 9>, 1506 <&k3_clks 152 13>; 1507 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1508 1509 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1510 1511 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1515 interrupt-names = "common_m", 1516 "common_s0", 1517 "common_s1", 1518 "common_s2"; 1519 1520 dss_ports: ports { 1521 }; 1522 }; 1523 1524 mcasp0: mcasp@2b00000 { 1525 compatible = "ti,am33xx-mcasp-audio"; 1526 reg = <0x0 0x02b00000 0x0 0x2000>, 1527 <0x0 0x02b08000 0x0 0x1000>; 1528 reg-names = "mpu","dat"; 1529 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1531 interrupt-names = "tx", "rx"; 1532 1533 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1534 dma-names = "tx", "rx"; 1535 1536 clocks = <&k3_clks 174 1>; 1537 clock-names = "fck"; 1538 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1539 status = "disabled"; 1540 }; 1541 1542 mcasp1: mcasp@2b10000 { 1543 compatible = "ti,am33xx-mcasp-audio"; 1544 reg = <0x0 0x02b10000 0x0 0x2000>, 1545 <0x0 0x02b18000 0x0 0x1000>; 1546 reg-names = "mpu","dat"; 1547 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1549 interrupt-names = "tx", "rx"; 1550 1551 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1552 dma-names = "tx", "rx"; 1553 1554 clocks = <&k3_clks 175 1>; 1555 clock-names = "fck"; 1556 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1557 status = "disabled"; 1558 }; 1559 1560 mcasp2: mcasp@2b20000 { 1561 compatible = "ti,am33xx-mcasp-audio"; 1562 reg = <0x0 0x02b20000 0x0 0x2000>, 1563 <0x0 0x02b28000 0x0 0x1000>; 1564 reg-names = "mpu","dat"; 1565 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1567 interrupt-names = "tx", "rx"; 1568 1569 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1570 dma-names = "tx", "rx"; 1571 1572 clocks = <&k3_clks 176 1>; 1573 clock-names = "fck"; 1574 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1575 status = "disabled"; 1576 }; 1577 1578 mcasp3: mcasp@2b30000 { 1579 compatible = "ti,am33xx-mcasp-audio"; 1580 reg = <0x0 0x02b30000 0x0 0x2000>, 1581 <0x0 0x02b38000 0x0 0x1000>; 1582 reg-names = "mpu","dat"; 1583 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1585 interrupt-names = "tx", "rx"; 1586 1587 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1588 dma-names = "tx", "rx"; 1589 1590 clocks = <&k3_clks 177 1>; 1591 clock-names = "fck"; 1592 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1593 status = "disabled"; 1594 }; 1595 1596 mcasp4: mcasp@2b40000 { 1597 compatible = "ti,am33xx-mcasp-audio"; 1598 reg = <0x0 0x02b40000 0x0 0x2000>, 1599 <0x0 0x02b48000 0x0 0x1000>; 1600 reg-names = "mpu","dat"; 1601 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1603 interrupt-names = "tx", "rx"; 1604 1605 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1606 dma-names = "tx", "rx"; 1607 1608 clocks = <&k3_clks 178 1>; 1609 clock-names = "fck"; 1610 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1611 status = "disabled"; 1612 }; 1613 1614 mcasp5: mcasp@2b50000 { 1615 compatible = "ti,am33xx-mcasp-audio"; 1616 reg = <0x0 0x02b50000 0x0 0x2000>, 1617 <0x0 0x02b58000 0x0 0x1000>; 1618 reg-names = "mpu","dat"; 1619 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1621 interrupt-names = "tx", "rx"; 1622 1623 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1624 dma-names = "tx", "rx"; 1625 1626 clocks = <&k3_clks 179 1>; 1627 clock-names = "fck"; 1628 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1629 status = "disabled"; 1630 }; 1631 1632 mcasp6: mcasp@2b60000 { 1633 compatible = "ti,am33xx-mcasp-audio"; 1634 reg = <0x0 0x02b60000 0x0 0x2000>, 1635 <0x0 0x02b68000 0x0 0x1000>; 1636 reg-names = "mpu","dat"; 1637 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1639 interrupt-names = "tx", "rx"; 1640 1641 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1642 dma-names = "tx", "rx"; 1643 1644 clocks = <&k3_clks 180 1>; 1645 clock-names = "fck"; 1646 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1647 status = "disabled"; 1648 }; 1649 1650 mcasp7: mcasp@2b70000 { 1651 compatible = "ti,am33xx-mcasp-audio"; 1652 reg = <0x0 0x02b70000 0x0 0x2000>, 1653 <0x0 0x02b78000 0x0 0x1000>; 1654 reg-names = "mpu","dat"; 1655 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1657 interrupt-names = "tx", "rx"; 1658 1659 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1660 dma-names = "tx", "rx"; 1661 1662 clocks = <&k3_clks 181 1>; 1663 clock-names = "fck"; 1664 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1665 status = "disabled"; 1666 }; 1667 1668 mcasp8: mcasp@2b80000 { 1669 compatible = "ti,am33xx-mcasp-audio"; 1670 reg = <0x0 0x02b80000 0x0 0x2000>, 1671 <0x0 0x02b88000 0x0 0x1000>; 1672 reg-names = "mpu","dat"; 1673 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1675 interrupt-names = "tx", "rx"; 1676 1677 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1678 dma-names = "tx", "rx"; 1679 1680 clocks = <&k3_clks 182 1>; 1681 clock-names = "fck"; 1682 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1683 status = "disabled"; 1684 }; 1685 1686 mcasp9: mcasp@2b90000 { 1687 compatible = "ti,am33xx-mcasp-audio"; 1688 reg = <0x0 0x02b90000 0x0 0x2000>, 1689 <0x0 0x02b98000 0x0 0x1000>; 1690 reg-names = "mpu","dat"; 1691 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1693 interrupt-names = "tx", "rx"; 1694 1695 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1696 dma-names = "tx", "rx"; 1697 1698 clocks = <&k3_clks 183 1>; 1699 clock-names = "fck"; 1700 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1701 status = "disabled"; 1702 }; 1703 1704 mcasp10: mcasp@2ba0000 { 1705 compatible = "ti,am33xx-mcasp-audio"; 1706 reg = <0x0 0x02ba0000 0x0 0x2000>, 1707 <0x0 0x02ba8000 0x0 0x1000>; 1708 reg-names = "mpu","dat"; 1709 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1711 interrupt-names = "tx", "rx"; 1712 1713 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1714 dma-names = "tx", "rx"; 1715 1716 clocks = <&k3_clks 184 1>; 1717 clock-names = "fck"; 1718 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1719 status = "disabled"; 1720 }; 1721 1722 mcasp11: mcasp@2bb0000 { 1723 compatible = "ti,am33xx-mcasp-audio"; 1724 reg = <0x0 0x02bb0000 0x0 0x2000>, 1725 <0x0 0x02bb8000 0x0 0x1000>; 1726 reg-names = "mpu","dat"; 1727 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1729 interrupt-names = "tx", "rx"; 1730 1731 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1732 dma-names = "tx", "rx"; 1733 1734 clocks = <&k3_clks 185 1>; 1735 clock-names = "fck"; 1736 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1737 status = "disabled"; 1738 }; 1739 1740 watchdog0: watchdog@2200000 { 1741 compatible = "ti,j7-rti-wdt"; 1742 reg = <0x0 0x2200000 0x0 0x100>; 1743 clocks = <&k3_clks 252 1>; 1744 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1745 assigned-clocks = <&k3_clks 252 1>; 1746 assigned-clock-parents = <&k3_clks 252 5>; 1747 }; 1748 1749 watchdog1: watchdog@2210000 { 1750 compatible = "ti,j7-rti-wdt"; 1751 reg = <0x0 0x2210000 0x0 0x100>; 1752 clocks = <&k3_clks 253 1>; 1753 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1754 assigned-clocks = <&k3_clks 253 1>; 1755 assigned-clock-parents = <&k3_clks 253 5>; 1756 }; 1757 1758 main_r5fss0: r5fss@5c00000 { 1759 compatible = "ti,j721e-r5fss"; 1760 ti,cluster-mode = <1>; 1761 #address-cells = <1>; 1762 #size-cells = <1>; 1763 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1764 <0x5d00000 0x00 0x5d00000 0x20000>; 1765 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 1766 1767 main_r5fss0_core0: r5f@5c00000 { 1768 compatible = "ti,j721e-r5f"; 1769 reg = <0x5c00000 0x00008000>, 1770 <0x5c10000 0x00008000>; 1771 reg-names = "atcm", "btcm"; 1772 ti,sci = <&dmsc>; 1773 ti,sci-dev-id = <245>; 1774 ti,sci-proc-ids = <0x06 0xff>; 1775 resets = <&k3_reset 245 1>; 1776 firmware-name = "j7-main-r5f0_0-fw"; 1777 ti,atcm-enable = <1>; 1778 ti,btcm-enable = <1>; 1779 ti,loczrama = <1>; 1780 }; 1781 1782 main_r5fss0_core1: r5f@5d00000 { 1783 compatible = "ti,j721e-r5f"; 1784 reg = <0x5d00000 0x00008000>, 1785 <0x5d10000 0x00008000>; 1786 reg-names = "atcm", "btcm"; 1787 ti,sci = <&dmsc>; 1788 ti,sci-dev-id = <246>; 1789 ti,sci-proc-ids = <0x07 0xff>; 1790 resets = <&k3_reset 246 1>; 1791 firmware-name = "j7-main-r5f0_1-fw"; 1792 ti,atcm-enable = <1>; 1793 ti,btcm-enable = <1>; 1794 ti,loczrama = <1>; 1795 }; 1796 }; 1797 1798 main_r5fss1: r5fss@5e00000 { 1799 compatible = "ti,j721e-r5fss"; 1800 ti,cluster-mode = <1>; 1801 #address-cells = <1>; 1802 #size-cells = <1>; 1803 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1804 <0x5f00000 0x00 0x5f00000 0x20000>; 1805 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; 1806 1807 main_r5fss1_core0: r5f@5e00000 { 1808 compatible = "ti,j721e-r5f"; 1809 reg = <0x5e00000 0x00008000>, 1810 <0x5e10000 0x00008000>; 1811 reg-names = "atcm", "btcm"; 1812 ti,sci = <&dmsc>; 1813 ti,sci-dev-id = <247>; 1814 ti,sci-proc-ids = <0x08 0xff>; 1815 resets = <&k3_reset 247 1>; 1816 firmware-name = "j7-main-r5f1_0-fw"; 1817 ti,atcm-enable = <1>; 1818 ti,btcm-enable = <1>; 1819 ti,loczrama = <1>; 1820 }; 1821 1822 main_r5fss1_core1: r5f@5f00000 { 1823 compatible = "ti,j721e-r5f"; 1824 reg = <0x5f00000 0x00008000>, 1825 <0x5f10000 0x00008000>; 1826 reg-names = "atcm", "btcm"; 1827 ti,sci = <&dmsc>; 1828 ti,sci-dev-id = <248>; 1829 ti,sci-proc-ids = <0x09 0xff>; 1830 resets = <&k3_reset 248 1>; 1831 firmware-name = "j7-main-r5f1_1-fw"; 1832 ti,atcm-enable = <1>; 1833 ti,btcm-enable = <1>; 1834 ti,loczrama = <1>; 1835 }; 1836 }; 1837 1838 c66_0: dsp@4d80800000 { 1839 compatible = "ti,j721e-c66-dsp"; 1840 reg = <0x4d 0x80800000 0x00 0x00048000>, 1841 <0x4d 0x80e00000 0x00 0x00008000>, 1842 <0x4d 0x80f00000 0x00 0x00008000>; 1843 reg-names = "l2sram", "l1pram", "l1dram"; 1844 ti,sci = <&dmsc>; 1845 ti,sci-dev-id = <142>; 1846 ti,sci-proc-ids = <0x03 0xff>; 1847 resets = <&k3_reset 142 1>; 1848 firmware-name = "j7-c66_0-fw"; 1849 }; 1850 1851 c66_1: dsp@4d81800000 { 1852 compatible = "ti,j721e-c66-dsp"; 1853 reg = <0x4d 0x81800000 0x00 0x00048000>, 1854 <0x4d 0x81e00000 0x00 0x00008000>, 1855 <0x4d 0x81f00000 0x00 0x00008000>; 1856 reg-names = "l2sram", "l1pram", "l1dram"; 1857 ti,sci = <&dmsc>; 1858 ti,sci-dev-id = <143>; 1859 ti,sci-proc-ids = <0x04 0xff>; 1860 resets = <&k3_reset 143 1>; 1861 firmware-name = "j7-c66_1-fw"; 1862 }; 1863 1864 c71_0: dsp@64800000 { 1865 compatible = "ti,j721e-c71-dsp"; 1866 reg = <0x00 0x64800000 0x00 0x00080000>, 1867 <0x00 0x64e00000 0x00 0x0000c000>; 1868 reg-names = "l2sram", "l1dram"; 1869 ti,sci = <&dmsc>; 1870 ti,sci-dev-id = <15>; 1871 ti,sci-proc-ids = <0x30 0xff>; 1872 resets = <&k3_reset 15 1>; 1873 firmware-name = "j7-c71_0-fw"; 1874 }; 1875 1876 icssg0: icssg@b000000 { 1877 compatible = "ti,j721e-icssg"; 1878 reg = <0x00 0xb000000 0x00 0x80000>; 1879 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 1880 #address-cells = <1>; 1881 #size-cells = <1>; 1882 ranges = <0x0 0x00 0x0b000000 0x100000>; 1883 1884 icssg0_mem: memories@0 { 1885 reg = <0x0 0x2000>, 1886 <0x2000 0x2000>, 1887 <0x10000 0x10000>; 1888 reg-names = "dram0", "dram1", 1889 "shrdram2"; 1890 }; 1891 1892 icssg0_cfg: cfg@26000 { 1893 compatible = "ti,pruss-cfg", "syscon"; 1894 reg = <0x26000 0x200>; 1895 #address-cells = <1>; 1896 #size-cells = <1>; 1897 ranges = <0x0 0x26000 0x2000>; 1898 1899 clocks { 1900 #address-cells = <1>; 1901 #size-cells = <0>; 1902 1903 icssg0_coreclk_mux: coreclk-mux@3c { 1904 reg = <0x3c>; 1905 #clock-cells = <0>; 1906 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ 1907 <&k3_clks 119 1>; /* icssg0_iclk */ 1908 assigned-clocks = <&icssg0_coreclk_mux>; 1909 assigned-clock-parents = <&k3_clks 119 1>; 1910 }; 1911 1912 icssg0_iepclk_mux: iepclk-mux@30 { 1913 reg = <0x30>; 1914 #clock-cells = <0>; 1915 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ 1916 <&icssg0_coreclk_mux>; /* core_clk */ 1917 assigned-clocks = <&icssg0_iepclk_mux>; 1918 assigned-clock-parents = <&icssg0_coreclk_mux>; 1919 }; 1920 }; 1921 }; 1922 1923 icssg0_mii_rt: mii-rt@32000 { 1924 compatible = "ti,pruss-mii", "syscon"; 1925 reg = <0x32000 0x100>; 1926 }; 1927 1928 icssg0_mii_g_rt: mii-g-rt@33000 { 1929 compatible = "ti,pruss-mii-g", "syscon"; 1930 reg = <0x33000 0x1000>; 1931 }; 1932 1933 icssg0_intc: interrupt-controller@20000 { 1934 compatible = "ti,icssg-intc"; 1935 reg = <0x20000 0x2000>; 1936 interrupt-controller; 1937 #interrupt-cells = <3>; 1938 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1946 interrupt-names = "host_intr0", "host_intr1", 1947 "host_intr2", "host_intr3", 1948 "host_intr4", "host_intr5", 1949 "host_intr6", "host_intr7"; 1950 }; 1951 1952 pru0_0: pru@34000 { 1953 compatible = "ti,j721e-pru"; 1954 reg = <0x34000 0x3000>, 1955 <0x22000 0x100>, 1956 <0x22400 0x100>; 1957 reg-names = "iram", "control", "debug"; 1958 firmware-name = "j7-pru0_0-fw"; 1959 }; 1960 1961 rtu0_0: rtu@4000 { 1962 compatible = "ti,j721e-rtu"; 1963 reg = <0x4000 0x2000>, 1964 <0x23000 0x100>, 1965 <0x23400 0x100>; 1966 reg-names = "iram", "control", "debug"; 1967 firmware-name = "j7-rtu0_0-fw"; 1968 }; 1969 1970 tx_pru0_0: txpru@a000 { 1971 compatible = "ti,j721e-tx-pru"; 1972 reg = <0xa000 0x1800>, 1973 <0x25000 0x100>, 1974 <0x25400 0x100>; 1975 reg-names = "iram", "control", "debug"; 1976 firmware-name = "j7-txpru0_0-fw"; 1977 }; 1978 1979 pru0_1: pru@38000 { 1980 compatible = "ti,j721e-pru"; 1981 reg = <0x38000 0x3000>, 1982 <0x24000 0x100>, 1983 <0x24400 0x100>; 1984 reg-names = "iram", "control", "debug"; 1985 firmware-name = "j7-pru0_1-fw"; 1986 }; 1987 1988 rtu0_1: rtu@6000 { 1989 compatible = "ti,j721e-rtu"; 1990 reg = <0x6000 0x2000>, 1991 <0x23800 0x100>, 1992 <0x23c00 0x100>; 1993 reg-names = "iram", "control", "debug"; 1994 firmware-name = "j7-rtu0_1-fw"; 1995 }; 1996 1997 tx_pru0_1: txpru@c000 { 1998 compatible = "ti,j721e-tx-pru"; 1999 reg = <0xc000 0x1800>, 2000 <0x25800 0x100>, 2001 <0x25c00 0x100>; 2002 reg-names = "iram", "control", "debug"; 2003 firmware-name = "j7-txpru0_1-fw"; 2004 }; 2005 2006 icssg0_mdio: mdio@32400 { 2007 compatible = "ti,davinci_mdio"; 2008 reg = <0x32400 0x100>; 2009 clocks = <&k3_clks 119 1>; 2010 clock-names = "fck"; 2011 #address-cells = <1>; 2012 #size-cells = <0>; 2013 bus_freq = <1000000>; 2014 }; 2015 }; 2016 2017 icssg1: icssg@b100000 { 2018 compatible = "ti,j721e-icssg"; 2019 reg = <0x00 0xb100000 0x00 0x80000>; 2020 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 2021 #address-cells = <1>; 2022 #size-cells = <1>; 2023 ranges = <0x0 0x00 0x0b100000 0x100000>; 2024 2025 icssg1_mem: memories@b100000 { 2026 reg = <0x0 0x2000>, 2027 <0x2000 0x2000>, 2028 <0x10000 0x10000>; 2029 reg-names = "dram0", "dram1", 2030 "shrdram2"; 2031 }; 2032 2033 icssg1_cfg: cfg@26000 { 2034 compatible = "ti,pruss-cfg", "syscon"; 2035 reg = <0x26000 0x200>; 2036 #address-cells = <1>; 2037 #size-cells = <1>; 2038 ranges = <0x0 0x26000 0x2000>; 2039 2040 clocks { 2041 #address-cells = <1>; 2042 #size-cells = <0>; 2043 2044 icssg1_coreclk_mux: coreclk-mux@3c { 2045 reg = <0x3c>; 2046 #clock-cells = <0>; 2047 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ 2048 <&k3_clks 120 4>; /* icssg1_iclk */ 2049 assigned-clocks = <&icssg1_coreclk_mux>; 2050 assigned-clock-parents = <&k3_clks 120 4>; 2051 }; 2052 2053 icssg1_iepclk_mux: iepclk-mux@30 { 2054 reg = <0x30>; 2055 #clock-cells = <0>; 2056 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ 2057 <&icssg1_coreclk_mux>; /* core_clk */ 2058 assigned-clocks = <&icssg1_iepclk_mux>; 2059 assigned-clock-parents = <&icssg1_coreclk_mux>; 2060 }; 2061 }; 2062 }; 2063 2064 icssg1_mii_rt: mii-rt@32000 { 2065 compatible = "ti,pruss-mii", "syscon"; 2066 reg = <0x32000 0x100>; 2067 }; 2068 2069 icssg1_mii_g_rt: mii-g-rt@33000 { 2070 compatible = "ti,pruss-mii-g", "syscon"; 2071 reg = <0x33000 0x1000>; 2072 }; 2073 2074 icssg1_intc: interrupt-controller@20000 { 2075 compatible = "ti,icssg-intc"; 2076 reg = <0x20000 0x2000>; 2077 interrupt-controller; 2078 #interrupt-cells = <3>; 2079 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2080 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2087 interrupt-names = "host_intr0", "host_intr1", 2088 "host_intr2", "host_intr3", 2089 "host_intr4", "host_intr5", 2090 "host_intr6", "host_intr7"; 2091 }; 2092 2093 pru1_0: pru@34000 { 2094 compatible = "ti,j721e-pru"; 2095 reg = <0x34000 0x4000>, 2096 <0x22000 0x100>, 2097 <0x22400 0x100>; 2098 reg-names = "iram", "control", "debug"; 2099 firmware-name = "j7-pru1_0-fw"; 2100 }; 2101 2102 rtu1_0: rtu@4000 { 2103 compatible = "ti,j721e-rtu"; 2104 reg = <0x4000 0x2000>, 2105 <0x23000 0x100>, 2106 <0x23400 0x100>; 2107 reg-names = "iram", "control", "debug"; 2108 firmware-name = "j7-rtu1_0-fw"; 2109 }; 2110 2111 tx_pru1_0: txpru@a000 { 2112 compatible = "ti,j721e-tx-pru"; 2113 reg = <0xa000 0x1800>, 2114 <0x25000 0x100>, 2115 <0x25400 0x100>; 2116 reg-names = "iram", "control", "debug"; 2117 firmware-name = "j7-txpru1_0-fw"; 2118 }; 2119 2120 pru1_1: pru@38000 { 2121 compatible = "ti,j721e-pru"; 2122 reg = <0x38000 0x4000>, 2123 <0x24000 0x100>, 2124 <0x24400 0x100>; 2125 reg-names = "iram", "control", "debug"; 2126 firmware-name = "j7-pru1_1-fw"; 2127 }; 2128 2129 rtu1_1: rtu@6000 { 2130 compatible = "ti,j721e-rtu"; 2131 reg = <0x6000 0x2000>, 2132 <0x23800 0x100>, 2133 <0x23c00 0x100>; 2134 reg-names = "iram", "control", "debug"; 2135 firmware-name = "j7-rtu1_1-fw"; 2136 }; 2137 2138 tx_pru1_1: txpru@c000 { 2139 compatible = "ti,j721e-tx-pru"; 2140 reg = <0xc000 0x1800>, 2141 <0x25800 0x100>, 2142 <0x25c00 0x100>; 2143 reg-names = "iram", "control", "debug"; 2144 firmware-name = "j7-txpru1_1-fw"; 2145 }; 2146 2147 icssg1_mdio: mdio@32400 { 2148 compatible = "ti,davinci_mdio"; 2149 reg = <0x32400 0x100>; 2150 clocks = <&k3_clks 120 4>; 2151 clock-names = "fck"; 2152 #address-cells = <1>; 2153 #size-cells = <0>; 2154 bus_freq = <1000000>; 2155 }; 2156 }; 2157 2158 main_mcan0: can@2701000 { 2159 compatible = "bosch,m_can"; 2160 reg = <0x00 0x02701000 0x00 0x200>, 2161 <0x00 0x02708000 0x00 0x8000>; 2162 reg-names = "m_can", "message_ram"; 2163 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 2164 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; 2165 clock-names = "hclk", "cclk"; 2166 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2168 interrupt-names = "int0", "int1"; 2169 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2170 status = "disabled"; 2171 }; 2172 2173 main_mcan1: can@2711000 { 2174 compatible = "bosch,m_can"; 2175 reg = <0x00 0x02711000 0x00 0x200>, 2176 <0x00 0x02718000 0x00 0x8000>; 2177 reg-names = "m_can", "message_ram"; 2178 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 2179 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; 2180 clock-names = "hclk", "cclk"; 2181 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 2183 interrupt-names = "int0", "int1"; 2184 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2185 status = "disabled"; 2186 }; 2187 2188 main_mcan2: can@2721000 { 2189 compatible = "bosch,m_can"; 2190 reg = <0x00 0x02721000 0x00 0x200>, 2191 <0x00 0x02728000 0x00 0x8000>; 2192 reg-names = "m_can", "message_ram"; 2193 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 2194 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; 2195 clock-names = "hclk", "cclk"; 2196 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2197 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2198 interrupt-names = "int0", "int1"; 2199 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2200 status = "disabled"; 2201 }; 2202 2203 main_mcan3: can@2731000 { 2204 compatible = "bosch,m_can"; 2205 reg = <0x00 0x02731000 0x00 0x200>, 2206 <0x00 0x02738000 0x00 0x8000>; 2207 reg-names = "m_can", "message_ram"; 2208 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 2209 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; 2210 clock-names = "hclk", "cclk"; 2211 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2212 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 2213 interrupt-names = "int0", "int1"; 2214 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2215 status = "disabled"; 2216 }; 2217 2218 main_mcan4: can@2741000 { 2219 compatible = "bosch,m_can"; 2220 reg = <0x00 0x02741000 0x00 0x200>, 2221 <0x00 0x02748000 0x00 0x8000>; 2222 reg-names = "m_can", "message_ram"; 2223 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 2224 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; 2225 clock-names = "hclk", "cclk"; 2226 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2228 interrupt-names = "int0", "int1"; 2229 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2230 status = "disabled"; 2231 }; 2232 2233 main_mcan5: can@2751000 { 2234 compatible = "bosch,m_can"; 2235 reg = <0x00 0x02751000 0x00 0x200>, 2236 <0x00 0x02758000 0x00 0x8000>; 2237 reg-names = "m_can", "message_ram"; 2238 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 2239 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; 2240 clock-names = "hclk", "cclk"; 2241 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2242 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2243 interrupt-names = "int0", "int1"; 2244 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2245 status = "disabled"; 2246 }; 2247 2248 main_mcan6: can@2761000 { 2249 compatible = "bosch,m_can"; 2250 reg = <0x00 0x02761000 0x00 0x200>, 2251 <0x00 0x02768000 0x00 0x8000>; 2252 reg-names = "m_can", "message_ram"; 2253 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 2254 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; 2255 clock-names = "hclk", "cclk"; 2256 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2257 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 2258 interrupt-names = "int0", "int1"; 2259 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2260 status = "disabled"; 2261 }; 2262 2263 main_mcan7: can@2771000 { 2264 compatible = "bosch,m_can"; 2265 reg = <0x00 0x02771000 0x00 0x200>, 2266 <0x00 0x02778000 0x00 0x8000>; 2267 reg-names = "m_can", "message_ram"; 2268 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 2269 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; 2270 clock-names = "hclk", "cclk"; 2271 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2272 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2273 interrupt-names = "int0", "int1"; 2274 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2275 status = "disabled"; 2276 }; 2277 2278 main_mcan8: can@2781000 { 2279 compatible = "bosch,m_can"; 2280 reg = <0x00 0x02781000 0x00 0x200>, 2281 <0x00 0x02788000 0x00 0x8000>; 2282 reg-names = "m_can", "message_ram"; 2283 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 2284 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; 2285 clock-names = "hclk", "cclk"; 2286 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2287 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 2288 interrupt-names = "int0", "int1"; 2289 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2290 status = "disabled"; 2291 }; 2292 2293 main_mcan9: can@2791000 { 2294 compatible = "bosch,m_can"; 2295 reg = <0x00 0x02791000 0x00 0x200>, 2296 <0x00 0x02798000 0x00 0x8000>; 2297 reg-names = "m_can", "message_ram"; 2298 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 2299 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; 2300 clock-names = "hclk", "cclk"; 2301 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 2302 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2303 interrupt-names = "int0", "int1"; 2304 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2305 status = "disabled"; 2306 }; 2307 2308 main_mcan10: can@27a1000 { 2309 compatible = "bosch,m_can"; 2310 reg = <0x00 0x027a1000 0x00 0x200>, 2311 <0x00 0x027a8000 0x00 0x8000>; 2312 reg-names = "m_can", "message_ram"; 2313 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 2314 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; 2315 clock-names = "hclk", "cclk"; 2316 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 2317 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2318 interrupt-names = "int0", "int1"; 2319 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2320 status = "disabled"; 2321 }; 2322 2323 main_mcan11: can@27b1000 { 2324 compatible = "bosch,m_can"; 2325 reg = <0x00 0x027b1000 0x00 0x200>, 2326 <0x00 0x027b8000 0x00 0x8000>; 2327 reg-names = "m_can", "message_ram"; 2328 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; 2329 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; 2330 clock-names = "hclk", "cclk"; 2331 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 2332 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2333 interrupt-names = "int0", "int1"; 2334 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2335 status = "disabled"; 2336 }; 2337 2338 main_mcan12: can@27c1000 { 2339 compatible = "bosch,m_can"; 2340 reg = <0x00 0x027c1000 0x00 0x200>, 2341 <0x00 0x027c8000 0x00 0x8000>; 2342 reg-names = "m_can", "message_ram"; 2343 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; 2344 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; 2345 clock-names = "hclk", "cclk"; 2346 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2347 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 2348 interrupt-names = "int0", "int1"; 2349 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2350 status = "disabled"; 2351 }; 2352 2353 main_mcan13: can@27d1000 { 2354 compatible = "bosch,m_can"; 2355 reg = <0x00 0x027d1000 0x00 0x200>, 2356 <0x00 0x027d8000 0x00 0x8000>; 2357 reg-names = "m_can", "message_ram"; 2358 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; 2359 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; 2360 clock-names = "hclk", "cclk"; 2361 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2362 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 2363 interrupt-names = "int0", "int1"; 2364 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2365 status = "disabled"; 2366 }; 2367 2368 main_spi0: spi@2100000 { 2369 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2370 reg = <0x00 0x02100000 0x00 0x400>; 2371 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2372 #address-cells = <1>; 2373 #size-cells = <0>; 2374 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 2375 clocks = <&k3_clks 266 1>; 2376 status = "disabled"; 2377 }; 2378 2379 main_spi1: spi@2110000 { 2380 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2381 reg = <0x00 0x02110000 0x00 0x400>; 2382 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 2383 #address-cells = <1>; 2384 #size-cells = <0>; 2385 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 2386 clocks = <&k3_clks 267 1>; 2387 status = "disabled"; 2388 }; 2389 2390 main_spi2: spi@2120000 { 2391 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2392 reg = <0x00 0x02120000 0x00 0x400>; 2393 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2394 #address-cells = <1>; 2395 #size-cells = <0>; 2396 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 2397 clocks = <&k3_clks 268 1>; 2398 status = "disabled"; 2399 }; 2400 2401 main_spi3: spi@2130000 { 2402 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2403 reg = <0x00 0x02130000 0x00 0x400>; 2404 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2405 #address-cells = <1>; 2406 #size-cells = <0>; 2407 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 2408 clocks = <&k3_clks 269 1>; 2409 status = "disabled"; 2410 }; 2411 2412 main_spi4: spi@2140000 { 2413 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2414 reg = <0x00 0x02140000 0x00 0x400>; 2415 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2416 #address-cells = <1>; 2417 #size-cells = <0>; 2418 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 2419 clocks = <&k3_clks 270 1>; 2420 status = "disabled"; 2421 }; 2422 2423 main_spi5: spi@2150000 { 2424 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2425 reg = <0x00 0x02150000 0x00 0x400>; 2426 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2427 #address-cells = <1>; 2428 #size-cells = <0>; 2429 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 2430 clocks = <&k3_clks 271 1>; 2431 status = "disabled"; 2432 }; 2433 2434 main_spi6: spi@2160000 { 2435 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2436 reg = <0x00 0x02160000 0x00 0x400>; 2437 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2438 #address-cells = <1>; 2439 #size-cells = <0>; 2440 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 2441 clocks = <&k3_clks 272 1>; 2442 status = "disabled"; 2443 }; 2444 2445 main_spi7: spi@2170000 { 2446 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2447 reg = <0x00 0x02170000 0x00 0x400>; 2448 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2449 #address-cells = <1>; 2450 #size-cells = <0>; 2451 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 2452 clocks = <&k3_clks 273 1>; 2453 status = "disabled"; 2454 }; 2455}; 2456