1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family
4 *
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/k3.h>
12
13/ {
14	model = "Texas Instruments K3 AM654 SoC";
15	compatible = "ti,am654";
16	interrupt-parent = <&gic500>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		serial0 = &wkup_uart0;
22		serial1 = &mcu_uart0;
23		serial2 = &main_uart0;
24		serial3 = &main_uart1;
25		serial4 = &main_uart2;
26	};
27
28	chosen { };
29
30	firmware {
31		optee {
32			compatible = "linaro,optee-tz";
33			method = "smc";
34		};
35
36		psci: psci {
37			compatible = "arm,psci-1.0";
38			method = "smc";
39		};
40	};
41
42	a53_timer0: timer-cl0-cpu0 {
43		compatible = "arm,armv8-timer";
44		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
45			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
46			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
47			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
48	};
49
50	pmu: pmu {
51		compatible = "arm,armv8-pmuv3";
52		/* Recommendation from GIC500 TRM Table A.3 */
53		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
54	};
55
56	cbass_main: interconnect@100000 {
57		compatible = "simple-bus";
58		#address-cells = <2>;
59		#size-cells = <2>;
60		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
61			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
62			 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
63			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
64			 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
65			 /* MCUSS Range */
66			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
67			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
68			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
69			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
70			 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
71			 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
72
73		cbass_mcu: interconnect@28380000 {
74			compatible = "simple-bus";
75			#address-cells = <2>;
76			#size-cells = <2>;
77			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
78				 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
79				 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
80				 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
81				 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
82				 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
83
84			cbass_wakeup: interconnect@42040000 {
85				compatible = "simple-bus";
86				#address-cells = <1>;
87				#size-cells = <1>;
88				/* WKUP  Basic peripherals */
89				ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
90			};
91		};
92	};
93};
94
95/* Now include the peripherals for each bus segments */
96#include "k3-am65-main.dtsi"
97#include "k3-am65-mcu.dtsi"
98#include "k3-am65-wakeup.dtsi"
99