1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family
4 *
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/soc/ti,sci_pm_domain.h>
12
13#include "k3-pinctrl.h"
14
15/ {
16	model = "Texas Instruments K3 AM654 SoC";
17	compatible = "ti,am654";
18	interrupt-parent = <&gic500>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	chosen { };
23
24	firmware {
25		optee {
26			compatible = "linaro,optee-tz";
27			method = "smc";
28		};
29
30		psci: psci {
31			compatible = "arm,psci-1.0";
32			method = "smc";
33		};
34	};
35
36	a53_timer0: timer-cl0-cpu0 {
37		compatible = "arm,armv8-timer";
38		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
39			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
40			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
41			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
42	};
43
44	pmu: pmu {
45		compatible = "arm,cortex-a53-pmu";
46		/* Recommendation from GIC500 TRM Table A.3 */
47		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
48	};
49
50	cbass_main: bus@100000 {
51		compatible = "simple-bus";
52		#address-cells = <2>;
53		#size-cells = <2>;
54		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56			 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58			 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
59			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
60			 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
61			 /* MCUSS Range */
62			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
64			 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
65			 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
66			 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
67			 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
68			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
69			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
70			 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
71			 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
72			 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
73			 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
74			 <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
75			 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
76			 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
77
78		cbass_mcu: bus@28380000 {
79			compatible = "simple-bus";
80			#address-cells = <2>;
81			#size-cells = <2>;
82			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
83				 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
84				 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
85				 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
86				 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
87				 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
88				 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
89				 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
90				 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
91				 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
92				 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /*  FSS OSPI0 data region 1 */
93				 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
94				 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
95
96			cbass_wakeup: bus@42040000 {
97				compatible = "simple-bus";
98				#address-cells = <1>;
99				#size-cells = <1>;
100				/* WKUP  Basic peripherals */
101				ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
102			};
103		};
104	};
105};
106
107/* Now include the peripherals for each bus segments */
108#include "k3-am65-main.dtsi"
109#include "k3-am65-mcu.dtsi"
110#include "k3-am65-wakeup.dtsi"
111