1*8abae938SDave Gerlach// SPDX-License-Identifier: GPL-2.0 2*8abae938SDave Gerlach/* 3*8abae938SDave Gerlach * Device Tree Source for AM64 SoC Family MCU Domain peripherals 4*8abae938SDave Gerlach * 5*8abae938SDave Gerlach * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6*8abae938SDave Gerlach */ 7*8abae938SDave Gerlach 8*8abae938SDave Gerlach&cbass_mcu { 9*8abae938SDave Gerlach mcu_uart0: serial@4a00000 { 10*8abae938SDave Gerlach compatible = "ti,am64-uart", "ti,am654-uart"; 11*8abae938SDave Gerlach reg = <0x00 0x04a00000 0x00 0x100>; 12*8abae938SDave Gerlach reg-shift = <2>; 13*8abae938SDave Gerlach reg-io-width = <4>; 14*8abae938SDave Gerlach interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 15*8abae938SDave Gerlach clock-frequency = <48000000>; 16*8abae938SDave Gerlach current-speed = <115200>; 17*8abae938SDave Gerlach power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 18*8abae938SDave Gerlach clocks = <&k3_clks 149 0>; 19*8abae938SDave Gerlach clock-names = "fclk"; 20*8abae938SDave Gerlach }; 21*8abae938SDave Gerlach 22*8abae938SDave Gerlach mcu_uart1: serial@4a10000 { 23*8abae938SDave Gerlach compatible = "ti,am64-uart", "ti,am654-uart"; 24*8abae938SDave Gerlach reg = <0x00 0x04a10000 0x00 0x100>; 25*8abae938SDave Gerlach reg-shift = <2>; 26*8abae938SDave Gerlach reg-io-width = <4>; 27*8abae938SDave Gerlach interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 28*8abae938SDave Gerlach clock-frequency = <48000000>; 29*8abae938SDave Gerlach current-speed = <115200>; 30*8abae938SDave Gerlach power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 31*8abae938SDave Gerlach clocks = <&k3_clks 160 0>; 32*8abae938SDave Gerlach clock-names = "fclk"; 33*8abae938SDave Gerlach }; 34*8abae938SDave Gerlach 35*8abae938SDave Gerlach mcu_i2c0: i2c@4900000 { 36*8abae938SDave Gerlach compatible = "ti,am64-i2c", "ti,omap4-i2c"; 37*8abae938SDave Gerlach reg = <0x00 0x04900000 0x00 0x100>; 38*8abae938SDave Gerlach interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 39*8abae938SDave Gerlach #address-cells = <1>; 40*8abae938SDave Gerlach #size-cells = <0>; 41*8abae938SDave Gerlach power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 42*8abae938SDave Gerlach clocks = <&k3_clks 106 2>; 43*8abae938SDave Gerlach clock-names = "fck"; 44*8abae938SDave Gerlach }; 45*8abae938SDave Gerlach 46*8abae938SDave Gerlach mcu_i2c1: i2c@4910000 { 47*8abae938SDave Gerlach compatible = "ti,am64-i2c", "ti,omap4-i2c"; 48*8abae938SDave Gerlach reg = <0x00 0x04910000 0x00 0x100>; 49*8abae938SDave Gerlach interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 50*8abae938SDave Gerlach #address-cells = <1>; 51*8abae938SDave Gerlach #size-cells = <0>; 52*8abae938SDave Gerlach power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 53*8abae938SDave Gerlach clocks = <&k3_clks 107 2>; 54*8abae938SDave Gerlach clock-names = "fck"; 55*8abae938SDave Gerlach }; 56*8abae938SDave Gerlach 57*8abae938SDave Gerlach mcu_spi0: spi@4b00000 { 58*8abae938SDave Gerlach compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 59*8abae938SDave Gerlach reg = <0x00 0x04b00000 0x00 0x400>; 60*8abae938SDave Gerlach interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 61*8abae938SDave Gerlach #address-cells = <1>; 62*8abae938SDave Gerlach #size-cells = <0>; 63*8abae938SDave Gerlach power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 64*8abae938SDave Gerlach clocks = <&k3_clks 147 0>; 65*8abae938SDave Gerlach }; 66*8abae938SDave Gerlach 67*8abae938SDave Gerlach mcu_spi1: spi@4b10000 { 68*8abae938SDave Gerlach compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 69*8abae938SDave Gerlach reg = <0x00 0x04b10000 0x00 0x400>; 70*8abae938SDave Gerlach interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 71*8abae938SDave Gerlach #address-cells = <1>; 72*8abae938SDave Gerlach #size-cells = <0>; 73*8abae938SDave Gerlach power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 74*8abae938SDave Gerlach clocks = <&k3_clks 148 0>; 75*8abae938SDave Gerlach }; 76*8abae938SDave Gerlach}; 77