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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32 |
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| #
f049b541 |
| 30-May-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am64: Add ESM support
Add Error Signaling Module (ESM) instances in MCU and MAIN domains.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530185335
arm64: dts: ti: k3-am64: Add ESM support
Add Error Signaling Module (ESM) instances in MCU and MAIN domains.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530185335.79942-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
show more ...
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| #
27f98f3e |
| 01-Jun-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Only set UART baud for used ports
As the binding for "current-speed" states, this should only be used
when the baud rate of an attached device cannot be detected. This is
th
arm64: dts: ti: k3-am64: Only set UART baud for used ports
As the binding for "current-speed" states, this should only be used
when the baud rate of an attached device cannot be detected. This is
the case for our attached on-board USB-to-UART converter used for
early kernel console. For all other unconnected/disabled ports this
can be configured in userspace later, DT is not the place for device
configuration, especially when there are already standard ways to
set serial baud in userspace.
Remove setting baud for all disabled serial ports and move setting
it for the couple enabled ports down into the board files.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230601184933.358731-1-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
show more ...
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|
Revision tags: v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25 |
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| #
9972b457 |
| 14-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am64: Add general purpose timers
There are 11 general purpose timers on am64 that can be used for things
like PWM using pwm-omap-dmtimer driver. There are also additional four
tim
arm64: dts: ti: k3-am64: Add general purpose timers
There are 11 general purpose timers on am64 that can be used for things
like PWM using pwm-omap-dmtimer driver. There are also additional four
timers in the MCU domain that do not have interrupts routable for Linux.
We configure the timers with the 25 MHz input clock by default as the
32.768 kHz clock may not be wired on the device. We leave the MCU domain
timers clock mux unconfigured, and mark the MCU domain timers reserved.
The MCU domain timers are likely reserved by the software for the ESM
module.
Compared to am65, the timers on am64 do not have a dedicated IO mux for
the timers. On am62, the timers have different interrupts, clocks and
power domains compared to am65, and the MCU timers are at a different
IO address. Compared to AM62, the AM64 times have different clocks and
count in main domain are different as well.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
show more ...
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Revision tags: v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3 |
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| #
79d4aa62 |
| 17-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable SPI nodes at the board level
SPI nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
in
arm64: dts: ti: k3-am64: Enable SPI nodes at the board level
SPI nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the SPI nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-4-afd@ti.com
show more ...
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| #
b80f75d8 |
| 17-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable I2C nodes at the board level
I2C nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
in
arm64: dts: ti: k3-am64: Enable I2C nodes at the board level
I2C nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the I2C nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-3-afd@ti.com
show more ...
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| #
dacf4705 |
| 17-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable UART nodes at the board level
UART nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
arm64: dts: ti: k3-am64: Enable UART nodes at the board level
UART nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the UART nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-2-afd@ti.com
show more ...
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Revision tags: v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35 |
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| #
439677d4 |
| 19-Apr-2022 |
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> |
arm64: dts: ti: k3-am64-mcu: remove incorrect UART base clock rates
We found that (at least some versions of) the sci-fw set the base clock
rate for UARTs in the MCU domain to 96 MHz instead of the
arm64: dts: ti: k3-am64-mcu: remove incorrect UART base clock rates
We found that (at least some versions of) the sci-fw set the base clock
rate for UARTs in the MCU domain to 96 MHz instead of the expected 48 MHz,
leading to incorrect baud rates when used from Linux.
As the 8250_omap driver will query the actual clock rate from the clk
driver when clock-frequency is unset, removing the incorrect property is
sufficient to fix the baud rate.
Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC")
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20220419075157.189347-1-matthias.schiffer@ew.tq-group.com
show more ...
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Revision tags: v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61 |
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| #
500e6dfb |
| 18-Aug-2021 |
Christian Gmeiner <christian.gmeiner@gmail.com> |
arm64: dts: ti: k3-am64-mcu: Add pinctrl
Add the definition of the pinctrl for the MCU domain.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Dave Gerlach <d-gerlach@ti
arm64: dts: ti: k3-am64-mcu: Add pinctrl
Add the definition of the pinctrl for the MCU domain.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210818111747.88569-1-christian.gmeiner@gmail.com
show more ...
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| #
d5e9dd4f |
| 19-Apr-2022 |
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> |
arm64: dts: ti: k3-am64-mcu: remove incorrect UART base clock rates
[ Upstream commit 439677d416b17dd39964d5f7d64b742a2e51da5b ]
We found that (at least some versions of) the sci-fw set the base cl
arm64: dts: ti: k3-am64-mcu: remove incorrect UART base clock rates
[ Upstream commit 439677d416b17dd39964d5f7d64b742a2e51da5b ]
We found that (at least some versions of) the sci-fw set the base clock
rate for UARTs in the MCU domain to 96 MHz instead of the expected 48 MHz,
leading to incorrect baud rates when used from Linux.
As the 8250_omap driver will query the actual clock rate from the clk
driver when clock-frequency is unset, removing the incorrect property is
sufficient to fix the baud rate.
Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC")
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20220419075157.189347-1-matthias.schiffer@ew.tq-group.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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| #
d5e9dd4f |
| 19-Apr-2022 |
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> |
arm64: dts: ti: k3-am64-mcu: remove incorrect UART base clock rates
[ Upstream commit 439677d416b17dd39964d5f7d64b742a2e51da5b ]
We found that (at least some versions of) the sci-fw set the base cl
arm64: dts: ti: k3-am64-mcu: remove incorrect UART base clock rates
[ Upstream commit 439677d416b17dd39964d5f7d64b742a2e51da5b ]
We found that (at least some versions of) the sci-fw set the base clock
rate for UARTs in the MCU domain to 96 MHz instead of the expected 48 MHz,
leading to incorrect baud rates when used from Linux.
As the 8250_omap driver will query the actual clock rate from the clk
driver when clock-frequency is unset, removing the incorrect property is
sufficient to fix the baud rate.
Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC")
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20220419075157.189347-1-matthias.schiffer@ew.tq-group.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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Revision tags: v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43 |
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| #
d65f069e |
| 07-Jun-2021 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes
8250_omap compatible UART IPs on all SoCs have registers aligned at 4
byte address boundary and constant byte addressability. Thus there i
arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes
8250_omap compatible UART IPs on all SoCs have registers aligned at 4
byte address boundary and constant byte addressability. Thus there is no
need for reg-io-width or reg-shift DT properties. These properties are
not used by 8250_omap driver nor documented as part of binding document.
Therefore drop them.
This is in preparation to move omap-serial.txt to YAML format.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210607134558.23704-1-vigneshr@ti.com
show more ...
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|
Revision tags: v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12 |
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| #
ec2fb989 |
| 23-Apr-2021 |
Aswath Govindraju <a-govindraju@ti.com> |
arm64: dts: ti: k3-am64-mcu: Fix the compatible string in GPIO DT node
Fix the compatible string in mcu domain GPIO device tree node.
Fixes: 01a91e01b8fd ("arm64: dts: ti: k3-am64: Add GPIO DT node
arm64: dts: ti: k3-am64-mcu: Fix the compatible string in GPIO DT node
Fix the compatible string in mcu domain GPIO device tree node.
Fixes: 01a91e01b8fd ("arm64: dts: ti: k3-am64: Add GPIO DT nodes")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210423060133.16473-1-a-govindraju@ti.com
show more ...
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| #
cab12bad |
| 11-May-2021 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3*: Introduce reg definition for interrupt routers
Interrupt routers are memory mapped peripherals, that are organized
in our dts bus hierarchy to closely represents the actual hard
arm64: dts: ti: k3*: Introduce reg definition for interrupt routers
Interrupt routers are memory mapped peripherals, that are organized
in our dts bus hierarchy to closely represents the actual hardware
behavior.
However, without explicitly calling out the reg property, using
2021.03+ dt-schema package, this exposes the following problem with
dtbs_check:
/arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml: bus@100000:
interrupt-controller0: {'type': 'object'} is not allowed for
{'compatible': ['ti,sci-intr'], .....
Even though we don't use interrupt router directly via memory mapped
registers and have to use it via the system controller, the hardware
block is memory mapped, so describe the base address in device tree.
This is a valid, comprehensive description of hardware and permitted
by the existing ti,sci-intr schema.
Reviewed-by: Tero Kristo <kristo@kernel.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210511194821.13919-1-nm@ti.com
show more ...
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|
Revision tags: v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25 |
|
| #
01a91e01 |
| 19-Mar-2021 |
Aswath Govindraju <a-govindraju@ti.com> |
arm64: dts: ti: k3-am64: Add GPIO DT nodes
Add device tree nodes for GPIO modules and interrupt controller in main
and mcu domains.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off
arm64: dts: ti: k3-am64: Add GPIO DT nodes
Add device tree nodes for GPIO modules and interrupt controller in main
and mcu domains.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210319051950.17549-2-a-govindraju@ti.com
show more ...
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|
Revision tags: v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20 |
|
| #
8abae938 |
| 26-Feb-2021 |
Dave Gerlach <d-gerlach@ti.com> |
arm64: dts: ti: Add support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC,
arm64: dts: ti: Add support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable ramdisk or MMC
boot. Introduce the sdhci, i2c, spi, and uart MAIN domain periperhals
under cbass_main and the i2c, spi, and uart MCU domain periperhals
under cbass_mcu.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Link: https://lore.kernel.org/r/20210226144257.5470-4-d-gerlach@ti.com
show more ...
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