1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM642 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 oc_sram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x00 0x70000000 0x00 0x200000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x00 0x70000000 0x200000>; 26 27 tfa-sram@1c0000 { 28 reg = <0x1c0000 0x20000>; 29 }; 30 31 dmsc-sram@1e0000 { 32 reg = <0x1e0000 0x1c000>; 33 }; 34 35 sproxy-sram@1fc000 { 36 reg = <0x1fc000 0x4000>; 37 }; 38 }; 39 40 main_conf: syscon@43000000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0x0 0x43000000 0x0 0x20000>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x0 0x0 0x43000000 0x20000>; 46 47 serdes_ln_ctrl: mux-controller { 48 compatible = "mmio-mux"; 49 #mux-control-cells = <1>; 50 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ 51 }; 52 }; 53 54 gic500: interrupt-controller@1800000 { 55 compatible = "arm,gic-v3"; 56 #address-cells = <2>; 57 #size-cells = <2>; 58 ranges; 59 #interrupt-cells = <3>; 60 interrupt-controller; 61 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 62 <0x00 0x01840000 0x00 0xC0000>, /* GICR */ 63 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 64 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 65 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 66 /* 67 * vcpumntirq: 68 * virtual CPU interface maintenance interrupt 69 */ 70 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 71 72 gic_its: msi-controller@1820000 { 73 compatible = "arm,gic-v3-its"; 74 reg = <0x00 0x01820000 0x00 0x10000>; 75 socionext,synquacer-pre-its = <0x1000000 0x400000>; 76 msi-controller; 77 #msi-cells = <1>; 78 }; 79 }; 80 81 dmss: bus@48000000 { 82 compatible = "simple-mfd"; 83 #address-cells = <2>; 84 #size-cells = <2>; 85 dma-ranges; 86 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 87 88 ti,sci-dev-id = <25>; 89 90 secure_proxy_main: mailbox@4d000000 { 91 compatible = "ti,am654-secure-proxy"; 92 #mbox-cells = <1>; 93 reg-names = "target_data", "rt", "scfg"; 94 reg = <0x00 0x4d000000 0x00 0x80000>, 95 <0x00 0x4a600000 0x00 0x80000>, 96 <0x00 0x4a400000 0x00 0x80000>; 97 interrupt-names = "rx_012"; 98 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 99 }; 100 101 inta_main_dmss: interrupt-controller@48000000 { 102 compatible = "ti,sci-inta"; 103 reg = <0x00 0x48000000 0x00 0x100000>; 104 #interrupt-cells = <0>; 105 interrupt-controller; 106 interrupt-parent = <&gic500>; 107 msi-controller; 108 ti,sci = <&dmsc>; 109 ti,sci-dev-id = <28>; 110 ti,interrupt-ranges = <4 68 36>; 111 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 112 }; 113 114 main_bcdma: dma-controller@485c0100 { 115 compatible = "ti,am64-dmss-bcdma"; 116 reg = <0x00 0x485c0100 0x00 0x100>, 117 <0x00 0x4c000000 0x00 0x20000>, 118 <0x00 0x4a820000 0x00 0x20000>, 119 <0x00 0x4aa40000 0x00 0x20000>, 120 <0x00 0x4bc00000 0x00 0x100000>; 121 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 122 msi-parent = <&inta_main_dmss>; 123 #dma-cells = <3>; 124 125 ti,sci = <&dmsc>; 126 ti,sci-dev-id = <26>; 127 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 128 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 129 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 130 }; 131 132 main_pktdma: dma-controller@485c0000 { 133 compatible = "ti,am64-dmss-pktdma"; 134 reg = <0x00 0x485c0000 0x00 0x100>, 135 <0x00 0x4a800000 0x00 0x20000>, 136 <0x00 0x4aa00000 0x00 0x40000>, 137 <0x00 0x4b800000 0x00 0x400000>; 138 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 139 msi-parent = <&inta_main_dmss>; 140 #dma-cells = <2>; 141 142 ti,sci = <&dmsc>; 143 ti,sci-dev-id = <30>; 144 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 145 <0x24>, /* CPSW_TX_CHAN */ 146 <0x25>, /* SAUL_TX_0_CHAN */ 147 <0x26>, /* SAUL_TX_1_CHAN */ 148 <0x27>, /* ICSSG_0_TX_CHAN */ 149 <0x28>; /* ICSSG_1_TX_CHAN */ 150 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 151 <0x11>, /* RING_CPSW_TX_CHAN */ 152 <0x12>, /* RING_SAUL_TX_0_CHAN */ 153 <0x13>, /* RING_SAUL_TX_1_CHAN */ 154 <0x14>, /* RING_ICSSG_0_TX_CHAN */ 155 <0x15>; /* RING_ICSSG_1_TX_CHAN */ 156 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 157 <0x2b>, /* CPSW_RX_CHAN */ 158 <0x2d>, /* SAUL_RX_0_CHAN */ 159 <0x2f>, /* SAUL_RX_1_CHAN */ 160 <0x31>, /* SAUL_RX_2_CHAN */ 161 <0x33>, /* SAUL_RX_3_CHAN */ 162 <0x35>, /* ICSSG_0_RX_CHAN */ 163 <0x37>; /* ICSSG_1_RX_CHAN */ 164 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 165 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 166 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 167 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ 168 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ 169 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ 170 }; 171 }; 172 173 dmsc: system-controller@44043000 { 174 compatible = "ti,k2g-sci"; 175 ti,host-id = <12>; 176 mbox-names = "rx", "tx"; 177 mboxes = <&secure_proxy_main 12>, 178 <&secure_proxy_main 13>; 179 reg-names = "debug_messages"; 180 reg = <0x00 0x44043000 0x00 0xfe0>; 181 182 k3_pds: power-controller { 183 compatible = "ti,sci-pm-domain"; 184 #power-domain-cells = <2>; 185 }; 186 187 k3_clks: clock-controller { 188 compatible = "ti,k2g-sci-clk"; 189 #clock-cells = <2>; 190 }; 191 192 k3_reset: reset-controller { 193 compatible = "ti,sci-reset"; 194 #reset-cells = <2>; 195 }; 196 }; 197 198 main_pmx0: pinctrl@f4000 { 199 compatible = "pinctrl-single"; 200 reg = <0x00 0xf4000 0x00 0x2d0>; 201 #pinctrl-cells = <1>; 202 pinctrl-single,register-width = <32>; 203 pinctrl-single,function-mask = <0xffffffff>; 204 }; 205 206 main_conf: syscon@43000000 { 207 compatible = "syscon", "simple-mfd"; 208 reg = <0x00 0x43000000 0x00 0x20000>; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 ranges = <0x00 0x00 0x43000000 0x20000>; 212 213 chipid@14 { 214 compatible = "ti,am654-chipid"; 215 reg = <0x00000014 0x4>; 216 }; 217 218 phy_gmii_sel: phy@4044 { 219 compatible = "ti,am654-phy-gmii-sel"; 220 reg = <0x4044 0x8>; 221 #phy-cells = <1>; 222 }; 223 224 epwm_tbclk: clock@4140 { 225 compatible = "ti,am64-epwm-tbclk", "syscon"; 226 reg = <0x4130 0x4>; 227 #clock-cells = <1>; 228 }; 229 }; 230 231 main_uart0: serial@2800000 { 232 compatible = "ti,am64-uart", "ti,am654-uart"; 233 reg = <0x00 0x02800000 0x00 0x100>; 234 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 235 clock-frequency = <48000000>; 236 current-speed = <115200>; 237 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 238 clocks = <&k3_clks 146 0>; 239 clock-names = "fclk"; 240 status = "disabled"; 241 }; 242 243 main_uart1: serial@2810000 { 244 compatible = "ti,am64-uart", "ti,am654-uart"; 245 reg = <0x00 0x02810000 0x00 0x100>; 246 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 247 clock-frequency = <48000000>; 248 current-speed = <115200>; 249 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 250 clocks = <&k3_clks 152 0>; 251 clock-names = "fclk"; 252 status = "disabled"; 253 }; 254 255 main_uart2: serial@2820000 { 256 compatible = "ti,am64-uart", "ti,am654-uart"; 257 reg = <0x00 0x02820000 0x00 0x100>; 258 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 259 clock-frequency = <48000000>; 260 current-speed = <115200>; 261 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 262 clocks = <&k3_clks 153 0>; 263 clock-names = "fclk"; 264 status = "disabled"; 265 }; 266 267 main_uart3: serial@2830000 { 268 compatible = "ti,am64-uart", "ti,am654-uart"; 269 reg = <0x00 0x02830000 0x00 0x100>; 270 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 271 clock-frequency = <48000000>; 272 current-speed = <115200>; 273 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 274 clocks = <&k3_clks 154 0>; 275 clock-names = "fclk"; 276 status = "disabled"; 277 }; 278 279 main_uart4: serial@2840000 { 280 compatible = "ti,am64-uart", "ti,am654-uart"; 281 reg = <0x00 0x02840000 0x00 0x100>; 282 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 283 clock-frequency = <48000000>; 284 current-speed = <115200>; 285 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 286 clocks = <&k3_clks 155 0>; 287 clock-names = "fclk"; 288 status = "disabled"; 289 }; 290 291 main_uart5: serial@2850000 { 292 compatible = "ti,am64-uart", "ti,am654-uart"; 293 reg = <0x00 0x02850000 0x00 0x100>; 294 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 295 clock-frequency = <48000000>; 296 current-speed = <115200>; 297 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 298 clocks = <&k3_clks 156 0>; 299 clock-names = "fclk"; 300 status = "disabled"; 301 }; 302 303 main_uart6: serial@2860000 { 304 compatible = "ti,am64-uart", "ti,am654-uart"; 305 reg = <0x00 0x02860000 0x00 0x100>; 306 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 307 clock-frequency = <48000000>; 308 current-speed = <115200>; 309 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 310 clocks = <&k3_clks 158 0>; 311 clock-names = "fclk"; 312 status = "disabled"; 313 }; 314 315 main_i2c0: i2c@20000000 { 316 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 317 reg = <0x00 0x20000000 0x00 0x100>; 318 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 322 clocks = <&k3_clks 102 2>; 323 clock-names = "fck"; 324 status = "disabled"; 325 }; 326 327 main_i2c1: i2c@20010000 { 328 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 329 reg = <0x00 0x20010000 0x00 0x100>; 330 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 334 clocks = <&k3_clks 103 2>; 335 clock-names = "fck"; 336 status = "disabled"; 337 }; 338 339 main_i2c2: i2c@20020000 { 340 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 341 reg = <0x00 0x20020000 0x00 0x100>; 342 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 346 clocks = <&k3_clks 104 2>; 347 clock-names = "fck"; 348 status = "disabled"; 349 }; 350 351 main_i2c3: i2c@20030000 { 352 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 353 reg = <0x00 0x20030000 0x00 0x100>; 354 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 358 clocks = <&k3_clks 105 2>; 359 clock-names = "fck"; 360 status = "disabled"; 361 }; 362 363 main_spi0: spi@20100000 { 364 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 365 reg = <0x00 0x20100000 0x00 0x400>; 366 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 370 clocks = <&k3_clks 141 0>; 371 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 372 dma-names = "tx0", "rx0"; 373 }; 374 375 main_spi1: spi@20110000 { 376 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 377 reg = <0x00 0x20110000 0x00 0x400>; 378 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 382 clocks = <&k3_clks 142 0>; 383 }; 384 385 main_spi2: spi@20120000 { 386 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 387 reg = <0x00 0x20120000 0x00 0x400>; 388 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 392 clocks = <&k3_clks 143 0>; 393 }; 394 395 main_spi3: spi@20130000 { 396 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 397 reg = <0x00 0x20130000 0x00 0x400>; 398 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 402 clocks = <&k3_clks 144 0>; 403 }; 404 405 main_spi4: spi@20140000 { 406 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 407 reg = <0x00 0x20140000 0x00 0x400>; 408 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 412 clocks = <&k3_clks 145 0>; 413 }; 414 415 main_gpio_intr: interrupt-controller@a00000 { 416 compatible = "ti,sci-intr"; 417 reg = <0x00 0x00a00000 0x00 0x800>; 418 ti,intr-trigger-type = <1>; 419 interrupt-controller; 420 interrupt-parent = <&gic500>; 421 #interrupt-cells = <1>; 422 ti,sci = <&dmsc>; 423 ti,sci-dev-id = <3>; 424 ti,interrupt-ranges = <0 32 16>; 425 }; 426 427 main_gpio0: gpio@600000 { 428 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 429 reg = <0x0 0x00600000 0x0 0x100>; 430 gpio-controller; 431 #gpio-cells = <2>; 432 interrupt-parent = <&main_gpio_intr>; 433 interrupts = <190>, <191>, <192>, 434 <193>, <194>, <195>; 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 ti,ngpio = <87>; 438 ti,davinci-gpio-unbanked = <0>; 439 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 440 clocks = <&k3_clks 77 0>; 441 clock-names = "gpio"; 442 }; 443 444 main_gpio1: gpio@601000 { 445 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 446 reg = <0x0 0x00601000 0x0 0x100>; 447 gpio-controller; 448 #gpio-cells = <2>; 449 interrupt-parent = <&main_gpio_intr>; 450 interrupts = <180>, <181>, <182>, 451 <183>, <184>, <185>; 452 interrupt-controller; 453 #interrupt-cells = <2>; 454 ti,ngpio = <88>; 455 ti,davinci-gpio-unbanked = <0>; 456 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 457 clocks = <&k3_clks 78 0>; 458 clock-names = "gpio"; 459 }; 460 461 sdhci0: mmc@fa10000 { 462 compatible = "ti,am64-sdhci-8bit"; 463 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 464 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 465 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 466 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; 467 clock-names = "clk_ahb", "clk_xin"; 468 mmc-ddr-1_8v; 469 mmc-hs200-1_8v; 470 ti,trm-icp = <0x2>; 471 ti,otap-del-sel-legacy = <0x0>; 472 ti,otap-del-sel-mmc-hs = <0x0>; 473 ti,otap-del-sel-ddr52 = <0x6>; 474 ti,otap-del-sel-hs200 = <0x7>; 475 }; 476 477 sdhci1: mmc@fa00000 { 478 compatible = "ti,am64-sdhci-4bit"; 479 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 480 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 481 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 482 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; 483 clock-names = "clk_ahb", "clk_xin"; 484 ti,trm-icp = <0x2>; 485 ti,otap-del-sel-legacy = <0x0>; 486 ti,otap-del-sel-sd-hs = <0xf>; 487 ti,otap-del-sel-sdr12 = <0xf>; 488 ti,otap-del-sel-sdr25 = <0xf>; 489 ti,otap-del-sel-sdr50 = <0xc>; 490 ti,otap-del-sel-sdr104 = <0x6>; 491 ti,otap-del-sel-ddr50 = <0x9>; 492 ti,clkbuf-sel = <0x7>; 493 }; 494 495 cpsw3g: ethernet@8000000 { 496 compatible = "ti,am642-cpsw-nuss"; 497 #address-cells = <2>; 498 #size-cells = <2>; 499 reg = <0x0 0x8000000 0x0 0x200000>; 500 reg-names = "cpsw_nuss"; 501 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 502 clocks = <&k3_clks 13 0>; 503 assigned-clocks = <&k3_clks 13 1>; 504 assigned-clock-parents = <&k3_clks 13 9>; 505 clock-names = "fck"; 506 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 507 508 dmas = <&main_pktdma 0xC500 15>, 509 <&main_pktdma 0xC501 15>, 510 <&main_pktdma 0xC502 15>, 511 <&main_pktdma 0xC503 15>, 512 <&main_pktdma 0xC504 15>, 513 <&main_pktdma 0xC505 15>, 514 <&main_pktdma 0xC506 15>, 515 <&main_pktdma 0xC507 15>, 516 <&main_pktdma 0x4500 15>; 517 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 518 "tx7", "rx"; 519 520 ethernet-ports { 521 #address-cells = <1>; 522 #size-cells = <0>; 523 524 cpsw_port1: port@1 { 525 reg = <1>; 526 ti,mac-only; 527 label = "port1"; 528 phys = <&phy_gmii_sel 1>; 529 mac-address = [00 00 00 00 00 00]; 530 ti,syscon-efuse = <&main_conf 0x200>; 531 }; 532 533 cpsw_port2: port@2 { 534 reg = <2>; 535 ti,mac-only; 536 label = "port2"; 537 phys = <&phy_gmii_sel 2>; 538 mac-address = [00 00 00 00 00 00]; 539 }; 540 }; 541 542 cpsw3g_mdio: mdio@f00 { 543 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 544 reg = <0x0 0xf00 0x0 0x100>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 clocks = <&k3_clks 13 0>; 548 clock-names = "fck"; 549 bus_freq = <1000000>; 550 }; 551 552 cpts@3d000 { 553 compatible = "ti,j721e-cpts"; 554 reg = <0x0 0x3d000 0x0 0x400>; 555 clocks = <&k3_clks 13 1>; 556 clock-names = "cpts"; 557 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 558 interrupt-names = "cpts"; 559 ti,cpts-ext-ts-inputs = <4>; 560 ti,cpts-periodic-outputs = <2>; 561 }; 562 }; 563 564 main_cpts0: cpts@39000000 { 565 compatible = "ti,j721e-cpts"; 566 reg = <0x0 0x39000000 0x0 0x400>; 567 reg-names = "cpts"; 568 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 569 clocks = <&k3_clks 84 0>; 570 clock-names = "cpts"; 571 assigned-clocks = <&k3_clks 84 0>; 572 assigned-clock-parents = <&k3_clks 84 8>; 573 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 574 interrupt-names = "cpts"; 575 ti,cpts-periodic-outputs = <6>; 576 ti,cpts-ext-ts-inputs = <8>; 577 }; 578 579 timesync_router: pinctrl@a40000 { 580 compatible = "pinctrl-single"; 581 reg = <0x0 0xa40000 0x0 0x800>; 582 #pinctrl-cells = <1>; 583 pinctrl-single,register-width = <32>; 584 pinctrl-single,function-mask = <0x000107ff>; 585 }; 586 587 usbss0: cdns-usb@f900000{ 588 compatible = "ti,am64-usb"; 589 reg = <0x00 0xf900000 0x00 0x100>; 590 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 591 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; 592 clock-names = "ref", "lpm"; 593 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ 594 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ 595 #address-cells = <2>; 596 #size-cells = <2>; 597 ranges; 598 usb0: usb@f400000{ 599 compatible = "cdns,usb3"; 600 reg = <0x00 0xf400000 0x00 0x10000>, 601 <0x00 0xf410000 0x00 0x10000>, 602 <0x00 0xf420000 0x00 0x10000>; 603 reg-names = "otg", 604 "xhci", 605 "dev"; 606 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 607 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 608 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 609 interrupt-names = "host", 610 "peripheral", 611 "otg"; 612 maximum-speed = "super-speed"; 613 dr_mode = "otg"; 614 }; 615 }; 616 617 tscadc0: tscadc@28001000 { 618 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 619 reg = <0x00 0x28001000 0x00 0x1000>; 620 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 621 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 622 clocks = <&k3_clks 0 0>; 623 assigned-clocks = <&k3_clks 0 0>; 624 assigned-clock-parents = <&k3_clks 0 3>; 625 assigned-clock-rates = <60000000>; 626 clock-names = "adc_tsc_fck"; 627 628 adc { 629 #io-channel-cells = <1>; 630 compatible = "ti,am654-adc", "ti,am3359-adc"; 631 }; 632 }; 633 634 fss: bus@fc00000 { 635 compatible = "simple-bus"; 636 reg = <0x00 0x0fc00000 0x00 0x70000>; 637 #address-cells = <2>; 638 #size-cells = <2>; 639 ranges; 640 641 ospi0: spi@fc40000 { 642 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 643 reg = <0x00 0x0fc40000 0x00 0x100>, 644 <0x05 0x00000000 0x01 0x00000000>; 645 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 646 cdns,fifo-depth = <256>; 647 cdns,fifo-width = <4>; 648 cdns,trigger-address = <0x0>; 649 #address-cells = <0x1>; 650 #size-cells = <0x0>; 651 clocks = <&k3_clks 75 6>; 652 assigned-clocks = <&k3_clks 75 6>; 653 assigned-clock-parents = <&k3_clks 75 7>; 654 assigned-clock-rates = <166666666>; 655 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 656 }; 657 }; 658 659 hwspinlock: spinlock@2a000000 { 660 compatible = "ti,am64-hwspinlock"; 661 reg = <0x00 0x2a000000 0x00 0x1000>; 662 #hwlock-cells = <1>; 663 }; 664 665 mailbox0_cluster2: mailbox@29020000 { 666 compatible = "ti,am64-mailbox"; 667 reg = <0x00 0x29020000 0x00 0x200>; 668 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 670 #mbox-cells = <1>; 671 ti,mbox-num-users = <4>; 672 ti,mbox-num-fifos = <16>; 673 }; 674 675 mailbox0_cluster3: mailbox@29030000 { 676 compatible = "ti,am64-mailbox"; 677 reg = <0x00 0x29030000 0x00 0x200>; 678 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 680 #mbox-cells = <1>; 681 ti,mbox-num-users = <4>; 682 ti,mbox-num-fifos = <16>; 683 }; 684 685 mailbox0_cluster4: mailbox@29040000 { 686 compatible = "ti,am64-mailbox"; 687 reg = <0x00 0x29040000 0x00 0x200>; 688 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 690 #mbox-cells = <1>; 691 ti,mbox-num-users = <4>; 692 ti,mbox-num-fifos = <16>; 693 }; 694 695 mailbox0_cluster5: mailbox@29050000 { 696 compatible = "ti,am64-mailbox"; 697 reg = <0x00 0x29050000 0x00 0x200>; 698 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 700 #mbox-cells = <1>; 701 ti,mbox-num-users = <4>; 702 ti,mbox-num-fifos = <16>; 703 }; 704 705 mailbox0_cluster6: mailbox@29060000 { 706 compatible = "ti,am64-mailbox"; 707 reg = <0x00 0x29060000 0x00 0x200>; 708 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 709 #mbox-cells = <1>; 710 ti,mbox-num-users = <4>; 711 ti,mbox-num-fifos = <16>; 712 }; 713 714 mailbox0_cluster7: mailbox@29070000 { 715 compatible = "ti,am64-mailbox"; 716 reg = <0x00 0x29070000 0x00 0x200>; 717 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 718 #mbox-cells = <1>; 719 ti,mbox-num-users = <4>; 720 ti,mbox-num-fifos = <16>; 721 }; 722 723 main_r5fss0: r5fss@78000000 { 724 compatible = "ti,am64-r5fss"; 725 ti,cluster-mode = <0>; 726 #address-cells = <1>; 727 #size-cells = <1>; 728 ranges = <0x78000000 0x00 0x78000000 0x10000>, 729 <0x78100000 0x00 0x78100000 0x10000>, 730 <0x78200000 0x00 0x78200000 0x08000>, 731 <0x78300000 0x00 0x78300000 0x08000>; 732 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 733 734 main_r5fss0_core0: r5f@78000000 { 735 compatible = "ti,am64-r5f"; 736 reg = <0x78000000 0x00010000>, 737 <0x78100000 0x00010000>; 738 reg-names = "atcm", "btcm"; 739 ti,sci = <&dmsc>; 740 ti,sci-dev-id = <121>; 741 ti,sci-proc-ids = <0x01 0xff>; 742 resets = <&k3_reset 121 1>; 743 firmware-name = "am64-main-r5f0_0-fw"; 744 ti,atcm-enable = <1>; 745 ti,btcm-enable = <1>; 746 ti,loczrama = <1>; 747 }; 748 749 main_r5fss0_core1: r5f@78200000 { 750 compatible = "ti,am64-r5f"; 751 reg = <0x78200000 0x00008000>, 752 <0x78300000 0x00008000>; 753 reg-names = "atcm", "btcm"; 754 ti,sci = <&dmsc>; 755 ti,sci-dev-id = <122>; 756 ti,sci-proc-ids = <0x02 0xff>; 757 resets = <&k3_reset 122 1>; 758 firmware-name = "am64-main-r5f0_1-fw"; 759 ti,atcm-enable = <1>; 760 ti,btcm-enable = <1>; 761 ti,loczrama = <1>; 762 }; 763 }; 764 765 main_r5fss1: r5fss@78400000 { 766 compatible = "ti,am64-r5fss"; 767 ti,cluster-mode = <0>; 768 #address-cells = <1>; 769 #size-cells = <1>; 770 ranges = <0x78400000 0x00 0x78400000 0x10000>, 771 <0x78500000 0x00 0x78500000 0x10000>, 772 <0x78600000 0x00 0x78600000 0x08000>, 773 <0x78700000 0x00 0x78700000 0x08000>; 774 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 775 776 main_r5fss1_core0: r5f@78400000 { 777 compatible = "ti,am64-r5f"; 778 reg = <0x78400000 0x00010000>, 779 <0x78500000 0x00010000>; 780 reg-names = "atcm", "btcm"; 781 ti,sci = <&dmsc>; 782 ti,sci-dev-id = <123>; 783 ti,sci-proc-ids = <0x06 0xff>; 784 resets = <&k3_reset 123 1>; 785 firmware-name = "am64-main-r5f1_0-fw"; 786 ti,atcm-enable = <1>; 787 ti,btcm-enable = <1>; 788 ti,loczrama = <1>; 789 }; 790 791 main_r5fss1_core1: r5f@78600000 { 792 compatible = "ti,am64-r5f"; 793 reg = <0x78600000 0x00008000>, 794 <0x78700000 0x00008000>; 795 reg-names = "atcm", "btcm"; 796 ti,sci = <&dmsc>; 797 ti,sci-dev-id = <124>; 798 ti,sci-proc-ids = <0x07 0xff>; 799 resets = <&k3_reset 124 1>; 800 firmware-name = "am64-main-r5f1_1-fw"; 801 ti,atcm-enable = <1>; 802 ti,btcm-enable = <1>; 803 ti,loczrama = <1>; 804 }; 805 }; 806 807 serdes_wiz0: wiz@f000000 { 808 compatible = "ti,am64-wiz-10g"; 809 #address-cells = <1>; 810 #size-cells = <1>; 811 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 812 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; 813 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 814 num-lanes = <1>; 815 #reset-cells = <1>; 816 #clock-cells = <1>; 817 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; 818 819 assigned-clocks = <&k3_clks 162 1>; 820 assigned-clock-parents = <&k3_clks 162 5>; 821 822 serdes0: serdes@f000000 { 823 compatible = "ti,j721e-serdes-10g"; 824 reg = <0x0f000000 0x00010000>; 825 reg-names = "torrent_phy"; 826 resets = <&serdes_wiz0 0>; 827 reset-names = "torrent_reset"; 828 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 829 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 830 clock-names = "refclk", "phy_en_refclk"; 831 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 832 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 833 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 834 assigned-clock-parents = <&k3_clks 162 1>, 835 <&k3_clks 162 1>, 836 <&k3_clks 162 1>; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 #clock-cells = <1>; 840 }; 841 }; 842 843 pcie0_rc: pcie@f102000 { 844 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; 845 reg = <0x00 0x0f102000 0x00 0x1000>, 846 <0x00 0x0f100000 0x00 0x400>, 847 <0x00 0x0d000000 0x00 0x00800000>, 848 <0x00 0x68000000 0x00 0x00001000>; 849 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 850 interrupt-names = "link_state"; 851 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 852 device_type = "pci"; 853 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 854 max-link-speed = <2>; 855 num-lanes = <1>; 856 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 857 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; 858 clock-names = "fck", "pcie_refclk"; 859 #address-cells = <3>; 860 #size-cells = <2>; 861 bus-range = <0x0 0xff>; 862 cdns,no-bar-match-nbits = <64>; 863 vendor-id = <0x104c>; 864 device-id = <0xb010>; 865 msi-map = <0x0 &gic_its 0x0 0x10000>; 866 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, 867 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; 868 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; 869 }; 870 871 pcie0_ep: pcie-ep@f102000 { 872 compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; 873 reg = <0x00 0x0f102000 0x00 0x1000>, 874 <0x00 0x0f100000 0x00 0x400>, 875 <0x00 0x0d000000 0x00 0x00800000>, 876 <0x00 0x68000000 0x00 0x08000000>; 877 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 878 interrupt-names = "link_state"; 879 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 880 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 881 max-link-speed = <2>; 882 num-lanes = <1>; 883 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 884 clocks = <&k3_clks 114 0>; 885 clock-names = "fck"; 886 max-functions = /bits/ 8 <1>; 887 }; 888 889 epwm0: pwm@23000000 { 890 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 891 #pwm-cells = <3>; 892 reg = <0x0 0x23000000 0x0 0x100>; 893 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 894 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 895 clock-names = "tbclk", "fck"; 896 }; 897 898 epwm1: pwm@23010000 { 899 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 900 #pwm-cells = <3>; 901 reg = <0x0 0x23010000 0x0 0x100>; 902 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 903 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 904 clock-names = "tbclk", "fck"; 905 }; 906 907 epwm2: pwm@23020000 { 908 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 909 #pwm-cells = <3>; 910 reg = <0x0 0x23020000 0x0 0x100>; 911 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 912 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 913 clock-names = "tbclk", "fck"; 914 }; 915 916 epwm3: pwm@23030000 { 917 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 918 #pwm-cells = <3>; 919 reg = <0x0 0x23030000 0x0 0x100>; 920 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 921 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; 922 clock-names = "tbclk", "fck"; 923 }; 924 925 epwm4: pwm@23040000 { 926 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 927 #pwm-cells = <3>; 928 reg = <0x0 0x23040000 0x0 0x100>; 929 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 930 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; 931 clock-names = "tbclk", "fck"; 932 }; 933 934 epwm5: pwm@23050000 { 935 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 936 #pwm-cells = <3>; 937 reg = <0x0 0x23050000 0x0 0x100>; 938 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 939 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; 940 clock-names = "tbclk", "fck"; 941 }; 942 943 epwm6: pwm@23060000 { 944 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 945 #pwm-cells = <3>; 946 reg = <0x0 0x23060000 0x0 0x100>; 947 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 948 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; 949 clock-names = "tbclk", "fck"; 950 }; 951 952 epwm7: pwm@23070000 { 953 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 954 #pwm-cells = <3>; 955 reg = <0x0 0x23070000 0x0 0x100>; 956 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 957 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; 958 clock-names = "tbclk", "fck"; 959 }; 960 961 epwm8: pwm@23080000 { 962 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 963 #pwm-cells = <3>; 964 reg = <0x0 0x23080000 0x0 0x100>; 965 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; 966 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; 967 clock-names = "tbclk", "fck"; 968 }; 969 970 ecap0: pwm@23100000 { 971 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 972 #pwm-cells = <3>; 973 reg = <0x0 0x23100000 0x0 0x60>; 974 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 975 clocks = <&k3_clks 51 0>; 976 clock-names = "fck"; 977 }; 978 979 ecap1: pwm@23110000 { 980 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 981 #pwm-cells = <3>; 982 reg = <0x0 0x23110000 0x0 0x60>; 983 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 984 clocks = <&k3_clks 52 0>; 985 clock-names = "fck"; 986 }; 987 988 ecap2: pwm@23120000 { 989 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 990 #pwm-cells = <3>; 991 reg = <0x0 0x23120000 0x0 0x60>; 992 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 993 clocks = <&k3_clks 53 0>; 994 clock-names = "fck"; 995 }; 996 997 main_rti0: watchdog@e000000 { 998 compatible = "ti,j7-rti-wdt"; 999 reg = <0x00 0xe000000 0x00 0x100>; 1000 clocks = <&k3_clks 125 0>; 1001 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 1002 assigned-clocks = <&k3_clks 125 0>; 1003 assigned-clock-parents = <&k3_clks 125 2>; 1004 }; 1005 1006 main_rti1: watchdog@e010000 { 1007 compatible = "ti,j7-rti-wdt"; 1008 reg = <0x00 0xe010000 0x00 0x100>; 1009 clocks = <&k3_clks 126 0>; 1010 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 1011 assigned-clocks = <&k3_clks 126 0>; 1012 assigned-clock-parents = <&k3_clks 126 2>; 1013 }; 1014 1015 icssg0: icssg@30000000 { 1016 compatible = "ti,am642-icssg"; 1017 reg = <0x00 0x30000000 0x00 0x80000>; 1018 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 1019 #address-cells = <1>; 1020 #size-cells = <1>; 1021 ranges = <0x0 0x00 0x30000000 0x80000>; 1022 1023 icssg0_mem: memories@0 { 1024 reg = <0x0 0x2000>, 1025 <0x2000 0x2000>, 1026 <0x10000 0x10000>; 1027 reg-names = "dram0", "dram1", "shrdram2"; 1028 }; 1029 1030 icssg0_cfg: cfg@26000 { 1031 compatible = "ti,pruss-cfg", "syscon"; 1032 reg = <0x26000 0x200>; 1033 #address-cells = <1>; 1034 #size-cells = <1>; 1035 ranges = <0x0 0x26000 0x2000>; 1036 1037 clocks { 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 1041 icssg0_coreclk_mux: coreclk-mux@3c { 1042 reg = <0x3c>; 1043 #clock-cells = <0>; 1044 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ 1045 <&k3_clks 81 20>; /* icssg0_iclk */ 1046 assigned-clocks = <&icssg0_coreclk_mux>; 1047 assigned-clock-parents = <&k3_clks 81 20>; 1048 }; 1049 1050 icssg0_iepclk_mux: iepclk-mux@30 { 1051 reg = <0x30>; 1052 #clock-cells = <0>; 1053 clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */ 1054 <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */ 1055 assigned-clocks = <&icssg0_iepclk_mux>; 1056 assigned-clock-parents = <&icssg0_coreclk_mux>; 1057 }; 1058 }; 1059 }; 1060 1061 icssg0_mii_rt: mii-rt@32000 { 1062 compatible = "ti,pruss-mii", "syscon"; 1063 reg = <0x32000 0x100>; 1064 }; 1065 1066 icssg0_mii_g_rt: mii-g-rt@33000 { 1067 compatible = "ti,pruss-mii-g", "syscon"; 1068 reg = <0x33000 0x1000>; 1069 }; 1070 1071 icssg0_intc: interrupt-controller@20000 { 1072 compatible = "ti,icssg-intc"; 1073 reg = <0x20000 0x2000>; 1074 interrupt-controller; 1075 #interrupt-cells = <3>; 1076 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1084 interrupt-names = "host_intr0", "host_intr1", 1085 "host_intr2", "host_intr3", 1086 "host_intr4", "host_intr5", 1087 "host_intr6", "host_intr7"; 1088 }; 1089 1090 pru0_0: pru@34000 { 1091 compatible = "ti,am642-pru"; 1092 reg = <0x34000 0x3000>, 1093 <0x22000 0x100>, 1094 <0x22400 0x100>; 1095 reg-names = "iram", "control", "debug"; 1096 firmware-name = "am64x-pru0_0-fw"; 1097 }; 1098 1099 rtu0_0: rtu@4000 { 1100 compatible = "ti,am642-rtu"; 1101 reg = <0x4000 0x2000>, 1102 <0x23000 0x100>, 1103 <0x23400 0x100>; 1104 reg-names = "iram", "control", "debug"; 1105 firmware-name = "am64x-rtu0_0-fw"; 1106 }; 1107 1108 tx_pru0_0: txpru@a000 { 1109 compatible = "ti,am642-tx-pru"; 1110 reg = <0xa000 0x1800>, 1111 <0x25000 0x100>, 1112 <0x25400 0x100>; 1113 reg-names = "iram", "control", "debug"; 1114 firmware-name = "am64x-txpru0_0-fw"; 1115 }; 1116 1117 pru0_1: pru@38000 { 1118 compatible = "ti,am642-pru"; 1119 reg = <0x38000 0x3000>, 1120 <0x24000 0x100>, 1121 <0x24400 0x100>; 1122 reg-names = "iram", "control", "debug"; 1123 firmware-name = "am64x-pru0_1-fw"; 1124 }; 1125 1126 rtu0_1: rtu@6000 { 1127 compatible = "ti,am642-rtu"; 1128 reg = <0x6000 0x2000>, 1129 <0x23800 0x100>, 1130 <0x23c00 0x100>; 1131 reg-names = "iram", "control", "debug"; 1132 firmware-name = "am64x-rtu0_1-fw"; 1133 }; 1134 1135 tx_pru0_1: txpru@c000 { 1136 compatible = "ti,am642-tx-pru"; 1137 reg = <0xc000 0x1800>, 1138 <0x25800 0x100>, 1139 <0x25c00 0x100>; 1140 reg-names = "iram", "control", "debug"; 1141 firmware-name = "am64x-txpru0_1-fw"; 1142 }; 1143 1144 icssg0_mdio: mdio@32400 { 1145 compatible = "ti,davinci_mdio"; 1146 reg = <0x32400 0x100>; 1147 clocks = <&k3_clks 62 3>; 1148 clock-names = "fck"; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 bus_freq = <1000000>; 1152 }; 1153 }; 1154 1155 icssg1: icssg@30080000 { 1156 compatible = "ti,am642-icssg"; 1157 reg = <0x00 0x30080000 0x00 0x80000>; 1158 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 1159 #address-cells = <1>; 1160 #size-cells = <1>; 1161 ranges = <0x0 0x00 0x30080000 0x80000>; 1162 1163 icssg1_mem: memories@0 { 1164 reg = <0x0 0x2000>, 1165 <0x2000 0x2000>, 1166 <0x10000 0x10000>; 1167 reg-names = "dram0", "dram1", "shrdram2"; 1168 }; 1169 1170 icssg1_cfg: cfg@26000 { 1171 compatible = "ti,pruss-cfg", "syscon"; 1172 reg = <0x26000 0x200>; 1173 #address-cells = <1>; 1174 #size-cells = <1>; 1175 ranges = <0x0 0x26000 0x2000>; 1176 1177 clocks { 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 1181 icssg1_coreclk_mux: coreclk-mux@3c { 1182 reg = <0x3c>; 1183 #clock-cells = <0>; 1184 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ 1185 <&k3_clks 82 20>; /* icssg1_iclk */ 1186 assigned-clocks = <&icssg1_coreclk_mux>; 1187 assigned-clock-parents = <&k3_clks 82 20>; 1188 }; 1189 1190 icssg1_iepclk_mux: iepclk-mux@30 { 1191 reg = <0x30>; 1192 #clock-cells = <0>; 1193 clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */ 1194 <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */ 1195 assigned-clocks = <&icssg1_iepclk_mux>; 1196 assigned-clock-parents = <&icssg1_coreclk_mux>; 1197 }; 1198 }; 1199 }; 1200 1201 icssg1_mii_rt: mii-rt@32000 { 1202 compatible = "ti,pruss-mii", "syscon"; 1203 reg = <0x32000 0x100>; 1204 }; 1205 1206 icssg1_mii_g_rt: mii-g-rt@33000 { 1207 compatible = "ti,pruss-mii-g", "syscon"; 1208 reg = <0x33000 0x1000>; 1209 }; 1210 1211 icssg1_intc: interrupt-controller@20000 { 1212 compatible = "ti,icssg-intc"; 1213 reg = <0x20000 0x2000>; 1214 interrupt-controller; 1215 #interrupt-cells = <3>; 1216 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1224 interrupt-names = "host_intr0", "host_intr1", 1225 "host_intr2", "host_intr3", 1226 "host_intr4", "host_intr5", 1227 "host_intr6", "host_intr7"; 1228 }; 1229 1230 pru1_0: pru@34000 { 1231 compatible = "ti,am642-pru"; 1232 reg = <0x34000 0x4000>, 1233 <0x22000 0x100>, 1234 <0x22400 0x100>; 1235 reg-names = "iram", "control", "debug"; 1236 firmware-name = "am64x-pru1_0-fw"; 1237 }; 1238 1239 rtu1_0: rtu@4000 { 1240 compatible = "ti,am642-rtu"; 1241 reg = <0x4000 0x2000>, 1242 <0x23000 0x100>, 1243 <0x23400 0x100>; 1244 reg-names = "iram", "control", "debug"; 1245 firmware-name = "am64x-rtu1_0-fw"; 1246 }; 1247 1248 tx_pru1_0: txpru@a000 { 1249 compatible = "ti,am642-tx-pru"; 1250 reg = <0xa000 0x1800>, 1251 <0x25000 0x100>, 1252 <0x25400 0x100>; 1253 reg-names = "iram", "control", "debug"; 1254 firmware-name = "am64x-txpru1_0-fw"; 1255 }; 1256 1257 pru1_1: pru@38000 { 1258 compatible = "ti,am642-pru"; 1259 reg = <0x38000 0x4000>, 1260 <0x24000 0x100>, 1261 <0x24400 0x100>; 1262 reg-names = "iram", "control", "debug"; 1263 firmware-name = "am64x-pru1_1-fw"; 1264 }; 1265 1266 rtu1_1: rtu@6000 { 1267 compatible = "ti,am642-rtu"; 1268 reg = <0x6000 0x2000>, 1269 <0x23800 0x100>, 1270 <0x23c00 0x100>; 1271 reg-names = "iram", "control", "debug"; 1272 firmware-name = "am64x-rtu1_1-fw"; 1273 }; 1274 1275 tx_pru1_1: txpru@c000 { 1276 compatible = "ti,am642-tx-pru"; 1277 reg = <0xc000 0x1800>, 1278 <0x25800 0x100>, 1279 <0x25c00 0x100>; 1280 reg-names = "iram", "control", "debug"; 1281 firmware-name = "am64x-txpru1_1-fw"; 1282 }; 1283 1284 icssg1_mdio: mdio@32400 { 1285 compatible = "ti,davinci_mdio"; 1286 reg = <0x32400 0x100>; 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 clocks = <&k3_clks 82 0>; 1290 clock-names = "fck"; 1291 bus_freq = <1000000>; 1292 }; 1293 }; 1294 1295 main_mcan0: can@20701000 { 1296 compatible = "bosch,m_can"; 1297 reg = <0x00 0x20701000 0x00 0x200>, 1298 <0x00 0x20708000 0x00 0x8000>; 1299 reg-names = "m_can", "message_ram"; 1300 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 1301 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; 1302 clock-names = "hclk", "cclk"; 1303 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1305 interrupt-names = "int0", "int1"; 1306 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1307 }; 1308 1309 main_mcan1: can@20711000 { 1310 compatible = "bosch,m_can"; 1311 reg = <0x00 0x20711000 0x00 0x200>, 1312 <0x00 0x20718000 0x00 0x8000>; 1313 reg-names = "m_can", "message_ram"; 1314 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 1315 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; 1316 clock-names = "hclk", "cclk"; 1317 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1319 interrupt-names = "int0", "int1"; 1320 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1321 }; 1322 1323 crypto: crypto@40900000 { 1324 compatible = "ti,am64-sa2ul"; 1325 reg = <0x00 0x40900000 0x00 0x1200>; 1326 power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>; 1327 #address-cells = <2>; 1328 #size-cells = <2>; 1329 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 1330 dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>, 1331 <&main_pktdma 0x4003 0>; 1332 dma-names = "tx", "rx1", "rx2"; 1333 1334 rng: rng@40910000 { 1335 compatible = "inside-secure,safexcel-eip76"; 1336 reg = <0x00 0x40910000 0x00 0x7d>; 1337 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1338 clocks = <&k3_clks 133 1>; 1339 status = "disabled"; /* Used by OP-TEE */ 1340 }; 1341 }; 1342 1343 gpmc0: memory-controller@3b000000 { 1344 compatible = "ti,am64-gpmc"; 1345 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 1346 clocks = <&k3_clks 80 0>; 1347 clock-names = "fck"; 1348 reg = <0x00 0x03b000000 0x00 0x400>, 1349 <0x00 0x050000000 0x00 0x8000000>; 1350 reg-names = "cfg", "data"; 1351 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1352 gpmc,num-cs = <3>; 1353 gpmc,num-waitpins = <2>; 1354 #address-cells = <2>; 1355 #size-cells = <1>; 1356 interrupt-controller; 1357 #interrupt-cells = <2>; 1358 gpio-controller; 1359 #gpio-cells = <2>; 1360 }; 1361 1362 elm0: ecc@25010000 { 1363 compatible = "ti,am64-elm"; 1364 reg = <0x00 0x25010000 0x00 0x2000>; 1365 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1366 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1367 clocks = <&k3_clks 54 0>; 1368 clock-names = "fck"; 1369 }; 1370}; 1371