1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM625 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 #interrupt-cells = <3>; 23 interrupt-controller; 24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 27 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 28 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 29 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 30 /* 31 * vcpumntirq: 32 * virtual CPU interface maintenance interrupt 33 */ 34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 35 36 gic_its: msi-controller@1820000 { 37 compatible = "arm,gic-v3-its"; 38 reg = <0x00 0x01820000 0x00 0x10000>; 39 socionext,synquacer-pre-its = <0x1000000 0x400000>; 40 msi-controller; 41 #msi-cells = <1>; 42 }; 43 }; 44 45 main_conf: syscon@100000 { 46 compatible = "syscon", "simple-mfd"; 47 reg = <0x00 0x00100000 0x00 0x20000>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges = <0x0 0x00 0x00100000 0x20000>; 51 52 phy_gmii_sel: phy@4044 { 53 compatible = "ti,am654-phy-gmii-sel"; 54 reg = <0x4044 0x8>; 55 #phy-cells = <1>; 56 }; 57 58 epwm_tbclk: clock-controller@4130 { 59 compatible = "ti,am62-epwm-tbclk"; 60 reg = <0x4130 0x4>; 61 #clock-cells = <1>; 62 }; 63 64 audio_refclk0: clock-controller@82e0 { 65 compatible = "ti,am62-audio-refclk"; 66 reg = <0x82e0 0x4>; 67 clocks = <&k3_clks 157 0>; 68 assigned-clocks = <&k3_clks 157 0>; 69 assigned-clock-parents = <&k3_clks 157 8>; 70 #clock-cells = <0>; 71 }; 72 73 audio_refclk1: clock-controller@82e4 { 74 compatible = "ti,am62-audio-refclk"; 75 reg = <0x82e4 0x4>; 76 clocks = <&k3_clks 157 10>; 77 assigned-clocks = <&k3_clks 157 10>; 78 assigned-clock-parents = <&k3_clks 157 18>; 79 #clock-cells = <0>; 80 }; 81 }; 82 83 dmss: bus@48000000 { 84 compatible = "simple-mfd"; 85 #address-cells = <2>; 86 #size-cells = <2>; 87 dma-ranges; 88 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 89 90 ti,sci-dev-id = <25>; 91 92 secure_proxy_main: mailbox@4d000000 { 93 compatible = "ti,am654-secure-proxy"; 94 #mbox-cells = <1>; 95 reg-names = "target_data", "rt", "scfg"; 96 reg = <0x00 0x4d000000 0x00 0x80000>, 97 <0x00 0x4a600000 0x00 0x80000>, 98 <0x00 0x4a400000 0x00 0x80000>; 99 interrupt-names = "rx_012"; 100 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 101 }; 102 103 inta_main_dmss: interrupt-controller@48000000 { 104 compatible = "ti,sci-inta"; 105 reg = <0x00 0x48000000 0x00 0x100000>; 106 #interrupt-cells = <0>; 107 interrupt-controller; 108 interrupt-parent = <&gic500>; 109 msi-controller; 110 ti,sci = <&dmsc>; 111 ti,sci-dev-id = <28>; 112 ti,interrupt-ranges = <4 68 36>; 113 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 114 }; 115 116 main_bcdma: dma-controller@485c0100 { 117 compatible = "ti,am64-dmss-bcdma"; 118 reg = <0x00 0x485c0100 0x00 0x100>, 119 <0x00 0x4c000000 0x00 0x20000>, 120 <0x00 0x4a820000 0x00 0x20000>, 121 <0x00 0x4aa40000 0x00 0x20000>, 122 <0x00 0x4bc00000 0x00 0x100000>; 123 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 124 msi-parent = <&inta_main_dmss>; 125 #dma-cells = <3>; 126 127 ti,sci = <&dmsc>; 128 ti,sci-dev-id = <26>; 129 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 130 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 131 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 132 }; 133 134 main_pktdma: dma-controller@485c0000 { 135 compatible = "ti,am64-dmss-pktdma"; 136 reg = <0x00 0x485c0000 0x00 0x100>, 137 <0x00 0x4a800000 0x00 0x20000>, 138 <0x00 0x4aa00000 0x00 0x40000>, 139 <0x00 0x4b800000 0x00 0x400000>; 140 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 141 msi-parent = <&inta_main_dmss>; 142 #dma-cells = <2>; 143 144 ti,sci = <&dmsc>; 145 ti,sci-dev-id = <30>; 146 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 147 <0x24>, /* CPSW_TX_CHAN */ 148 <0x25>, /* SAUL_TX_0_CHAN */ 149 <0x26>; /* SAUL_TX_1_CHAN */ 150 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 151 <0x11>, /* RING_CPSW_TX_CHAN */ 152 <0x12>, /* RING_SAUL_TX_0_CHAN */ 153 <0x13>; /* RING_SAUL_TX_1_CHAN */ 154 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 155 <0x2b>, /* CPSW_RX_CHAN */ 156 <0x2d>, /* SAUL_RX_0_CHAN */ 157 <0x2f>, /* SAUL_RX_1_CHAN */ 158 <0x31>, /* SAUL_RX_2_CHAN */ 159 <0x33>; /* SAUL_RX_3_CHAN */ 160 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 161 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 162 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 163 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 164 }; 165 }; 166 167 dmsc: system-controller@44043000 { 168 compatible = "ti,k2g-sci"; 169 ti,host-id = <12>; 170 mbox-names = "rx", "tx"; 171 mboxes = <&secure_proxy_main 12>, 172 <&secure_proxy_main 13>; 173 reg-names = "debug_messages"; 174 reg = <0x00 0x44043000 0x00 0xfe0>; 175 176 k3_pds: power-controller { 177 compatible = "ti,sci-pm-domain"; 178 #power-domain-cells = <2>; 179 }; 180 181 k3_clks: clock-controller { 182 compatible = "ti,k2g-sci-clk"; 183 #clock-cells = <2>; 184 }; 185 186 k3_reset: reset-controller { 187 compatible = "ti,sci-reset"; 188 #reset-cells = <2>; 189 }; 190 }; 191 192 crypto: crypto@40900000 { 193 compatible = "ti,am62-sa3ul"; 194 reg = <0x00 0x40900000 0x00 0x1200>; 195 #address-cells = <2>; 196 #size-cells = <2>; 197 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 198 199 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 200 <&main_pktdma 0x7507 0>; 201 dma-names = "tx", "rx1", "rx2"; 202 }; 203 204 secure_proxy_sa3: mailbox@43600000 { 205 compatible = "ti,am654-secure-proxy"; 206 #mbox-cells = <1>; 207 reg-names = "target_data", "rt", "scfg"; 208 reg = <0x00 0x43600000 0x00 0x10000>, 209 <0x00 0x44880000 0x00 0x20000>, 210 <0x00 0x44860000 0x00 0x20000>; 211 /* 212 * Marked Disabled: 213 * Node is incomplete as it is meant for bootloaders and 214 * firmware on non-MPU processors 215 */ 216 status = "disabled"; 217 }; 218 219 main_pmx0: pinctrl@f4000 { 220 compatible = "pinctrl-single"; 221 reg = <0x00 0xf4000 0x00 0x2ac>; 222 #pinctrl-cells = <1>; 223 pinctrl-single,register-width = <32>; 224 pinctrl-single,function-mask = <0xffffffff>; 225 }; 226 227 main_esm: esm@420000 { 228 compatible = "ti,j721e-esm"; 229 reg = <0x00 0x420000 0x00 0x1000>; 230 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; 231 }; 232 233 main_timer0: timer@2400000 { 234 compatible = "ti,am654-timer"; 235 reg = <0x00 0x2400000 0x00 0x400>; 236 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&k3_clks 36 2>; 238 clock-names = "fck"; 239 assigned-clocks = <&k3_clks 36 2>; 240 assigned-clock-parents = <&k3_clks 36 3>; 241 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 242 ti,timer-pwm; 243 }; 244 245 main_timer1: timer@2410000 { 246 compatible = "ti,am654-timer"; 247 reg = <0x00 0x2410000 0x00 0x400>; 248 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&k3_clks 37 2>; 250 clock-names = "fck"; 251 assigned-clocks = <&k3_clks 37 2>; 252 assigned-clock-parents = <&k3_clks 37 3>; 253 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 254 ti,timer-pwm; 255 }; 256 257 main_timer2: timer@2420000 { 258 compatible = "ti,am654-timer"; 259 reg = <0x00 0x2420000 0x00 0x400>; 260 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&k3_clks 38 2>; 262 clock-names = "fck"; 263 assigned-clocks = <&k3_clks 38 2>; 264 assigned-clock-parents = <&k3_clks 38 3>; 265 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 266 ti,timer-pwm; 267 }; 268 269 main_timer3: timer@2430000 { 270 compatible = "ti,am654-timer"; 271 reg = <0x00 0x2430000 0x00 0x400>; 272 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&k3_clks 39 2>; 274 clock-names = "fck"; 275 assigned-clocks = <&k3_clks 39 2>; 276 assigned-clock-parents = <&k3_clks 39 3>; 277 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 278 ti,timer-pwm; 279 }; 280 281 main_timer4: timer@2440000 { 282 compatible = "ti,am654-timer"; 283 reg = <0x00 0x2440000 0x00 0x400>; 284 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&k3_clks 40 2>; 286 clock-names = "fck"; 287 assigned-clocks = <&k3_clks 40 2>; 288 assigned-clock-parents = <&k3_clks 40 3>; 289 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 290 ti,timer-pwm; 291 }; 292 293 main_timer5: timer@2450000 { 294 compatible = "ti,am654-timer"; 295 reg = <0x00 0x2450000 0x00 0x400>; 296 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&k3_clks 41 2>; 298 clock-names = "fck"; 299 assigned-clocks = <&k3_clks 41 2>; 300 assigned-clock-parents = <&k3_clks 41 3>; 301 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 302 ti,timer-pwm; 303 }; 304 305 main_timer6: timer@2460000 { 306 compatible = "ti,am654-timer"; 307 reg = <0x00 0x2460000 0x00 0x400>; 308 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&k3_clks 42 2>; 310 clock-names = "fck"; 311 assigned-clocks = <&k3_clks 42 2>; 312 assigned-clock-parents = <&k3_clks 42 3>; 313 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 314 ti,timer-pwm; 315 }; 316 317 main_timer7: timer@2470000 { 318 compatible = "ti,am654-timer"; 319 reg = <0x00 0x2470000 0x00 0x400>; 320 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&k3_clks 43 2>; 322 clock-names = "fck"; 323 assigned-clocks = <&k3_clks 43 2>; 324 assigned-clock-parents = <&k3_clks 43 3>; 325 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 326 ti,timer-pwm; 327 }; 328 329 main_uart0: serial@2800000 { 330 compatible = "ti,am64-uart", "ti,am654-uart"; 331 reg = <0x00 0x02800000 0x00 0x100>; 332 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 333 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 334 clocks = <&k3_clks 146 0>; 335 clock-names = "fclk"; 336 status = "disabled"; 337 }; 338 339 main_uart1: serial@2810000 { 340 compatible = "ti,am64-uart", "ti,am654-uart"; 341 reg = <0x00 0x02810000 0x00 0x100>; 342 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 343 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 344 clocks = <&k3_clks 152 0>; 345 clock-names = "fclk"; 346 status = "disabled"; 347 }; 348 349 main_uart2: serial@2820000 { 350 compatible = "ti,am64-uart", "ti,am654-uart"; 351 reg = <0x00 0x02820000 0x00 0x100>; 352 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 353 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 354 clocks = <&k3_clks 153 0>; 355 clock-names = "fclk"; 356 status = "disabled"; 357 }; 358 359 main_uart3: serial@2830000 { 360 compatible = "ti,am64-uart", "ti,am654-uart"; 361 reg = <0x00 0x02830000 0x00 0x100>; 362 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 363 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 364 clocks = <&k3_clks 154 0>; 365 clock-names = "fclk"; 366 status = "disabled"; 367 }; 368 369 main_uart4: serial@2840000 { 370 compatible = "ti,am64-uart", "ti,am654-uart"; 371 reg = <0x00 0x02840000 0x00 0x100>; 372 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 373 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 374 clocks = <&k3_clks 155 0>; 375 clock-names = "fclk"; 376 status = "disabled"; 377 }; 378 379 main_uart5: serial@2850000 { 380 compatible = "ti,am64-uart", "ti,am654-uart"; 381 reg = <0x00 0x02850000 0x00 0x100>; 382 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 383 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 384 clocks = <&k3_clks 156 0>; 385 clock-names = "fclk"; 386 status = "disabled"; 387 }; 388 389 main_uart6: serial@2860000 { 390 compatible = "ti,am64-uart", "ti,am654-uart"; 391 reg = <0x00 0x02860000 0x00 0x100>; 392 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 393 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 394 clocks = <&k3_clks 158 0>; 395 clock-names = "fclk"; 396 status = "disabled"; 397 }; 398 399 main_i2c0: i2c@20000000 { 400 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 401 reg = <0x00 0x20000000 0x00 0x100>; 402 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 406 clocks = <&k3_clks 102 2>; 407 clock-names = "fck"; 408 status = "disabled"; 409 }; 410 411 main_i2c1: i2c@20010000 { 412 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 413 reg = <0x00 0x20010000 0x00 0x100>; 414 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 418 clocks = <&k3_clks 103 2>; 419 clock-names = "fck"; 420 status = "disabled"; 421 }; 422 423 main_i2c2: i2c@20020000 { 424 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 425 reg = <0x00 0x20020000 0x00 0x100>; 426 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 430 clocks = <&k3_clks 104 2>; 431 clock-names = "fck"; 432 status = "disabled"; 433 }; 434 435 main_i2c3: i2c@20030000 { 436 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 437 reg = <0x00 0x20030000 0x00 0x100>; 438 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 442 clocks = <&k3_clks 105 2>; 443 clock-names = "fck"; 444 status = "disabled"; 445 }; 446 447 main_spi0: spi@20100000 { 448 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 449 reg = <0x00 0x20100000 0x00 0x400>; 450 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 454 clocks = <&k3_clks 141 0>; 455 status = "disabled"; 456 }; 457 458 main_spi1: spi@20110000 { 459 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 460 reg = <0x00 0x20110000 0x00 0x400>; 461 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 465 clocks = <&k3_clks 142 0>; 466 status = "disabled"; 467 }; 468 469 main_spi2: spi@20120000 { 470 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 471 reg = <0x00 0x20120000 0x00 0x400>; 472 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 476 clocks = <&k3_clks 143 0>; 477 status = "disabled"; 478 }; 479 480 main_gpio_intr: interrupt-controller@a00000 { 481 compatible = "ti,sci-intr"; 482 reg = <0x00 0x00a00000 0x00 0x800>; 483 ti,intr-trigger-type = <1>; 484 interrupt-controller; 485 interrupt-parent = <&gic500>; 486 #interrupt-cells = <1>; 487 ti,sci = <&dmsc>; 488 ti,sci-dev-id = <3>; 489 ti,interrupt-ranges = <0 32 16>; 490 }; 491 492 main_gpio0: gpio@600000 { 493 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 494 reg = <0x0 0x00600000 0x0 0x100>; 495 gpio-controller; 496 #gpio-cells = <2>; 497 interrupt-parent = <&main_gpio_intr>; 498 interrupts = <190>, <191>, <192>, 499 <193>, <194>, <195>; 500 interrupt-controller; 501 #interrupt-cells = <2>; 502 ti,ngpio = <92>; 503 ti,davinci-gpio-unbanked = <0>; 504 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 505 clocks = <&k3_clks 77 0>; 506 clock-names = "gpio"; 507 }; 508 509 main_gpio1: gpio@601000 { 510 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 511 reg = <0x0 0x00601000 0x0 0x100>; 512 gpio-controller; 513 #gpio-cells = <2>; 514 interrupt-parent = <&main_gpio_intr>; 515 interrupts = <180>, <181>, <182>, 516 <183>, <184>, <185>; 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 ti,ngpio = <52>; 520 ti,davinci-gpio-unbanked = <0>; 521 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 522 clocks = <&k3_clks 78 0>; 523 clock-names = "gpio"; 524 }; 525 526 sdhci0: mmc@fa10000 { 527 compatible = "ti,am62-sdhci"; 528 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; 529 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 530 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 531 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; 532 clock-names = "clk_ahb", "clk_xin"; 533 assigned-clocks = <&k3_clks 57 6>; 534 assigned-clock-parents = <&k3_clks 57 8>; 535 mmc-ddr-1_8v; 536 mmc-hs200-1_8v; 537 ti,trm-icp = <0x2>; 538 bus-width = <8>; 539 ti,clkbuf-sel = <0x7>; 540 ti,otap-del-sel-legacy = <0x0>; 541 ti,otap-del-sel-mmc-hs = <0x0>; 542 ti,otap-del-sel-ddr52 = <0x5>; 543 ti,otap-del-sel-hs200 = <0x5>; 544 ti,itap-del-sel-legacy = <0xa>; 545 ti,itap-del-sel-mmc-hs = <0x1>; 546 status = "disabled"; 547 }; 548 549 sdhci1: mmc@fa00000 { 550 compatible = "ti,am62-sdhci"; 551 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; 552 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 553 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 554 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 555 clock-names = "clk_ahb", "clk_xin"; 556 ti,trm-icp = <0x2>; 557 ti,otap-del-sel-legacy = <0x8>; 558 ti,otap-del-sel-sd-hs = <0x0>; 559 ti,otap-del-sel-sdr12 = <0x0>; 560 ti,otap-del-sel-sdr25 = <0x0>; 561 ti,otap-del-sel-sdr50 = <0x8>; 562 ti,otap-del-sel-sdr104 = <0x7>; 563 ti,otap-del-sel-ddr50 = <0x4>; 564 ti,itap-del-sel-legacy = <0xa>; 565 ti,itap-del-sel-sd-hs = <0x1>; 566 ti,itap-del-sel-sdr12 = <0xa>; 567 ti,itap-del-sel-sdr25 = <0x1>; 568 ti,clkbuf-sel = <0x7>; 569 bus-width = <4>; 570 status = "disabled"; 571 }; 572 573 sdhci2: mmc@fa20000 { 574 compatible = "ti,am62-sdhci"; 575 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; 576 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 577 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 578 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 579 clock-names = "clk_ahb", "clk_xin"; 580 ti,trm-icp = <0x2>; 581 ti,otap-del-sel-legacy = <0x8>; 582 ti,otap-del-sel-sd-hs = <0x0>; 583 ti,otap-del-sel-sdr12 = <0x0>; 584 ti,otap-del-sel-sdr25 = <0x0>; 585 ti,otap-del-sel-sdr50 = <0x8>; 586 ti,otap-del-sel-sdr104 = <0x7>; 587 ti,otap-del-sel-ddr50 = <0x8>; 588 ti,itap-del-sel-legacy = <0xa>; 589 ti,itap-del-sel-sd-hs = <0xa>; 590 ti,itap-del-sel-sdr12 = <0xa>; 591 ti,itap-del-sel-sdr25 = <0x1>; 592 ti,clkbuf-sel = <0x7>; 593 status = "disabled"; 594 }; 595 596 usbss0: dwc3-usb@f900000 { 597 compatible = "ti,am62-usb"; 598 reg = <0x00 0x0f900000 0x00 0x800>; 599 clocks = <&k3_clks 161 3>; 600 clock-names = "ref"; 601 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; 602 #address-cells = <2>; 603 #size-cells = <2>; 604 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 605 ranges; 606 status = "disabled"; 607 608 usb0: usb@31000000 { 609 compatible = "snps,dwc3"; 610 reg = <0x00 0x31000000 0x00 0x50000>; 611 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 612 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 613 interrupt-names = "host", "peripheral"; 614 maximum-speed = "high-speed"; 615 dr_mode = "otg"; 616 snps,usb2-gadget-lpm-disable; 617 snps,usb2-lpm-disable; 618 }; 619 }; 620 621 usbss1: dwc3-usb@f910000 { 622 compatible = "ti,am62-usb"; 623 reg = <0x00 0x0f910000 0x00 0x800>; 624 clocks = <&k3_clks 162 3>; 625 clock-names = "ref"; 626 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; 627 #address-cells = <2>; 628 #size-cells = <2>; 629 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 630 ranges; 631 status = "disabled"; 632 633 usb1: usb@31100000 { 634 compatible = "snps,dwc3"; 635 reg = <0x00 0x31100000 0x00 0x50000>; 636 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 637 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 638 interrupt-names = "host", "peripheral"; 639 maximum-speed = "high-speed"; 640 dr_mode = "otg"; 641 snps,usb2-gadget-lpm-disable; 642 snps,usb2-lpm-disable; 643 }; 644 }; 645 646 fss: bus@fc00000 { 647 compatible = "simple-bus"; 648 reg = <0x00 0x0fc00000 0x00 0x70000>; 649 #address-cells = <2>; 650 #size-cells = <2>; 651 ranges; 652 653 ospi0: spi@fc40000 { 654 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 655 reg = <0x00 0x0fc40000 0x00 0x100>, 656 <0x05 0x00000000 0x01 0x00000000>; 657 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 658 cdns,fifo-depth = <256>; 659 cdns,fifo-width = <4>; 660 cdns,trigger-address = <0x0>; 661 clocks = <&k3_clks 75 7>; 662 assigned-clocks = <&k3_clks 75 7>; 663 assigned-clock-parents = <&k3_clks 75 8>; 664 assigned-clock-rates = <166666666>; 665 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 status = "disabled"; 669 }; 670 }; 671 672 cpsw3g: ethernet@8000000 { 673 compatible = "ti,am642-cpsw-nuss"; 674 #address-cells = <2>; 675 #size-cells = <2>; 676 reg = <0x00 0x08000000 0x00 0x200000>; 677 reg-names = "cpsw_nuss"; 678 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; 679 clocks = <&k3_clks 13 0>; 680 assigned-clocks = <&k3_clks 13 3>; 681 assigned-clock-parents = <&k3_clks 13 11>; 682 clock-names = "fck"; 683 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 684 685 dmas = <&main_pktdma 0xc600 15>, 686 <&main_pktdma 0xc601 15>, 687 <&main_pktdma 0xc602 15>, 688 <&main_pktdma 0xc603 15>, 689 <&main_pktdma 0xc604 15>, 690 <&main_pktdma 0xc605 15>, 691 <&main_pktdma 0xc606 15>, 692 <&main_pktdma 0xc607 15>, 693 <&main_pktdma 0x4600 15>; 694 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 695 "tx7", "rx"; 696 697 ethernet-ports { 698 #address-cells = <1>; 699 #size-cells = <0>; 700 701 cpsw_port1: port@1 { 702 reg = <1>; 703 ti,mac-only; 704 label = "port1"; 705 phys = <&phy_gmii_sel 1>; 706 mac-address = [00 00 00 00 00 00]; 707 ti,syscon-efuse = <&wkup_conf 0x200>; 708 }; 709 710 cpsw_port2: port@2 { 711 reg = <2>; 712 ti,mac-only; 713 label = "port2"; 714 phys = <&phy_gmii_sel 2>; 715 mac-address = [00 00 00 00 00 00]; 716 }; 717 }; 718 719 cpsw3g_mdio: mdio@f00 { 720 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 721 reg = <0x00 0xf00 0x00 0x100>; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 clocks = <&k3_clks 13 0>; 725 clock-names = "fck"; 726 bus_freq = <1000000>; 727 status = "disabled"; 728 }; 729 730 cpts@3d000 { 731 compatible = "ti,j721e-cpts"; 732 reg = <0x00 0x3d000 0x00 0x400>; 733 clocks = <&k3_clks 13 3>; 734 clock-names = "cpts"; 735 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 736 interrupt-names = "cpts"; 737 ti,cpts-ext-ts-inputs = <4>; 738 ti,cpts-periodic-outputs = <2>; 739 }; 740 }; 741 742 dss: dss@30200000 { 743 compatible = "ti,am625-dss"; 744 reg = <0x00 0x30200000 0x00 0x1000>, /* common */ 745 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ 746 <0x00 0x30206000 0x00 0x1000>, /* vid */ 747 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ 748 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ 749 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ 750 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ 751 <0x00 0x30201000 0x00 0x1000>; /* common1 */ 752 reg-names = "common", "vidl1", "vid", 753 "ovr1", "ovr2", "vp1", "vp2", "common1"; 754 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 755 clocks = <&k3_clks 186 6>, 756 <&dss_vp1_clk>, 757 <&k3_clks 186 2>; 758 clock-names = "fck", "vp1", "vp2"; 759 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 760 status = "disabled"; 761 762 dss_ports: ports { 763 #address-cells = <1>; 764 #size-cells = <0>; 765 }; 766 }; 767 768 hwspinlock: spinlock@2a000000 { 769 compatible = "ti,am64-hwspinlock"; 770 reg = <0x00 0x2a000000 0x00 0x1000>; 771 #hwlock-cells = <1>; 772 }; 773 774 mailbox0_cluster0: mailbox@29000000 { 775 compatible = "ti,am64-mailbox"; 776 reg = <0x00 0x29000000 0x00 0x200>; 777 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 779 #mbox-cells = <1>; 780 ti,mbox-num-users = <4>; 781 ti,mbox-num-fifos = <16>; 782 }; 783 784 ecap0: pwm@23100000 { 785 compatible = "ti,am3352-ecap"; 786 #pwm-cells = <3>; 787 reg = <0x00 0x23100000 0x00 0x100>; 788 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 789 clocks = <&k3_clks 51 0>; 790 clock-names = "fck"; 791 status = "disabled"; 792 }; 793 794 ecap1: pwm@23110000 { 795 compatible = "ti,am3352-ecap"; 796 #pwm-cells = <3>; 797 reg = <0x00 0x23110000 0x00 0x100>; 798 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 799 clocks = <&k3_clks 52 0>; 800 clock-names = "fck"; 801 status = "disabled"; 802 }; 803 804 ecap2: pwm@23120000 { 805 compatible = "ti,am3352-ecap"; 806 #pwm-cells = <3>; 807 reg = <0x00 0x23120000 0x00 0x100>; 808 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 809 clocks = <&k3_clks 53 0>; 810 clock-names = "fck"; 811 status = "disabled"; 812 }; 813 814 main_mcan0: can@20701000 { 815 compatible = "bosch,m_can"; 816 reg = <0x00 0x20701000 0x00 0x200>, 817 <0x00 0x20708000 0x00 0x8000>; 818 reg-names = "m_can", "message_ram"; 819 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 820 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 821 clock-names = "hclk", "cclk"; 822 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 824 interrupt-names = "int0", "int1"; 825 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 826 status = "disabled"; 827 }; 828 829 main_rti0: watchdog@e000000 { 830 compatible = "ti,j7-rti-wdt"; 831 reg = <0x00 0x0e000000 0x00 0x100>; 832 clocks = <&k3_clks 125 0>; 833 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 834 assigned-clocks = <&k3_clks 125 0>; 835 assigned-clock-parents = <&k3_clks 125 2>; 836 }; 837 838 main_rti1: watchdog@e010000 { 839 compatible = "ti,j7-rti-wdt"; 840 reg = <0x00 0x0e010000 0x00 0x100>; 841 clocks = <&k3_clks 126 0>; 842 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 843 assigned-clocks = <&k3_clks 126 0>; 844 assigned-clock-parents = <&k3_clks 126 2>; 845 }; 846 847 main_rti2: watchdog@e020000 { 848 compatible = "ti,j7-rti-wdt"; 849 reg = <0x00 0x0e020000 0x00 0x100>; 850 clocks = <&k3_clks 127 0>; 851 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 852 assigned-clocks = <&k3_clks 127 0>; 853 assigned-clock-parents = <&k3_clks 127 2>; 854 }; 855 856 main_rti3: watchdog@e030000 { 857 compatible = "ti,j7-rti-wdt"; 858 reg = <0x00 0x0e030000 0x00 0x100>; 859 clocks = <&k3_clks 128 0>; 860 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 861 assigned-clocks = <&k3_clks 128 0>; 862 assigned-clock-parents = <&k3_clks 128 2>; 863 }; 864 865 main_rti15: watchdog@e0f0000 { 866 compatible = "ti,j7-rti-wdt"; 867 reg = <0x00 0x0e0f0000 0x00 0x100>; 868 clocks = <&k3_clks 130 0>; 869 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; 870 assigned-clocks = <&k3_clks 130 0>; 871 assigned-clock-parents = <&k3_clks 130 2>; 872 }; 873 874 epwm0: pwm@23000000 { 875 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 876 #pwm-cells = <3>; 877 reg = <0x00 0x23000000 0x00 0x100>; 878 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 879 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 880 clock-names = "tbclk", "fck"; 881 status = "disabled"; 882 }; 883 884 epwm1: pwm@23010000 { 885 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 886 #pwm-cells = <3>; 887 reg = <0x00 0x23010000 0x00 0x100>; 888 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 889 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 890 clock-names = "tbclk", "fck"; 891 status = "disabled"; 892 }; 893 894 epwm2: pwm@23020000 { 895 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 896 #pwm-cells = <3>; 897 reg = <0x00 0x23020000 0x00 0x100>; 898 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 899 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 900 clock-names = "tbclk", "fck"; 901 status = "disabled"; 902 }; 903 904 mcasp0: audio-controller@2b00000 { 905 compatible = "ti,am33xx-mcasp-audio"; 906 reg = <0x00 0x02b00000 0x00 0x2000>, 907 <0x00 0x02b08000 0x00 0x400>; 908 reg-names = "mpu", "dat"; 909 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 911 interrupt-names = "tx", "rx"; 912 913 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 914 dma-names = "tx", "rx"; 915 916 clocks = <&k3_clks 190 0>; 917 clock-names = "fck"; 918 assigned-clocks = <&k3_clks 190 0>; 919 assigned-clock-parents = <&k3_clks 190 2>; 920 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 921 status = "disabled"; 922 }; 923 924 mcasp1: audio-controller@2b10000 { 925 compatible = "ti,am33xx-mcasp-audio"; 926 reg = <0x00 0x02b10000 0x00 0x2000>, 927 <0x00 0x02b18000 0x00 0x400>; 928 reg-names = "mpu", "dat"; 929 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 931 interrupt-names = "tx", "rx"; 932 933 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 934 dma-names = "tx", "rx"; 935 936 clocks = <&k3_clks 191 0>; 937 clock-names = "fck"; 938 assigned-clocks = <&k3_clks 191 0>; 939 assigned-clock-parents = <&k3_clks 191 2>; 940 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 941 status = "disabled"; 942 }; 943 944 mcasp2: audio-controller@2b20000 { 945 compatible = "ti,am33xx-mcasp-audio"; 946 reg = <0x00 0x02b20000 0x00 0x2000>, 947 <0x00 0x02b28000 0x00 0x400>; 948 reg-names = "mpu", "dat"; 949 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 951 interrupt-names = "tx", "rx"; 952 953 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 954 dma-names = "tx", "rx"; 955 956 clocks = <&k3_clks 192 0>; 957 clock-names = "fck"; 958 assigned-clocks = <&k3_clks 192 0>; 959 assigned-clock-parents = <&k3_clks 192 2>; 960 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 961 status = "disabled"; 962 }; 963}; 964