1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2M SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a09g011-cpg.h> 10 11/ { 12 compatible = "renesas,r9a09g011"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 17 extal_clk: extal { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 /* This value must be overridden by the board */ 21 clock-frequency = <0>; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu-map { 29 cluster0 { 30 core0 { 31 cpu = <&cpu0>; 32 }; 33 }; 34 }; 35 36 cpu0: cpu@0 { 37 compatible = "arm,cortex-a53"; 38 reg = <0>; 39 device_type = "cpu"; 40 next-level-cache = <&L2_CA53>; 41 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>; 42 }; 43 44 L2_CA53: cache-controller-0 { 45 compatible = "cache"; 46 cache-unified; 47 cache-level = <2>; 48 }; 49 }; 50 51 soc: soc { 52 compatible = "simple-bus"; 53 interrupt-parent = <&gic>; 54 #address-cells = <2>; 55 #size-cells = <2>; 56 ranges; 57 58 gic: interrupt-controller@82010000 { 59 compatible = "arm,gic-400"; 60 #interrupt-cells = <3>; 61 #address-cells = <0>; 62 interrupt-controller; 63 reg = <0x0 0x82010000 0 0x1000>, 64 <0x0 0x82020000 0 0x20000>, 65 <0x0 0x82040000 0 0x20000>, 66 <0x0 0x82060000 0 0x20000>; 67 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 68 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>; 69 clock-names = "clk"; 70 }; 71 72 avb: ethernet@a3300000 { 73 compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m"; 74 reg = <0 0xa3300000 0 0x800>; 75 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */ 76 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */ 77 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */ 94 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */ 95 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* DiA */ 98 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */ 99 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */ 100 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */ 101 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */ 102 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */ 103 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* Line3 MAC */ 104 interrupt-names = "ch0", "ch1", "ch2", "ch3", 105 "ch4", "ch5", "ch6", "ch7", 106 "ch8", "ch9", "ch10", "ch11", 107 "ch12", "ch13", "ch14", "ch15", 108 "ch16", "ch17", "ch18", "ch19", 109 "ch20", "ch21", "dia", "dib", 110 "err_a", "err_b", "mgmt_a", "mgmt_b", 111 "line3"; 112 clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>, 113 <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>, 114 <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>; 115 clock-names = "axi", "chi", "gptp"; 116 resets = <&cpg R9A09G011_ETH0_RST_HW_N>; 117 power-domains = <&cpg>; 118 #address-cells = <1>; 119 #size-cells = <0>; 120 status = "disable"; 121 }; 122 123 cpg: clock-controller@a3500000 { 124 compatible = "renesas,r9a09g011-cpg"; 125 reg = <0 0xa3500000 0 0x1000>; 126 clocks = <&extal_clk>; 127 clock-names = "extal"; 128 #clock-cells = <2>; 129 #reset-cells = <1>; 130 #power-domain-cells = <0>; 131 }; 132 133 i2c0: i2c@a4030000 { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c"; 137 reg = <0 0xa4030000 0 0x80>; 138 interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>, 139 <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 140 interrupt-names = "tia", "tis"; 141 clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>; 142 resets = <&cpg R9A09G011_IIC_GPA_PRESETN>; 143 power-domains = <&cpg>; 144 status = "disabled"; 145 }; 146 147 i2c2: i2c@a4030100 { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c"; 151 reg = <0 0xa4030100 0 0x80>; 152 interrupts = <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>, 153 <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>; 154 interrupt-names = "tia", "tis"; 155 clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK1>; 156 resets = <&cpg R9A09G011_IIC_GPB_PRESETN>; 157 power-domains = <&cpg>; 158 status = "disabled"; 159 }; 160 161 uart0: serial@a4040000 { 162 compatible = "renesas,r9a09g011-uart", "renesas,em-uart"; 163 reg = <0 0xa4040000 0 0x80>; 164 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>, 166 <&cpg CPG_MOD R9A09G011_URT_PCLK>; 167 clock-names = "sclk", "pclk"; 168 status = "disabled"; 169 }; 170 171 wdt0: watchdog@a4050000 { 172 compatible = "renesas,r9a09g011-wdt", 173 "renesas,rzv2m-wdt"; 174 reg = <0 0xa4050000 0 0x80>; 175 clocks = <&cpg CPG_MOD R9A09G011_WDT0_PCLK>, 176 <&cpg CPG_MOD R9A09G011_WDT0_CLK>; 177 clock-names = "pclk", "oscclk"; 178 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 179 resets = <&cpg R9A09G011_WDT0_PRESETN>; 180 power-domains = <&cpg>; 181 status = "disabled"; 182 }; 183 184 pinctrl: pinctrl@b6250000 { 185 compatible = "renesas,r9a09g011-pinctrl"; 186 reg = <0 0xb6250000 0 0x800>; 187 gpio-controller; 188 #gpio-cells = <2>; 189 gpio-ranges = <&pinctrl 0 0 352>; 190 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>; 230 power-domains = <&cpg>; 231 resets = <&cpg R9A09G011_PFC_PRESETN>; 232 }; 233 }; 234 235 timer { 236 compatible = "arm,armv8-timer"; 237 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 238 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 239 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 240 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 241 }; 242}; 243