1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2M SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a09g011-cpg.h> 10 11/ { 12 compatible = "renesas,r9a09g011"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 17 extal_clk: extal { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 /* This value must be overridden by the board */ 21 clock-frequency = <0>; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu-map { 29 cluster0 { 30 core0 { 31 cpu = <&cpu0>; 32 }; 33 }; 34 }; 35 36 cpu0: cpu@0 { 37 compatible = "arm,cortex-a53"; 38 reg = <0>; 39 device_type = "cpu"; 40 next-level-cache = <&L2_CA53>; 41 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>; 42 }; 43 44 L2_CA53: cache-controller-0 { 45 compatible = "cache"; 46 cache-unified; 47 cache-level = <2>; 48 }; 49 }; 50 51 soc: soc { 52 compatible = "simple-bus"; 53 interrupt-parent = <&gic>; 54 #address-cells = <2>; 55 #size-cells = <2>; 56 ranges; 57 58 gic: interrupt-controller@82010000 { 59 compatible = "arm,gic-400"; 60 #interrupt-cells = <3>; 61 #address-cells = <0>; 62 interrupt-controller; 63 reg = <0x0 0x82010000 0 0x1000>, 64 <0x0 0x82020000 0 0x20000>, 65 <0x0 0x82040000 0 0x20000>, 66 <0x0 0x82060000 0 0x20000>; 67 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 68 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>; 69 clock-names = "clk"; 70 }; 71 72 sdhi0: mmc@85000000 { 73 compatible = "renesas,sdhi-r9a09g011", 74 "renesas,rcar-gen3-sdhi"; 75 reg = <0x0 0x85000000 0 0x2000>; 76 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>, 79 <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>, 80 <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>, 81 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>; 82 clock-names = "core", "clkh", "cd", "aclk"; 83 resets = <&cpg R9A09G011_SDI0_IXRST>; 84 power-domains = <&cpg>; 85 status = "disabled"; 86 }; 87 88 sdhi1: mmc@85010000 { 89 compatible = "renesas,sdhi-r9a09g011", 90 "renesas,rcar-gen3-sdhi"; 91 reg = <0x0 0x85010000 0 0x2000>; 92 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 94 clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>, 95 <&cpg CPG_MOD R9A09G011_SDI1_CLK_HS>, 96 <&cpg CPG_MOD R9A09G011_SDI1_IMCLK2>, 97 <&cpg CPG_MOD R9A09G011_SDI1_ACLK>; 98 clock-names = "core", "clkh", "cd", "aclk"; 99 resets = <&cpg R9A09G011_SDI1_IXRST>; 100 power-domains = <&cpg>; 101 status = "disabled"; 102 }; 103 104 emmc: mmc@85020000 { 105 compatible = "renesas,sdhi-r9a09g011", 106 "renesas,rcar-gen3-sdhi"; 107 reg = <0x0 0x85020000 0 0x2000>; 108 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&cpg CPG_MOD R9A09G011_EMM_IMCLK>, 111 <&cpg CPG_MOD R9A09G011_EMM_CLK_HS>, 112 <&cpg CPG_MOD R9A09G011_EMM_IMCLK2>, 113 <&cpg CPG_MOD R9A09G011_EMM_ACLK>; 114 clock-names = "core", "clkh", "cd", "aclk"; 115 resets = <&cpg R9A09G011_EMM_IXRST>; 116 power-domains = <&cpg>; 117 status = "disabled"; 118 }; 119 120 avb: ethernet@a3300000 { 121 compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m"; 122 reg = <0 0xa3300000 0 0x800>; 123 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */ 124 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */ 125 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */ 142 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */ 143 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* DiA */ 146 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */ 147 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */ 148 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */ 149 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */ 150 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */ 151 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* Line3 MAC */ 152 interrupt-names = "ch0", "ch1", "ch2", "ch3", 153 "ch4", "ch5", "ch6", "ch7", 154 "ch8", "ch9", "ch10", "ch11", 155 "ch12", "ch13", "ch14", "ch15", 156 "ch16", "ch17", "ch18", "ch19", 157 "ch20", "ch21", "dia", "dib", 158 "err_a", "err_b", "mgmt_a", "mgmt_b", 159 "line3"; 160 clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>, 161 <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>, 162 <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>; 163 clock-names = "axi", "chi", "gptp"; 164 resets = <&cpg R9A09G011_ETH0_RST_HW_N>; 165 power-domains = <&cpg>; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 status = "disabled"; 169 }; 170 171 cpg: clock-controller@a3500000 { 172 compatible = "renesas,r9a09g011-cpg"; 173 reg = <0 0xa3500000 0 0x1000>; 174 clocks = <&extal_clk>; 175 clock-names = "extal"; 176 #clock-cells = <2>; 177 #reset-cells = <1>; 178 #power-domain-cells = <0>; 179 }; 180 181 sys: system-controller@a3f03000 { 182 compatible = "renesas,r9a09g011-sys"; 183 reg = <0 0xa3f03000 0 0x400>; 184 }; 185 186 i2c0: i2c@a4030000 { 187 #address-cells = <1>; 188 #size-cells = <0>; 189 compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c"; 190 reg = <0 0xa4030000 0 0x80>; 191 interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>, 192 <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 193 interrupt-names = "tia", "tis"; 194 clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>; 195 resets = <&cpg R9A09G011_IIC_GPA_PRESETN>; 196 power-domains = <&cpg>; 197 status = "disabled"; 198 }; 199 200 i2c2: i2c@a4030100 { 201 #address-cells = <1>; 202 #size-cells = <0>; 203 compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c"; 204 reg = <0 0xa4030100 0 0x80>; 205 interrupts = <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>, 206 <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>; 207 interrupt-names = "tia", "tis"; 208 clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK1>; 209 resets = <&cpg R9A09G011_IIC_GPB_PRESETN>; 210 power-domains = <&cpg>; 211 status = "disabled"; 212 }; 213 214 uart0: serial@a4040000 { 215 compatible = "renesas,r9a09g011-uart", "renesas,em-uart"; 216 reg = <0 0xa4040000 0 0x80>; 217 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>, 219 <&cpg CPG_MOD R9A09G011_URT_PCLK>; 220 clock-names = "sclk", "pclk"; 221 status = "disabled"; 222 }; 223 224 wdt0: watchdog@a4050000 { 225 compatible = "renesas,r9a09g011-wdt", 226 "renesas,rzv2m-wdt"; 227 reg = <0 0xa4050000 0 0x80>; 228 clocks = <&cpg CPG_MOD R9A09G011_WDT0_PCLK>, 229 <&cpg CPG_MOD R9A09G011_WDT0_CLK>; 230 clock-names = "pclk", "oscclk"; 231 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 232 resets = <&cpg R9A09G011_WDT0_PRESETN>; 233 power-domains = <&cpg>; 234 status = "disabled"; 235 }; 236 237 pinctrl: pinctrl@b6250000 { 238 compatible = "renesas,r9a09g011-pinctrl"; 239 reg = <0 0xb6250000 0 0x800>; 240 gpio-controller; 241 #gpio-cells = <2>; 242 gpio-ranges = <&pinctrl 0 0 352>; 243 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>; 283 power-domains = <&cpg>; 284 resets = <&cpg R9A09G011_PFC_PRESETN>; 285 }; 286 }; 287 288 timer { 289 compatible = "arm,armv8-timer"; 290 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 291 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 292 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 293 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 294 }; 295}; 296