1ad1bd2bfSPhil Edworthy// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2ad1bd2bfSPhil Edworthy/*
3ad1bd2bfSPhil Edworthy * Device Tree Source for the RZ/V2M (r9a09g011) Evaluation Kit Board
4ad1bd2bfSPhil Edworthy *
5ad1bd2bfSPhil Edworthy * Copyright (C) 2022 Renesas Electronics Corp.
6ad1bd2bfSPhil Edworthy */
7ad1bd2bfSPhil Edworthy
8ad1bd2bfSPhil Edworthy/dts-v1/;
9ad1bd2bfSPhil Edworthy#include "r9a09g011.dtsi"
10ad1bd2bfSPhil Edworthy
11ad1bd2bfSPhil Edworthy/ {
12ad1bd2bfSPhil Edworthy	model = "RZ/V2M Evaluation Kit 2.0";
13ad1bd2bfSPhil Edworthy	compatible = "renesas,rzv2mevk2", "renesas,r9a09g011";
14ad1bd2bfSPhil Edworthy
15ad1bd2bfSPhil Edworthy	aliases {
16ad1bd2bfSPhil Edworthy		serial0 = &uart0;
17*dc242571SPhil Edworthy		ethernet0 = &avb;
18ad1bd2bfSPhil Edworthy	};
19ad1bd2bfSPhil Edworthy
20ad1bd2bfSPhil Edworthy	chosen {
21ad1bd2bfSPhil Edworthy		stdout-path = "serial0:115200n8";
22ad1bd2bfSPhil Edworthy	};
23ad1bd2bfSPhil Edworthy
24ad1bd2bfSPhil Edworthy	memory@58000000 {
25ad1bd2bfSPhil Edworthy		device_type = "memory";
26ad1bd2bfSPhil Edworthy		/*
27ad1bd2bfSPhil Edworthy		 * first 1.25GiB is reserved for ISP Firmware,
28ad1bd2bfSPhil Edworthy		 * next 128MiB is reserved for secure area.
29ad1bd2bfSPhil Edworthy		 */
30ad1bd2bfSPhil Edworthy		reg = <0x0 0x58000000 0x0 0x28000000>;
31ad1bd2bfSPhil Edworthy	};
32ad1bd2bfSPhil Edworthy
33ad1bd2bfSPhil Edworthy	memory@180000000 {
34ad1bd2bfSPhil Edworthy		device_type = "memory";
35ad1bd2bfSPhil Edworthy		reg = <0x1 0x80000000 0x0 0x80000000>;
36ad1bd2bfSPhil Edworthy	};
37ad1bd2bfSPhil Edworthy};
38ad1bd2bfSPhil Edworthy
39*dc242571SPhil Edworthy&avb {
40*dc242571SPhil Edworthy	renesas,no-ether-link;
41*dc242571SPhil Edworthy	phy-handle = <&phy0>;
42*dc242571SPhil Edworthy	phy-mode = "gmii";
43*dc242571SPhil Edworthy	status = "okay";
44*dc242571SPhil Edworthy
45*dc242571SPhil Edworthy	phy0: ethernet-phy@0 {
46*dc242571SPhil Edworthy		compatible = "ethernet-phy-id001c.c916",
47*dc242571SPhil Edworthy			     "ethernet-phy-ieee802.3-c22";
48*dc242571SPhil Edworthy		reg = <0>;
49*dc242571SPhil Edworthy	};
50*dc242571SPhil Edworthy};
51*dc242571SPhil Edworthy
52ad1bd2bfSPhil Edworthy&extal_clk {
53ad1bd2bfSPhil Edworthy	clock-frequency = <48000000>;
54ad1bd2bfSPhil Edworthy};
55ad1bd2bfSPhil Edworthy
56ad1bd2bfSPhil Edworthy&uart0 {
57ad1bd2bfSPhil Edworthy	status = "okay";
58ad1bd2bfSPhil Edworthy};
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