1ad1bd2bfSPhil Edworthy// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2ad1bd2bfSPhil Edworthy/* 3ad1bd2bfSPhil Edworthy * Device Tree Source for the RZ/V2M (r9a09g011) Evaluation Kit Board 4ad1bd2bfSPhil Edworthy * 5ad1bd2bfSPhil Edworthy * Copyright (C) 2022 Renesas Electronics Corp. 6ad1bd2bfSPhil Edworthy */ 7ad1bd2bfSPhil Edworthy 8ad1bd2bfSPhil Edworthy/dts-v1/; 9ad1bd2bfSPhil Edworthy#include "r9a09g011.dtsi" 10*39ffd330SPhil Edworthy#include <dt-bindings/pinctrl/rzv2m-pinctrl.h> 11ad1bd2bfSPhil Edworthy 12ad1bd2bfSPhil Edworthy/ { 13ad1bd2bfSPhil Edworthy model = "RZ/V2M Evaluation Kit 2.0"; 14ad1bd2bfSPhil Edworthy compatible = "renesas,rzv2mevk2", "renesas,r9a09g011"; 15ad1bd2bfSPhil Edworthy 16ad1bd2bfSPhil Edworthy aliases { 17ad1bd2bfSPhil Edworthy serial0 = &uart0; 18dc242571SPhil Edworthy ethernet0 = &avb; 19ad1bd2bfSPhil Edworthy }; 20ad1bd2bfSPhil Edworthy 21ad1bd2bfSPhil Edworthy chosen { 22ad1bd2bfSPhil Edworthy stdout-path = "serial0:115200n8"; 23ad1bd2bfSPhil Edworthy }; 24ad1bd2bfSPhil Edworthy 25ad1bd2bfSPhil Edworthy memory@58000000 { 26ad1bd2bfSPhil Edworthy device_type = "memory"; 27ad1bd2bfSPhil Edworthy /* 28ad1bd2bfSPhil Edworthy * first 1.25GiB is reserved for ISP Firmware, 29ad1bd2bfSPhil Edworthy * next 128MiB is reserved for secure area. 30ad1bd2bfSPhil Edworthy */ 31ad1bd2bfSPhil Edworthy reg = <0x0 0x58000000 0x0 0x28000000>; 32ad1bd2bfSPhil Edworthy }; 33ad1bd2bfSPhil Edworthy 34ad1bd2bfSPhil Edworthy memory@180000000 { 35ad1bd2bfSPhil Edworthy device_type = "memory"; 36ad1bd2bfSPhil Edworthy reg = <0x1 0x80000000 0x0 0x80000000>; 37ad1bd2bfSPhil Edworthy }; 38ad1bd2bfSPhil Edworthy}; 39ad1bd2bfSPhil Edworthy 40dc242571SPhil Edworthy&avb { 41dc242571SPhil Edworthy renesas,no-ether-link; 42dc242571SPhil Edworthy phy-handle = <&phy0>; 43dc242571SPhil Edworthy phy-mode = "gmii"; 44dc242571SPhil Edworthy status = "okay"; 45dc242571SPhil Edworthy 46dc242571SPhil Edworthy phy0: ethernet-phy@0 { 47dc242571SPhil Edworthy compatible = "ethernet-phy-id001c.c916", 48dc242571SPhil Edworthy "ethernet-phy-ieee802.3-c22"; 49dc242571SPhil Edworthy reg = <0>; 50dc242571SPhil Edworthy }; 51dc242571SPhil Edworthy}; 52dc242571SPhil Edworthy 53ad1bd2bfSPhil Edworthy&extal_clk { 54ad1bd2bfSPhil Edworthy clock-frequency = <48000000>; 55ad1bd2bfSPhil Edworthy}; 56ad1bd2bfSPhil Edworthy 57*39ffd330SPhil Edworthy&i2c0 { 58*39ffd330SPhil Edworthy pinctrl-0 = <&i2c0_pins>; 59*39ffd330SPhil Edworthy pinctrl-names = "default"; 60*39ffd330SPhil Edworthy clock-frequency = <400000>; 61*39ffd330SPhil Edworthy status = "okay"; 62*39ffd330SPhil Edworthy}; 63*39ffd330SPhil Edworthy 64*39ffd330SPhil Edworthy&i2c2 { 65*39ffd330SPhil Edworthy pinctrl-0 = <&i2c2_pins>; 66*39ffd330SPhil Edworthy pinctrl-names = "default"; 67*39ffd330SPhil Edworthy clock-frequency = <100000>; 68*39ffd330SPhil Edworthy status = "okay"; 69*39ffd330SPhil Edworthy}; 70*39ffd330SPhil Edworthy 71*39ffd330SPhil Edworthy&pinctrl { 72*39ffd330SPhil Edworthy i2c0_pins: i2c0 { 73*39ffd330SPhil Edworthy pinmux = <RZV2M_PORT_PINMUX(5, 0, 2)>, /* SDA */ 74*39ffd330SPhil Edworthy <RZV2M_PORT_PINMUX(5, 1, 2)>; /* SCL */ 75*39ffd330SPhil Edworthy }; 76*39ffd330SPhil Edworthy 77*39ffd330SPhil Edworthy i2c2_pins: i2c2 { 78*39ffd330SPhil Edworthy pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */ 79*39ffd330SPhil Edworthy <RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */ 80*39ffd330SPhil Edworthy }; 81*39ffd330SPhil Edworthy}; 82*39ffd330SPhil Edworthy 83ad1bd2bfSPhil Edworthy&uart0 { 84ad1bd2bfSPhil Edworthy status = "okay"; 85ad1bd2bfSPhil Edworthy}; 86