1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 }; 90 91 ethernet@2490000 { 92 compatible = "nvidia,tegra194-eqos", 93 "nvidia,tegra186-eqos", 94 "snps,dwc-qos-ethernet-4.10"; 95 reg = <0x02490000 0x10000>; 96 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 98 <&bpmp TEGRA194_CLK_EQOS_AXI>, 99 <&bpmp TEGRA194_CLK_EQOS_RX>, 100 <&bpmp TEGRA194_CLK_EQOS_TX>, 101 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 102 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 103 resets = <&bpmp TEGRA194_RESET_EQOS>; 104 reset-names = "eqos"; 105 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 106 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 107 interconnect-names = "dma-mem", "write"; 108 iommus = <&smmu TEGRA194_SID_EQOS>; 109 status = "disabled"; 110 111 snps,write-requests = <1>; 112 snps,read-requests = <3>; 113 snps,burst-map = <0x7>; 114 snps,txpbl = <16>; 115 snps,rxpbl = <8>; 116 }; 117 118 aconnect@2900000 { 119 compatible = "nvidia,tegra194-aconnect", 120 "nvidia,tegra210-aconnect"; 121 clocks = <&bpmp TEGRA194_CLK_APE>, 122 <&bpmp TEGRA194_CLK_APB2APE>; 123 clock-names = "ape", "apb2ape"; 124 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges = <0x02900000 0x02900000 0x200000>; 128 status = "disabled"; 129 130 adma: dma-controller@2930000 { 131 compatible = "nvidia,tegra194-adma", 132 "nvidia,tegra186-adma"; 133 reg = <0x02930000 0x20000>; 134 interrupt-parent = <&agic>; 135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 167 #dma-cells = <1>; 168 clocks = <&bpmp TEGRA194_CLK_AHUB>; 169 clock-names = "d_audio"; 170 status = "disabled"; 171 }; 172 173 agic: interrupt-controller@2a40000 { 174 compatible = "nvidia,tegra194-agic", 175 "nvidia,tegra210-agic"; 176 #interrupt-cells = <3>; 177 interrupt-controller; 178 reg = <0x02a41000 0x1000>, 179 <0x02a42000 0x2000>; 180 interrupts = <GIC_SPI 145 181 (GIC_CPU_MASK_SIMPLE(4) | 182 IRQ_TYPE_LEVEL_HIGH)>; 183 clocks = <&bpmp TEGRA194_CLK_APE>; 184 clock-names = "clk"; 185 status = "disabled"; 186 }; 187 188 tegra_ahub: ahub@2900800 { 189 compatible = "nvidia,tegra194-ahub", 190 "nvidia,tegra186-ahub"; 191 reg = <0x02900800 0x800>; 192 clocks = <&bpmp TEGRA194_CLK_AHUB>; 193 clock-names = "ahub"; 194 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 195 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 ranges = <0x02900800 0x02900800 0x11800>; 199 status = "disabled"; 200 201 tegra_admaif: admaif@290f000 { 202 compatible = "nvidia,tegra194-admaif", 203 "nvidia,tegra186-admaif"; 204 reg = <0x0290f000 0x1000>; 205 dmas = <&adma 1>, <&adma 1>, 206 <&adma 2>, <&adma 2>, 207 <&adma 3>, <&adma 3>, 208 <&adma 4>, <&adma 4>, 209 <&adma 5>, <&adma 5>, 210 <&adma 6>, <&adma 6>, 211 <&adma 7>, <&adma 7>, 212 <&adma 8>, <&adma 8>, 213 <&adma 9>, <&adma 9>, 214 <&adma 10>, <&adma 10>, 215 <&adma 11>, <&adma 11>, 216 <&adma 12>, <&adma 12>, 217 <&adma 13>, <&adma 13>, 218 <&adma 14>, <&adma 14>, 219 <&adma 15>, <&adma 15>, 220 <&adma 16>, <&adma 16>, 221 <&adma 17>, <&adma 17>, 222 <&adma 18>, <&adma 18>, 223 <&adma 19>, <&adma 19>, 224 <&adma 20>, <&adma 20>; 225 dma-names = "rx1", "tx1", 226 "rx2", "tx2", 227 "rx3", "tx3", 228 "rx4", "tx4", 229 "rx5", "tx5", 230 "rx6", "tx6", 231 "rx7", "tx7", 232 "rx8", "tx8", 233 "rx9", "tx9", 234 "rx10", "tx10", 235 "rx11", "tx11", 236 "rx12", "tx12", 237 "rx13", "tx13", 238 "rx14", "tx14", 239 "rx15", "tx15", 240 "rx16", "tx16", 241 "rx17", "tx17", 242 "rx18", "tx18", 243 "rx19", "tx19", 244 "rx20", "tx20"; 245 status = "disabled"; 246 }; 247 248 tegra_i2s1: i2s@2901000 { 249 compatible = "nvidia,tegra194-i2s", 250 "nvidia,tegra210-i2s"; 251 reg = <0x2901000 0x100>; 252 clocks = <&bpmp TEGRA194_CLK_I2S1>, 253 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 254 clock-names = "i2s", "sync_input"; 255 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 256 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 257 assigned-clock-rates = <1536000>; 258 sound-name-prefix = "I2S1"; 259 status = "disabled"; 260 }; 261 262 tegra_i2s2: i2s@2901100 { 263 compatible = "nvidia,tegra194-i2s", 264 "nvidia,tegra210-i2s"; 265 reg = <0x2901100 0x100>; 266 clocks = <&bpmp TEGRA194_CLK_I2S2>, 267 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 268 clock-names = "i2s", "sync_input"; 269 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 270 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 271 assigned-clock-rates = <1536000>; 272 sound-name-prefix = "I2S2"; 273 status = "disabled"; 274 }; 275 276 tegra_i2s3: i2s@2901200 { 277 compatible = "nvidia,tegra194-i2s", 278 "nvidia,tegra210-i2s"; 279 reg = <0x2901200 0x100>; 280 clocks = <&bpmp TEGRA194_CLK_I2S3>, 281 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 282 clock-names = "i2s", "sync_input"; 283 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 284 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 285 assigned-clock-rates = <1536000>; 286 sound-name-prefix = "I2S3"; 287 status = "disabled"; 288 }; 289 290 tegra_i2s4: i2s@2901300 { 291 compatible = "nvidia,tegra194-i2s", 292 "nvidia,tegra210-i2s"; 293 reg = <0x2901300 0x100>; 294 clocks = <&bpmp TEGRA194_CLK_I2S4>, 295 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 296 clock-names = "i2s", "sync_input"; 297 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 298 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 299 assigned-clock-rates = <1536000>; 300 sound-name-prefix = "I2S4"; 301 status = "disabled"; 302 }; 303 304 tegra_i2s5: i2s@2901400 { 305 compatible = "nvidia,tegra194-i2s", 306 "nvidia,tegra210-i2s"; 307 reg = <0x2901400 0x100>; 308 clocks = <&bpmp TEGRA194_CLK_I2S5>, 309 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 310 clock-names = "i2s", "sync_input"; 311 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 312 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 313 assigned-clock-rates = <1536000>; 314 sound-name-prefix = "I2S5"; 315 status = "disabled"; 316 }; 317 318 tegra_i2s6: i2s@2901500 { 319 compatible = "nvidia,tegra194-i2s", 320 "nvidia,tegra210-i2s"; 321 reg = <0x2901500 0x100>; 322 clocks = <&bpmp TEGRA194_CLK_I2S6>, 323 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 324 clock-names = "i2s", "sync_input"; 325 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 326 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 327 assigned-clock-rates = <1536000>; 328 sound-name-prefix = "I2S6"; 329 status = "disabled"; 330 }; 331 332 tegra_dmic1: dmic@2904000 { 333 compatible = "nvidia,tegra194-dmic", 334 "nvidia,tegra210-dmic"; 335 reg = <0x2904000 0x100>; 336 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 337 clock-names = "dmic"; 338 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 339 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 340 assigned-clock-rates = <3072000>; 341 sound-name-prefix = "DMIC1"; 342 status = "disabled"; 343 }; 344 345 tegra_dmic2: dmic@2904100 { 346 compatible = "nvidia,tegra194-dmic", 347 "nvidia,tegra210-dmic"; 348 reg = <0x2904100 0x100>; 349 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 350 clock-names = "dmic"; 351 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 352 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 353 assigned-clock-rates = <3072000>; 354 sound-name-prefix = "DMIC2"; 355 status = "disabled"; 356 }; 357 358 tegra_dmic3: dmic@2904200 { 359 compatible = "nvidia,tegra194-dmic", 360 "nvidia,tegra210-dmic"; 361 reg = <0x2904200 0x100>; 362 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 363 clock-names = "dmic"; 364 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 365 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 366 assigned-clock-rates = <3072000>; 367 sound-name-prefix = "DMIC3"; 368 status = "disabled"; 369 }; 370 371 tegra_dmic4: dmic@2904300 { 372 compatible = "nvidia,tegra194-dmic", 373 "nvidia,tegra210-dmic"; 374 reg = <0x2904300 0x100>; 375 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 376 clock-names = "dmic"; 377 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 378 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 379 assigned-clock-rates = <3072000>; 380 sound-name-prefix = "DMIC4"; 381 status = "disabled"; 382 }; 383 384 tegra_dspk1: dspk@2905000 { 385 compatible = "nvidia,tegra194-dspk", 386 "nvidia,tegra186-dspk"; 387 reg = <0x2905000 0x100>; 388 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 389 clock-names = "dspk"; 390 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 391 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 392 assigned-clock-rates = <12288000>; 393 sound-name-prefix = "DSPK1"; 394 status = "disabled"; 395 }; 396 397 tegra_dspk2: dspk@2905100 { 398 compatible = "nvidia,tegra194-dspk", 399 "nvidia,tegra186-dspk"; 400 reg = <0x2905100 0x100>; 401 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 402 clock-names = "dspk"; 403 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 404 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 405 assigned-clock-rates = <12288000>; 406 sound-name-prefix = "DSPK2"; 407 status = "disabled"; 408 }; 409 410 tegra_sfc1: sfc@2902000 { 411 compatible = "nvidia,tegra194-sfc", 412 "nvidia,tegra210-sfc"; 413 reg = <0x2902000 0x200>; 414 sound-name-prefix = "SFC1"; 415 status = "disabled"; 416 }; 417 418 tegra_sfc2: sfc@2902200 { 419 compatible = "nvidia,tegra194-sfc", 420 "nvidia,tegra210-sfc"; 421 reg = <0x2902200 0x200>; 422 sound-name-prefix = "SFC2"; 423 status = "disabled"; 424 }; 425 426 tegra_sfc3: sfc@2902400 { 427 compatible = "nvidia,tegra194-sfc", 428 "nvidia,tegra210-sfc"; 429 reg = <0x2902400 0x200>; 430 sound-name-prefix = "SFC3"; 431 status = "disabled"; 432 }; 433 434 tegra_sfc4: sfc@2902600 { 435 compatible = "nvidia,tegra194-sfc", 436 "nvidia,tegra210-sfc"; 437 reg = <0x2902600 0x200>; 438 sound-name-prefix = "SFC4"; 439 status = "disabled"; 440 }; 441 442 tegra_mvc1: mvc@290a000 { 443 compatible = "nvidia,tegra194-mvc", 444 "nvidia,tegra210-mvc"; 445 reg = <0x290a000 0x200>; 446 sound-name-prefix = "MVC1"; 447 status = "disabled"; 448 }; 449 450 tegra_mvc2: mvc@290a200 { 451 compatible = "nvidia,tegra194-mvc", 452 "nvidia,tegra210-mvc"; 453 reg = <0x290a200 0x200>; 454 sound-name-prefix = "MVC2"; 455 status = "disabled"; 456 }; 457 458 tegra_amx1: amx@2903000 { 459 compatible = "nvidia,tegra194-amx"; 460 reg = <0x2903000 0x100>; 461 sound-name-prefix = "AMX1"; 462 status = "disabled"; 463 }; 464 465 tegra_amx2: amx@2903100 { 466 compatible = "nvidia,tegra194-amx"; 467 reg = <0x2903100 0x100>; 468 sound-name-prefix = "AMX2"; 469 status = "disabled"; 470 }; 471 472 tegra_amx3: amx@2903200 { 473 compatible = "nvidia,tegra194-amx"; 474 reg = <0x2903200 0x100>; 475 sound-name-prefix = "AMX3"; 476 status = "disabled"; 477 }; 478 479 tegra_amx4: amx@2903300 { 480 compatible = "nvidia,tegra194-amx"; 481 reg = <0x2903300 0x100>; 482 sound-name-prefix = "AMX4"; 483 status = "disabled"; 484 }; 485 486 tegra_adx1: adx@2903800 { 487 compatible = "nvidia,tegra194-adx", 488 "nvidia,tegra210-adx"; 489 reg = <0x2903800 0x100>; 490 sound-name-prefix = "ADX1"; 491 status = "disabled"; 492 }; 493 494 tegra_adx2: adx@2903900 { 495 compatible = "nvidia,tegra194-adx", 496 "nvidia,tegra210-adx"; 497 reg = <0x2903900 0x100>; 498 sound-name-prefix = "ADX2"; 499 status = "disabled"; 500 }; 501 502 tegra_adx3: adx@2903a00 { 503 compatible = "nvidia,tegra194-adx", 504 "nvidia,tegra210-adx"; 505 reg = <0x2903a00 0x100>; 506 sound-name-prefix = "ADX3"; 507 status = "disabled"; 508 }; 509 510 tegra_adx4: adx@2903b00 { 511 compatible = "nvidia,tegra194-adx", 512 "nvidia,tegra210-adx"; 513 reg = <0x2903b00 0x100>; 514 sound-name-prefix = "ADX4"; 515 status = "disabled"; 516 }; 517 518 tegra_amixer: amixer@290bb00 { 519 compatible = "nvidia,tegra194-amixer", 520 "nvidia,tegra210-amixer"; 521 reg = <0x290bb00 0x800>; 522 sound-name-prefix = "MIXER1"; 523 status = "disabled"; 524 }; 525 }; 526 }; 527 528 pinmux: pinmux@2430000 { 529 compatible = "nvidia,tegra194-pinmux"; 530 reg = <0x2430000 0x17000>, 531 <0xc300000 0x4000>; 532 533 status = "okay"; 534 535 pex_rst_c5_out_state: pex_rst_c5_out { 536 pex_rst { 537 nvidia,pins = "pex_l5_rst_n_pgg1"; 538 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 539 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 540 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 541 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 542 nvidia,tristate = <TEGRA_PIN_DISABLE>; 543 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 544 }; 545 }; 546 547 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 548 clkreq { 549 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 550 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 551 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 552 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 553 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 554 nvidia,tristate = <TEGRA_PIN_DISABLE>; 555 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 556 }; 557 }; 558 }; 559 560 mc: memory-controller@2c00000 { 561 compatible = "nvidia,tegra194-mc"; 562 reg = <0x02c00000 0x100000>, 563 <0x02b80000 0x040000>, 564 <0x01700000 0x100000>; 565 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 566 #interconnect-cells = <1>; 567 status = "disabled"; 568 569 #address-cells = <2>; 570 #size-cells = <2>; 571 572 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 573 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 574 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 575 576 /* 577 * Bit 39 of addresses passing through the memory 578 * controller selects the XBAR format used when memory 579 * is accessed. This is used to transparently access 580 * memory in the XBAR format used by the discrete GPU 581 * (bit 39 set) or Tegra (bit 39 clear). 582 * 583 * As a consequence, the operating system must ensure 584 * that bit 39 is never used implicitly, for example 585 * via an I/O virtual address mapping of an IOMMU. If 586 * devices require access to the XBAR switch, their 587 * drivers must set this bit explicitly. 588 * 589 * Limit the DMA range for memory clients to [38:0]. 590 */ 591 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 592 593 emc: external-memory-controller@2c60000 { 594 compatible = "nvidia,tegra194-emc"; 595 reg = <0x0 0x02c60000 0x0 0x90000>, 596 <0x0 0x01780000 0x0 0x80000>; 597 clocks = <&bpmp TEGRA194_CLK_EMC>; 598 clock-names = "emc"; 599 600 #interconnect-cells = <0>; 601 602 nvidia,bpmp = <&bpmp>; 603 }; 604 }; 605 606 uarta: serial@3100000 { 607 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 608 reg = <0x03100000 0x40>; 609 reg-shift = <2>; 610 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&bpmp TEGRA194_CLK_UARTA>; 612 clock-names = "serial"; 613 resets = <&bpmp TEGRA194_RESET_UARTA>; 614 reset-names = "serial"; 615 status = "disabled"; 616 }; 617 618 uartb: serial@3110000 { 619 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 620 reg = <0x03110000 0x40>; 621 reg-shift = <2>; 622 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&bpmp TEGRA194_CLK_UARTB>; 624 clock-names = "serial"; 625 resets = <&bpmp TEGRA194_RESET_UARTB>; 626 reset-names = "serial"; 627 status = "disabled"; 628 }; 629 630 uartd: serial@3130000 { 631 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 632 reg = <0x03130000 0x40>; 633 reg-shift = <2>; 634 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&bpmp TEGRA194_CLK_UARTD>; 636 clock-names = "serial"; 637 resets = <&bpmp TEGRA194_RESET_UARTD>; 638 reset-names = "serial"; 639 status = "disabled"; 640 }; 641 642 uarte: serial@3140000 { 643 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 644 reg = <0x03140000 0x40>; 645 reg-shift = <2>; 646 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&bpmp TEGRA194_CLK_UARTE>; 648 clock-names = "serial"; 649 resets = <&bpmp TEGRA194_RESET_UARTE>; 650 reset-names = "serial"; 651 status = "disabled"; 652 }; 653 654 uartf: serial@3150000 { 655 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 656 reg = <0x03150000 0x40>; 657 reg-shift = <2>; 658 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&bpmp TEGRA194_CLK_UARTF>; 660 clock-names = "serial"; 661 resets = <&bpmp TEGRA194_RESET_UARTF>; 662 reset-names = "serial"; 663 status = "disabled"; 664 }; 665 666 gen1_i2c: i2c@3160000 { 667 compatible = "nvidia,tegra194-i2c"; 668 reg = <0x03160000 0x10000>; 669 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 clocks = <&bpmp TEGRA194_CLK_I2C1>; 673 clock-names = "div-clk"; 674 resets = <&bpmp TEGRA194_RESET_I2C1>; 675 reset-names = "i2c"; 676 status = "disabled"; 677 }; 678 679 uarth: serial@3170000 { 680 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 681 reg = <0x03170000 0x40>; 682 reg-shift = <2>; 683 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&bpmp TEGRA194_CLK_UARTH>; 685 clock-names = "serial"; 686 resets = <&bpmp TEGRA194_RESET_UARTH>; 687 reset-names = "serial"; 688 status = "disabled"; 689 }; 690 691 cam_i2c: i2c@3180000 { 692 compatible = "nvidia,tegra194-i2c"; 693 reg = <0x03180000 0x10000>; 694 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 clocks = <&bpmp TEGRA194_CLK_I2C3>; 698 clock-names = "div-clk"; 699 resets = <&bpmp TEGRA194_RESET_I2C3>; 700 reset-names = "i2c"; 701 status = "disabled"; 702 }; 703 704 /* shares pads with dpaux1 */ 705 dp_aux_ch1_i2c: i2c@3190000 { 706 compatible = "nvidia,tegra194-i2c"; 707 reg = <0x03190000 0x10000>; 708 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 clocks = <&bpmp TEGRA194_CLK_I2C4>; 712 clock-names = "div-clk"; 713 resets = <&bpmp TEGRA194_RESET_I2C4>; 714 reset-names = "i2c"; 715 pinctrl-0 = <&state_dpaux1_i2c>; 716 pinctrl-1 = <&state_dpaux1_off>; 717 pinctrl-names = "default", "idle"; 718 status = "disabled"; 719 }; 720 721 /* shares pads with dpaux0 */ 722 dp_aux_ch0_i2c: i2c@31b0000 { 723 compatible = "nvidia,tegra194-i2c"; 724 reg = <0x031b0000 0x10000>; 725 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 726 #address-cells = <1>; 727 #size-cells = <0>; 728 clocks = <&bpmp TEGRA194_CLK_I2C6>; 729 clock-names = "div-clk"; 730 resets = <&bpmp TEGRA194_RESET_I2C6>; 731 reset-names = "i2c"; 732 pinctrl-0 = <&state_dpaux0_i2c>; 733 pinctrl-1 = <&state_dpaux0_off>; 734 pinctrl-names = "default", "idle"; 735 status = "disabled"; 736 }; 737 738 /* shares pads with dpaux2 */ 739 dp_aux_ch2_i2c: i2c@31c0000 { 740 compatible = "nvidia,tegra194-i2c"; 741 reg = <0x031c0000 0x10000>; 742 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 clocks = <&bpmp TEGRA194_CLK_I2C7>; 746 clock-names = "div-clk"; 747 resets = <&bpmp TEGRA194_RESET_I2C7>; 748 reset-names = "i2c"; 749 pinctrl-0 = <&state_dpaux2_i2c>; 750 pinctrl-1 = <&state_dpaux2_off>; 751 pinctrl-names = "default", "idle"; 752 status = "disabled"; 753 }; 754 755 /* shares pads with dpaux3 */ 756 dp_aux_ch3_i2c: i2c@31e0000 { 757 compatible = "nvidia,tegra194-i2c"; 758 reg = <0x031e0000 0x10000>; 759 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 clocks = <&bpmp TEGRA194_CLK_I2C9>; 763 clock-names = "div-clk"; 764 resets = <&bpmp TEGRA194_RESET_I2C9>; 765 reset-names = "i2c"; 766 pinctrl-0 = <&state_dpaux3_i2c>; 767 pinctrl-1 = <&state_dpaux3_off>; 768 pinctrl-names = "default", "idle"; 769 status = "disabled"; 770 }; 771 772 spi@3270000 { 773 compatible = "nvidia,tegra194-qspi"; 774 reg = <0x3270000 0x1000>; 775 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 779 <&bpmp TEGRA194_CLK_QSPI0_PM>; 780 clock-names = "qspi", "qspi_out"; 781 resets = <&bpmp TEGRA194_RESET_QSPI0>; 782 reset-names = "qspi"; 783 status = "disabled"; 784 }; 785 786 spi@3300000 { 787 compatible = "nvidia,tegra194-qspi"; 788 reg = <0x3300000 0x1000>; 789 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 793 <&bpmp TEGRA194_CLK_QSPI1_PM>; 794 clock-names = "qspi", "qspi_out"; 795 resets = <&bpmp TEGRA194_RESET_QSPI1>; 796 reset-names = "qspi"; 797 status = "disabled"; 798 }; 799 800 pwm1: pwm@3280000 { 801 compatible = "nvidia,tegra194-pwm", 802 "nvidia,tegra186-pwm"; 803 reg = <0x3280000 0x10000>; 804 clocks = <&bpmp TEGRA194_CLK_PWM1>; 805 clock-names = "pwm"; 806 resets = <&bpmp TEGRA194_RESET_PWM1>; 807 reset-names = "pwm"; 808 status = "disabled"; 809 #pwm-cells = <2>; 810 }; 811 812 pwm2: pwm@3290000 { 813 compatible = "nvidia,tegra194-pwm", 814 "nvidia,tegra186-pwm"; 815 reg = <0x3290000 0x10000>; 816 clocks = <&bpmp TEGRA194_CLK_PWM2>; 817 clock-names = "pwm"; 818 resets = <&bpmp TEGRA194_RESET_PWM2>; 819 reset-names = "pwm"; 820 status = "disabled"; 821 #pwm-cells = <2>; 822 }; 823 824 pwm3: pwm@32a0000 { 825 compatible = "nvidia,tegra194-pwm", 826 "nvidia,tegra186-pwm"; 827 reg = <0x32a0000 0x10000>; 828 clocks = <&bpmp TEGRA194_CLK_PWM3>; 829 clock-names = "pwm"; 830 resets = <&bpmp TEGRA194_RESET_PWM3>; 831 reset-names = "pwm"; 832 status = "disabled"; 833 #pwm-cells = <2>; 834 }; 835 836 pwm5: pwm@32c0000 { 837 compatible = "nvidia,tegra194-pwm", 838 "nvidia,tegra186-pwm"; 839 reg = <0x32c0000 0x10000>; 840 clocks = <&bpmp TEGRA194_CLK_PWM5>; 841 clock-names = "pwm"; 842 resets = <&bpmp TEGRA194_RESET_PWM5>; 843 reset-names = "pwm"; 844 status = "disabled"; 845 #pwm-cells = <2>; 846 }; 847 848 pwm6: pwm@32d0000 { 849 compatible = "nvidia,tegra194-pwm", 850 "nvidia,tegra186-pwm"; 851 reg = <0x32d0000 0x10000>; 852 clocks = <&bpmp TEGRA194_CLK_PWM6>; 853 clock-names = "pwm"; 854 resets = <&bpmp TEGRA194_RESET_PWM6>; 855 reset-names = "pwm"; 856 status = "disabled"; 857 #pwm-cells = <2>; 858 }; 859 860 pwm7: pwm@32e0000 { 861 compatible = "nvidia,tegra194-pwm", 862 "nvidia,tegra186-pwm"; 863 reg = <0x32e0000 0x10000>; 864 clocks = <&bpmp TEGRA194_CLK_PWM7>; 865 clock-names = "pwm"; 866 resets = <&bpmp TEGRA194_RESET_PWM7>; 867 reset-names = "pwm"; 868 status = "disabled"; 869 #pwm-cells = <2>; 870 }; 871 872 pwm8: pwm@32f0000 { 873 compatible = "nvidia,tegra194-pwm", 874 "nvidia,tegra186-pwm"; 875 reg = <0x32f0000 0x10000>; 876 clocks = <&bpmp TEGRA194_CLK_PWM8>; 877 clock-names = "pwm"; 878 resets = <&bpmp TEGRA194_RESET_PWM8>; 879 reset-names = "pwm"; 880 status = "disabled"; 881 #pwm-cells = <2>; 882 }; 883 884 sdmmc1: mmc@3400000 { 885 compatible = "nvidia,tegra194-sdhci"; 886 reg = <0x03400000 0x10000>; 887 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 889 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 890 clock-names = "sdhci", "tmclk"; 891 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 892 reset-names = "sdhci"; 893 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 894 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 895 interconnect-names = "dma-mem", "write"; 896 iommus = <&smmu TEGRA194_SID_SDMMC1>; 897 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 898 pinctrl-0 = <&sdmmc1_3v3>; 899 pinctrl-1 = <&sdmmc1_1v8>; 900 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 901 <0x07>; 902 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 903 <0x07>; 904 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 905 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 906 <0x07>; 907 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 908 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 909 nvidia,default-tap = <0x9>; 910 nvidia,default-trim = <0x5>; 911 sd-uhs-sdr25; 912 sd-uhs-sdr50; 913 sd-uhs-ddr50; 914 sd-uhs-sdr104; 915 status = "disabled"; 916 }; 917 918 sdmmc3: mmc@3440000 { 919 compatible = "nvidia,tegra194-sdhci"; 920 reg = <0x03440000 0x10000>; 921 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 923 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 924 clock-names = "sdhci", "tmclk"; 925 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 926 reset-names = "sdhci"; 927 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 928 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 929 interconnect-names = "dma-mem", "write"; 930 iommus = <&smmu TEGRA194_SID_SDMMC3>; 931 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 932 pinctrl-0 = <&sdmmc3_3v3>; 933 pinctrl-1 = <&sdmmc3_1v8>; 934 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 935 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 936 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 937 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 938 <0x07>; 939 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 940 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 941 <0x07>; 942 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 943 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 944 nvidia,default-tap = <0x9>; 945 nvidia,default-trim = <0x5>; 946 sd-uhs-sdr25; 947 sd-uhs-sdr50; 948 sd-uhs-ddr50; 949 sd-uhs-sdr104; 950 status = "disabled"; 951 }; 952 953 sdmmc4: mmc@3460000 { 954 compatible = "nvidia,tegra194-sdhci"; 955 reg = <0x03460000 0x10000>; 956 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 958 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 959 clock-names = "sdhci", "tmclk"; 960 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 961 <&bpmp TEGRA194_CLK_PLLC4>; 962 assigned-clock-parents = 963 <&bpmp TEGRA194_CLK_PLLC4>; 964 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 965 reset-names = "sdhci"; 966 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 967 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 968 interconnect-names = "dma-mem", "write"; 969 iommus = <&smmu TEGRA194_SID_SDMMC4>; 970 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 971 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 972 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 973 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 974 <0x0a>; 975 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 976 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 977 <0x0a>; 978 nvidia,default-tap = <0x8>; 979 nvidia,default-trim = <0x14>; 980 nvidia,dqs-trim = <40>; 981 supports-cqe; 982 status = "disabled"; 983 }; 984 985 hda@3510000 { 986 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 987 reg = <0x3510000 0x10000>; 988 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&bpmp TEGRA194_CLK_HDA>, 990 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 991 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 992 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 993 resets = <&bpmp TEGRA194_RESET_HDA>, 994 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>, 995 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>; 996 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 997 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 998 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 999 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1000 interconnect-names = "dma-mem", "write"; 1001 iommus = <&smmu TEGRA194_SID_HDA>; 1002 status = "disabled"; 1003 }; 1004 1005 xusb_padctl: padctl@3520000 { 1006 compatible = "nvidia,tegra194-xusb-padctl"; 1007 reg = <0x03520000 0x1000>, 1008 <0x03540000 0x1000>; 1009 reg-names = "padctl", "ao"; 1010 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1011 1012 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1013 reset-names = "padctl"; 1014 1015 status = "disabled"; 1016 1017 pads { 1018 usb2 { 1019 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1020 clock-names = "trk"; 1021 1022 lanes { 1023 usb2-0 { 1024 nvidia,function = "xusb"; 1025 status = "disabled"; 1026 #phy-cells = <0>; 1027 }; 1028 1029 usb2-1 { 1030 nvidia,function = "xusb"; 1031 status = "disabled"; 1032 #phy-cells = <0>; 1033 }; 1034 1035 usb2-2 { 1036 nvidia,function = "xusb"; 1037 status = "disabled"; 1038 #phy-cells = <0>; 1039 }; 1040 1041 usb2-3 { 1042 nvidia,function = "xusb"; 1043 status = "disabled"; 1044 #phy-cells = <0>; 1045 }; 1046 }; 1047 }; 1048 1049 usb3 { 1050 lanes { 1051 usb3-0 { 1052 nvidia,function = "xusb"; 1053 status = "disabled"; 1054 #phy-cells = <0>; 1055 }; 1056 1057 usb3-1 { 1058 nvidia,function = "xusb"; 1059 status = "disabled"; 1060 #phy-cells = <0>; 1061 }; 1062 1063 usb3-2 { 1064 nvidia,function = "xusb"; 1065 status = "disabled"; 1066 #phy-cells = <0>; 1067 }; 1068 1069 usb3-3 { 1070 nvidia,function = "xusb"; 1071 status = "disabled"; 1072 #phy-cells = <0>; 1073 }; 1074 }; 1075 }; 1076 }; 1077 1078 ports { 1079 usb2-0 { 1080 status = "disabled"; 1081 }; 1082 1083 usb2-1 { 1084 status = "disabled"; 1085 }; 1086 1087 usb2-2 { 1088 status = "disabled"; 1089 }; 1090 1091 usb2-3 { 1092 status = "disabled"; 1093 }; 1094 1095 usb3-0 { 1096 status = "disabled"; 1097 }; 1098 1099 usb3-1 { 1100 status = "disabled"; 1101 }; 1102 1103 usb3-2 { 1104 status = "disabled"; 1105 }; 1106 1107 usb3-3 { 1108 status = "disabled"; 1109 }; 1110 }; 1111 }; 1112 1113 usb@3550000 { 1114 compatible = "nvidia,tegra194-xudc"; 1115 reg = <0x03550000 0x8000>, 1116 <0x03558000 0x1000>; 1117 reg-names = "base", "fpci"; 1118 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1119 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1120 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1121 <&bpmp TEGRA194_CLK_XUSB_SS>, 1122 <&bpmp TEGRA194_CLK_XUSB_FS>; 1123 clock-names = "dev", "ss", "ss_src", "fs_src"; 1124 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1125 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1126 interconnect-names = "dma-mem", "write"; 1127 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1128 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1129 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1130 power-domain-names = "dev", "ss"; 1131 nvidia,xusb-padctl = <&xusb_padctl>; 1132 status = "disabled"; 1133 }; 1134 1135 usb@3610000 { 1136 compatible = "nvidia,tegra194-xusb"; 1137 reg = <0x03610000 0x40000>, 1138 <0x03600000 0x10000>; 1139 reg-names = "hcd", "fpci"; 1140 1141 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1143 1144 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1145 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1146 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1147 <&bpmp TEGRA194_CLK_XUSB_SS>, 1148 <&bpmp TEGRA194_CLK_CLK_M>, 1149 <&bpmp TEGRA194_CLK_XUSB_FS>, 1150 <&bpmp TEGRA194_CLK_UTMIPLL>, 1151 <&bpmp TEGRA194_CLK_CLK_M>, 1152 <&bpmp TEGRA194_CLK_PLLE>; 1153 clock-names = "xusb_host", "xusb_falcon_src", 1154 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1155 "xusb_fs_src", "pll_u_480m", "clk_m", 1156 "pll_e"; 1157 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1158 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1159 interconnect-names = "dma-mem", "write"; 1160 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1161 1162 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1163 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1164 power-domain-names = "xusb_host", "xusb_ss"; 1165 1166 nvidia,xusb-padctl = <&xusb_padctl>; 1167 status = "disabled"; 1168 }; 1169 1170 fuse@3820000 { 1171 compatible = "nvidia,tegra194-efuse"; 1172 reg = <0x03820000 0x10000>; 1173 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1174 clock-names = "fuse"; 1175 }; 1176 1177 gic: interrupt-controller@3881000 { 1178 compatible = "arm,gic-400"; 1179 #interrupt-cells = <3>; 1180 interrupt-controller; 1181 reg = <0x03881000 0x1000>, 1182 <0x03882000 0x2000>, 1183 <0x03884000 0x2000>, 1184 <0x03886000 0x2000>; 1185 interrupts = <GIC_PPI 9 1186 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1187 interrupt-parent = <&gic>; 1188 }; 1189 1190 cec@3960000 { 1191 compatible = "nvidia,tegra194-cec"; 1192 reg = <0x03960000 0x10000>; 1193 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1194 clocks = <&bpmp TEGRA194_CLK_CEC>; 1195 clock-names = "cec"; 1196 status = "disabled"; 1197 }; 1198 1199 hsp_top0: hsp@3c00000 { 1200 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1201 reg = <0x03c00000 0xa0000>; 1202 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1211 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1212 "shared3", "shared4", "shared5", "shared6", 1213 "shared7"; 1214 #mbox-cells = <2>; 1215 }; 1216 1217 p2u_hsio_0: phy@3e10000 { 1218 compatible = "nvidia,tegra194-p2u"; 1219 reg = <0x03e10000 0x10000>; 1220 reg-names = "ctl"; 1221 1222 #phy-cells = <0>; 1223 }; 1224 1225 p2u_hsio_1: phy@3e20000 { 1226 compatible = "nvidia,tegra194-p2u"; 1227 reg = <0x03e20000 0x10000>; 1228 reg-names = "ctl"; 1229 1230 #phy-cells = <0>; 1231 }; 1232 1233 p2u_hsio_2: phy@3e30000 { 1234 compatible = "nvidia,tegra194-p2u"; 1235 reg = <0x03e30000 0x10000>; 1236 reg-names = "ctl"; 1237 1238 #phy-cells = <0>; 1239 }; 1240 1241 p2u_hsio_3: phy@3e40000 { 1242 compatible = "nvidia,tegra194-p2u"; 1243 reg = <0x03e40000 0x10000>; 1244 reg-names = "ctl"; 1245 1246 #phy-cells = <0>; 1247 }; 1248 1249 p2u_hsio_4: phy@3e50000 { 1250 compatible = "nvidia,tegra194-p2u"; 1251 reg = <0x03e50000 0x10000>; 1252 reg-names = "ctl"; 1253 1254 #phy-cells = <0>; 1255 }; 1256 1257 p2u_hsio_5: phy@3e60000 { 1258 compatible = "nvidia,tegra194-p2u"; 1259 reg = <0x03e60000 0x10000>; 1260 reg-names = "ctl"; 1261 1262 #phy-cells = <0>; 1263 }; 1264 1265 p2u_hsio_6: phy@3e70000 { 1266 compatible = "nvidia,tegra194-p2u"; 1267 reg = <0x03e70000 0x10000>; 1268 reg-names = "ctl"; 1269 1270 #phy-cells = <0>; 1271 }; 1272 1273 p2u_hsio_7: phy@3e80000 { 1274 compatible = "nvidia,tegra194-p2u"; 1275 reg = <0x03e80000 0x10000>; 1276 reg-names = "ctl"; 1277 1278 #phy-cells = <0>; 1279 }; 1280 1281 p2u_hsio_8: phy@3e90000 { 1282 compatible = "nvidia,tegra194-p2u"; 1283 reg = <0x03e90000 0x10000>; 1284 reg-names = "ctl"; 1285 1286 #phy-cells = <0>; 1287 }; 1288 1289 p2u_hsio_9: phy@3ea0000 { 1290 compatible = "nvidia,tegra194-p2u"; 1291 reg = <0x03ea0000 0x10000>; 1292 reg-names = "ctl"; 1293 1294 #phy-cells = <0>; 1295 }; 1296 1297 p2u_nvhs_0: phy@3eb0000 { 1298 compatible = "nvidia,tegra194-p2u"; 1299 reg = <0x03eb0000 0x10000>; 1300 reg-names = "ctl"; 1301 1302 #phy-cells = <0>; 1303 }; 1304 1305 p2u_nvhs_1: phy@3ec0000 { 1306 compatible = "nvidia,tegra194-p2u"; 1307 reg = <0x03ec0000 0x10000>; 1308 reg-names = "ctl"; 1309 1310 #phy-cells = <0>; 1311 }; 1312 1313 p2u_nvhs_2: phy@3ed0000 { 1314 compatible = "nvidia,tegra194-p2u"; 1315 reg = <0x03ed0000 0x10000>; 1316 reg-names = "ctl"; 1317 1318 #phy-cells = <0>; 1319 }; 1320 1321 p2u_nvhs_3: phy@3ee0000 { 1322 compatible = "nvidia,tegra194-p2u"; 1323 reg = <0x03ee0000 0x10000>; 1324 reg-names = "ctl"; 1325 1326 #phy-cells = <0>; 1327 }; 1328 1329 p2u_nvhs_4: phy@3ef0000 { 1330 compatible = "nvidia,tegra194-p2u"; 1331 reg = <0x03ef0000 0x10000>; 1332 reg-names = "ctl"; 1333 1334 #phy-cells = <0>; 1335 }; 1336 1337 p2u_nvhs_5: phy@3f00000 { 1338 compatible = "nvidia,tegra194-p2u"; 1339 reg = <0x03f00000 0x10000>; 1340 reg-names = "ctl"; 1341 1342 #phy-cells = <0>; 1343 }; 1344 1345 p2u_nvhs_6: phy@3f10000 { 1346 compatible = "nvidia,tegra194-p2u"; 1347 reg = <0x03f10000 0x10000>; 1348 reg-names = "ctl"; 1349 1350 #phy-cells = <0>; 1351 }; 1352 1353 p2u_nvhs_7: phy@3f20000 { 1354 compatible = "nvidia,tegra194-p2u"; 1355 reg = <0x03f20000 0x10000>; 1356 reg-names = "ctl"; 1357 1358 #phy-cells = <0>; 1359 }; 1360 1361 p2u_hsio_10: phy@3f30000 { 1362 compatible = "nvidia,tegra194-p2u"; 1363 reg = <0x03f30000 0x10000>; 1364 reg-names = "ctl"; 1365 1366 #phy-cells = <0>; 1367 }; 1368 1369 p2u_hsio_11: phy@3f40000 { 1370 compatible = "nvidia,tegra194-p2u"; 1371 reg = <0x03f40000 0x10000>; 1372 reg-names = "ctl"; 1373 1374 #phy-cells = <0>; 1375 }; 1376 1377 hsp_aon: hsp@c150000 { 1378 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1379 reg = <0x0c150000 0x90000>; 1380 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1384 /* 1385 * Shared interrupt 0 is routed only to AON/SPE, so 1386 * we only have 4 shared interrupts for the CCPLEX. 1387 */ 1388 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1389 #mbox-cells = <2>; 1390 }; 1391 1392 gen2_i2c: i2c@c240000 { 1393 compatible = "nvidia,tegra194-i2c"; 1394 reg = <0x0c240000 0x10000>; 1395 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1399 clock-names = "div-clk"; 1400 resets = <&bpmp TEGRA194_RESET_I2C2>; 1401 reset-names = "i2c"; 1402 status = "disabled"; 1403 }; 1404 1405 gen8_i2c: i2c@c250000 { 1406 compatible = "nvidia,tegra194-i2c"; 1407 reg = <0x0c250000 0x10000>; 1408 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1412 clock-names = "div-clk"; 1413 resets = <&bpmp TEGRA194_RESET_I2C8>; 1414 reset-names = "i2c"; 1415 status = "disabled"; 1416 }; 1417 1418 uartc: serial@c280000 { 1419 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1420 reg = <0x0c280000 0x40>; 1421 reg-shift = <2>; 1422 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1423 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1424 clock-names = "serial"; 1425 resets = <&bpmp TEGRA194_RESET_UARTC>; 1426 reset-names = "serial"; 1427 status = "disabled"; 1428 }; 1429 1430 uartg: serial@c290000 { 1431 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1432 reg = <0x0c290000 0x40>; 1433 reg-shift = <2>; 1434 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1435 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1436 clock-names = "serial"; 1437 resets = <&bpmp TEGRA194_RESET_UARTG>; 1438 reset-names = "serial"; 1439 status = "disabled"; 1440 }; 1441 1442 rtc: rtc@c2a0000 { 1443 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1444 reg = <0x0c2a0000 0x10000>; 1445 interrupt-parent = <&pmc>; 1446 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1447 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1448 clock-names = "rtc"; 1449 status = "disabled"; 1450 }; 1451 1452 gpio_aon: gpio@c2f0000 { 1453 compatible = "nvidia,tegra194-gpio-aon"; 1454 reg-names = "security", "gpio"; 1455 reg = <0xc2f0000 0x1000>, 1456 <0xc2f1000 0x1000>; 1457 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1461 gpio-controller; 1462 #gpio-cells = <2>; 1463 interrupt-controller; 1464 #interrupt-cells = <2>; 1465 }; 1466 1467 pwm4: pwm@c340000 { 1468 compatible = "nvidia,tegra194-pwm", 1469 "nvidia,tegra186-pwm"; 1470 reg = <0xc340000 0x10000>; 1471 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1472 clock-names = "pwm"; 1473 resets = <&bpmp TEGRA194_RESET_PWM4>; 1474 reset-names = "pwm"; 1475 status = "disabled"; 1476 #pwm-cells = <2>; 1477 }; 1478 1479 pmc: pmc@c360000 { 1480 compatible = "nvidia,tegra194-pmc"; 1481 reg = <0x0c360000 0x10000>, 1482 <0x0c370000 0x10000>, 1483 <0x0c380000 0x10000>, 1484 <0x0c390000 0x10000>, 1485 <0x0c3a0000 0x10000>; 1486 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1487 1488 #interrupt-cells = <2>; 1489 interrupt-controller; 1490 sdmmc1_3v3: sdmmc1-3v3 { 1491 pins = "sdmmc1-hv"; 1492 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1493 }; 1494 1495 sdmmc1_1v8: sdmmc1-1v8 { 1496 pins = "sdmmc1-hv"; 1497 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1498 }; 1499 sdmmc3_3v3: sdmmc3-3v3 { 1500 pins = "sdmmc3-hv"; 1501 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1502 }; 1503 1504 sdmmc3_1v8: sdmmc3-1v8 { 1505 pins = "sdmmc3-hv"; 1506 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1507 }; 1508 1509 }; 1510 1511 smmu: iommu@12000000 { 1512 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1513 reg = <0x12000000 0x800000>, 1514 <0x11000000 0x800000>; 1515 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1549 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1581 stream-match-mask = <0x7f80>; 1582 #global-interrupts = <2>; 1583 #iommu-cells = <1>; 1584 1585 nvidia,memory-controller = <&mc>; 1586 status = "okay"; 1587 }; 1588 1589 host1x@13e00000 { 1590 compatible = "nvidia,tegra194-host1x"; 1591 reg = <0x13e00000 0x10000>, 1592 <0x13e10000 0x10000>; 1593 reg-names = "hypervisor", "vm"; 1594 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1596 interrupt-names = "syncpt", "host1x"; 1597 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1598 clock-names = "host1x"; 1599 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1600 reset-names = "host1x"; 1601 1602 #address-cells = <1>; 1603 #size-cells = <1>; 1604 1605 ranges = <0x15000000 0x15000000 0x01000000>; 1606 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1607 interconnect-names = "dma-mem"; 1608 iommus = <&smmu TEGRA194_SID_HOST1X>; 1609 1610 nvdec@15140000 { 1611 compatible = "nvidia,tegra194-nvdec"; 1612 reg = <0x15140000 0x00040000>; 1613 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1614 clock-names = "nvdec"; 1615 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1616 reset-names = "nvdec"; 1617 1618 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1619 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1620 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1621 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1622 interconnect-names = "dma-mem", "read-1", "write"; 1623 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1624 dma-coherent; 1625 1626 nvidia,host1x-class = <0xf5>; 1627 }; 1628 1629 display-hub@15200000 { 1630 compatible = "nvidia,tegra194-display"; 1631 reg = <0x15200000 0x00040000>; 1632 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1633 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1634 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1635 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1636 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1637 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1638 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1639 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1640 "wgrp3", "wgrp4", "wgrp5"; 1641 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1642 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1643 clock-names = "disp", "hub"; 1644 status = "disabled"; 1645 1646 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1647 1648 #address-cells = <1>; 1649 #size-cells = <1>; 1650 1651 ranges = <0x15200000 0x15200000 0x40000>; 1652 1653 display@15200000 { 1654 compatible = "nvidia,tegra194-dc"; 1655 reg = <0x15200000 0x10000>; 1656 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1657 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1658 clock-names = "dc"; 1659 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1660 reset-names = "dc"; 1661 1662 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1663 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1664 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1665 interconnect-names = "dma-mem", "read-1"; 1666 1667 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1668 nvidia,head = <0>; 1669 }; 1670 1671 display@15210000 { 1672 compatible = "nvidia,tegra194-dc"; 1673 reg = <0x15210000 0x10000>; 1674 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1675 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1676 clock-names = "dc"; 1677 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1678 reset-names = "dc"; 1679 1680 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1681 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1682 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1683 interconnect-names = "dma-mem", "read-1"; 1684 1685 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1686 nvidia,head = <1>; 1687 }; 1688 1689 display@15220000 { 1690 compatible = "nvidia,tegra194-dc"; 1691 reg = <0x15220000 0x10000>; 1692 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1693 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1694 clock-names = "dc"; 1695 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1696 reset-names = "dc"; 1697 1698 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1699 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1700 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1701 interconnect-names = "dma-mem", "read-1"; 1702 1703 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1704 nvidia,head = <2>; 1705 }; 1706 1707 display@15230000 { 1708 compatible = "nvidia,tegra194-dc"; 1709 reg = <0x15230000 0x10000>; 1710 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1711 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1712 clock-names = "dc"; 1713 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1714 reset-names = "dc"; 1715 1716 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1717 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1718 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1719 interconnect-names = "dma-mem", "read-1"; 1720 1721 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1722 nvidia,head = <3>; 1723 }; 1724 }; 1725 1726 vic@15340000 { 1727 compatible = "nvidia,tegra194-vic"; 1728 reg = <0x15340000 0x00040000>; 1729 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1730 clocks = <&bpmp TEGRA194_CLK_VIC>; 1731 clock-names = "vic"; 1732 resets = <&bpmp TEGRA194_RESET_VIC>; 1733 reset-names = "vic"; 1734 1735 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1736 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1737 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1738 interconnect-names = "dma-mem", "write"; 1739 iommus = <&smmu TEGRA194_SID_VIC>; 1740 }; 1741 1742 nvjpg@15380000 { 1743 compatible = "nvidia,tegra194-nvjpg"; 1744 reg = <0x15380000 0x40000>; 1745 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1746 clock-names = "nvjpg"; 1747 resets = <&bpmp TEGRA194_RESET_NVJPG>; 1748 reset-names = "nvjpg"; 1749 1750 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1751 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1752 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1753 interconnect-names = "dma-mem", "write"; 1754 iommus = <&smmu TEGRA194_SID_NVJPG>; 1755 dma-coherent; 1756 }; 1757 1758 nvdec@15480000 { 1759 compatible = "nvidia,tegra194-nvdec"; 1760 reg = <0x15480000 0x00040000>; 1761 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 1762 clock-names = "nvdec"; 1763 resets = <&bpmp TEGRA194_RESET_NVDEC>; 1764 reset-names = "nvdec"; 1765 1766 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 1767 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 1768 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 1769 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 1770 interconnect-names = "dma-mem", "read-1", "write"; 1771 iommus = <&smmu TEGRA194_SID_NVDEC>; 1772 dma-coherent; 1773 1774 nvidia,host1x-class = <0xf0>; 1775 }; 1776 1777 nvenc@154c0000 { 1778 compatible = "nvidia,tegra194-nvenc"; 1779 reg = <0x154c0000 0x40000>; 1780 clocks = <&bpmp TEGRA194_CLK_NVENC>; 1781 clock-names = "nvenc"; 1782 resets = <&bpmp TEGRA194_RESET_NVENC>; 1783 reset-names = "nvenc"; 1784 1785 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 1786 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 1787 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 1788 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 1789 interconnect-names = "dma-mem", "read-1", "write"; 1790 iommus = <&smmu TEGRA194_SID_NVENC>; 1791 dma-coherent; 1792 1793 nvidia,host1x-class = <0x21>; 1794 }; 1795 1796 dpaux0: dpaux@155c0000 { 1797 compatible = "nvidia,tegra194-dpaux"; 1798 reg = <0x155c0000 0x10000>; 1799 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1800 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1801 <&bpmp TEGRA194_CLK_PLLDP>; 1802 clock-names = "dpaux", "parent"; 1803 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1804 reset-names = "dpaux"; 1805 status = "disabled"; 1806 1807 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1808 1809 state_dpaux0_aux: pinmux-aux { 1810 groups = "dpaux-io"; 1811 function = "aux"; 1812 }; 1813 1814 state_dpaux0_i2c: pinmux-i2c { 1815 groups = "dpaux-io"; 1816 function = "i2c"; 1817 }; 1818 1819 state_dpaux0_off: pinmux-off { 1820 groups = "dpaux-io"; 1821 function = "off"; 1822 }; 1823 1824 i2c-bus { 1825 #address-cells = <1>; 1826 #size-cells = <0>; 1827 }; 1828 }; 1829 1830 dpaux1: dpaux@155d0000 { 1831 compatible = "nvidia,tegra194-dpaux"; 1832 reg = <0x155d0000 0x10000>; 1833 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1834 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1835 <&bpmp TEGRA194_CLK_PLLDP>; 1836 clock-names = "dpaux", "parent"; 1837 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1838 reset-names = "dpaux"; 1839 status = "disabled"; 1840 1841 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1842 1843 state_dpaux1_aux: pinmux-aux { 1844 groups = "dpaux-io"; 1845 function = "aux"; 1846 }; 1847 1848 state_dpaux1_i2c: pinmux-i2c { 1849 groups = "dpaux-io"; 1850 function = "i2c"; 1851 }; 1852 1853 state_dpaux1_off: pinmux-off { 1854 groups = "dpaux-io"; 1855 function = "off"; 1856 }; 1857 1858 i2c-bus { 1859 #address-cells = <1>; 1860 #size-cells = <0>; 1861 }; 1862 }; 1863 1864 dpaux2: dpaux@155e0000 { 1865 compatible = "nvidia,tegra194-dpaux"; 1866 reg = <0x155e0000 0x10000>; 1867 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1868 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1869 <&bpmp TEGRA194_CLK_PLLDP>; 1870 clock-names = "dpaux", "parent"; 1871 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1872 reset-names = "dpaux"; 1873 status = "disabled"; 1874 1875 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1876 1877 state_dpaux2_aux: pinmux-aux { 1878 groups = "dpaux-io"; 1879 function = "aux"; 1880 }; 1881 1882 state_dpaux2_i2c: pinmux-i2c { 1883 groups = "dpaux-io"; 1884 function = "i2c"; 1885 }; 1886 1887 state_dpaux2_off: pinmux-off { 1888 groups = "dpaux-io"; 1889 function = "off"; 1890 }; 1891 1892 i2c-bus { 1893 #address-cells = <1>; 1894 #size-cells = <0>; 1895 }; 1896 }; 1897 1898 dpaux3: dpaux@155f0000 { 1899 compatible = "nvidia,tegra194-dpaux"; 1900 reg = <0x155f0000 0x10000>; 1901 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1902 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1903 <&bpmp TEGRA194_CLK_PLLDP>; 1904 clock-names = "dpaux", "parent"; 1905 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1906 reset-names = "dpaux"; 1907 status = "disabled"; 1908 1909 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1910 1911 state_dpaux3_aux: pinmux-aux { 1912 groups = "dpaux-io"; 1913 function = "aux"; 1914 }; 1915 1916 state_dpaux3_i2c: pinmux-i2c { 1917 groups = "dpaux-io"; 1918 function = "i2c"; 1919 }; 1920 1921 state_dpaux3_off: pinmux-off { 1922 groups = "dpaux-io"; 1923 function = "off"; 1924 }; 1925 1926 i2c-bus { 1927 #address-cells = <1>; 1928 #size-cells = <0>; 1929 }; 1930 }; 1931 1932 nvenc@15a80000 { 1933 compatible = "nvidia,tegra194-nvenc"; 1934 reg = <0x15a80000 0x00040000>; 1935 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 1936 clock-names = "nvenc"; 1937 resets = <&bpmp TEGRA194_RESET_NVENC1>; 1938 reset-names = "nvenc"; 1939 1940 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 1941 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 1942 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 1943 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 1944 interconnect-names = "dma-mem", "read-1", "write"; 1945 iommus = <&smmu TEGRA194_SID_NVENC1>; 1946 dma-coherent; 1947 1948 nvidia,host1x-class = <0x22>; 1949 }; 1950 1951 sor0: sor@15b00000 { 1952 compatible = "nvidia,tegra194-sor"; 1953 reg = <0x15b00000 0x40000>; 1954 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1955 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1956 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1957 <&bpmp TEGRA194_CLK_PLLD>, 1958 <&bpmp TEGRA194_CLK_PLLDP>, 1959 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1960 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1961 clock-names = "sor", "out", "parent", "dp", "safe", 1962 "pad"; 1963 resets = <&bpmp TEGRA194_RESET_SOR0>; 1964 reset-names = "sor"; 1965 pinctrl-0 = <&state_dpaux0_aux>; 1966 pinctrl-1 = <&state_dpaux0_i2c>; 1967 pinctrl-2 = <&state_dpaux0_off>; 1968 pinctrl-names = "aux", "i2c", "off"; 1969 status = "disabled"; 1970 1971 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1972 nvidia,interface = <0>; 1973 }; 1974 1975 sor1: sor@15b40000 { 1976 compatible = "nvidia,tegra194-sor"; 1977 reg = <0x15b40000 0x40000>; 1978 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1979 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1980 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1981 <&bpmp TEGRA194_CLK_PLLD2>, 1982 <&bpmp TEGRA194_CLK_PLLDP>, 1983 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1984 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1985 clock-names = "sor", "out", "parent", "dp", "safe", 1986 "pad"; 1987 resets = <&bpmp TEGRA194_RESET_SOR1>; 1988 reset-names = "sor"; 1989 pinctrl-0 = <&state_dpaux1_aux>; 1990 pinctrl-1 = <&state_dpaux1_i2c>; 1991 pinctrl-2 = <&state_dpaux1_off>; 1992 pinctrl-names = "aux", "i2c", "off"; 1993 status = "disabled"; 1994 1995 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1996 nvidia,interface = <1>; 1997 }; 1998 1999 sor2: sor@15b80000 { 2000 compatible = "nvidia,tegra194-sor"; 2001 reg = <0x15b80000 0x40000>; 2002 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2003 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2004 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2005 <&bpmp TEGRA194_CLK_PLLD3>, 2006 <&bpmp TEGRA194_CLK_PLLDP>, 2007 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2008 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2009 clock-names = "sor", "out", "parent", "dp", "safe", 2010 "pad"; 2011 resets = <&bpmp TEGRA194_RESET_SOR2>; 2012 reset-names = "sor"; 2013 pinctrl-0 = <&state_dpaux2_aux>; 2014 pinctrl-1 = <&state_dpaux2_i2c>; 2015 pinctrl-2 = <&state_dpaux2_off>; 2016 pinctrl-names = "aux", "i2c", "off"; 2017 status = "disabled"; 2018 2019 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2020 nvidia,interface = <2>; 2021 }; 2022 2023 sor3: sor@15bc0000 { 2024 compatible = "nvidia,tegra194-sor"; 2025 reg = <0x15bc0000 0x40000>; 2026 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2027 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2028 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2029 <&bpmp TEGRA194_CLK_PLLD4>, 2030 <&bpmp TEGRA194_CLK_PLLDP>, 2031 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2032 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2033 clock-names = "sor", "out", "parent", "dp", "safe", 2034 "pad"; 2035 resets = <&bpmp TEGRA194_RESET_SOR3>; 2036 reset-names = "sor"; 2037 pinctrl-0 = <&state_dpaux3_aux>; 2038 pinctrl-1 = <&state_dpaux3_i2c>; 2039 pinctrl-2 = <&state_dpaux3_off>; 2040 pinctrl-names = "aux", "i2c", "off"; 2041 status = "disabled"; 2042 2043 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2044 nvidia,interface = <3>; 2045 }; 2046 }; 2047 2048 gpu@17000000 { 2049 compatible = "nvidia,gv11b"; 2050 reg = <0x17000000 0x1000000>, 2051 <0x18000000 0x1000000>; 2052 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2054 interrupt-names = "stall", "nonstall"; 2055 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2056 <&bpmp TEGRA194_CLK_GPU_PWR>, 2057 <&bpmp TEGRA194_CLK_FUSE>; 2058 clock-names = "gpu", "pwr", "fuse"; 2059 resets = <&bpmp TEGRA194_RESET_GPU>; 2060 reset-names = "gpu"; 2061 dma-coherent; 2062 2063 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2064 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2065 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2066 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2067 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2068 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2069 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2070 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2071 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2072 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2073 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2074 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2075 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2076 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2077 "read-1", "read-1-hp", "write-1", 2078 "read-2", "read-2-hp", "write-2", 2079 "read-3", "read-3-hp", "write-3"; 2080 }; 2081 }; 2082 2083 pcie@14100000 { 2084 compatible = "nvidia,tegra194-pcie"; 2085 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2086 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2087 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2088 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2089 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2090 reg-names = "appl", "config", "atu_dma", "dbi"; 2091 2092 status = "disabled"; 2093 2094 #address-cells = <3>; 2095 #size-cells = <2>; 2096 device_type = "pci"; 2097 num-lanes = <1>; 2098 num-viewport = <8>; 2099 linux,pci-domain = <1>; 2100 2101 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2102 clock-names = "core"; 2103 2104 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2105 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2106 reset-names = "apb", "core"; 2107 2108 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2109 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2110 interrupt-names = "intr", "msi"; 2111 2112 #interrupt-cells = <1>; 2113 interrupt-map-mask = <0 0 0 0>; 2114 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2115 2116 nvidia,bpmp = <&bpmp 1>; 2117 2118 nvidia,aspm-cmrt-us = <60>; 2119 nvidia,aspm-pwr-on-t-us = <20>; 2120 nvidia,aspm-l0s-entrance-latency-us = <3>; 2121 2122 bus-range = <0x0 0xff>; 2123 2124 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2125 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2126 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2127 2128 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2129 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2130 interconnect-names = "dma-mem", "write"; 2131 iommus = <&smmu TEGRA194_SID_PCIE1>; 2132 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2133 iommu-map-mask = <0x0>; 2134 dma-coherent; 2135 }; 2136 2137 pcie@14120000 { 2138 compatible = "nvidia,tegra194-pcie"; 2139 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2140 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2141 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2142 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2143 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2144 reg-names = "appl", "config", "atu_dma", "dbi"; 2145 2146 status = "disabled"; 2147 2148 #address-cells = <3>; 2149 #size-cells = <2>; 2150 device_type = "pci"; 2151 num-lanes = <1>; 2152 num-viewport = <8>; 2153 linux,pci-domain = <2>; 2154 2155 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2156 clock-names = "core"; 2157 2158 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2159 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2160 reset-names = "apb", "core"; 2161 2162 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2163 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2164 interrupt-names = "intr", "msi"; 2165 2166 #interrupt-cells = <1>; 2167 interrupt-map-mask = <0 0 0 0>; 2168 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2169 2170 nvidia,bpmp = <&bpmp 2>; 2171 2172 nvidia,aspm-cmrt-us = <60>; 2173 nvidia,aspm-pwr-on-t-us = <20>; 2174 nvidia,aspm-l0s-entrance-latency-us = <3>; 2175 2176 bus-range = <0x0 0xff>; 2177 2178 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2179 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2180 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2181 2182 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2183 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2184 interconnect-names = "dma-mem", "write"; 2185 iommus = <&smmu TEGRA194_SID_PCIE2>; 2186 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2187 iommu-map-mask = <0x0>; 2188 dma-coherent; 2189 }; 2190 2191 pcie@14140000 { 2192 compatible = "nvidia,tegra194-pcie"; 2193 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2194 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2195 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2196 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2197 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2198 reg-names = "appl", "config", "atu_dma", "dbi"; 2199 2200 status = "disabled"; 2201 2202 #address-cells = <3>; 2203 #size-cells = <2>; 2204 device_type = "pci"; 2205 num-lanes = <1>; 2206 num-viewport = <8>; 2207 linux,pci-domain = <3>; 2208 2209 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2210 clock-names = "core"; 2211 2212 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2213 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2214 reset-names = "apb", "core"; 2215 2216 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2217 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2218 interrupt-names = "intr", "msi"; 2219 2220 #interrupt-cells = <1>; 2221 interrupt-map-mask = <0 0 0 0>; 2222 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2223 2224 nvidia,bpmp = <&bpmp 3>; 2225 2226 nvidia,aspm-cmrt-us = <60>; 2227 nvidia,aspm-pwr-on-t-us = <20>; 2228 nvidia,aspm-l0s-entrance-latency-us = <3>; 2229 2230 bus-range = <0x0 0xff>; 2231 2232 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2233 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2234 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2235 2236 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2237 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2238 interconnect-names = "dma-mem", "write"; 2239 iommus = <&smmu TEGRA194_SID_PCIE3>; 2240 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2241 iommu-map-mask = <0x0>; 2242 dma-coherent; 2243 }; 2244 2245 pcie@14160000 { 2246 compatible = "nvidia,tegra194-pcie"; 2247 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2248 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2249 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2250 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2251 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2252 reg-names = "appl", "config", "atu_dma", "dbi"; 2253 2254 status = "disabled"; 2255 2256 #address-cells = <3>; 2257 #size-cells = <2>; 2258 device_type = "pci"; 2259 num-lanes = <4>; 2260 num-viewport = <8>; 2261 linux,pci-domain = <4>; 2262 2263 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2264 clock-names = "core"; 2265 2266 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2267 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2268 reset-names = "apb", "core"; 2269 2270 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2271 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2272 interrupt-names = "intr", "msi"; 2273 2274 #interrupt-cells = <1>; 2275 interrupt-map-mask = <0 0 0 0>; 2276 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2277 2278 nvidia,bpmp = <&bpmp 4>; 2279 2280 nvidia,aspm-cmrt-us = <60>; 2281 nvidia,aspm-pwr-on-t-us = <20>; 2282 nvidia,aspm-l0s-entrance-latency-us = <3>; 2283 2284 bus-range = <0x0 0xff>; 2285 2286 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2287 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2288 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2289 2290 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2291 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2292 interconnect-names = "dma-mem", "write"; 2293 iommus = <&smmu TEGRA194_SID_PCIE4>; 2294 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2295 iommu-map-mask = <0x0>; 2296 dma-coherent; 2297 }; 2298 2299 pcie@14180000 { 2300 compatible = "nvidia,tegra194-pcie"; 2301 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2302 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2303 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2304 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2305 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2306 reg-names = "appl", "config", "atu_dma", "dbi"; 2307 2308 status = "disabled"; 2309 2310 #address-cells = <3>; 2311 #size-cells = <2>; 2312 device_type = "pci"; 2313 num-lanes = <8>; 2314 num-viewport = <8>; 2315 linux,pci-domain = <0>; 2316 2317 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2318 clock-names = "core"; 2319 2320 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2321 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2322 reset-names = "apb", "core"; 2323 2324 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2325 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2326 interrupt-names = "intr", "msi"; 2327 2328 #interrupt-cells = <1>; 2329 interrupt-map-mask = <0 0 0 0>; 2330 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2331 2332 nvidia,bpmp = <&bpmp 0>; 2333 2334 nvidia,aspm-cmrt-us = <60>; 2335 nvidia,aspm-pwr-on-t-us = <20>; 2336 nvidia,aspm-l0s-entrance-latency-us = <3>; 2337 2338 bus-range = <0x0 0xff>; 2339 2340 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2341 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2342 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2343 2344 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2345 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2346 interconnect-names = "dma-mem", "write"; 2347 iommus = <&smmu TEGRA194_SID_PCIE0>; 2348 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2349 iommu-map-mask = <0x0>; 2350 dma-coherent; 2351 }; 2352 2353 pcie@141a0000 { 2354 compatible = "nvidia,tegra194-pcie"; 2355 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2356 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2357 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2358 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2359 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2360 reg-names = "appl", "config", "atu_dma", "dbi"; 2361 2362 status = "disabled"; 2363 2364 #address-cells = <3>; 2365 #size-cells = <2>; 2366 device_type = "pci"; 2367 num-lanes = <8>; 2368 num-viewport = <8>; 2369 linux,pci-domain = <5>; 2370 2371 pinctrl-names = "default"; 2372 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2373 2374 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 2375 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 2376 clock-names = "core", "core_m"; 2377 2378 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2379 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2380 reset-names = "apb", "core"; 2381 2382 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2383 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2384 interrupt-names = "intr", "msi"; 2385 2386 nvidia,bpmp = <&bpmp 5>; 2387 2388 #interrupt-cells = <1>; 2389 interrupt-map-mask = <0 0 0 0>; 2390 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2391 2392 nvidia,aspm-cmrt-us = <60>; 2393 nvidia,aspm-pwr-on-t-us = <20>; 2394 nvidia,aspm-l0s-entrance-latency-us = <3>; 2395 2396 bus-range = <0x0 0xff>; 2397 2398 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2399 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2400 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2401 2402 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2403 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2404 interconnect-names = "dma-mem", "write"; 2405 iommus = <&smmu TEGRA194_SID_PCIE5>; 2406 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2407 iommu-map-mask = <0x0>; 2408 dma-coherent; 2409 }; 2410 2411 pcie-ep@14160000 { 2412 compatible = "nvidia,tegra194-pcie-ep"; 2413 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2414 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2415 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2416 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2417 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2418 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2419 2420 status = "disabled"; 2421 2422 num-lanes = <4>; 2423 num-ib-windows = <2>; 2424 num-ob-windows = <8>; 2425 2426 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2427 clock-names = "core"; 2428 2429 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2430 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2431 reset-names = "apb", "core"; 2432 2433 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2434 interrupt-names = "intr"; 2435 2436 nvidia,bpmp = <&bpmp 4>; 2437 2438 nvidia,aspm-cmrt-us = <60>; 2439 nvidia,aspm-pwr-on-t-us = <20>; 2440 nvidia,aspm-l0s-entrance-latency-us = <3>; 2441 2442 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2443 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2444 interconnect-names = "dma-mem", "write"; 2445 iommus = <&smmu TEGRA194_SID_PCIE4>; 2446 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2447 iommu-map-mask = <0x0>; 2448 dma-coherent; 2449 }; 2450 2451 pcie-ep@14180000 { 2452 compatible = "nvidia,tegra194-pcie-ep"; 2453 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2454 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2455 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2456 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2457 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2458 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2459 2460 status = "disabled"; 2461 2462 num-lanes = <8>; 2463 num-ib-windows = <2>; 2464 num-ob-windows = <8>; 2465 2466 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2467 clock-names = "core"; 2468 2469 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2470 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2471 reset-names = "apb", "core"; 2472 2473 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2474 interrupt-names = "intr"; 2475 2476 nvidia,bpmp = <&bpmp 0>; 2477 2478 nvidia,aspm-cmrt-us = <60>; 2479 nvidia,aspm-pwr-on-t-us = <20>; 2480 nvidia,aspm-l0s-entrance-latency-us = <3>; 2481 2482 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2483 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2484 interconnect-names = "dma-mem", "write"; 2485 iommus = <&smmu TEGRA194_SID_PCIE0>; 2486 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2487 iommu-map-mask = <0x0>; 2488 dma-coherent; 2489 }; 2490 2491 pcie-ep@141a0000 { 2492 compatible = "nvidia,tegra194-pcie-ep"; 2493 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2494 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2495 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2496 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2497 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2498 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2499 2500 status = "disabled"; 2501 2502 num-lanes = <8>; 2503 num-ib-windows = <2>; 2504 num-ob-windows = <8>; 2505 2506 pinctrl-names = "default"; 2507 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2508 2509 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2510 clock-names = "core"; 2511 2512 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2513 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2514 reset-names = "apb", "core"; 2515 2516 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2517 interrupt-names = "intr"; 2518 2519 nvidia,bpmp = <&bpmp 5>; 2520 2521 nvidia,aspm-cmrt-us = <60>; 2522 nvidia,aspm-pwr-on-t-us = <20>; 2523 nvidia,aspm-l0s-entrance-latency-us = <3>; 2524 2525 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2526 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2527 interconnect-names = "dma-mem", "write"; 2528 iommus = <&smmu TEGRA194_SID_PCIE5>; 2529 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2530 iommu-map-mask = <0x0>; 2531 dma-coherent; 2532 }; 2533 2534 sram@40000000 { 2535 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2536 reg = <0x0 0x40000000 0x0 0x50000>; 2537 #address-cells = <1>; 2538 #size-cells = <1>; 2539 ranges = <0x0 0x0 0x40000000 0x50000>; 2540 2541 cpu_bpmp_tx: sram@4e000 { 2542 reg = <0x4e000 0x1000>; 2543 label = "cpu-bpmp-tx"; 2544 pool; 2545 }; 2546 2547 cpu_bpmp_rx: sram@4f000 { 2548 reg = <0x4f000 0x1000>; 2549 label = "cpu-bpmp-rx"; 2550 pool; 2551 }; 2552 }; 2553 2554 bpmp: bpmp { 2555 compatible = "nvidia,tegra186-bpmp"; 2556 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2557 TEGRA_HSP_DB_MASTER_BPMP>; 2558 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2559 #clock-cells = <1>; 2560 #reset-cells = <1>; 2561 #power-domain-cells = <1>; 2562 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2563 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2564 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2565 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2566 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2567 iommus = <&smmu TEGRA194_SID_BPMP>; 2568 2569 bpmp_i2c: i2c { 2570 compatible = "nvidia,tegra186-bpmp-i2c"; 2571 nvidia,bpmp-bus-id = <5>; 2572 #address-cells = <1>; 2573 #size-cells = <0>; 2574 }; 2575 2576 bpmp_thermal: thermal { 2577 compatible = "nvidia,tegra186-bpmp-thermal"; 2578 #thermal-sensor-cells = <1>; 2579 }; 2580 }; 2581 2582 cpus { 2583 compatible = "nvidia,tegra194-ccplex"; 2584 nvidia,bpmp = <&bpmp>; 2585 #address-cells = <1>; 2586 #size-cells = <0>; 2587 2588 cpu0_0: cpu@0 { 2589 compatible = "nvidia,tegra194-carmel"; 2590 device_type = "cpu"; 2591 reg = <0x000>; 2592 enable-method = "psci"; 2593 i-cache-size = <131072>; 2594 i-cache-line-size = <64>; 2595 i-cache-sets = <512>; 2596 d-cache-size = <65536>; 2597 d-cache-line-size = <64>; 2598 d-cache-sets = <256>; 2599 next-level-cache = <&l2c_0>; 2600 }; 2601 2602 cpu0_1: cpu@1 { 2603 compatible = "nvidia,tegra194-carmel"; 2604 device_type = "cpu"; 2605 reg = <0x001>; 2606 enable-method = "psci"; 2607 i-cache-size = <131072>; 2608 i-cache-line-size = <64>; 2609 i-cache-sets = <512>; 2610 d-cache-size = <65536>; 2611 d-cache-line-size = <64>; 2612 d-cache-sets = <256>; 2613 next-level-cache = <&l2c_0>; 2614 }; 2615 2616 cpu1_0: cpu@100 { 2617 compatible = "nvidia,tegra194-carmel"; 2618 device_type = "cpu"; 2619 reg = <0x100>; 2620 enable-method = "psci"; 2621 i-cache-size = <131072>; 2622 i-cache-line-size = <64>; 2623 i-cache-sets = <512>; 2624 d-cache-size = <65536>; 2625 d-cache-line-size = <64>; 2626 d-cache-sets = <256>; 2627 next-level-cache = <&l2c_1>; 2628 }; 2629 2630 cpu1_1: cpu@101 { 2631 compatible = "nvidia,tegra194-carmel"; 2632 device_type = "cpu"; 2633 reg = <0x101>; 2634 enable-method = "psci"; 2635 i-cache-size = <131072>; 2636 i-cache-line-size = <64>; 2637 i-cache-sets = <512>; 2638 d-cache-size = <65536>; 2639 d-cache-line-size = <64>; 2640 d-cache-sets = <256>; 2641 next-level-cache = <&l2c_1>; 2642 }; 2643 2644 cpu2_0: cpu@200 { 2645 compatible = "nvidia,tegra194-carmel"; 2646 device_type = "cpu"; 2647 reg = <0x200>; 2648 enable-method = "psci"; 2649 i-cache-size = <131072>; 2650 i-cache-line-size = <64>; 2651 i-cache-sets = <512>; 2652 d-cache-size = <65536>; 2653 d-cache-line-size = <64>; 2654 d-cache-sets = <256>; 2655 next-level-cache = <&l2c_2>; 2656 }; 2657 2658 cpu2_1: cpu@201 { 2659 compatible = "nvidia,tegra194-carmel"; 2660 device_type = "cpu"; 2661 reg = <0x201>; 2662 enable-method = "psci"; 2663 i-cache-size = <131072>; 2664 i-cache-line-size = <64>; 2665 i-cache-sets = <512>; 2666 d-cache-size = <65536>; 2667 d-cache-line-size = <64>; 2668 d-cache-sets = <256>; 2669 next-level-cache = <&l2c_2>; 2670 }; 2671 2672 cpu3_0: cpu@300 { 2673 compatible = "nvidia,tegra194-carmel"; 2674 device_type = "cpu"; 2675 reg = <0x300>; 2676 enable-method = "psci"; 2677 i-cache-size = <131072>; 2678 i-cache-line-size = <64>; 2679 i-cache-sets = <512>; 2680 d-cache-size = <65536>; 2681 d-cache-line-size = <64>; 2682 d-cache-sets = <256>; 2683 next-level-cache = <&l2c_3>; 2684 }; 2685 2686 cpu3_1: cpu@301 { 2687 compatible = "nvidia,tegra194-carmel"; 2688 device_type = "cpu"; 2689 reg = <0x301>; 2690 enable-method = "psci"; 2691 i-cache-size = <131072>; 2692 i-cache-line-size = <64>; 2693 i-cache-sets = <512>; 2694 d-cache-size = <65536>; 2695 d-cache-line-size = <64>; 2696 d-cache-sets = <256>; 2697 next-level-cache = <&l2c_3>; 2698 }; 2699 2700 cpu-map { 2701 cluster0 { 2702 core0 { 2703 cpu = <&cpu0_0>; 2704 }; 2705 2706 core1 { 2707 cpu = <&cpu0_1>; 2708 }; 2709 }; 2710 2711 cluster1 { 2712 core0 { 2713 cpu = <&cpu1_0>; 2714 }; 2715 2716 core1 { 2717 cpu = <&cpu1_1>; 2718 }; 2719 }; 2720 2721 cluster2 { 2722 core0 { 2723 cpu = <&cpu2_0>; 2724 }; 2725 2726 core1 { 2727 cpu = <&cpu2_1>; 2728 }; 2729 }; 2730 2731 cluster3 { 2732 core0 { 2733 cpu = <&cpu3_0>; 2734 }; 2735 2736 core1 { 2737 cpu = <&cpu3_1>; 2738 }; 2739 }; 2740 }; 2741 2742 l2c_0: l2-cache0 { 2743 cache-size = <2097152>; 2744 cache-line-size = <64>; 2745 cache-sets = <2048>; 2746 next-level-cache = <&l3c>; 2747 }; 2748 2749 l2c_1: l2-cache1 { 2750 cache-size = <2097152>; 2751 cache-line-size = <64>; 2752 cache-sets = <2048>; 2753 next-level-cache = <&l3c>; 2754 }; 2755 2756 l2c_2: l2-cache2 { 2757 cache-size = <2097152>; 2758 cache-line-size = <64>; 2759 cache-sets = <2048>; 2760 next-level-cache = <&l3c>; 2761 }; 2762 2763 l2c_3: l2-cache3 { 2764 cache-size = <2097152>; 2765 cache-line-size = <64>; 2766 cache-sets = <2048>; 2767 next-level-cache = <&l3c>; 2768 }; 2769 2770 l3c: l3-cache { 2771 cache-size = <4194304>; 2772 cache-line-size = <64>; 2773 cache-sets = <4096>; 2774 }; 2775 }; 2776 2777 pmu { 2778 compatible = "arm,armv8-pmuv3"; 2779 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2780 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2781 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2782 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 2783 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 2784 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 2785 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 2786 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 2787 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 2788 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 2789 }; 2790 2791 psci { 2792 compatible = "arm,psci-1.0"; 2793 status = "okay"; 2794 method = "smc"; 2795 }; 2796 2797 sound { 2798 status = "disabled"; 2799 2800 clocks = <&bpmp TEGRA194_CLK_PLLA>, 2801 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2802 clock-names = "pll_a", "plla_out0"; 2803 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 2804 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 2805 <&bpmp TEGRA194_CLK_AUD_MCLK>; 2806 assigned-clock-parents = <0>, 2807 <&bpmp TEGRA194_CLK_PLLA>, 2808 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2809 /* 2810 * PLLA supports dynamic ramp. Below initial rate is chosen 2811 * for this to work and oscillate between base rates required 2812 * for 8x and 11.025x sample rate streams. 2813 */ 2814 assigned-clock-rates = <258000000>; 2815 2816 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 2817 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 2818 interconnect-names = "dma-mem", "write"; 2819 iommus = <&smmu TEGRA194_SID_APE>; 2820 }; 2821 2822 tcu: tcu { 2823 compatible = "nvidia,tegra194-tcu"; 2824 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2825 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2826 mbox-names = "rx", "tx"; 2827 }; 2828 2829 thermal-zones { 2830 cpu { 2831 thermal-sensors = <&{/bpmp/thermal} 2832 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2833 status = "disabled"; 2834 }; 2835 2836 gpu { 2837 thermal-sensors = <&{/bpmp/thermal} 2838 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2839 status = "disabled"; 2840 }; 2841 2842 aux { 2843 thermal-sensors = <&{/bpmp/thermal} 2844 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2845 status = "disabled"; 2846 }; 2847 2848 pllx { 2849 thermal-sensors = <&{/bpmp/thermal} 2850 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2851 status = "disabled"; 2852 }; 2853 2854 ao { 2855 thermal-sensors = <&{/bpmp/thermal} 2856 TEGRA194_BPMP_THERMAL_ZONE_AO>; 2857 status = "disabled"; 2858 }; 2859 2860 tj { 2861 thermal-sensors = <&{/bpmp/thermal} 2862 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2863 status = "disabled"; 2864 }; 2865 }; 2866 2867 timer { 2868 compatible = "arm,armv8-timer"; 2869 interrupts = <GIC_PPI 13 2870 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2871 <GIC_PPI 14 2872 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2873 <GIC_PPI 11 2874 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2875 <GIC_PPI 10 2876 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2877 interrupt-parent = <&gic>; 2878 always-on; 2879 }; 2880}; 2881