1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 }; 90 91 ethernet@2490000 { 92 compatible = "nvidia,tegra194-eqos", 93 "nvidia,tegra186-eqos", 94 "snps,dwc-qos-ethernet-4.10"; 95 reg = <0x02490000 0x10000>; 96 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 98 <&bpmp TEGRA194_CLK_EQOS_AXI>, 99 <&bpmp TEGRA194_CLK_EQOS_RX>, 100 <&bpmp TEGRA194_CLK_EQOS_TX>, 101 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 102 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 103 resets = <&bpmp TEGRA194_RESET_EQOS>; 104 reset-names = "eqos"; 105 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 106 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 107 interconnect-names = "dma-mem", "write"; 108 iommus = <&smmu TEGRA194_SID_EQOS>; 109 status = "disabled"; 110 111 snps,write-requests = <1>; 112 snps,read-requests = <3>; 113 snps,burst-map = <0x7>; 114 snps,txpbl = <16>; 115 snps,rxpbl = <8>; 116 }; 117 118 aconnect@2900000 { 119 compatible = "nvidia,tegra194-aconnect", 120 "nvidia,tegra210-aconnect"; 121 clocks = <&bpmp TEGRA194_CLK_APE>, 122 <&bpmp TEGRA194_CLK_APB2APE>; 123 clock-names = "ape", "apb2ape"; 124 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges = <0x02900000 0x02900000 0x200000>; 128 status = "disabled"; 129 130 adma: dma-controller@2930000 { 131 compatible = "nvidia,tegra194-adma", 132 "nvidia,tegra186-adma"; 133 reg = <0x02930000 0x20000>; 134 interrupt-parent = <&agic>; 135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 167 #dma-cells = <1>; 168 clocks = <&bpmp TEGRA194_CLK_AHUB>; 169 clock-names = "d_audio"; 170 status = "disabled"; 171 }; 172 173 agic: interrupt-controller@2a40000 { 174 compatible = "nvidia,tegra194-agic", 175 "nvidia,tegra210-agic"; 176 #interrupt-cells = <3>; 177 interrupt-controller; 178 reg = <0x02a41000 0x1000>, 179 <0x02a42000 0x2000>; 180 interrupts = <GIC_SPI 145 181 (GIC_CPU_MASK_SIMPLE(4) | 182 IRQ_TYPE_LEVEL_HIGH)>; 183 clocks = <&bpmp TEGRA194_CLK_APE>; 184 clock-names = "clk"; 185 status = "disabled"; 186 }; 187 188 tegra_ahub: ahub@2900800 { 189 compatible = "nvidia,tegra194-ahub", 190 "nvidia,tegra186-ahub"; 191 reg = <0x02900800 0x800>; 192 clocks = <&bpmp TEGRA194_CLK_AHUB>; 193 clock-names = "ahub"; 194 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 195 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 ranges = <0x02900800 0x02900800 0x11800>; 199 status = "disabled"; 200 201 tegra_admaif: admaif@290f000 { 202 compatible = "nvidia,tegra194-admaif", 203 "nvidia,tegra186-admaif"; 204 reg = <0x0290f000 0x1000>; 205 dmas = <&adma 1>, <&adma 1>, 206 <&adma 2>, <&adma 2>, 207 <&adma 3>, <&adma 3>, 208 <&adma 4>, <&adma 4>, 209 <&adma 5>, <&adma 5>, 210 <&adma 6>, <&adma 6>, 211 <&adma 7>, <&adma 7>, 212 <&adma 8>, <&adma 8>, 213 <&adma 9>, <&adma 9>, 214 <&adma 10>, <&adma 10>, 215 <&adma 11>, <&adma 11>, 216 <&adma 12>, <&adma 12>, 217 <&adma 13>, <&adma 13>, 218 <&adma 14>, <&adma 14>, 219 <&adma 15>, <&adma 15>, 220 <&adma 16>, <&adma 16>, 221 <&adma 17>, <&adma 17>, 222 <&adma 18>, <&adma 18>, 223 <&adma 19>, <&adma 19>, 224 <&adma 20>, <&adma 20>; 225 dma-names = "rx1", "tx1", 226 "rx2", "tx2", 227 "rx3", "tx3", 228 "rx4", "tx4", 229 "rx5", "tx5", 230 "rx6", "tx6", 231 "rx7", "tx7", 232 "rx8", "tx8", 233 "rx9", "tx9", 234 "rx10", "tx10", 235 "rx11", "tx11", 236 "rx12", "tx12", 237 "rx13", "tx13", 238 "rx14", "tx14", 239 "rx15", "tx15", 240 "rx16", "tx16", 241 "rx17", "tx17", 242 "rx18", "tx18", 243 "rx19", "tx19", 244 "rx20", "tx20"; 245 status = "disabled"; 246 }; 247 248 tegra_i2s1: i2s@2901000 { 249 compatible = "nvidia,tegra194-i2s", 250 "nvidia,tegra210-i2s"; 251 reg = <0x2901000 0x100>; 252 clocks = <&bpmp TEGRA194_CLK_I2S1>, 253 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 254 clock-names = "i2s", "sync_input"; 255 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 256 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 257 assigned-clock-rates = <1536000>; 258 sound-name-prefix = "I2S1"; 259 status = "disabled"; 260 }; 261 262 tegra_i2s2: i2s@2901100 { 263 compatible = "nvidia,tegra194-i2s", 264 "nvidia,tegra210-i2s"; 265 reg = <0x2901100 0x100>; 266 clocks = <&bpmp TEGRA194_CLK_I2S2>, 267 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 268 clock-names = "i2s", "sync_input"; 269 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 270 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 271 assigned-clock-rates = <1536000>; 272 sound-name-prefix = "I2S2"; 273 status = "disabled"; 274 }; 275 276 tegra_i2s3: i2s@2901200 { 277 compatible = "nvidia,tegra194-i2s", 278 "nvidia,tegra210-i2s"; 279 reg = <0x2901200 0x100>; 280 clocks = <&bpmp TEGRA194_CLK_I2S3>, 281 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 282 clock-names = "i2s", "sync_input"; 283 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 284 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 285 assigned-clock-rates = <1536000>; 286 sound-name-prefix = "I2S3"; 287 status = "disabled"; 288 }; 289 290 tegra_i2s4: i2s@2901300 { 291 compatible = "nvidia,tegra194-i2s", 292 "nvidia,tegra210-i2s"; 293 reg = <0x2901300 0x100>; 294 clocks = <&bpmp TEGRA194_CLK_I2S4>, 295 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 296 clock-names = "i2s", "sync_input"; 297 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 298 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 299 assigned-clock-rates = <1536000>; 300 sound-name-prefix = "I2S4"; 301 status = "disabled"; 302 }; 303 304 tegra_i2s5: i2s@2901400 { 305 compatible = "nvidia,tegra194-i2s", 306 "nvidia,tegra210-i2s"; 307 reg = <0x2901400 0x100>; 308 clocks = <&bpmp TEGRA194_CLK_I2S5>, 309 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 310 clock-names = "i2s", "sync_input"; 311 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 312 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 313 assigned-clock-rates = <1536000>; 314 sound-name-prefix = "I2S5"; 315 status = "disabled"; 316 }; 317 318 tegra_i2s6: i2s@2901500 { 319 compatible = "nvidia,tegra194-i2s", 320 "nvidia,tegra210-i2s"; 321 reg = <0x2901500 0x100>; 322 clocks = <&bpmp TEGRA194_CLK_I2S6>, 323 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 324 clock-names = "i2s", "sync_input"; 325 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 326 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 327 assigned-clock-rates = <1536000>; 328 sound-name-prefix = "I2S6"; 329 status = "disabled"; 330 }; 331 332 tegra_dmic1: dmic@2904000 { 333 compatible = "nvidia,tegra194-dmic", 334 "nvidia,tegra210-dmic"; 335 reg = <0x2904000 0x100>; 336 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 337 clock-names = "dmic"; 338 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 339 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 340 assigned-clock-rates = <3072000>; 341 sound-name-prefix = "DMIC1"; 342 status = "disabled"; 343 }; 344 345 tegra_dmic2: dmic@2904100 { 346 compatible = "nvidia,tegra194-dmic", 347 "nvidia,tegra210-dmic"; 348 reg = <0x2904100 0x100>; 349 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 350 clock-names = "dmic"; 351 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 352 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 353 assigned-clock-rates = <3072000>; 354 sound-name-prefix = "DMIC2"; 355 status = "disabled"; 356 }; 357 358 tegra_dmic3: dmic@2904200 { 359 compatible = "nvidia,tegra194-dmic", 360 "nvidia,tegra210-dmic"; 361 reg = <0x2904200 0x100>; 362 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 363 clock-names = "dmic"; 364 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 365 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 366 assigned-clock-rates = <3072000>; 367 sound-name-prefix = "DMIC3"; 368 status = "disabled"; 369 }; 370 371 tegra_dmic4: dmic@2904300 { 372 compatible = "nvidia,tegra194-dmic", 373 "nvidia,tegra210-dmic"; 374 reg = <0x2904300 0x100>; 375 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 376 clock-names = "dmic"; 377 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 378 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 379 assigned-clock-rates = <3072000>; 380 sound-name-prefix = "DMIC4"; 381 status = "disabled"; 382 }; 383 384 tegra_dspk1: dspk@2905000 { 385 compatible = "nvidia,tegra194-dspk", 386 "nvidia,tegra186-dspk"; 387 reg = <0x2905000 0x100>; 388 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 389 clock-names = "dspk"; 390 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 391 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 392 assigned-clock-rates = <12288000>; 393 sound-name-prefix = "DSPK1"; 394 status = "disabled"; 395 }; 396 397 tegra_dspk2: dspk@2905100 { 398 compatible = "nvidia,tegra194-dspk", 399 "nvidia,tegra186-dspk"; 400 reg = <0x2905100 0x100>; 401 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 402 clock-names = "dspk"; 403 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 404 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 405 assigned-clock-rates = <12288000>; 406 sound-name-prefix = "DSPK2"; 407 status = "disabled"; 408 }; 409 410 tegra_sfc1: sfc@2902000 { 411 compatible = "nvidia,tegra194-sfc", 412 "nvidia,tegra210-sfc"; 413 reg = <0x2902000 0x200>; 414 sound-name-prefix = "SFC1"; 415 status = "disabled"; 416 }; 417 418 tegra_sfc2: sfc@2902200 { 419 compatible = "nvidia,tegra194-sfc", 420 "nvidia,tegra210-sfc"; 421 reg = <0x2902200 0x200>; 422 sound-name-prefix = "SFC2"; 423 status = "disabled"; 424 }; 425 426 tegra_sfc3: sfc@2902400 { 427 compatible = "nvidia,tegra194-sfc", 428 "nvidia,tegra210-sfc"; 429 reg = <0x2902400 0x200>; 430 sound-name-prefix = "SFC3"; 431 status = "disabled"; 432 }; 433 434 tegra_sfc4: sfc@2902600 { 435 compatible = "nvidia,tegra194-sfc", 436 "nvidia,tegra210-sfc"; 437 reg = <0x2902600 0x200>; 438 sound-name-prefix = "SFC4"; 439 status = "disabled"; 440 }; 441 442 tegra_mvc1: mvc@290a000 { 443 compatible = "nvidia,tegra194-mvc", 444 "nvidia,tegra210-mvc"; 445 reg = <0x290a000 0x200>; 446 sound-name-prefix = "MVC1"; 447 status = "disabled"; 448 }; 449 450 tegra_mvc2: mvc@290a200 { 451 compatible = "nvidia,tegra194-mvc", 452 "nvidia,tegra210-mvc"; 453 reg = <0x290a200 0x200>; 454 sound-name-prefix = "MVC2"; 455 status = "disabled"; 456 }; 457 458 tegra_amx1: amx@2903000 { 459 compatible = "nvidia,tegra194-amx"; 460 reg = <0x2903000 0x100>; 461 sound-name-prefix = "AMX1"; 462 status = "disabled"; 463 }; 464 465 tegra_amx2: amx@2903100 { 466 compatible = "nvidia,tegra194-amx"; 467 reg = <0x2903100 0x100>; 468 sound-name-prefix = "AMX2"; 469 status = "disabled"; 470 }; 471 472 tegra_amx3: amx@2903200 { 473 compatible = "nvidia,tegra194-amx"; 474 reg = <0x2903200 0x100>; 475 sound-name-prefix = "AMX3"; 476 status = "disabled"; 477 }; 478 479 tegra_amx4: amx@2903300 { 480 compatible = "nvidia,tegra194-amx"; 481 reg = <0x2903300 0x100>; 482 sound-name-prefix = "AMX4"; 483 status = "disabled"; 484 }; 485 486 tegra_adx1: adx@2903800 { 487 compatible = "nvidia,tegra194-adx", 488 "nvidia,tegra210-adx"; 489 reg = <0x2903800 0x100>; 490 sound-name-prefix = "ADX1"; 491 status = "disabled"; 492 }; 493 494 tegra_adx2: adx@2903900 { 495 compatible = "nvidia,tegra194-adx", 496 "nvidia,tegra210-adx"; 497 reg = <0x2903900 0x100>; 498 sound-name-prefix = "ADX2"; 499 status = "disabled"; 500 }; 501 502 tegra_adx3: adx@2903a00 { 503 compatible = "nvidia,tegra194-adx", 504 "nvidia,tegra210-adx"; 505 reg = <0x2903a00 0x100>; 506 sound-name-prefix = "ADX3"; 507 status = "disabled"; 508 }; 509 510 tegra_adx4: adx@2903b00 { 511 compatible = "nvidia,tegra194-adx", 512 "nvidia,tegra210-adx"; 513 reg = <0x2903b00 0x100>; 514 sound-name-prefix = "ADX4"; 515 status = "disabled"; 516 }; 517 518 tegra_amixer: amixer@290bb00 { 519 compatible = "nvidia,tegra194-amixer", 520 "nvidia,tegra210-amixer"; 521 reg = <0x290bb00 0x800>; 522 sound-name-prefix = "MIXER1"; 523 status = "disabled"; 524 }; 525 }; 526 }; 527 528 pinmux: pinmux@2430000 { 529 compatible = "nvidia,tegra194-pinmux"; 530 reg = <0x2430000 0x17000>, 531 <0xc300000 0x4000>; 532 533 status = "okay"; 534 535 pex_rst_c5_out_state: pex_rst_c5_out { 536 pex_rst { 537 nvidia,pins = "pex_l5_rst_n_pgg1"; 538 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 539 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 540 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 541 nvidia,tristate = <TEGRA_PIN_DISABLE>; 542 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 543 }; 544 }; 545 546 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 547 clkreq { 548 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 549 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 550 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 551 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 552 nvidia,tristate = <TEGRA_PIN_DISABLE>; 553 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 554 }; 555 }; 556 }; 557 558 mc: memory-controller@2c00000 { 559 compatible = "nvidia,tegra194-mc"; 560 reg = <0x02c00000 0x100000>, 561 <0x02b80000 0x040000>, 562 <0x01700000 0x100000>; 563 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 564 #interconnect-cells = <1>; 565 status = "disabled"; 566 567 #address-cells = <2>; 568 #size-cells = <2>; 569 570 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 571 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 572 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 573 574 /* 575 * Bit 39 of addresses passing through the memory 576 * controller selects the XBAR format used when memory 577 * is accessed. This is used to transparently access 578 * memory in the XBAR format used by the discrete GPU 579 * (bit 39 set) or Tegra (bit 39 clear). 580 * 581 * As a consequence, the operating system must ensure 582 * that bit 39 is never used implicitly, for example 583 * via an I/O virtual address mapping of an IOMMU. If 584 * devices require access to the XBAR switch, their 585 * drivers must set this bit explicitly. 586 * 587 * Limit the DMA range for memory clients to [38:0]. 588 */ 589 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 590 591 emc: external-memory-controller@2c60000 { 592 compatible = "nvidia,tegra194-emc"; 593 reg = <0x0 0x02c60000 0x0 0x90000>, 594 <0x0 0x01780000 0x0 0x80000>; 595 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&bpmp TEGRA194_CLK_EMC>; 597 clock-names = "emc"; 598 599 #interconnect-cells = <0>; 600 601 nvidia,bpmp = <&bpmp>; 602 }; 603 }; 604 605 uarta: serial@3100000 { 606 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 607 reg = <0x03100000 0x40>; 608 reg-shift = <2>; 609 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&bpmp TEGRA194_CLK_UARTA>; 611 clock-names = "serial"; 612 resets = <&bpmp TEGRA194_RESET_UARTA>; 613 reset-names = "serial"; 614 status = "disabled"; 615 }; 616 617 uartb: serial@3110000 { 618 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 619 reg = <0x03110000 0x40>; 620 reg-shift = <2>; 621 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&bpmp TEGRA194_CLK_UARTB>; 623 clock-names = "serial"; 624 resets = <&bpmp TEGRA194_RESET_UARTB>; 625 reset-names = "serial"; 626 status = "disabled"; 627 }; 628 629 uartd: serial@3130000 { 630 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 631 reg = <0x03130000 0x40>; 632 reg-shift = <2>; 633 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&bpmp TEGRA194_CLK_UARTD>; 635 clock-names = "serial"; 636 resets = <&bpmp TEGRA194_RESET_UARTD>; 637 reset-names = "serial"; 638 status = "disabled"; 639 }; 640 641 uarte: serial@3140000 { 642 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 643 reg = <0x03140000 0x40>; 644 reg-shift = <2>; 645 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&bpmp TEGRA194_CLK_UARTE>; 647 clock-names = "serial"; 648 resets = <&bpmp TEGRA194_RESET_UARTE>; 649 reset-names = "serial"; 650 status = "disabled"; 651 }; 652 653 uartf: serial@3150000 { 654 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 655 reg = <0x03150000 0x40>; 656 reg-shift = <2>; 657 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&bpmp TEGRA194_CLK_UARTF>; 659 clock-names = "serial"; 660 resets = <&bpmp TEGRA194_RESET_UARTF>; 661 reset-names = "serial"; 662 status = "disabled"; 663 }; 664 665 gen1_i2c: i2c@3160000 { 666 compatible = "nvidia,tegra194-i2c"; 667 reg = <0x03160000 0x10000>; 668 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 clocks = <&bpmp TEGRA194_CLK_I2C1>; 672 clock-names = "div-clk"; 673 resets = <&bpmp TEGRA194_RESET_I2C1>; 674 reset-names = "i2c"; 675 status = "disabled"; 676 }; 677 678 uarth: serial@3170000 { 679 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 680 reg = <0x03170000 0x40>; 681 reg-shift = <2>; 682 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&bpmp TEGRA194_CLK_UARTH>; 684 clock-names = "serial"; 685 resets = <&bpmp TEGRA194_RESET_UARTH>; 686 reset-names = "serial"; 687 status = "disabled"; 688 }; 689 690 cam_i2c: i2c@3180000 { 691 compatible = "nvidia,tegra194-i2c"; 692 reg = <0x03180000 0x10000>; 693 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 clocks = <&bpmp TEGRA194_CLK_I2C3>; 697 clock-names = "div-clk"; 698 resets = <&bpmp TEGRA194_RESET_I2C3>; 699 reset-names = "i2c"; 700 status = "disabled"; 701 }; 702 703 /* shares pads with dpaux1 */ 704 dp_aux_ch1_i2c: i2c@3190000 { 705 compatible = "nvidia,tegra194-i2c"; 706 reg = <0x03190000 0x10000>; 707 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 clocks = <&bpmp TEGRA194_CLK_I2C4>; 711 clock-names = "div-clk"; 712 resets = <&bpmp TEGRA194_RESET_I2C4>; 713 reset-names = "i2c"; 714 pinctrl-0 = <&state_dpaux1_i2c>; 715 pinctrl-1 = <&state_dpaux1_off>; 716 pinctrl-names = "default", "idle"; 717 status = "disabled"; 718 }; 719 720 /* shares pads with dpaux0 */ 721 dp_aux_ch0_i2c: i2c@31b0000 { 722 compatible = "nvidia,tegra194-i2c"; 723 reg = <0x031b0000 0x10000>; 724 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 clocks = <&bpmp TEGRA194_CLK_I2C6>; 728 clock-names = "div-clk"; 729 resets = <&bpmp TEGRA194_RESET_I2C6>; 730 reset-names = "i2c"; 731 pinctrl-0 = <&state_dpaux0_i2c>; 732 pinctrl-1 = <&state_dpaux0_off>; 733 pinctrl-names = "default", "idle"; 734 status = "disabled"; 735 }; 736 737 /* shares pads with dpaux2 */ 738 dp_aux_ch2_i2c: i2c@31c0000 { 739 compatible = "nvidia,tegra194-i2c"; 740 reg = <0x031c0000 0x10000>; 741 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 clocks = <&bpmp TEGRA194_CLK_I2C7>; 745 clock-names = "div-clk"; 746 resets = <&bpmp TEGRA194_RESET_I2C7>; 747 reset-names = "i2c"; 748 pinctrl-0 = <&state_dpaux2_i2c>; 749 pinctrl-1 = <&state_dpaux2_off>; 750 pinctrl-names = "default", "idle"; 751 status = "disabled"; 752 }; 753 754 /* shares pads with dpaux3 */ 755 dp_aux_ch3_i2c: i2c@31e0000 { 756 compatible = "nvidia,tegra194-i2c"; 757 reg = <0x031e0000 0x10000>; 758 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 clocks = <&bpmp TEGRA194_CLK_I2C9>; 762 clock-names = "div-clk"; 763 resets = <&bpmp TEGRA194_RESET_I2C9>; 764 reset-names = "i2c"; 765 pinctrl-0 = <&state_dpaux3_i2c>; 766 pinctrl-1 = <&state_dpaux3_off>; 767 pinctrl-names = "default", "idle"; 768 status = "disabled"; 769 }; 770 771 spi@3270000 { 772 compatible = "nvidia,tegra194-qspi"; 773 reg = <0x3270000 0x1000>; 774 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 775 #address-cells = <1>; 776 #size-cells = <0>; 777 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 778 <&bpmp TEGRA194_CLK_QSPI0_PM>; 779 clock-names = "qspi", "qspi_out"; 780 resets = <&bpmp TEGRA194_RESET_QSPI0>; 781 reset-names = "qspi"; 782 status = "disabled"; 783 }; 784 785 spi@3300000 { 786 compatible = "nvidia,tegra194-qspi"; 787 reg = <0x3300000 0x1000>; 788 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 792 <&bpmp TEGRA194_CLK_QSPI1_PM>; 793 clock-names = "qspi", "qspi_out"; 794 resets = <&bpmp TEGRA194_RESET_QSPI1>; 795 reset-names = "qspi"; 796 status = "disabled"; 797 }; 798 799 pwm1: pwm@3280000 { 800 compatible = "nvidia,tegra194-pwm", 801 "nvidia,tegra186-pwm"; 802 reg = <0x3280000 0x10000>; 803 clocks = <&bpmp TEGRA194_CLK_PWM1>; 804 clock-names = "pwm"; 805 resets = <&bpmp TEGRA194_RESET_PWM1>; 806 reset-names = "pwm"; 807 status = "disabled"; 808 #pwm-cells = <2>; 809 }; 810 811 pwm2: pwm@3290000 { 812 compatible = "nvidia,tegra194-pwm", 813 "nvidia,tegra186-pwm"; 814 reg = <0x3290000 0x10000>; 815 clocks = <&bpmp TEGRA194_CLK_PWM2>; 816 clock-names = "pwm"; 817 resets = <&bpmp TEGRA194_RESET_PWM2>; 818 reset-names = "pwm"; 819 status = "disabled"; 820 #pwm-cells = <2>; 821 }; 822 823 pwm3: pwm@32a0000 { 824 compatible = "nvidia,tegra194-pwm", 825 "nvidia,tegra186-pwm"; 826 reg = <0x32a0000 0x10000>; 827 clocks = <&bpmp TEGRA194_CLK_PWM3>; 828 clock-names = "pwm"; 829 resets = <&bpmp TEGRA194_RESET_PWM3>; 830 reset-names = "pwm"; 831 status = "disabled"; 832 #pwm-cells = <2>; 833 }; 834 835 pwm5: pwm@32c0000 { 836 compatible = "nvidia,tegra194-pwm", 837 "nvidia,tegra186-pwm"; 838 reg = <0x32c0000 0x10000>; 839 clocks = <&bpmp TEGRA194_CLK_PWM5>; 840 clock-names = "pwm"; 841 resets = <&bpmp TEGRA194_RESET_PWM5>; 842 reset-names = "pwm"; 843 status = "disabled"; 844 #pwm-cells = <2>; 845 }; 846 847 pwm6: pwm@32d0000 { 848 compatible = "nvidia,tegra194-pwm", 849 "nvidia,tegra186-pwm"; 850 reg = <0x32d0000 0x10000>; 851 clocks = <&bpmp TEGRA194_CLK_PWM6>; 852 clock-names = "pwm"; 853 resets = <&bpmp TEGRA194_RESET_PWM6>; 854 reset-names = "pwm"; 855 status = "disabled"; 856 #pwm-cells = <2>; 857 }; 858 859 pwm7: pwm@32e0000 { 860 compatible = "nvidia,tegra194-pwm", 861 "nvidia,tegra186-pwm"; 862 reg = <0x32e0000 0x10000>; 863 clocks = <&bpmp TEGRA194_CLK_PWM7>; 864 clock-names = "pwm"; 865 resets = <&bpmp TEGRA194_RESET_PWM7>; 866 reset-names = "pwm"; 867 status = "disabled"; 868 #pwm-cells = <2>; 869 }; 870 871 pwm8: pwm@32f0000 { 872 compatible = "nvidia,tegra194-pwm", 873 "nvidia,tegra186-pwm"; 874 reg = <0x32f0000 0x10000>; 875 clocks = <&bpmp TEGRA194_CLK_PWM8>; 876 clock-names = "pwm"; 877 resets = <&bpmp TEGRA194_RESET_PWM8>; 878 reset-names = "pwm"; 879 status = "disabled"; 880 #pwm-cells = <2>; 881 }; 882 883 sdmmc1: mmc@3400000 { 884 compatible = "nvidia,tegra194-sdhci"; 885 reg = <0x03400000 0x10000>; 886 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 888 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 889 clock-names = "sdhci", "tmclk"; 890 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 891 reset-names = "sdhci"; 892 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 893 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 894 interconnect-names = "dma-mem", "write"; 895 iommus = <&smmu TEGRA194_SID_SDMMC1>; 896 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 897 pinctrl-0 = <&sdmmc1_3v3>; 898 pinctrl-1 = <&sdmmc1_1v8>; 899 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 900 <0x07>; 901 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 902 <0x07>; 903 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 904 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 905 <0x07>; 906 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 907 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 908 nvidia,default-tap = <0x9>; 909 nvidia,default-trim = <0x5>; 910 sd-uhs-sdr25; 911 sd-uhs-sdr50; 912 sd-uhs-ddr50; 913 sd-uhs-sdr104; 914 status = "disabled"; 915 }; 916 917 sdmmc3: mmc@3440000 { 918 compatible = "nvidia,tegra194-sdhci"; 919 reg = <0x03440000 0x10000>; 920 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 922 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 923 clock-names = "sdhci", "tmclk"; 924 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 925 reset-names = "sdhci"; 926 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 927 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 928 interconnect-names = "dma-mem", "write"; 929 iommus = <&smmu TEGRA194_SID_SDMMC3>; 930 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 931 pinctrl-0 = <&sdmmc3_3v3>; 932 pinctrl-1 = <&sdmmc3_1v8>; 933 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 934 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 935 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 936 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 937 <0x07>; 938 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 939 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 940 <0x07>; 941 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 942 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 943 nvidia,default-tap = <0x9>; 944 nvidia,default-trim = <0x5>; 945 sd-uhs-sdr25; 946 sd-uhs-sdr50; 947 sd-uhs-ddr50; 948 sd-uhs-sdr104; 949 status = "disabled"; 950 }; 951 952 sdmmc4: mmc@3460000 { 953 compatible = "nvidia,tegra194-sdhci"; 954 reg = <0x03460000 0x10000>; 955 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 957 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 958 clock-names = "sdhci", "tmclk"; 959 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 960 <&bpmp TEGRA194_CLK_PLLC4>; 961 assigned-clock-parents = 962 <&bpmp TEGRA194_CLK_PLLC4>; 963 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 964 reset-names = "sdhci"; 965 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 966 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 967 interconnect-names = "dma-mem", "write"; 968 iommus = <&smmu TEGRA194_SID_SDMMC4>; 969 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 970 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 971 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 972 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 973 <0x0a>; 974 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 975 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 976 <0x0a>; 977 nvidia,default-tap = <0x8>; 978 nvidia,default-trim = <0x14>; 979 nvidia,dqs-trim = <40>; 980 cap-mmc-highspeed; 981 mmc-ddr-1_8v; 982 mmc-hs200-1_8v; 983 mmc-hs400-1_8v; 984 mmc-hs400-enhanced-strobe; 985 supports-cqe; 986 status = "disabled"; 987 }; 988 989 hda@3510000 { 990 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 991 reg = <0x3510000 0x10000>; 992 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&bpmp TEGRA194_CLK_HDA>, 994 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 995 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 996 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 997 resets = <&bpmp TEGRA194_RESET_HDA>, 998 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>, 999 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>; 1000 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1001 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1002 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1003 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1004 interconnect-names = "dma-mem", "write"; 1005 iommus = <&smmu TEGRA194_SID_HDA>; 1006 status = "disabled"; 1007 }; 1008 1009 xusb_padctl: padctl@3520000 { 1010 compatible = "nvidia,tegra194-xusb-padctl"; 1011 reg = <0x03520000 0x1000>, 1012 <0x03540000 0x1000>; 1013 reg-names = "padctl", "ao"; 1014 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1015 1016 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1017 reset-names = "padctl"; 1018 1019 status = "disabled"; 1020 1021 pads { 1022 usb2 { 1023 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1024 clock-names = "trk"; 1025 1026 lanes { 1027 usb2-0 { 1028 nvidia,function = "xusb"; 1029 status = "disabled"; 1030 #phy-cells = <0>; 1031 }; 1032 1033 usb2-1 { 1034 nvidia,function = "xusb"; 1035 status = "disabled"; 1036 #phy-cells = <0>; 1037 }; 1038 1039 usb2-2 { 1040 nvidia,function = "xusb"; 1041 status = "disabled"; 1042 #phy-cells = <0>; 1043 }; 1044 1045 usb2-3 { 1046 nvidia,function = "xusb"; 1047 status = "disabled"; 1048 #phy-cells = <0>; 1049 }; 1050 }; 1051 }; 1052 1053 usb3 { 1054 lanes { 1055 usb3-0 { 1056 nvidia,function = "xusb"; 1057 status = "disabled"; 1058 #phy-cells = <0>; 1059 }; 1060 1061 usb3-1 { 1062 nvidia,function = "xusb"; 1063 status = "disabled"; 1064 #phy-cells = <0>; 1065 }; 1066 1067 usb3-2 { 1068 nvidia,function = "xusb"; 1069 status = "disabled"; 1070 #phy-cells = <0>; 1071 }; 1072 1073 usb3-3 { 1074 nvidia,function = "xusb"; 1075 status = "disabled"; 1076 #phy-cells = <0>; 1077 }; 1078 }; 1079 }; 1080 }; 1081 1082 ports { 1083 usb2-0 { 1084 status = "disabled"; 1085 }; 1086 1087 usb2-1 { 1088 status = "disabled"; 1089 }; 1090 1091 usb2-2 { 1092 status = "disabled"; 1093 }; 1094 1095 usb2-3 { 1096 status = "disabled"; 1097 }; 1098 1099 usb3-0 { 1100 status = "disabled"; 1101 }; 1102 1103 usb3-1 { 1104 status = "disabled"; 1105 }; 1106 1107 usb3-2 { 1108 status = "disabled"; 1109 }; 1110 1111 usb3-3 { 1112 status = "disabled"; 1113 }; 1114 }; 1115 }; 1116 1117 usb@3550000 { 1118 compatible = "nvidia,tegra194-xudc"; 1119 reg = <0x03550000 0x8000>, 1120 <0x03558000 0x1000>; 1121 reg-names = "base", "fpci"; 1122 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1124 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1125 <&bpmp TEGRA194_CLK_XUSB_SS>, 1126 <&bpmp TEGRA194_CLK_XUSB_FS>; 1127 clock-names = "dev", "ss", "ss_src", "fs_src"; 1128 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1129 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1130 interconnect-names = "dma-mem", "write"; 1131 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1132 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1133 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1134 power-domain-names = "dev", "ss"; 1135 nvidia,xusb-padctl = <&xusb_padctl>; 1136 status = "disabled"; 1137 }; 1138 1139 usb@3610000 { 1140 compatible = "nvidia,tegra194-xusb"; 1141 reg = <0x03610000 0x40000>, 1142 <0x03600000 0x10000>; 1143 reg-names = "hcd", "fpci"; 1144 1145 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1147 1148 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1149 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1150 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1151 <&bpmp TEGRA194_CLK_XUSB_SS>, 1152 <&bpmp TEGRA194_CLK_CLK_M>, 1153 <&bpmp TEGRA194_CLK_XUSB_FS>, 1154 <&bpmp TEGRA194_CLK_UTMIPLL>, 1155 <&bpmp TEGRA194_CLK_CLK_M>, 1156 <&bpmp TEGRA194_CLK_PLLE>; 1157 clock-names = "xusb_host", "xusb_falcon_src", 1158 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1159 "xusb_fs_src", "pll_u_480m", "clk_m", 1160 "pll_e"; 1161 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1162 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1163 interconnect-names = "dma-mem", "write"; 1164 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1165 1166 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1167 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1168 power-domain-names = "xusb_host", "xusb_ss"; 1169 1170 nvidia,xusb-padctl = <&xusb_padctl>; 1171 status = "disabled"; 1172 }; 1173 1174 fuse@3820000 { 1175 compatible = "nvidia,tegra194-efuse"; 1176 reg = <0x03820000 0x10000>; 1177 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1178 clock-names = "fuse"; 1179 }; 1180 1181 gic: interrupt-controller@3881000 { 1182 compatible = "arm,gic-400"; 1183 #interrupt-cells = <3>; 1184 interrupt-controller; 1185 reg = <0x03881000 0x1000>, 1186 <0x03882000 0x2000>, 1187 <0x03884000 0x2000>, 1188 <0x03886000 0x2000>; 1189 interrupts = <GIC_PPI 9 1190 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1191 interrupt-parent = <&gic>; 1192 }; 1193 1194 cec@3960000 { 1195 compatible = "nvidia,tegra194-cec"; 1196 reg = <0x03960000 0x10000>; 1197 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&bpmp TEGRA194_CLK_CEC>; 1199 clock-names = "cec"; 1200 status = "disabled"; 1201 }; 1202 1203 hsp_top0: hsp@3c00000 { 1204 compatible = "nvidia,tegra194-hsp"; 1205 reg = <0x03c00000 0xa0000>; 1206 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1215 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1216 "shared3", "shared4", "shared5", "shared6", 1217 "shared7"; 1218 #mbox-cells = <2>; 1219 }; 1220 1221 p2u_hsio_0: phy@3e10000 { 1222 compatible = "nvidia,tegra194-p2u"; 1223 reg = <0x03e10000 0x10000>; 1224 reg-names = "ctl"; 1225 1226 #phy-cells = <0>; 1227 }; 1228 1229 p2u_hsio_1: phy@3e20000 { 1230 compatible = "nvidia,tegra194-p2u"; 1231 reg = <0x03e20000 0x10000>; 1232 reg-names = "ctl"; 1233 1234 #phy-cells = <0>; 1235 }; 1236 1237 p2u_hsio_2: phy@3e30000 { 1238 compatible = "nvidia,tegra194-p2u"; 1239 reg = <0x03e30000 0x10000>; 1240 reg-names = "ctl"; 1241 1242 #phy-cells = <0>; 1243 }; 1244 1245 p2u_hsio_3: phy@3e40000 { 1246 compatible = "nvidia,tegra194-p2u"; 1247 reg = <0x03e40000 0x10000>; 1248 reg-names = "ctl"; 1249 1250 #phy-cells = <0>; 1251 }; 1252 1253 p2u_hsio_4: phy@3e50000 { 1254 compatible = "nvidia,tegra194-p2u"; 1255 reg = <0x03e50000 0x10000>; 1256 reg-names = "ctl"; 1257 1258 #phy-cells = <0>; 1259 }; 1260 1261 p2u_hsio_5: phy@3e60000 { 1262 compatible = "nvidia,tegra194-p2u"; 1263 reg = <0x03e60000 0x10000>; 1264 reg-names = "ctl"; 1265 1266 #phy-cells = <0>; 1267 }; 1268 1269 p2u_hsio_6: phy@3e70000 { 1270 compatible = "nvidia,tegra194-p2u"; 1271 reg = <0x03e70000 0x10000>; 1272 reg-names = "ctl"; 1273 1274 #phy-cells = <0>; 1275 }; 1276 1277 p2u_hsio_7: phy@3e80000 { 1278 compatible = "nvidia,tegra194-p2u"; 1279 reg = <0x03e80000 0x10000>; 1280 reg-names = "ctl"; 1281 1282 #phy-cells = <0>; 1283 }; 1284 1285 p2u_hsio_8: phy@3e90000 { 1286 compatible = "nvidia,tegra194-p2u"; 1287 reg = <0x03e90000 0x10000>; 1288 reg-names = "ctl"; 1289 1290 #phy-cells = <0>; 1291 }; 1292 1293 p2u_hsio_9: phy@3ea0000 { 1294 compatible = "nvidia,tegra194-p2u"; 1295 reg = <0x03ea0000 0x10000>; 1296 reg-names = "ctl"; 1297 1298 #phy-cells = <0>; 1299 }; 1300 1301 p2u_nvhs_0: phy@3eb0000 { 1302 compatible = "nvidia,tegra194-p2u"; 1303 reg = <0x03eb0000 0x10000>; 1304 reg-names = "ctl"; 1305 1306 #phy-cells = <0>; 1307 }; 1308 1309 p2u_nvhs_1: phy@3ec0000 { 1310 compatible = "nvidia,tegra194-p2u"; 1311 reg = <0x03ec0000 0x10000>; 1312 reg-names = "ctl"; 1313 1314 #phy-cells = <0>; 1315 }; 1316 1317 p2u_nvhs_2: phy@3ed0000 { 1318 compatible = "nvidia,tegra194-p2u"; 1319 reg = <0x03ed0000 0x10000>; 1320 reg-names = "ctl"; 1321 1322 #phy-cells = <0>; 1323 }; 1324 1325 p2u_nvhs_3: phy@3ee0000 { 1326 compatible = "nvidia,tegra194-p2u"; 1327 reg = <0x03ee0000 0x10000>; 1328 reg-names = "ctl"; 1329 1330 #phy-cells = <0>; 1331 }; 1332 1333 p2u_nvhs_4: phy@3ef0000 { 1334 compatible = "nvidia,tegra194-p2u"; 1335 reg = <0x03ef0000 0x10000>; 1336 reg-names = "ctl"; 1337 1338 #phy-cells = <0>; 1339 }; 1340 1341 p2u_nvhs_5: phy@3f00000 { 1342 compatible = "nvidia,tegra194-p2u"; 1343 reg = <0x03f00000 0x10000>; 1344 reg-names = "ctl"; 1345 1346 #phy-cells = <0>; 1347 }; 1348 1349 p2u_nvhs_6: phy@3f10000 { 1350 compatible = "nvidia,tegra194-p2u"; 1351 reg = <0x03f10000 0x10000>; 1352 reg-names = "ctl"; 1353 1354 #phy-cells = <0>; 1355 }; 1356 1357 p2u_nvhs_7: phy@3f20000 { 1358 compatible = "nvidia,tegra194-p2u"; 1359 reg = <0x03f20000 0x10000>; 1360 reg-names = "ctl"; 1361 1362 #phy-cells = <0>; 1363 }; 1364 1365 p2u_hsio_10: phy@3f30000 { 1366 compatible = "nvidia,tegra194-p2u"; 1367 reg = <0x03f30000 0x10000>; 1368 reg-names = "ctl"; 1369 1370 #phy-cells = <0>; 1371 }; 1372 1373 p2u_hsio_11: phy@3f40000 { 1374 compatible = "nvidia,tegra194-p2u"; 1375 reg = <0x03f40000 0x10000>; 1376 reg-names = "ctl"; 1377 1378 #phy-cells = <0>; 1379 }; 1380 1381 hsp_aon: hsp@c150000 { 1382 compatible = "nvidia,tegra194-hsp"; 1383 reg = <0x0c150000 0x90000>; 1384 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1388 /* 1389 * Shared interrupt 0 is routed only to AON/SPE, so 1390 * we only have 4 shared interrupts for the CCPLEX. 1391 */ 1392 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1393 #mbox-cells = <2>; 1394 }; 1395 1396 gen2_i2c: i2c@c240000 { 1397 compatible = "nvidia,tegra194-i2c"; 1398 reg = <0x0c240000 0x10000>; 1399 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1400 #address-cells = <1>; 1401 #size-cells = <0>; 1402 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1403 clock-names = "div-clk"; 1404 resets = <&bpmp TEGRA194_RESET_I2C2>; 1405 reset-names = "i2c"; 1406 status = "disabled"; 1407 }; 1408 1409 gen8_i2c: i2c@c250000 { 1410 compatible = "nvidia,tegra194-i2c"; 1411 reg = <0x0c250000 0x10000>; 1412 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1416 clock-names = "div-clk"; 1417 resets = <&bpmp TEGRA194_RESET_I2C8>; 1418 reset-names = "i2c"; 1419 status = "disabled"; 1420 }; 1421 1422 uartc: serial@c280000 { 1423 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1424 reg = <0x0c280000 0x40>; 1425 reg-shift = <2>; 1426 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1427 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1428 clock-names = "serial"; 1429 resets = <&bpmp TEGRA194_RESET_UARTC>; 1430 reset-names = "serial"; 1431 status = "disabled"; 1432 }; 1433 1434 uartg: serial@c290000 { 1435 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1436 reg = <0x0c290000 0x40>; 1437 reg-shift = <2>; 1438 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1439 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1440 clock-names = "serial"; 1441 resets = <&bpmp TEGRA194_RESET_UARTG>; 1442 reset-names = "serial"; 1443 status = "disabled"; 1444 }; 1445 1446 rtc: rtc@c2a0000 { 1447 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1448 reg = <0x0c2a0000 0x10000>; 1449 interrupt-parent = <&pmc>; 1450 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1451 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1452 clock-names = "rtc"; 1453 status = "disabled"; 1454 }; 1455 1456 gpio_aon: gpio@c2f0000 { 1457 compatible = "nvidia,tegra194-gpio-aon"; 1458 reg-names = "security", "gpio"; 1459 reg = <0xc2f0000 0x1000>, 1460 <0xc2f1000 0x1000>; 1461 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1465 gpio-controller; 1466 #gpio-cells = <2>; 1467 interrupt-controller; 1468 #interrupt-cells = <2>; 1469 }; 1470 1471 pwm4: pwm@c340000 { 1472 compatible = "nvidia,tegra194-pwm", 1473 "nvidia,tegra186-pwm"; 1474 reg = <0xc340000 0x10000>; 1475 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1476 clock-names = "pwm"; 1477 resets = <&bpmp TEGRA194_RESET_PWM4>; 1478 reset-names = "pwm"; 1479 status = "disabled"; 1480 #pwm-cells = <2>; 1481 }; 1482 1483 pmc: pmc@c360000 { 1484 compatible = "nvidia,tegra194-pmc"; 1485 reg = <0x0c360000 0x10000>, 1486 <0x0c370000 0x10000>, 1487 <0x0c380000 0x10000>, 1488 <0x0c390000 0x10000>, 1489 <0x0c3a0000 0x10000>; 1490 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1491 1492 #interrupt-cells = <2>; 1493 interrupt-controller; 1494 sdmmc1_3v3: sdmmc1-3v3 { 1495 pins = "sdmmc1-hv"; 1496 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1497 }; 1498 1499 sdmmc1_1v8: sdmmc1-1v8 { 1500 pins = "sdmmc1-hv"; 1501 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1502 }; 1503 sdmmc3_3v3: sdmmc3-3v3 { 1504 pins = "sdmmc3-hv"; 1505 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1506 }; 1507 1508 sdmmc3_1v8: sdmmc3-1v8 { 1509 pins = "sdmmc3-hv"; 1510 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1511 }; 1512 1513 }; 1514 1515 iommu@10000000 { 1516 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1517 reg = <0x10000000 0x800000>; 1518 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1549 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1583 stream-match-mask = <0x7f80>; 1584 #global-interrupts = <1>; 1585 #iommu-cells = <1>; 1586 1587 nvidia,memory-controller = <&mc>; 1588 status = "disabled"; 1589 }; 1590 1591 smmu: iommu@12000000 { 1592 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1593 reg = <0x12000000 0x800000>, 1594 <0x11000000 0x800000>; 1595 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1661 stream-match-mask = <0x7f80>; 1662 #global-interrupts = <2>; 1663 #iommu-cells = <1>; 1664 1665 nvidia,memory-controller = <&mc>; 1666 status = "okay"; 1667 }; 1668 1669 host1x@13e00000 { 1670 compatible = "nvidia,tegra194-host1x"; 1671 reg = <0x13e00000 0x10000>, 1672 <0x13e10000 0x10000>; 1673 reg-names = "hypervisor", "vm"; 1674 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1676 interrupt-names = "syncpt", "host1x"; 1677 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1678 clock-names = "host1x"; 1679 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1680 reset-names = "host1x"; 1681 1682 #address-cells = <1>; 1683 #size-cells = <1>; 1684 1685 ranges = <0x15000000 0x15000000 0x01000000>; 1686 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1687 interconnect-names = "dma-mem"; 1688 iommus = <&smmu TEGRA194_SID_HOST1X>; 1689 1690 nvdec@15140000 { 1691 compatible = "nvidia,tegra194-nvdec"; 1692 reg = <0x15140000 0x00040000>; 1693 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1694 clock-names = "nvdec"; 1695 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1696 reset-names = "nvdec"; 1697 1698 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1699 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1700 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1701 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1702 interconnect-names = "dma-mem", "read-1", "write"; 1703 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1704 dma-coherent; 1705 1706 nvidia,host1x-class = <0xf5>; 1707 }; 1708 1709 display-hub@15200000 { 1710 compatible = "nvidia,tegra194-display"; 1711 reg = <0x15200000 0x00040000>; 1712 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1713 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1714 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1715 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1716 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1717 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1718 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1719 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1720 "wgrp3", "wgrp4", "wgrp5"; 1721 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1722 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1723 clock-names = "disp", "hub"; 1724 status = "disabled"; 1725 1726 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1727 1728 #address-cells = <1>; 1729 #size-cells = <1>; 1730 1731 ranges = <0x15200000 0x15200000 0x40000>; 1732 1733 display@15200000 { 1734 compatible = "nvidia,tegra194-dc"; 1735 reg = <0x15200000 0x10000>; 1736 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1737 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1738 clock-names = "dc"; 1739 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1740 reset-names = "dc"; 1741 1742 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1743 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1744 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1745 interconnect-names = "dma-mem", "read-1"; 1746 1747 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1748 nvidia,head = <0>; 1749 }; 1750 1751 display@15210000 { 1752 compatible = "nvidia,tegra194-dc"; 1753 reg = <0x15210000 0x10000>; 1754 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1755 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1756 clock-names = "dc"; 1757 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1758 reset-names = "dc"; 1759 1760 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1761 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1762 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1763 interconnect-names = "dma-mem", "read-1"; 1764 1765 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1766 nvidia,head = <1>; 1767 }; 1768 1769 display@15220000 { 1770 compatible = "nvidia,tegra194-dc"; 1771 reg = <0x15220000 0x10000>; 1772 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1773 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1774 clock-names = "dc"; 1775 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1776 reset-names = "dc"; 1777 1778 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1779 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1780 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1781 interconnect-names = "dma-mem", "read-1"; 1782 1783 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1784 nvidia,head = <2>; 1785 }; 1786 1787 display@15230000 { 1788 compatible = "nvidia,tegra194-dc"; 1789 reg = <0x15230000 0x10000>; 1790 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1791 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1792 clock-names = "dc"; 1793 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1794 reset-names = "dc"; 1795 1796 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1797 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1798 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1799 interconnect-names = "dma-mem", "read-1"; 1800 1801 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1802 nvidia,head = <3>; 1803 }; 1804 }; 1805 1806 vic@15340000 { 1807 compatible = "nvidia,tegra194-vic"; 1808 reg = <0x15340000 0x00040000>; 1809 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1810 clocks = <&bpmp TEGRA194_CLK_VIC>; 1811 clock-names = "vic"; 1812 resets = <&bpmp TEGRA194_RESET_VIC>; 1813 reset-names = "vic"; 1814 1815 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1816 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1817 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1818 interconnect-names = "dma-mem", "write"; 1819 iommus = <&smmu TEGRA194_SID_VIC>; 1820 dma-coherent; 1821 }; 1822 1823 nvjpg@15380000 { 1824 compatible = "nvidia,tegra194-nvjpg"; 1825 reg = <0x15380000 0x40000>; 1826 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1827 clock-names = "nvjpg"; 1828 resets = <&bpmp TEGRA194_RESET_NVJPG>; 1829 reset-names = "nvjpg"; 1830 1831 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1832 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1833 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1834 interconnect-names = "dma-mem", "write"; 1835 iommus = <&smmu TEGRA194_SID_NVJPG>; 1836 dma-coherent; 1837 }; 1838 1839 nvdec@15480000 { 1840 compatible = "nvidia,tegra194-nvdec"; 1841 reg = <0x15480000 0x00040000>; 1842 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 1843 clock-names = "nvdec"; 1844 resets = <&bpmp TEGRA194_RESET_NVDEC>; 1845 reset-names = "nvdec"; 1846 1847 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 1848 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 1849 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 1850 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 1851 interconnect-names = "dma-mem", "read-1", "write"; 1852 iommus = <&smmu TEGRA194_SID_NVDEC>; 1853 dma-coherent; 1854 1855 nvidia,host1x-class = <0xf0>; 1856 }; 1857 1858 nvenc@154c0000 { 1859 compatible = "nvidia,tegra194-nvenc"; 1860 reg = <0x154c0000 0x40000>; 1861 clocks = <&bpmp TEGRA194_CLK_NVENC>; 1862 clock-names = "nvenc"; 1863 resets = <&bpmp TEGRA194_RESET_NVENC>; 1864 reset-names = "nvenc"; 1865 1866 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 1867 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 1868 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 1869 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 1870 interconnect-names = "dma-mem", "read-1", "write"; 1871 iommus = <&smmu TEGRA194_SID_NVENC>; 1872 dma-coherent; 1873 1874 nvidia,host1x-class = <0x21>; 1875 }; 1876 1877 dpaux0: dpaux@155c0000 { 1878 compatible = "nvidia,tegra194-dpaux"; 1879 reg = <0x155c0000 0x10000>; 1880 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1881 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1882 <&bpmp TEGRA194_CLK_PLLDP>; 1883 clock-names = "dpaux", "parent"; 1884 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1885 reset-names = "dpaux"; 1886 status = "disabled"; 1887 1888 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1889 1890 state_dpaux0_aux: pinmux-aux { 1891 groups = "dpaux-io"; 1892 function = "aux"; 1893 }; 1894 1895 state_dpaux0_i2c: pinmux-i2c { 1896 groups = "dpaux-io"; 1897 function = "i2c"; 1898 }; 1899 1900 state_dpaux0_off: pinmux-off { 1901 groups = "dpaux-io"; 1902 function = "off"; 1903 }; 1904 1905 i2c-bus { 1906 #address-cells = <1>; 1907 #size-cells = <0>; 1908 }; 1909 }; 1910 1911 dpaux1: dpaux@155d0000 { 1912 compatible = "nvidia,tegra194-dpaux"; 1913 reg = <0x155d0000 0x10000>; 1914 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1915 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1916 <&bpmp TEGRA194_CLK_PLLDP>; 1917 clock-names = "dpaux", "parent"; 1918 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1919 reset-names = "dpaux"; 1920 status = "disabled"; 1921 1922 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1923 1924 state_dpaux1_aux: pinmux-aux { 1925 groups = "dpaux-io"; 1926 function = "aux"; 1927 }; 1928 1929 state_dpaux1_i2c: pinmux-i2c { 1930 groups = "dpaux-io"; 1931 function = "i2c"; 1932 }; 1933 1934 state_dpaux1_off: pinmux-off { 1935 groups = "dpaux-io"; 1936 function = "off"; 1937 }; 1938 1939 i2c-bus { 1940 #address-cells = <1>; 1941 #size-cells = <0>; 1942 }; 1943 }; 1944 1945 dpaux2: dpaux@155e0000 { 1946 compatible = "nvidia,tegra194-dpaux"; 1947 reg = <0x155e0000 0x10000>; 1948 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1949 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1950 <&bpmp TEGRA194_CLK_PLLDP>; 1951 clock-names = "dpaux", "parent"; 1952 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1953 reset-names = "dpaux"; 1954 status = "disabled"; 1955 1956 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1957 1958 state_dpaux2_aux: pinmux-aux { 1959 groups = "dpaux-io"; 1960 function = "aux"; 1961 }; 1962 1963 state_dpaux2_i2c: pinmux-i2c { 1964 groups = "dpaux-io"; 1965 function = "i2c"; 1966 }; 1967 1968 state_dpaux2_off: pinmux-off { 1969 groups = "dpaux-io"; 1970 function = "off"; 1971 }; 1972 1973 i2c-bus { 1974 #address-cells = <1>; 1975 #size-cells = <0>; 1976 }; 1977 }; 1978 1979 dpaux3: dpaux@155f0000 { 1980 compatible = "nvidia,tegra194-dpaux"; 1981 reg = <0x155f0000 0x10000>; 1982 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1983 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1984 <&bpmp TEGRA194_CLK_PLLDP>; 1985 clock-names = "dpaux", "parent"; 1986 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1987 reset-names = "dpaux"; 1988 status = "disabled"; 1989 1990 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1991 1992 state_dpaux3_aux: pinmux-aux { 1993 groups = "dpaux-io"; 1994 function = "aux"; 1995 }; 1996 1997 state_dpaux3_i2c: pinmux-i2c { 1998 groups = "dpaux-io"; 1999 function = "i2c"; 2000 }; 2001 2002 state_dpaux3_off: pinmux-off { 2003 groups = "dpaux-io"; 2004 function = "off"; 2005 }; 2006 2007 i2c-bus { 2008 #address-cells = <1>; 2009 #size-cells = <0>; 2010 }; 2011 }; 2012 2013 nvenc@15a80000 { 2014 compatible = "nvidia,tegra194-nvenc"; 2015 reg = <0x15a80000 0x00040000>; 2016 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2017 clock-names = "nvenc"; 2018 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2019 reset-names = "nvenc"; 2020 2021 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2022 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2023 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2024 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2025 interconnect-names = "dma-mem", "read-1", "write"; 2026 iommus = <&smmu TEGRA194_SID_NVENC1>; 2027 dma-coherent; 2028 2029 nvidia,host1x-class = <0x22>; 2030 }; 2031 2032 sor0: sor@15b00000 { 2033 compatible = "nvidia,tegra194-sor"; 2034 reg = <0x15b00000 0x40000>; 2035 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2036 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2037 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2038 <&bpmp TEGRA194_CLK_PLLD>, 2039 <&bpmp TEGRA194_CLK_PLLDP>, 2040 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2041 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2042 clock-names = "sor", "out", "parent", "dp", "safe", 2043 "pad"; 2044 resets = <&bpmp TEGRA194_RESET_SOR0>; 2045 reset-names = "sor"; 2046 pinctrl-0 = <&state_dpaux0_aux>; 2047 pinctrl-1 = <&state_dpaux0_i2c>; 2048 pinctrl-2 = <&state_dpaux0_off>; 2049 pinctrl-names = "aux", "i2c", "off"; 2050 status = "disabled"; 2051 2052 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2053 nvidia,interface = <0>; 2054 }; 2055 2056 sor1: sor@15b40000 { 2057 compatible = "nvidia,tegra194-sor"; 2058 reg = <0x15b40000 0x40000>; 2059 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2060 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2061 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2062 <&bpmp TEGRA194_CLK_PLLD2>, 2063 <&bpmp TEGRA194_CLK_PLLDP>, 2064 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2065 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2066 clock-names = "sor", "out", "parent", "dp", "safe", 2067 "pad"; 2068 resets = <&bpmp TEGRA194_RESET_SOR1>; 2069 reset-names = "sor"; 2070 pinctrl-0 = <&state_dpaux1_aux>; 2071 pinctrl-1 = <&state_dpaux1_i2c>; 2072 pinctrl-2 = <&state_dpaux1_off>; 2073 pinctrl-names = "aux", "i2c", "off"; 2074 status = "disabled"; 2075 2076 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2077 nvidia,interface = <1>; 2078 }; 2079 2080 sor2: sor@15b80000 { 2081 compatible = "nvidia,tegra194-sor"; 2082 reg = <0x15b80000 0x40000>; 2083 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2084 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2085 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2086 <&bpmp TEGRA194_CLK_PLLD3>, 2087 <&bpmp TEGRA194_CLK_PLLDP>, 2088 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2089 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2090 clock-names = "sor", "out", "parent", "dp", "safe", 2091 "pad"; 2092 resets = <&bpmp TEGRA194_RESET_SOR2>; 2093 reset-names = "sor"; 2094 pinctrl-0 = <&state_dpaux2_aux>; 2095 pinctrl-1 = <&state_dpaux2_i2c>; 2096 pinctrl-2 = <&state_dpaux2_off>; 2097 pinctrl-names = "aux", "i2c", "off"; 2098 status = "disabled"; 2099 2100 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2101 nvidia,interface = <2>; 2102 }; 2103 2104 sor3: sor@15bc0000 { 2105 compatible = "nvidia,tegra194-sor"; 2106 reg = <0x15bc0000 0x40000>; 2107 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2108 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2109 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2110 <&bpmp TEGRA194_CLK_PLLD4>, 2111 <&bpmp TEGRA194_CLK_PLLDP>, 2112 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2113 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2114 clock-names = "sor", "out", "parent", "dp", "safe", 2115 "pad"; 2116 resets = <&bpmp TEGRA194_RESET_SOR3>; 2117 reset-names = "sor"; 2118 pinctrl-0 = <&state_dpaux3_aux>; 2119 pinctrl-1 = <&state_dpaux3_i2c>; 2120 pinctrl-2 = <&state_dpaux3_off>; 2121 pinctrl-names = "aux", "i2c", "off"; 2122 status = "disabled"; 2123 2124 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2125 nvidia,interface = <3>; 2126 }; 2127 }; 2128 2129 gpu@17000000 { 2130 compatible = "nvidia,gv11b"; 2131 reg = <0x17000000 0x1000000>, 2132 <0x18000000 0x1000000>; 2133 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2135 interrupt-names = "stall", "nonstall"; 2136 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2137 <&bpmp TEGRA194_CLK_GPU_PWR>, 2138 <&bpmp TEGRA194_CLK_FUSE>; 2139 clock-names = "gpu", "pwr", "fuse"; 2140 resets = <&bpmp TEGRA194_RESET_GPU>; 2141 reset-names = "gpu"; 2142 dma-coherent; 2143 2144 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2145 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2146 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2147 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2148 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2149 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2150 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2151 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2152 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2153 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2154 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2155 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2156 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2157 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2158 "read-1", "read-1-hp", "write-1", 2159 "read-2", "read-2-hp", "write-2", 2160 "read-3", "read-3-hp", "write-3"; 2161 }; 2162 }; 2163 2164 pcie@14100000 { 2165 compatible = "nvidia,tegra194-pcie"; 2166 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2167 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2168 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2169 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2170 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2171 reg-names = "appl", "config", "atu_dma", "dbi"; 2172 2173 status = "disabled"; 2174 2175 #address-cells = <3>; 2176 #size-cells = <2>; 2177 device_type = "pci"; 2178 num-lanes = <1>; 2179 linux,pci-domain = <1>; 2180 2181 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2182 clock-names = "core"; 2183 2184 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2185 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2186 reset-names = "apb", "core"; 2187 2188 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2189 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2190 interrupt-names = "intr", "msi"; 2191 2192 #interrupt-cells = <1>; 2193 interrupt-map-mask = <0 0 0 0>; 2194 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2195 2196 nvidia,bpmp = <&bpmp 1>; 2197 2198 nvidia,aspm-cmrt-us = <60>; 2199 nvidia,aspm-pwr-on-t-us = <20>; 2200 nvidia,aspm-l0s-entrance-latency-us = <3>; 2201 2202 bus-range = <0x0 0xff>; 2203 2204 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2205 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2206 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2207 2208 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2209 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2210 interconnect-names = "dma-mem", "write"; 2211 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2212 iommu-map-mask = <0x0>; 2213 dma-coherent; 2214 }; 2215 2216 pcie@14120000 { 2217 compatible = "nvidia,tegra194-pcie"; 2218 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2219 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2220 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2221 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2222 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2223 reg-names = "appl", "config", "atu_dma", "dbi"; 2224 2225 status = "disabled"; 2226 2227 #address-cells = <3>; 2228 #size-cells = <2>; 2229 device_type = "pci"; 2230 num-lanes = <1>; 2231 linux,pci-domain = <2>; 2232 2233 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2234 clock-names = "core"; 2235 2236 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2237 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2238 reset-names = "apb", "core"; 2239 2240 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2241 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2242 interrupt-names = "intr", "msi"; 2243 2244 #interrupt-cells = <1>; 2245 interrupt-map-mask = <0 0 0 0>; 2246 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2247 2248 nvidia,bpmp = <&bpmp 2>; 2249 2250 nvidia,aspm-cmrt-us = <60>; 2251 nvidia,aspm-pwr-on-t-us = <20>; 2252 nvidia,aspm-l0s-entrance-latency-us = <3>; 2253 2254 bus-range = <0x0 0xff>; 2255 2256 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2257 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2258 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2259 2260 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2261 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2262 interconnect-names = "dma-mem", "write"; 2263 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2264 iommu-map-mask = <0x0>; 2265 dma-coherent; 2266 }; 2267 2268 pcie@14140000 { 2269 compatible = "nvidia,tegra194-pcie"; 2270 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2271 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2272 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2273 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2274 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2275 reg-names = "appl", "config", "atu_dma", "dbi"; 2276 2277 status = "disabled"; 2278 2279 #address-cells = <3>; 2280 #size-cells = <2>; 2281 device_type = "pci"; 2282 num-lanes = <1>; 2283 linux,pci-domain = <3>; 2284 2285 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2286 clock-names = "core"; 2287 2288 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2289 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2290 reset-names = "apb", "core"; 2291 2292 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2293 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2294 interrupt-names = "intr", "msi"; 2295 2296 #interrupt-cells = <1>; 2297 interrupt-map-mask = <0 0 0 0>; 2298 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2299 2300 nvidia,bpmp = <&bpmp 3>; 2301 2302 nvidia,aspm-cmrt-us = <60>; 2303 nvidia,aspm-pwr-on-t-us = <20>; 2304 nvidia,aspm-l0s-entrance-latency-us = <3>; 2305 2306 bus-range = <0x0 0xff>; 2307 2308 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2309 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2310 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2311 2312 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2313 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2314 interconnect-names = "dma-mem", "write"; 2315 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2316 iommu-map-mask = <0x0>; 2317 dma-coherent; 2318 }; 2319 2320 pcie@14160000 { 2321 compatible = "nvidia,tegra194-pcie"; 2322 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2323 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2324 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2325 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2326 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2327 reg-names = "appl", "config", "atu_dma", "dbi"; 2328 2329 status = "disabled"; 2330 2331 #address-cells = <3>; 2332 #size-cells = <2>; 2333 device_type = "pci"; 2334 num-lanes = <4>; 2335 linux,pci-domain = <4>; 2336 2337 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2338 clock-names = "core"; 2339 2340 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2341 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2342 reset-names = "apb", "core"; 2343 2344 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2345 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2346 interrupt-names = "intr", "msi"; 2347 2348 #interrupt-cells = <1>; 2349 interrupt-map-mask = <0 0 0 0>; 2350 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2351 2352 nvidia,bpmp = <&bpmp 4>; 2353 2354 nvidia,aspm-cmrt-us = <60>; 2355 nvidia,aspm-pwr-on-t-us = <20>; 2356 nvidia,aspm-l0s-entrance-latency-us = <3>; 2357 2358 bus-range = <0x0 0xff>; 2359 2360 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2361 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2362 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2363 2364 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2365 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2366 interconnect-names = "dma-mem", "write"; 2367 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2368 iommu-map-mask = <0x0>; 2369 dma-coherent; 2370 }; 2371 2372 pcie@14180000 { 2373 compatible = "nvidia,tegra194-pcie"; 2374 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2375 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2376 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2377 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2378 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2379 reg-names = "appl", "config", "atu_dma", "dbi"; 2380 2381 status = "disabled"; 2382 2383 #address-cells = <3>; 2384 #size-cells = <2>; 2385 device_type = "pci"; 2386 num-lanes = <8>; 2387 linux,pci-domain = <0>; 2388 2389 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2390 clock-names = "core"; 2391 2392 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2393 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2394 reset-names = "apb", "core"; 2395 2396 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2397 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2398 interrupt-names = "intr", "msi"; 2399 2400 #interrupt-cells = <1>; 2401 interrupt-map-mask = <0 0 0 0>; 2402 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2403 2404 nvidia,bpmp = <&bpmp 0>; 2405 2406 nvidia,aspm-cmrt-us = <60>; 2407 nvidia,aspm-pwr-on-t-us = <20>; 2408 nvidia,aspm-l0s-entrance-latency-us = <3>; 2409 2410 bus-range = <0x0 0xff>; 2411 2412 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2413 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2414 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2415 2416 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2417 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2418 interconnect-names = "dma-mem", "write"; 2419 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2420 iommu-map-mask = <0x0>; 2421 dma-coherent; 2422 }; 2423 2424 pcie@141a0000 { 2425 compatible = "nvidia,tegra194-pcie"; 2426 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2427 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2428 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2429 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2430 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2431 reg-names = "appl", "config", "atu_dma", "dbi"; 2432 2433 status = "disabled"; 2434 2435 #address-cells = <3>; 2436 #size-cells = <2>; 2437 device_type = "pci"; 2438 num-lanes = <8>; 2439 linux,pci-domain = <5>; 2440 2441 pinctrl-names = "default"; 2442 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2443 2444 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2445 clock-names = "core"; 2446 2447 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2448 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2449 reset-names = "apb", "core"; 2450 2451 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2452 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2453 interrupt-names = "intr", "msi"; 2454 2455 nvidia,bpmp = <&bpmp 5>; 2456 2457 #interrupt-cells = <1>; 2458 interrupt-map-mask = <0 0 0 0>; 2459 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2460 2461 nvidia,aspm-cmrt-us = <60>; 2462 nvidia,aspm-pwr-on-t-us = <20>; 2463 nvidia,aspm-l0s-entrance-latency-us = <3>; 2464 2465 bus-range = <0x0 0xff>; 2466 2467 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2468 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2469 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2470 2471 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2472 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2473 interconnect-names = "dma-mem", "write"; 2474 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2475 iommu-map-mask = <0x0>; 2476 dma-coherent; 2477 }; 2478 2479 pcie-ep@14160000 { 2480 compatible = "nvidia,tegra194-pcie-ep"; 2481 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2482 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2483 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2484 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2485 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2486 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2487 2488 status = "disabled"; 2489 2490 num-lanes = <4>; 2491 num-ib-windows = <2>; 2492 num-ob-windows = <8>; 2493 2494 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2495 clock-names = "core"; 2496 2497 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2498 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2499 reset-names = "apb", "core"; 2500 2501 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2502 interrupt-names = "intr"; 2503 2504 nvidia,bpmp = <&bpmp 4>; 2505 2506 nvidia,aspm-cmrt-us = <60>; 2507 nvidia,aspm-pwr-on-t-us = <20>; 2508 nvidia,aspm-l0s-entrance-latency-us = <3>; 2509 2510 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2511 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2512 interconnect-names = "dma-mem", "write"; 2513 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2514 iommu-map-mask = <0x0>; 2515 dma-coherent; 2516 }; 2517 2518 pcie-ep@14180000 { 2519 compatible = "nvidia,tegra194-pcie-ep"; 2520 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2521 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2522 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2523 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2524 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2525 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2526 2527 status = "disabled"; 2528 2529 num-lanes = <8>; 2530 num-ib-windows = <2>; 2531 num-ob-windows = <8>; 2532 2533 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2534 clock-names = "core"; 2535 2536 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2537 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2538 reset-names = "apb", "core"; 2539 2540 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2541 interrupt-names = "intr"; 2542 2543 nvidia,bpmp = <&bpmp 0>; 2544 2545 nvidia,aspm-cmrt-us = <60>; 2546 nvidia,aspm-pwr-on-t-us = <20>; 2547 nvidia,aspm-l0s-entrance-latency-us = <3>; 2548 2549 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2550 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2551 interconnect-names = "dma-mem", "write"; 2552 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2553 iommu-map-mask = <0x0>; 2554 dma-coherent; 2555 }; 2556 2557 pcie-ep@141a0000 { 2558 compatible = "nvidia,tegra194-pcie-ep"; 2559 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2560 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2561 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2562 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2563 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2564 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2565 2566 status = "disabled"; 2567 2568 num-lanes = <8>; 2569 num-ib-windows = <2>; 2570 num-ob-windows = <8>; 2571 2572 pinctrl-names = "default"; 2573 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2574 2575 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2576 clock-names = "core"; 2577 2578 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2579 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2580 reset-names = "apb", "core"; 2581 2582 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2583 interrupt-names = "intr"; 2584 2585 nvidia,bpmp = <&bpmp 5>; 2586 2587 nvidia,aspm-cmrt-us = <60>; 2588 nvidia,aspm-pwr-on-t-us = <20>; 2589 nvidia,aspm-l0s-entrance-latency-us = <3>; 2590 2591 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2592 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2593 interconnect-names = "dma-mem", "write"; 2594 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2595 iommu-map-mask = <0x0>; 2596 dma-coherent; 2597 }; 2598 2599 sram@40000000 { 2600 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2601 reg = <0x0 0x40000000 0x0 0x50000>; 2602 #address-cells = <1>; 2603 #size-cells = <1>; 2604 ranges = <0x0 0x0 0x40000000 0x50000>; 2605 2606 cpu_bpmp_tx: sram@4e000 { 2607 reg = <0x4e000 0x1000>; 2608 label = "cpu-bpmp-tx"; 2609 pool; 2610 }; 2611 2612 cpu_bpmp_rx: sram@4f000 { 2613 reg = <0x4f000 0x1000>; 2614 label = "cpu-bpmp-rx"; 2615 pool; 2616 }; 2617 }; 2618 2619 bpmp: bpmp { 2620 compatible = "nvidia,tegra186-bpmp"; 2621 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2622 TEGRA_HSP_DB_MASTER_BPMP>; 2623 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2624 #clock-cells = <1>; 2625 #reset-cells = <1>; 2626 #power-domain-cells = <1>; 2627 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2628 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2629 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2630 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2631 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2632 iommus = <&smmu TEGRA194_SID_BPMP>; 2633 2634 bpmp_i2c: i2c { 2635 compatible = "nvidia,tegra186-bpmp-i2c"; 2636 nvidia,bpmp-bus-id = <5>; 2637 #address-cells = <1>; 2638 #size-cells = <0>; 2639 }; 2640 2641 bpmp_thermal: thermal { 2642 compatible = "nvidia,tegra186-bpmp-thermal"; 2643 #thermal-sensor-cells = <1>; 2644 }; 2645 }; 2646 2647 cpus { 2648 compatible = "nvidia,tegra194-ccplex"; 2649 nvidia,bpmp = <&bpmp>; 2650 #address-cells = <1>; 2651 #size-cells = <0>; 2652 2653 cpu0_0: cpu@0 { 2654 compatible = "nvidia,tegra194-carmel"; 2655 device_type = "cpu"; 2656 reg = <0x000>; 2657 enable-method = "psci"; 2658 i-cache-size = <131072>; 2659 i-cache-line-size = <64>; 2660 i-cache-sets = <512>; 2661 d-cache-size = <65536>; 2662 d-cache-line-size = <64>; 2663 d-cache-sets = <256>; 2664 next-level-cache = <&l2c_0>; 2665 }; 2666 2667 cpu0_1: cpu@1 { 2668 compatible = "nvidia,tegra194-carmel"; 2669 device_type = "cpu"; 2670 reg = <0x001>; 2671 enable-method = "psci"; 2672 i-cache-size = <131072>; 2673 i-cache-line-size = <64>; 2674 i-cache-sets = <512>; 2675 d-cache-size = <65536>; 2676 d-cache-line-size = <64>; 2677 d-cache-sets = <256>; 2678 next-level-cache = <&l2c_0>; 2679 }; 2680 2681 cpu1_0: cpu@100 { 2682 compatible = "nvidia,tegra194-carmel"; 2683 device_type = "cpu"; 2684 reg = <0x100>; 2685 enable-method = "psci"; 2686 i-cache-size = <131072>; 2687 i-cache-line-size = <64>; 2688 i-cache-sets = <512>; 2689 d-cache-size = <65536>; 2690 d-cache-line-size = <64>; 2691 d-cache-sets = <256>; 2692 next-level-cache = <&l2c_1>; 2693 }; 2694 2695 cpu1_1: cpu@101 { 2696 compatible = "nvidia,tegra194-carmel"; 2697 device_type = "cpu"; 2698 reg = <0x101>; 2699 enable-method = "psci"; 2700 i-cache-size = <131072>; 2701 i-cache-line-size = <64>; 2702 i-cache-sets = <512>; 2703 d-cache-size = <65536>; 2704 d-cache-line-size = <64>; 2705 d-cache-sets = <256>; 2706 next-level-cache = <&l2c_1>; 2707 }; 2708 2709 cpu2_0: cpu@200 { 2710 compatible = "nvidia,tegra194-carmel"; 2711 device_type = "cpu"; 2712 reg = <0x200>; 2713 enable-method = "psci"; 2714 i-cache-size = <131072>; 2715 i-cache-line-size = <64>; 2716 i-cache-sets = <512>; 2717 d-cache-size = <65536>; 2718 d-cache-line-size = <64>; 2719 d-cache-sets = <256>; 2720 next-level-cache = <&l2c_2>; 2721 }; 2722 2723 cpu2_1: cpu@201 { 2724 compatible = "nvidia,tegra194-carmel"; 2725 device_type = "cpu"; 2726 reg = <0x201>; 2727 enable-method = "psci"; 2728 i-cache-size = <131072>; 2729 i-cache-line-size = <64>; 2730 i-cache-sets = <512>; 2731 d-cache-size = <65536>; 2732 d-cache-line-size = <64>; 2733 d-cache-sets = <256>; 2734 next-level-cache = <&l2c_2>; 2735 }; 2736 2737 cpu3_0: cpu@300 { 2738 compatible = "nvidia,tegra194-carmel"; 2739 device_type = "cpu"; 2740 reg = <0x300>; 2741 enable-method = "psci"; 2742 i-cache-size = <131072>; 2743 i-cache-line-size = <64>; 2744 i-cache-sets = <512>; 2745 d-cache-size = <65536>; 2746 d-cache-line-size = <64>; 2747 d-cache-sets = <256>; 2748 next-level-cache = <&l2c_3>; 2749 }; 2750 2751 cpu3_1: cpu@301 { 2752 compatible = "nvidia,tegra194-carmel"; 2753 device_type = "cpu"; 2754 reg = <0x301>; 2755 enable-method = "psci"; 2756 i-cache-size = <131072>; 2757 i-cache-line-size = <64>; 2758 i-cache-sets = <512>; 2759 d-cache-size = <65536>; 2760 d-cache-line-size = <64>; 2761 d-cache-sets = <256>; 2762 next-level-cache = <&l2c_3>; 2763 }; 2764 2765 cpu-map { 2766 cluster0 { 2767 core0 { 2768 cpu = <&cpu0_0>; 2769 }; 2770 2771 core1 { 2772 cpu = <&cpu0_1>; 2773 }; 2774 }; 2775 2776 cluster1 { 2777 core0 { 2778 cpu = <&cpu1_0>; 2779 }; 2780 2781 core1 { 2782 cpu = <&cpu1_1>; 2783 }; 2784 }; 2785 2786 cluster2 { 2787 core0 { 2788 cpu = <&cpu2_0>; 2789 }; 2790 2791 core1 { 2792 cpu = <&cpu2_1>; 2793 }; 2794 }; 2795 2796 cluster3 { 2797 core0 { 2798 cpu = <&cpu3_0>; 2799 }; 2800 2801 core1 { 2802 cpu = <&cpu3_1>; 2803 }; 2804 }; 2805 }; 2806 2807 l2c_0: l2-cache0 { 2808 cache-size = <2097152>; 2809 cache-line-size = <64>; 2810 cache-sets = <2048>; 2811 next-level-cache = <&l3c>; 2812 }; 2813 2814 l2c_1: l2-cache1 { 2815 cache-size = <2097152>; 2816 cache-line-size = <64>; 2817 cache-sets = <2048>; 2818 next-level-cache = <&l3c>; 2819 }; 2820 2821 l2c_2: l2-cache2 { 2822 cache-size = <2097152>; 2823 cache-line-size = <64>; 2824 cache-sets = <2048>; 2825 next-level-cache = <&l3c>; 2826 }; 2827 2828 l2c_3: l2-cache3 { 2829 cache-size = <2097152>; 2830 cache-line-size = <64>; 2831 cache-sets = <2048>; 2832 next-level-cache = <&l3c>; 2833 }; 2834 2835 l3c: l3-cache { 2836 cache-size = <4194304>; 2837 cache-line-size = <64>; 2838 cache-sets = <4096>; 2839 }; 2840 }; 2841 2842 pmu { 2843 compatible = "arm,armv8-pmuv3"; 2844 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2845 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2846 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2847 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 2848 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 2849 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 2850 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 2851 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 2852 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 2853 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 2854 }; 2855 2856 psci { 2857 compatible = "arm,psci-1.0"; 2858 status = "okay"; 2859 method = "smc"; 2860 }; 2861 2862 sound { 2863 status = "disabled"; 2864 2865 clocks = <&bpmp TEGRA194_CLK_PLLA>, 2866 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2867 clock-names = "pll_a", "plla_out0"; 2868 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 2869 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 2870 <&bpmp TEGRA194_CLK_AUD_MCLK>; 2871 assigned-clock-parents = <0>, 2872 <&bpmp TEGRA194_CLK_PLLA>, 2873 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2874 /* 2875 * PLLA supports dynamic ramp. Below initial rate is chosen 2876 * for this to work and oscillate between base rates required 2877 * for 8x and 11.025x sample rate streams. 2878 */ 2879 assigned-clock-rates = <258000000>; 2880 2881 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 2882 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 2883 interconnect-names = "dma-mem", "write"; 2884 iommus = <&smmu TEGRA194_SID_APE>; 2885 }; 2886 2887 tcu: serial { 2888 compatible = "nvidia,tegra194-tcu"; 2889 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2890 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2891 mbox-names = "rx", "tx"; 2892 }; 2893 2894 thermal-zones { 2895 cpu-thermal { 2896 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2897 status = "disabled"; 2898 }; 2899 2900 gpu-thermal { 2901 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2902 status = "disabled"; 2903 }; 2904 2905 aux-thermal { 2906 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2907 status = "disabled"; 2908 }; 2909 2910 pllx-thermal { 2911 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2912 status = "disabled"; 2913 }; 2914 2915 ao-thermal { 2916 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 2917 status = "disabled"; 2918 }; 2919 2920 tj-thermal { 2921 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2922 status = "disabled"; 2923 }; 2924 }; 2925 2926 timer { 2927 compatible = "arm,armv8-timer"; 2928 interrupts = <GIC_PPI 13 2929 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2930 <GIC_PPI 14 2931 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2932 <GIC_PPI 11 2933 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2934 <GIC_PPI 10 2935 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2936 interrupt-parent = <&gic>; 2937 always-on; 2938 }; 2939}; 2940