1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 }; 90 91 ethernet@2490000 { 92 compatible = "nvidia,tegra194-eqos", 93 "nvidia,tegra186-eqos", 94 "snps,dwc-qos-ethernet-4.10"; 95 reg = <0x02490000 0x10000>; 96 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 98 <&bpmp TEGRA194_CLK_EQOS_AXI>, 99 <&bpmp TEGRA194_CLK_EQOS_RX>, 100 <&bpmp TEGRA194_CLK_EQOS_TX>, 101 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 102 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 103 resets = <&bpmp TEGRA194_RESET_EQOS>; 104 reset-names = "eqos"; 105 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 106 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 107 interconnect-names = "dma-mem", "write"; 108 iommus = <&smmu TEGRA194_SID_EQOS>; 109 status = "disabled"; 110 111 snps,write-requests = <1>; 112 snps,read-requests = <3>; 113 snps,burst-map = <0x7>; 114 snps,txpbl = <16>; 115 snps,rxpbl = <8>; 116 }; 117 118 aconnect@2900000 { 119 compatible = "nvidia,tegra194-aconnect", 120 "nvidia,tegra210-aconnect"; 121 clocks = <&bpmp TEGRA194_CLK_APE>, 122 <&bpmp TEGRA194_CLK_APB2APE>; 123 clock-names = "ape", "apb2ape"; 124 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges = <0x02900000 0x02900000 0x200000>; 128 status = "disabled"; 129 130 adma: dma-controller@2930000 { 131 compatible = "nvidia,tegra194-adma", 132 "nvidia,tegra186-adma"; 133 reg = <0x02930000 0x20000>; 134 interrupt-parent = <&agic>; 135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 167 #dma-cells = <1>; 168 clocks = <&bpmp TEGRA194_CLK_AHUB>; 169 clock-names = "d_audio"; 170 status = "disabled"; 171 }; 172 173 agic: interrupt-controller@2a40000 { 174 compatible = "nvidia,tegra194-agic", 175 "nvidia,tegra210-agic"; 176 #interrupt-cells = <3>; 177 interrupt-controller; 178 reg = <0x02a41000 0x1000>, 179 <0x02a42000 0x2000>; 180 interrupts = <GIC_SPI 145 181 (GIC_CPU_MASK_SIMPLE(4) | 182 IRQ_TYPE_LEVEL_HIGH)>; 183 clocks = <&bpmp TEGRA194_CLK_APE>; 184 clock-names = "clk"; 185 status = "disabled"; 186 }; 187 188 tegra_ahub: ahub@2900800 { 189 compatible = "nvidia,tegra194-ahub", 190 "nvidia,tegra186-ahub"; 191 reg = <0x02900800 0x800>; 192 clocks = <&bpmp TEGRA194_CLK_AHUB>; 193 clock-names = "ahub"; 194 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 195 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 ranges = <0x02900800 0x02900800 0x11800>; 199 status = "disabled"; 200 201 tegra_admaif: admaif@290f000 { 202 compatible = "nvidia,tegra194-admaif", 203 "nvidia,tegra186-admaif"; 204 reg = <0x0290f000 0x1000>; 205 dmas = <&adma 1>, <&adma 1>, 206 <&adma 2>, <&adma 2>, 207 <&adma 3>, <&adma 3>, 208 <&adma 4>, <&adma 4>, 209 <&adma 5>, <&adma 5>, 210 <&adma 6>, <&adma 6>, 211 <&adma 7>, <&adma 7>, 212 <&adma 8>, <&adma 8>, 213 <&adma 9>, <&adma 9>, 214 <&adma 10>, <&adma 10>, 215 <&adma 11>, <&adma 11>, 216 <&adma 12>, <&adma 12>, 217 <&adma 13>, <&adma 13>, 218 <&adma 14>, <&adma 14>, 219 <&adma 15>, <&adma 15>, 220 <&adma 16>, <&adma 16>, 221 <&adma 17>, <&adma 17>, 222 <&adma 18>, <&adma 18>, 223 <&adma 19>, <&adma 19>, 224 <&adma 20>, <&adma 20>; 225 dma-names = "rx1", "tx1", 226 "rx2", "tx2", 227 "rx3", "tx3", 228 "rx4", "tx4", 229 "rx5", "tx5", 230 "rx6", "tx6", 231 "rx7", "tx7", 232 "rx8", "tx8", 233 "rx9", "tx9", 234 "rx10", "tx10", 235 "rx11", "tx11", 236 "rx12", "tx12", 237 "rx13", "tx13", 238 "rx14", "tx14", 239 "rx15", "tx15", 240 "rx16", "tx16", 241 "rx17", "tx17", 242 "rx18", "tx18", 243 "rx19", "tx19", 244 "rx20", "tx20"; 245 status = "disabled"; 246 }; 247 248 tegra_i2s1: i2s@2901000 { 249 compatible = "nvidia,tegra194-i2s", 250 "nvidia,tegra210-i2s"; 251 reg = <0x2901000 0x100>; 252 clocks = <&bpmp TEGRA194_CLK_I2S1>, 253 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 254 clock-names = "i2s", "sync_input"; 255 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 256 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 257 assigned-clock-rates = <1536000>; 258 sound-name-prefix = "I2S1"; 259 status = "disabled"; 260 }; 261 262 tegra_i2s2: i2s@2901100 { 263 compatible = "nvidia,tegra194-i2s", 264 "nvidia,tegra210-i2s"; 265 reg = <0x2901100 0x100>; 266 clocks = <&bpmp TEGRA194_CLK_I2S2>, 267 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 268 clock-names = "i2s", "sync_input"; 269 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 270 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 271 assigned-clock-rates = <1536000>; 272 sound-name-prefix = "I2S2"; 273 status = "disabled"; 274 }; 275 276 tegra_i2s3: i2s@2901200 { 277 compatible = "nvidia,tegra194-i2s", 278 "nvidia,tegra210-i2s"; 279 reg = <0x2901200 0x100>; 280 clocks = <&bpmp TEGRA194_CLK_I2S3>, 281 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 282 clock-names = "i2s", "sync_input"; 283 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 284 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 285 assigned-clock-rates = <1536000>; 286 sound-name-prefix = "I2S3"; 287 status = "disabled"; 288 }; 289 290 tegra_i2s4: i2s@2901300 { 291 compatible = "nvidia,tegra194-i2s", 292 "nvidia,tegra210-i2s"; 293 reg = <0x2901300 0x100>; 294 clocks = <&bpmp TEGRA194_CLK_I2S4>, 295 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 296 clock-names = "i2s", "sync_input"; 297 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 298 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 299 assigned-clock-rates = <1536000>; 300 sound-name-prefix = "I2S4"; 301 status = "disabled"; 302 }; 303 304 tegra_i2s5: i2s@2901400 { 305 compatible = "nvidia,tegra194-i2s", 306 "nvidia,tegra210-i2s"; 307 reg = <0x2901400 0x100>; 308 clocks = <&bpmp TEGRA194_CLK_I2S5>, 309 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 310 clock-names = "i2s", "sync_input"; 311 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 312 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 313 assigned-clock-rates = <1536000>; 314 sound-name-prefix = "I2S5"; 315 status = "disabled"; 316 }; 317 318 tegra_i2s6: i2s@2901500 { 319 compatible = "nvidia,tegra194-i2s", 320 "nvidia,tegra210-i2s"; 321 reg = <0x2901500 0x100>; 322 clocks = <&bpmp TEGRA194_CLK_I2S6>, 323 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 324 clock-names = "i2s", "sync_input"; 325 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 326 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 327 assigned-clock-rates = <1536000>; 328 sound-name-prefix = "I2S6"; 329 status = "disabled"; 330 }; 331 332 tegra_dmic1: dmic@2904000 { 333 compatible = "nvidia,tegra194-dmic", 334 "nvidia,tegra210-dmic"; 335 reg = <0x2904000 0x100>; 336 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 337 clock-names = "dmic"; 338 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 339 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 340 assigned-clock-rates = <3072000>; 341 sound-name-prefix = "DMIC1"; 342 status = "disabled"; 343 }; 344 345 tegra_dmic2: dmic@2904100 { 346 compatible = "nvidia,tegra194-dmic", 347 "nvidia,tegra210-dmic"; 348 reg = <0x2904100 0x100>; 349 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 350 clock-names = "dmic"; 351 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 352 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 353 assigned-clock-rates = <3072000>; 354 sound-name-prefix = "DMIC2"; 355 status = "disabled"; 356 }; 357 358 tegra_dmic3: dmic@2904200 { 359 compatible = "nvidia,tegra194-dmic", 360 "nvidia,tegra210-dmic"; 361 reg = <0x2904200 0x100>; 362 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 363 clock-names = "dmic"; 364 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 365 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 366 assigned-clock-rates = <3072000>; 367 sound-name-prefix = "DMIC3"; 368 status = "disabled"; 369 }; 370 371 tegra_dmic4: dmic@2904300 { 372 compatible = "nvidia,tegra194-dmic", 373 "nvidia,tegra210-dmic"; 374 reg = <0x2904300 0x100>; 375 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 376 clock-names = "dmic"; 377 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 378 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 379 assigned-clock-rates = <3072000>; 380 sound-name-prefix = "DMIC4"; 381 status = "disabled"; 382 }; 383 384 tegra_dspk1: dspk@2905000 { 385 compatible = "nvidia,tegra194-dspk", 386 "nvidia,tegra186-dspk"; 387 reg = <0x2905000 0x100>; 388 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 389 clock-names = "dspk"; 390 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 391 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 392 assigned-clock-rates = <12288000>; 393 sound-name-prefix = "DSPK1"; 394 status = "disabled"; 395 }; 396 397 tegra_dspk2: dspk@2905100 { 398 compatible = "nvidia,tegra194-dspk", 399 "nvidia,tegra186-dspk"; 400 reg = <0x2905100 0x100>; 401 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 402 clock-names = "dspk"; 403 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 404 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 405 assigned-clock-rates = <12288000>; 406 sound-name-prefix = "DSPK2"; 407 status = "disabled"; 408 }; 409 410 tegra_sfc1: sfc@2902000 { 411 compatible = "nvidia,tegra194-sfc", 412 "nvidia,tegra210-sfc"; 413 reg = <0x2902000 0x200>; 414 sound-name-prefix = "SFC1"; 415 status = "disabled"; 416 }; 417 418 tegra_sfc2: sfc@2902200 { 419 compatible = "nvidia,tegra194-sfc", 420 "nvidia,tegra210-sfc"; 421 reg = <0x2902200 0x200>; 422 sound-name-prefix = "SFC2"; 423 status = "disabled"; 424 }; 425 426 tegra_sfc3: sfc@2902400 { 427 compatible = "nvidia,tegra194-sfc", 428 "nvidia,tegra210-sfc"; 429 reg = <0x2902400 0x200>; 430 sound-name-prefix = "SFC3"; 431 status = "disabled"; 432 }; 433 434 tegra_sfc4: sfc@2902600 { 435 compatible = "nvidia,tegra194-sfc", 436 "nvidia,tegra210-sfc"; 437 reg = <0x2902600 0x200>; 438 sound-name-prefix = "SFC4"; 439 status = "disabled"; 440 }; 441 442 tegra_mvc1: mvc@290a000 { 443 compatible = "nvidia,tegra194-mvc", 444 "nvidia,tegra210-mvc"; 445 reg = <0x290a000 0x200>; 446 sound-name-prefix = "MVC1"; 447 status = "disabled"; 448 }; 449 450 tegra_mvc2: mvc@290a200 { 451 compatible = "nvidia,tegra194-mvc", 452 "nvidia,tegra210-mvc"; 453 reg = <0x290a200 0x200>; 454 sound-name-prefix = "MVC2"; 455 status = "disabled"; 456 }; 457 458 tegra_amx1: amx@2903000 { 459 compatible = "nvidia,tegra194-amx"; 460 reg = <0x2903000 0x100>; 461 sound-name-prefix = "AMX1"; 462 status = "disabled"; 463 }; 464 465 tegra_amx2: amx@2903100 { 466 compatible = "nvidia,tegra194-amx"; 467 reg = <0x2903100 0x100>; 468 sound-name-prefix = "AMX2"; 469 status = "disabled"; 470 }; 471 472 tegra_amx3: amx@2903200 { 473 compatible = "nvidia,tegra194-amx"; 474 reg = <0x2903200 0x100>; 475 sound-name-prefix = "AMX3"; 476 status = "disabled"; 477 }; 478 479 tegra_amx4: amx@2903300 { 480 compatible = "nvidia,tegra194-amx"; 481 reg = <0x2903300 0x100>; 482 sound-name-prefix = "AMX4"; 483 status = "disabled"; 484 }; 485 486 tegra_adx1: adx@2903800 { 487 compatible = "nvidia,tegra194-adx", 488 "nvidia,tegra210-adx"; 489 reg = <0x2903800 0x100>; 490 sound-name-prefix = "ADX1"; 491 status = "disabled"; 492 }; 493 494 tegra_adx2: adx@2903900 { 495 compatible = "nvidia,tegra194-adx", 496 "nvidia,tegra210-adx"; 497 reg = <0x2903900 0x100>; 498 sound-name-prefix = "ADX2"; 499 status = "disabled"; 500 }; 501 502 tegra_adx3: adx@2903a00 { 503 compatible = "nvidia,tegra194-adx", 504 "nvidia,tegra210-adx"; 505 reg = <0x2903a00 0x100>; 506 sound-name-prefix = "ADX3"; 507 status = "disabled"; 508 }; 509 510 tegra_adx4: adx@2903b00 { 511 compatible = "nvidia,tegra194-adx", 512 "nvidia,tegra210-adx"; 513 reg = <0x2903b00 0x100>; 514 sound-name-prefix = "ADX4"; 515 status = "disabled"; 516 }; 517 518 tegra_amixer: amixer@290bb00 { 519 compatible = "nvidia,tegra194-amixer", 520 "nvidia,tegra210-amixer"; 521 reg = <0x290bb00 0x800>; 522 sound-name-prefix = "MIXER1"; 523 status = "disabled"; 524 }; 525 }; 526 }; 527 528 pinmux: pinmux@2430000 { 529 compatible = "nvidia,tegra194-pinmux"; 530 reg = <0x2430000 0x17000>, 531 <0xc300000 0x4000>; 532 533 status = "okay"; 534 535 pex_rst_c5_out_state: pex_rst_c5_out { 536 pex_rst { 537 nvidia,pins = "pex_l5_rst_n_pgg1"; 538 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 539 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 540 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 541 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 542 nvidia,tristate = <TEGRA_PIN_DISABLE>; 543 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 544 }; 545 }; 546 547 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 548 clkreq { 549 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 550 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 551 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 552 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 553 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 554 nvidia,tristate = <TEGRA_PIN_DISABLE>; 555 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 556 }; 557 }; 558 }; 559 560 mc: memory-controller@2c00000 { 561 compatible = "nvidia,tegra194-mc"; 562 reg = <0x02c00000 0x100000>, 563 <0x02b80000 0x040000>, 564 <0x01700000 0x100000>; 565 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 566 #interconnect-cells = <1>; 567 status = "disabled"; 568 569 #address-cells = <2>; 570 #size-cells = <2>; 571 572 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 573 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 574 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 575 576 /* 577 * Bit 39 of addresses passing through the memory 578 * controller selects the XBAR format used when memory 579 * is accessed. This is used to transparently access 580 * memory in the XBAR format used by the discrete GPU 581 * (bit 39 set) or Tegra (bit 39 clear). 582 * 583 * As a consequence, the operating system must ensure 584 * that bit 39 is never used implicitly, for example 585 * via an I/O virtual address mapping of an IOMMU. If 586 * devices require access to the XBAR switch, their 587 * drivers must set this bit explicitly. 588 * 589 * Limit the DMA range for memory clients to [38:0]. 590 */ 591 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 592 593 emc: external-memory-controller@2c60000 { 594 compatible = "nvidia,tegra194-emc"; 595 reg = <0x0 0x02c60000 0x0 0x90000>, 596 <0x0 0x01780000 0x0 0x80000>; 597 clocks = <&bpmp TEGRA194_CLK_EMC>; 598 clock-names = "emc"; 599 600 #interconnect-cells = <0>; 601 602 nvidia,bpmp = <&bpmp>; 603 }; 604 }; 605 606 uarta: serial@3100000 { 607 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 608 reg = <0x03100000 0x40>; 609 reg-shift = <2>; 610 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&bpmp TEGRA194_CLK_UARTA>; 612 clock-names = "serial"; 613 resets = <&bpmp TEGRA194_RESET_UARTA>; 614 reset-names = "serial"; 615 status = "disabled"; 616 }; 617 618 uartb: serial@3110000 { 619 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 620 reg = <0x03110000 0x40>; 621 reg-shift = <2>; 622 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&bpmp TEGRA194_CLK_UARTB>; 624 clock-names = "serial"; 625 resets = <&bpmp TEGRA194_RESET_UARTB>; 626 reset-names = "serial"; 627 status = "disabled"; 628 }; 629 630 uartd: serial@3130000 { 631 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 632 reg = <0x03130000 0x40>; 633 reg-shift = <2>; 634 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&bpmp TEGRA194_CLK_UARTD>; 636 clock-names = "serial"; 637 resets = <&bpmp TEGRA194_RESET_UARTD>; 638 reset-names = "serial"; 639 status = "disabled"; 640 }; 641 642 uarte: serial@3140000 { 643 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 644 reg = <0x03140000 0x40>; 645 reg-shift = <2>; 646 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&bpmp TEGRA194_CLK_UARTE>; 648 clock-names = "serial"; 649 resets = <&bpmp TEGRA194_RESET_UARTE>; 650 reset-names = "serial"; 651 status = "disabled"; 652 }; 653 654 uartf: serial@3150000 { 655 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 656 reg = <0x03150000 0x40>; 657 reg-shift = <2>; 658 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&bpmp TEGRA194_CLK_UARTF>; 660 clock-names = "serial"; 661 resets = <&bpmp TEGRA194_RESET_UARTF>; 662 reset-names = "serial"; 663 status = "disabled"; 664 }; 665 666 gen1_i2c: i2c@3160000 { 667 compatible = "nvidia,tegra194-i2c"; 668 reg = <0x03160000 0x10000>; 669 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 clocks = <&bpmp TEGRA194_CLK_I2C1>; 673 clock-names = "div-clk"; 674 resets = <&bpmp TEGRA194_RESET_I2C1>; 675 reset-names = "i2c"; 676 status = "disabled"; 677 }; 678 679 uarth: serial@3170000 { 680 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 681 reg = <0x03170000 0x40>; 682 reg-shift = <2>; 683 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&bpmp TEGRA194_CLK_UARTH>; 685 clock-names = "serial"; 686 resets = <&bpmp TEGRA194_RESET_UARTH>; 687 reset-names = "serial"; 688 status = "disabled"; 689 }; 690 691 cam_i2c: i2c@3180000 { 692 compatible = "nvidia,tegra194-i2c"; 693 reg = <0x03180000 0x10000>; 694 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 clocks = <&bpmp TEGRA194_CLK_I2C3>; 698 clock-names = "div-clk"; 699 resets = <&bpmp TEGRA194_RESET_I2C3>; 700 reset-names = "i2c"; 701 status = "disabled"; 702 }; 703 704 /* shares pads with dpaux1 */ 705 dp_aux_ch1_i2c: i2c@3190000 { 706 compatible = "nvidia,tegra194-i2c"; 707 reg = <0x03190000 0x10000>; 708 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 clocks = <&bpmp TEGRA194_CLK_I2C4>; 712 clock-names = "div-clk"; 713 resets = <&bpmp TEGRA194_RESET_I2C4>; 714 reset-names = "i2c"; 715 pinctrl-0 = <&state_dpaux1_i2c>; 716 pinctrl-1 = <&state_dpaux1_off>; 717 pinctrl-names = "default", "idle"; 718 status = "disabled"; 719 }; 720 721 /* shares pads with dpaux0 */ 722 dp_aux_ch0_i2c: i2c@31b0000 { 723 compatible = "nvidia,tegra194-i2c"; 724 reg = <0x031b0000 0x10000>; 725 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 726 #address-cells = <1>; 727 #size-cells = <0>; 728 clocks = <&bpmp TEGRA194_CLK_I2C6>; 729 clock-names = "div-clk"; 730 resets = <&bpmp TEGRA194_RESET_I2C6>; 731 reset-names = "i2c"; 732 pinctrl-0 = <&state_dpaux0_i2c>; 733 pinctrl-1 = <&state_dpaux0_off>; 734 pinctrl-names = "default", "idle"; 735 status = "disabled"; 736 }; 737 738 /* shares pads with dpaux2 */ 739 dp_aux_ch2_i2c: i2c@31c0000 { 740 compatible = "nvidia,tegra194-i2c"; 741 reg = <0x031c0000 0x10000>; 742 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 clocks = <&bpmp TEGRA194_CLK_I2C7>; 746 clock-names = "div-clk"; 747 resets = <&bpmp TEGRA194_RESET_I2C7>; 748 reset-names = "i2c"; 749 pinctrl-0 = <&state_dpaux2_i2c>; 750 pinctrl-1 = <&state_dpaux2_off>; 751 pinctrl-names = "default", "idle"; 752 status = "disabled"; 753 }; 754 755 /* shares pads with dpaux3 */ 756 dp_aux_ch3_i2c: i2c@31e0000 { 757 compatible = "nvidia,tegra194-i2c"; 758 reg = <0x031e0000 0x10000>; 759 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 clocks = <&bpmp TEGRA194_CLK_I2C9>; 763 clock-names = "div-clk"; 764 resets = <&bpmp TEGRA194_RESET_I2C9>; 765 reset-names = "i2c"; 766 pinctrl-0 = <&state_dpaux3_i2c>; 767 pinctrl-1 = <&state_dpaux3_off>; 768 pinctrl-names = "default", "idle"; 769 status = "disabled"; 770 }; 771 772 spi@3270000 { 773 compatible = "nvidia,tegra194-qspi"; 774 reg = <0x3270000 0x1000>; 775 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 779 <&bpmp TEGRA194_CLK_QSPI0_PM>; 780 clock-names = "qspi", "qspi_out"; 781 resets = <&bpmp TEGRA194_RESET_QSPI0>; 782 reset-names = "qspi"; 783 status = "disabled"; 784 }; 785 786 spi@3300000 { 787 compatible = "nvidia,tegra194-qspi"; 788 reg = <0x3300000 0x1000>; 789 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 793 <&bpmp TEGRA194_CLK_QSPI1_PM>; 794 clock-names = "qspi", "qspi_out"; 795 resets = <&bpmp TEGRA194_RESET_QSPI1>; 796 reset-names = "qspi"; 797 status = "disabled"; 798 }; 799 800 pwm1: pwm@3280000 { 801 compatible = "nvidia,tegra194-pwm", 802 "nvidia,tegra186-pwm"; 803 reg = <0x3280000 0x10000>; 804 clocks = <&bpmp TEGRA194_CLK_PWM1>; 805 clock-names = "pwm"; 806 resets = <&bpmp TEGRA194_RESET_PWM1>; 807 reset-names = "pwm"; 808 status = "disabled"; 809 #pwm-cells = <2>; 810 }; 811 812 pwm2: pwm@3290000 { 813 compatible = "nvidia,tegra194-pwm", 814 "nvidia,tegra186-pwm"; 815 reg = <0x3290000 0x10000>; 816 clocks = <&bpmp TEGRA194_CLK_PWM2>; 817 clock-names = "pwm"; 818 resets = <&bpmp TEGRA194_RESET_PWM2>; 819 reset-names = "pwm"; 820 status = "disabled"; 821 #pwm-cells = <2>; 822 }; 823 824 pwm3: pwm@32a0000 { 825 compatible = "nvidia,tegra194-pwm", 826 "nvidia,tegra186-pwm"; 827 reg = <0x32a0000 0x10000>; 828 clocks = <&bpmp TEGRA194_CLK_PWM3>; 829 clock-names = "pwm"; 830 resets = <&bpmp TEGRA194_RESET_PWM3>; 831 reset-names = "pwm"; 832 status = "disabled"; 833 #pwm-cells = <2>; 834 }; 835 836 pwm5: pwm@32c0000 { 837 compatible = "nvidia,tegra194-pwm", 838 "nvidia,tegra186-pwm"; 839 reg = <0x32c0000 0x10000>; 840 clocks = <&bpmp TEGRA194_CLK_PWM5>; 841 clock-names = "pwm"; 842 resets = <&bpmp TEGRA194_RESET_PWM5>; 843 reset-names = "pwm"; 844 status = "disabled"; 845 #pwm-cells = <2>; 846 }; 847 848 pwm6: pwm@32d0000 { 849 compatible = "nvidia,tegra194-pwm", 850 "nvidia,tegra186-pwm"; 851 reg = <0x32d0000 0x10000>; 852 clocks = <&bpmp TEGRA194_CLK_PWM6>; 853 clock-names = "pwm"; 854 resets = <&bpmp TEGRA194_RESET_PWM6>; 855 reset-names = "pwm"; 856 status = "disabled"; 857 #pwm-cells = <2>; 858 }; 859 860 pwm7: pwm@32e0000 { 861 compatible = "nvidia,tegra194-pwm", 862 "nvidia,tegra186-pwm"; 863 reg = <0x32e0000 0x10000>; 864 clocks = <&bpmp TEGRA194_CLK_PWM7>; 865 clock-names = "pwm"; 866 resets = <&bpmp TEGRA194_RESET_PWM7>; 867 reset-names = "pwm"; 868 status = "disabled"; 869 #pwm-cells = <2>; 870 }; 871 872 pwm8: pwm@32f0000 { 873 compatible = "nvidia,tegra194-pwm", 874 "nvidia,tegra186-pwm"; 875 reg = <0x32f0000 0x10000>; 876 clocks = <&bpmp TEGRA194_CLK_PWM8>; 877 clock-names = "pwm"; 878 resets = <&bpmp TEGRA194_RESET_PWM8>; 879 reset-names = "pwm"; 880 status = "disabled"; 881 #pwm-cells = <2>; 882 }; 883 884 sdmmc1: mmc@3400000 { 885 compatible = "nvidia,tegra194-sdhci"; 886 reg = <0x03400000 0x10000>; 887 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 889 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 890 clock-names = "sdhci", "tmclk"; 891 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 892 reset-names = "sdhci"; 893 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 894 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 895 interconnect-names = "dma-mem", "write"; 896 iommus = <&smmu TEGRA194_SID_SDMMC1>; 897 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 898 pinctrl-0 = <&sdmmc1_3v3>; 899 pinctrl-1 = <&sdmmc1_1v8>; 900 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 901 <0x07>; 902 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 903 <0x07>; 904 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 905 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 906 <0x07>; 907 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 908 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 909 nvidia,default-tap = <0x9>; 910 nvidia,default-trim = <0x5>; 911 sd-uhs-sdr25; 912 sd-uhs-sdr50; 913 sd-uhs-ddr50; 914 sd-uhs-sdr104; 915 status = "disabled"; 916 }; 917 918 sdmmc3: mmc@3440000 { 919 compatible = "nvidia,tegra194-sdhci"; 920 reg = <0x03440000 0x10000>; 921 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 923 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 924 clock-names = "sdhci", "tmclk"; 925 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 926 reset-names = "sdhci"; 927 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 928 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 929 interconnect-names = "dma-mem", "write"; 930 iommus = <&smmu TEGRA194_SID_SDMMC3>; 931 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 932 pinctrl-0 = <&sdmmc3_3v3>; 933 pinctrl-1 = <&sdmmc3_1v8>; 934 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 935 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 936 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 937 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 938 <0x07>; 939 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 940 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 941 <0x07>; 942 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 943 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 944 nvidia,default-tap = <0x9>; 945 nvidia,default-trim = <0x5>; 946 sd-uhs-sdr25; 947 sd-uhs-sdr50; 948 sd-uhs-ddr50; 949 sd-uhs-sdr104; 950 status = "disabled"; 951 }; 952 953 sdmmc4: mmc@3460000 { 954 compatible = "nvidia,tegra194-sdhci"; 955 reg = <0x03460000 0x10000>; 956 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 958 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 959 clock-names = "sdhci", "tmclk"; 960 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 961 <&bpmp TEGRA194_CLK_PLLC4>; 962 assigned-clock-parents = 963 <&bpmp TEGRA194_CLK_PLLC4>; 964 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 965 reset-names = "sdhci"; 966 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 967 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 968 interconnect-names = "dma-mem", "write"; 969 iommus = <&smmu TEGRA194_SID_SDMMC4>; 970 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 971 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 972 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 973 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 974 <0x0a>; 975 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 976 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 977 <0x0a>; 978 nvidia,default-tap = <0x8>; 979 nvidia,default-trim = <0x14>; 980 nvidia,dqs-trim = <40>; 981 supports-cqe; 982 status = "disabled"; 983 }; 984 985 hda@3510000 { 986 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 987 reg = <0x3510000 0x10000>; 988 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&bpmp TEGRA194_CLK_HDA>, 990 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 991 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 992 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 993 resets = <&bpmp TEGRA194_RESET_HDA>, 994 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>, 995 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>; 996 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 997 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 998 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 999 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1000 interconnect-names = "dma-mem", "write"; 1001 iommus = <&smmu TEGRA194_SID_HDA>; 1002 status = "disabled"; 1003 }; 1004 1005 xusb_padctl: padctl@3520000 { 1006 compatible = "nvidia,tegra194-xusb-padctl"; 1007 reg = <0x03520000 0x1000>, 1008 <0x03540000 0x1000>; 1009 reg-names = "padctl", "ao"; 1010 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1011 1012 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1013 reset-names = "padctl"; 1014 1015 status = "disabled"; 1016 1017 pads { 1018 usb2 { 1019 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1020 clock-names = "trk"; 1021 1022 lanes { 1023 usb2-0 { 1024 nvidia,function = "xusb"; 1025 status = "disabled"; 1026 #phy-cells = <0>; 1027 }; 1028 1029 usb2-1 { 1030 nvidia,function = "xusb"; 1031 status = "disabled"; 1032 #phy-cells = <0>; 1033 }; 1034 1035 usb2-2 { 1036 nvidia,function = "xusb"; 1037 status = "disabled"; 1038 #phy-cells = <0>; 1039 }; 1040 1041 usb2-3 { 1042 nvidia,function = "xusb"; 1043 status = "disabled"; 1044 #phy-cells = <0>; 1045 }; 1046 }; 1047 }; 1048 1049 usb3 { 1050 lanes { 1051 usb3-0 { 1052 nvidia,function = "xusb"; 1053 status = "disabled"; 1054 #phy-cells = <0>; 1055 }; 1056 1057 usb3-1 { 1058 nvidia,function = "xusb"; 1059 status = "disabled"; 1060 #phy-cells = <0>; 1061 }; 1062 1063 usb3-2 { 1064 nvidia,function = "xusb"; 1065 status = "disabled"; 1066 #phy-cells = <0>; 1067 }; 1068 1069 usb3-3 { 1070 nvidia,function = "xusb"; 1071 status = "disabled"; 1072 #phy-cells = <0>; 1073 }; 1074 }; 1075 }; 1076 }; 1077 1078 ports { 1079 usb2-0 { 1080 status = "disabled"; 1081 }; 1082 1083 usb2-1 { 1084 status = "disabled"; 1085 }; 1086 1087 usb2-2 { 1088 status = "disabled"; 1089 }; 1090 1091 usb2-3 { 1092 status = "disabled"; 1093 }; 1094 1095 usb3-0 { 1096 status = "disabled"; 1097 }; 1098 1099 usb3-1 { 1100 status = "disabled"; 1101 }; 1102 1103 usb3-2 { 1104 status = "disabled"; 1105 }; 1106 1107 usb3-3 { 1108 status = "disabled"; 1109 }; 1110 }; 1111 }; 1112 1113 usb@3550000 { 1114 compatible = "nvidia,tegra194-xudc"; 1115 reg = <0x03550000 0x8000>, 1116 <0x03558000 0x1000>; 1117 reg-names = "base", "fpci"; 1118 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1119 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1120 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1121 <&bpmp TEGRA194_CLK_XUSB_SS>, 1122 <&bpmp TEGRA194_CLK_XUSB_FS>; 1123 clock-names = "dev", "ss", "ss_src", "fs_src"; 1124 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1125 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1126 interconnect-names = "dma-mem", "write"; 1127 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1128 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1129 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1130 power-domain-names = "dev", "ss"; 1131 nvidia,xusb-padctl = <&xusb_padctl>; 1132 status = "disabled"; 1133 }; 1134 1135 usb@3610000 { 1136 compatible = "nvidia,tegra194-xusb"; 1137 reg = <0x03610000 0x40000>, 1138 <0x03600000 0x10000>; 1139 reg-names = "hcd", "fpci"; 1140 1141 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1143 1144 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1145 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1146 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1147 <&bpmp TEGRA194_CLK_XUSB_SS>, 1148 <&bpmp TEGRA194_CLK_CLK_M>, 1149 <&bpmp TEGRA194_CLK_XUSB_FS>, 1150 <&bpmp TEGRA194_CLK_UTMIPLL>, 1151 <&bpmp TEGRA194_CLK_CLK_M>, 1152 <&bpmp TEGRA194_CLK_PLLE>; 1153 clock-names = "xusb_host", "xusb_falcon_src", 1154 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1155 "xusb_fs_src", "pll_u_480m", "clk_m", 1156 "pll_e"; 1157 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1158 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1159 interconnect-names = "dma-mem", "write"; 1160 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1161 1162 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1163 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1164 power-domain-names = "xusb_host", "xusb_ss"; 1165 1166 nvidia,xusb-padctl = <&xusb_padctl>; 1167 status = "disabled"; 1168 }; 1169 1170 fuse@3820000 { 1171 compatible = "nvidia,tegra194-efuse"; 1172 reg = <0x03820000 0x10000>; 1173 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1174 clock-names = "fuse"; 1175 }; 1176 1177 gic: interrupt-controller@3881000 { 1178 compatible = "arm,gic-400"; 1179 #interrupt-cells = <3>; 1180 interrupt-controller; 1181 reg = <0x03881000 0x1000>, 1182 <0x03882000 0x2000>, 1183 <0x03884000 0x2000>, 1184 <0x03886000 0x2000>; 1185 interrupts = <GIC_PPI 9 1186 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1187 interrupt-parent = <&gic>; 1188 }; 1189 1190 cec@3960000 { 1191 compatible = "nvidia,tegra194-cec"; 1192 reg = <0x03960000 0x10000>; 1193 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1194 clocks = <&bpmp TEGRA194_CLK_CEC>; 1195 clock-names = "cec"; 1196 status = "disabled"; 1197 }; 1198 1199 hsp_top0: hsp@3c00000 { 1200 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1201 reg = <0x03c00000 0xa0000>; 1202 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1211 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1212 "shared3", "shared4", "shared5", "shared6", 1213 "shared7"; 1214 #mbox-cells = <2>; 1215 }; 1216 1217 p2u_hsio_0: phy@3e10000 { 1218 compatible = "nvidia,tegra194-p2u"; 1219 reg = <0x03e10000 0x10000>; 1220 reg-names = "ctl"; 1221 1222 #phy-cells = <0>; 1223 }; 1224 1225 p2u_hsio_1: phy@3e20000 { 1226 compatible = "nvidia,tegra194-p2u"; 1227 reg = <0x03e20000 0x10000>; 1228 reg-names = "ctl"; 1229 1230 #phy-cells = <0>; 1231 }; 1232 1233 p2u_hsio_2: phy@3e30000 { 1234 compatible = "nvidia,tegra194-p2u"; 1235 reg = <0x03e30000 0x10000>; 1236 reg-names = "ctl"; 1237 1238 #phy-cells = <0>; 1239 }; 1240 1241 p2u_hsio_3: phy@3e40000 { 1242 compatible = "nvidia,tegra194-p2u"; 1243 reg = <0x03e40000 0x10000>; 1244 reg-names = "ctl"; 1245 1246 #phy-cells = <0>; 1247 }; 1248 1249 p2u_hsio_4: phy@3e50000 { 1250 compatible = "nvidia,tegra194-p2u"; 1251 reg = <0x03e50000 0x10000>; 1252 reg-names = "ctl"; 1253 1254 #phy-cells = <0>; 1255 }; 1256 1257 p2u_hsio_5: phy@3e60000 { 1258 compatible = "nvidia,tegra194-p2u"; 1259 reg = <0x03e60000 0x10000>; 1260 reg-names = "ctl"; 1261 1262 #phy-cells = <0>; 1263 }; 1264 1265 p2u_hsio_6: phy@3e70000 { 1266 compatible = "nvidia,tegra194-p2u"; 1267 reg = <0x03e70000 0x10000>; 1268 reg-names = "ctl"; 1269 1270 #phy-cells = <0>; 1271 }; 1272 1273 p2u_hsio_7: phy@3e80000 { 1274 compatible = "nvidia,tegra194-p2u"; 1275 reg = <0x03e80000 0x10000>; 1276 reg-names = "ctl"; 1277 1278 #phy-cells = <0>; 1279 }; 1280 1281 p2u_hsio_8: phy@3e90000 { 1282 compatible = "nvidia,tegra194-p2u"; 1283 reg = <0x03e90000 0x10000>; 1284 reg-names = "ctl"; 1285 1286 #phy-cells = <0>; 1287 }; 1288 1289 p2u_hsio_9: phy@3ea0000 { 1290 compatible = "nvidia,tegra194-p2u"; 1291 reg = <0x03ea0000 0x10000>; 1292 reg-names = "ctl"; 1293 1294 #phy-cells = <0>; 1295 }; 1296 1297 p2u_nvhs_0: phy@3eb0000 { 1298 compatible = "nvidia,tegra194-p2u"; 1299 reg = <0x03eb0000 0x10000>; 1300 reg-names = "ctl"; 1301 1302 #phy-cells = <0>; 1303 }; 1304 1305 p2u_nvhs_1: phy@3ec0000 { 1306 compatible = "nvidia,tegra194-p2u"; 1307 reg = <0x03ec0000 0x10000>; 1308 reg-names = "ctl"; 1309 1310 #phy-cells = <0>; 1311 }; 1312 1313 p2u_nvhs_2: phy@3ed0000 { 1314 compatible = "nvidia,tegra194-p2u"; 1315 reg = <0x03ed0000 0x10000>; 1316 reg-names = "ctl"; 1317 1318 #phy-cells = <0>; 1319 }; 1320 1321 p2u_nvhs_3: phy@3ee0000 { 1322 compatible = "nvidia,tegra194-p2u"; 1323 reg = <0x03ee0000 0x10000>; 1324 reg-names = "ctl"; 1325 1326 #phy-cells = <0>; 1327 }; 1328 1329 p2u_nvhs_4: phy@3ef0000 { 1330 compatible = "nvidia,tegra194-p2u"; 1331 reg = <0x03ef0000 0x10000>; 1332 reg-names = "ctl"; 1333 1334 #phy-cells = <0>; 1335 }; 1336 1337 p2u_nvhs_5: phy@3f00000 { 1338 compatible = "nvidia,tegra194-p2u"; 1339 reg = <0x03f00000 0x10000>; 1340 reg-names = "ctl"; 1341 1342 #phy-cells = <0>; 1343 }; 1344 1345 p2u_nvhs_6: phy@3f10000 { 1346 compatible = "nvidia,tegra194-p2u"; 1347 reg = <0x03f10000 0x10000>; 1348 reg-names = "ctl"; 1349 1350 #phy-cells = <0>; 1351 }; 1352 1353 p2u_nvhs_7: phy@3f20000 { 1354 compatible = "nvidia,tegra194-p2u"; 1355 reg = <0x03f20000 0x10000>; 1356 reg-names = "ctl"; 1357 1358 #phy-cells = <0>; 1359 }; 1360 1361 p2u_hsio_10: phy@3f30000 { 1362 compatible = "nvidia,tegra194-p2u"; 1363 reg = <0x03f30000 0x10000>; 1364 reg-names = "ctl"; 1365 1366 #phy-cells = <0>; 1367 }; 1368 1369 p2u_hsio_11: phy@3f40000 { 1370 compatible = "nvidia,tegra194-p2u"; 1371 reg = <0x03f40000 0x10000>; 1372 reg-names = "ctl"; 1373 1374 #phy-cells = <0>; 1375 }; 1376 1377 hsp_aon: hsp@c150000 { 1378 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1379 reg = <0x0c150000 0x90000>; 1380 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1384 /* 1385 * Shared interrupt 0 is routed only to AON/SPE, so 1386 * we only have 4 shared interrupts for the CCPLEX. 1387 */ 1388 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1389 #mbox-cells = <2>; 1390 }; 1391 1392 gen2_i2c: i2c@c240000 { 1393 compatible = "nvidia,tegra194-i2c"; 1394 reg = <0x0c240000 0x10000>; 1395 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1399 clock-names = "div-clk"; 1400 resets = <&bpmp TEGRA194_RESET_I2C2>; 1401 reset-names = "i2c"; 1402 status = "disabled"; 1403 }; 1404 1405 gen8_i2c: i2c@c250000 { 1406 compatible = "nvidia,tegra194-i2c"; 1407 reg = <0x0c250000 0x10000>; 1408 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1412 clock-names = "div-clk"; 1413 resets = <&bpmp TEGRA194_RESET_I2C8>; 1414 reset-names = "i2c"; 1415 status = "disabled"; 1416 }; 1417 1418 uartc: serial@c280000 { 1419 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1420 reg = <0x0c280000 0x40>; 1421 reg-shift = <2>; 1422 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1423 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1424 clock-names = "serial"; 1425 resets = <&bpmp TEGRA194_RESET_UARTC>; 1426 reset-names = "serial"; 1427 status = "disabled"; 1428 }; 1429 1430 uartg: serial@c290000 { 1431 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1432 reg = <0x0c290000 0x40>; 1433 reg-shift = <2>; 1434 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1435 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1436 clock-names = "serial"; 1437 resets = <&bpmp TEGRA194_RESET_UARTG>; 1438 reset-names = "serial"; 1439 status = "disabled"; 1440 }; 1441 1442 rtc: rtc@c2a0000 { 1443 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1444 reg = <0x0c2a0000 0x10000>; 1445 interrupt-parent = <&pmc>; 1446 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1447 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1448 clock-names = "rtc"; 1449 status = "disabled"; 1450 }; 1451 1452 gpio_aon: gpio@c2f0000 { 1453 compatible = "nvidia,tegra194-gpio-aon"; 1454 reg-names = "security", "gpio"; 1455 reg = <0xc2f0000 0x1000>, 1456 <0xc2f1000 0x1000>; 1457 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1461 gpio-controller; 1462 #gpio-cells = <2>; 1463 interrupt-controller; 1464 #interrupt-cells = <2>; 1465 }; 1466 1467 pwm4: pwm@c340000 { 1468 compatible = "nvidia,tegra194-pwm", 1469 "nvidia,tegra186-pwm"; 1470 reg = <0xc340000 0x10000>; 1471 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1472 clock-names = "pwm"; 1473 resets = <&bpmp TEGRA194_RESET_PWM4>; 1474 reset-names = "pwm"; 1475 status = "disabled"; 1476 #pwm-cells = <2>; 1477 }; 1478 1479 pmc: pmc@c360000 { 1480 compatible = "nvidia,tegra194-pmc"; 1481 reg = <0x0c360000 0x10000>, 1482 <0x0c370000 0x10000>, 1483 <0x0c380000 0x10000>, 1484 <0x0c390000 0x10000>, 1485 <0x0c3a0000 0x10000>; 1486 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1487 1488 #interrupt-cells = <2>; 1489 interrupt-controller; 1490 sdmmc1_3v3: sdmmc1-3v3 { 1491 pins = "sdmmc1-hv"; 1492 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1493 }; 1494 1495 sdmmc1_1v8: sdmmc1-1v8 { 1496 pins = "sdmmc1-hv"; 1497 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1498 }; 1499 sdmmc3_3v3: sdmmc3-3v3 { 1500 pins = "sdmmc3-hv"; 1501 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1502 }; 1503 1504 sdmmc3_1v8: sdmmc3-1v8 { 1505 pins = "sdmmc3-hv"; 1506 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1507 }; 1508 1509 }; 1510 1511 iommu@10000000 { 1512 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1513 reg = <0x10000000 0x800000>; 1514 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1549 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1579 stream-match-mask = <0x7f80>; 1580 #global-interrupts = <1>; 1581 #iommu-cells = <1>; 1582 1583 nvidia,memory-controller = <&mc>; 1584 status = "okay"; 1585 }; 1586 1587 smmu: iommu@12000000 { 1588 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1589 reg = <0x12000000 0x800000>, 1590 <0x11000000 0x800000>; 1591 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1657 stream-match-mask = <0x7f80>; 1658 #global-interrupts = <2>; 1659 #iommu-cells = <1>; 1660 1661 nvidia,memory-controller = <&mc>; 1662 status = "okay"; 1663 }; 1664 1665 host1x@13e00000 { 1666 compatible = "nvidia,tegra194-host1x"; 1667 reg = <0x13e00000 0x10000>, 1668 <0x13e10000 0x10000>; 1669 reg-names = "hypervisor", "vm"; 1670 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1672 interrupt-names = "syncpt", "host1x"; 1673 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1674 clock-names = "host1x"; 1675 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1676 reset-names = "host1x"; 1677 1678 #address-cells = <1>; 1679 #size-cells = <1>; 1680 1681 ranges = <0x15000000 0x15000000 0x01000000>; 1682 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1683 interconnect-names = "dma-mem"; 1684 iommus = <&smmu TEGRA194_SID_HOST1X>; 1685 1686 nvdec@15140000 { 1687 compatible = "nvidia,tegra194-nvdec"; 1688 reg = <0x15140000 0x00040000>; 1689 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1690 clock-names = "nvdec"; 1691 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1692 reset-names = "nvdec"; 1693 1694 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1695 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1696 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1697 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1698 interconnect-names = "dma-mem", "read-1", "write"; 1699 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1700 dma-coherent; 1701 1702 nvidia,host1x-class = <0xf5>; 1703 }; 1704 1705 display-hub@15200000 { 1706 compatible = "nvidia,tegra194-display"; 1707 reg = <0x15200000 0x00040000>; 1708 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1709 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1710 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1711 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1712 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1713 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1714 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1715 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1716 "wgrp3", "wgrp4", "wgrp5"; 1717 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1718 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1719 clock-names = "disp", "hub"; 1720 status = "disabled"; 1721 1722 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1723 1724 #address-cells = <1>; 1725 #size-cells = <1>; 1726 1727 ranges = <0x15200000 0x15200000 0x40000>; 1728 1729 display@15200000 { 1730 compatible = "nvidia,tegra194-dc"; 1731 reg = <0x15200000 0x10000>; 1732 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1733 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1734 clock-names = "dc"; 1735 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1736 reset-names = "dc"; 1737 1738 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1739 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1740 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1741 interconnect-names = "dma-mem", "read-1"; 1742 1743 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1744 nvidia,head = <0>; 1745 }; 1746 1747 display@15210000 { 1748 compatible = "nvidia,tegra194-dc"; 1749 reg = <0x15210000 0x10000>; 1750 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1751 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1752 clock-names = "dc"; 1753 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1754 reset-names = "dc"; 1755 1756 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1757 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1758 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1759 interconnect-names = "dma-mem", "read-1"; 1760 1761 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1762 nvidia,head = <1>; 1763 }; 1764 1765 display@15220000 { 1766 compatible = "nvidia,tegra194-dc"; 1767 reg = <0x15220000 0x10000>; 1768 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1769 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1770 clock-names = "dc"; 1771 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1772 reset-names = "dc"; 1773 1774 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1775 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1776 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1777 interconnect-names = "dma-mem", "read-1"; 1778 1779 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1780 nvidia,head = <2>; 1781 }; 1782 1783 display@15230000 { 1784 compatible = "nvidia,tegra194-dc"; 1785 reg = <0x15230000 0x10000>; 1786 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1787 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1788 clock-names = "dc"; 1789 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1790 reset-names = "dc"; 1791 1792 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1793 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1794 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1795 interconnect-names = "dma-mem", "read-1"; 1796 1797 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1798 nvidia,head = <3>; 1799 }; 1800 }; 1801 1802 vic@15340000 { 1803 compatible = "nvidia,tegra194-vic"; 1804 reg = <0x15340000 0x00040000>; 1805 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1806 clocks = <&bpmp TEGRA194_CLK_VIC>; 1807 clock-names = "vic"; 1808 resets = <&bpmp TEGRA194_RESET_VIC>; 1809 reset-names = "vic"; 1810 1811 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1812 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1813 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1814 interconnect-names = "dma-mem", "write"; 1815 iommus = <&smmu TEGRA194_SID_VIC>; 1816 }; 1817 1818 nvjpg@15380000 { 1819 compatible = "nvidia,tegra194-nvjpg"; 1820 reg = <0x15380000 0x40000>; 1821 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1822 clock-names = "nvjpg"; 1823 resets = <&bpmp TEGRA194_RESET_NVJPG>; 1824 reset-names = "nvjpg"; 1825 1826 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1827 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1828 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1829 interconnect-names = "dma-mem", "write"; 1830 iommus = <&smmu TEGRA194_SID_NVJPG>; 1831 dma-coherent; 1832 }; 1833 1834 nvdec@15480000 { 1835 compatible = "nvidia,tegra194-nvdec"; 1836 reg = <0x15480000 0x00040000>; 1837 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 1838 clock-names = "nvdec"; 1839 resets = <&bpmp TEGRA194_RESET_NVDEC>; 1840 reset-names = "nvdec"; 1841 1842 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 1843 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 1844 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 1845 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 1846 interconnect-names = "dma-mem", "read-1", "write"; 1847 iommus = <&smmu TEGRA194_SID_NVDEC>; 1848 dma-coherent; 1849 1850 nvidia,host1x-class = <0xf0>; 1851 }; 1852 1853 nvenc@154c0000 { 1854 compatible = "nvidia,tegra194-nvenc"; 1855 reg = <0x154c0000 0x40000>; 1856 clocks = <&bpmp TEGRA194_CLK_NVENC>; 1857 clock-names = "nvenc"; 1858 resets = <&bpmp TEGRA194_RESET_NVENC>; 1859 reset-names = "nvenc"; 1860 1861 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 1862 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 1863 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 1864 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 1865 interconnect-names = "dma-mem", "read-1", "write"; 1866 iommus = <&smmu TEGRA194_SID_NVENC>; 1867 dma-coherent; 1868 1869 nvidia,host1x-class = <0x21>; 1870 }; 1871 1872 dpaux0: dpaux@155c0000 { 1873 compatible = "nvidia,tegra194-dpaux"; 1874 reg = <0x155c0000 0x10000>; 1875 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1876 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1877 <&bpmp TEGRA194_CLK_PLLDP>; 1878 clock-names = "dpaux", "parent"; 1879 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1880 reset-names = "dpaux"; 1881 status = "disabled"; 1882 1883 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1884 1885 state_dpaux0_aux: pinmux-aux { 1886 groups = "dpaux-io"; 1887 function = "aux"; 1888 }; 1889 1890 state_dpaux0_i2c: pinmux-i2c { 1891 groups = "dpaux-io"; 1892 function = "i2c"; 1893 }; 1894 1895 state_dpaux0_off: pinmux-off { 1896 groups = "dpaux-io"; 1897 function = "off"; 1898 }; 1899 1900 i2c-bus { 1901 #address-cells = <1>; 1902 #size-cells = <0>; 1903 }; 1904 }; 1905 1906 dpaux1: dpaux@155d0000 { 1907 compatible = "nvidia,tegra194-dpaux"; 1908 reg = <0x155d0000 0x10000>; 1909 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1910 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1911 <&bpmp TEGRA194_CLK_PLLDP>; 1912 clock-names = "dpaux", "parent"; 1913 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1914 reset-names = "dpaux"; 1915 status = "disabled"; 1916 1917 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1918 1919 state_dpaux1_aux: pinmux-aux { 1920 groups = "dpaux-io"; 1921 function = "aux"; 1922 }; 1923 1924 state_dpaux1_i2c: pinmux-i2c { 1925 groups = "dpaux-io"; 1926 function = "i2c"; 1927 }; 1928 1929 state_dpaux1_off: pinmux-off { 1930 groups = "dpaux-io"; 1931 function = "off"; 1932 }; 1933 1934 i2c-bus { 1935 #address-cells = <1>; 1936 #size-cells = <0>; 1937 }; 1938 }; 1939 1940 dpaux2: dpaux@155e0000 { 1941 compatible = "nvidia,tegra194-dpaux"; 1942 reg = <0x155e0000 0x10000>; 1943 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1944 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1945 <&bpmp TEGRA194_CLK_PLLDP>; 1946 clock-names = "dpaux", "parent"; 1947 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1948 reset-names = "dpaux"; 1949 status = "disabled"; 1950 1951 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1952 1953 state_dpaux2_aux: pinmux-aux { 1954 groups = "dpaux-io"; 1955 function = "aux"; 1956 }; 1957 1958 state_dpaux2_i2c: pinmux-i2c { 1959 groups = "dpaux-io"; 1960 function = "i2c"; 1961 }; 1962 1963 state_dpaux2_off: pinmux-off { 1964 groups = "dpaux-io"; 1965 function = "off"; 1966 }; 1967 1968 i2c-bus { 1969 #address-cells = <1>; 1970 #size-cells = <0>; 1971 }; 1972 }; 1973 1974 dpaux3: dpaux@155f0000 { 1975 compatible = "nvidia,tegra194-dpaux"; 1976 reg = <0x155f0000 0x10000>; 1977 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1978 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1979 <&bpmp TEGRA194_CLK_PLLDP>; 1980 clock-names = "dpaux", "parent"; 1981 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1982 reset-names = "dpaux"; 1983 status = "disabled"; 1984 1985 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1986 1987 state_dpaux3_aux: pinmux-aux { 1988 groups = "dpaux-io"; 1989 function = "aux"; 1990 }; 1991 1992 state_dpaux3_i2c: pinmux-i2c { 1993 groups = "dpaux-io"; 1994 function = "i2c"; 1995 }; 1996 1997 state_dpaux3_off: pinmux-off { 1998 groups = "dpaux-io"; 1999 function = "off"; 2000 }; 2001 2002 i2c-bus { 2003 #address-cells = <1>; 2004 #size-cells = <0>; 2005 }; 2006 }; 2007 2008 nvenc@15a80000 { 2009 compatible = "nvidia,tegra194-nvenc"; 2010 reg = <0x15a80000 0x00040000>; 2011 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2012 clock-names = "nvenc"; 2013 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2014 reset-names = "nvenc"; 2015 2016 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2017 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2018 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2019 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2020 interconnect-names = "dma-mem", "read-1", "write"; 2021 iommus = <&smmu TEGRA194_SID_NVENC1>; 2022 dma-coherent; 2023 2024 nvidia,host1x-class = <0x22>; 2025 }; 2026 2027 sor0: sor@15b00000 { 2028 compatible = "nvidia,tegra194-sor"; 2029 reg = <0x15b00000 0x40000>; 2030 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2031 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2032 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2033 <&bpmp TEGRA194_CLK_PLLD>, 2034 <&bpmp TEGRA194_CLK_PLLDP>, 2035 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2036 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2037 clock-names = "sor", "out", "parent", "dp", "safe", 2038 "pad"; 2039 resets = <&bpmp TEGRA194_RESET_SOR0>; 2040 reset-names = "sor"; 2041 pinctrl-0 = <&state_dpaux0_aux>; 2042 pinctrl-1 = <&state_dpaux0_i2c>; 2043 pinctrl-2 = <&state_dpaux0_off>; 2044 pinctrl-names = "aux", "i2c", "off"; 2045 status = "disabled"; 2046 2047 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2048 nvidia,interface = <0>; 2049 }; 2050 2051 sor1: sor@15b40000 { 2052 compatible = "nvidia,tegra194-sor"; 2053 reg = <0x15b40000 0x40000>; 2054 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2055 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2056 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2057 <&bpmp TEGRA194_CLK_PLLD2>, 2058 <&bpmp TEGRA194_CLK_PLLDP>, 2059 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2060 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2061 clock-names = "sor", "out", "parent", "dp", "safe", 2062 "pad"; 2063 resets = <&bpmp TEGRA194_RESET_SOR1>; 2064 reset-names = "sor"; 2065 pinctrl-0 = <&state_dpaux1_aux>; 2066 pinctrl-1 = <&state_dpaux1_i2c>; 2067 pinctrl-2 = <&state_dpaux1_off>; 2068 pinctrl-names = "aux", "i2c", "off"; 2069 status = "disabled"; 2070 2071 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2072 nvidia,interface = <1>; 2073 }; 2074 2075 sor2: sor@15b80000 { 2076 compatible = "nvidia,tegra194-sor"; 2077 reg = <0x15b80000 0x40000>; 2078 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2079 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2080 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2081 <&bpmp TEGRA194_CLK_PLLD3>, 2082 <&bpmp TEGRA194_CLK_PLLDP>, 2083 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2084 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2085 clock-names = "sor", "out", "parent", "dp", "safe", 2086 "pad"; 2087 resets = <&bpmp TEGRA194_RESET_SOR2>; 2088 reset-names = "sor"; 2089 pinctrl-0 = <&state_dpaux2_aux>; 2090 pinctrl-1 = <&state_dpaux2_i2c>; 2091 pinctrl-2 = <&state_dpaux2_off>; 2092 pinctrl-names = "aux", "i2c", "off"; 2093 status = "disabled"; 2094 2095 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2096 nvidia,interface = <2>; 2097 }; 2098 2099 sor3: sor@15bc0000 { 2100 compatible = "nvidia,tegra194-sor"; 2101 reg = <0x15bc0000 0x40000>; 2102 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2103 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2104 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2105 <&bpmp TEGRA194_CLK_PLLD4>, 2106 <&bpmp TEGRA194_CLK_PLLDP>, 2107 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2108 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2109 clock-names = "sor", "out", "parent", "dp", "safe", 2110 "pad"; 2111 resets = <&bpmp TEGRA194_RESET_SOR3>; 2112 reset-names = "sor"; 2113 pinctrl-0 = <&state_dpaux3_aux>; 2114 pinctrl-1 = <&state_dpaux3_i2c>; 2115 pinctrl-2 = <&state_dpaux3_off>; 2116 pinctrl-names = "aux", "i2c", "off"; 2117 status = "disabled"; 2118 2119 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2120 nvidia,interface = <3>; 2121 }; 2122 }; 2123 2124 gpu@17000000 { 2125 compatible = "nvidia,gv11b"; 2126 reg = <0x17000000 0x1000000>, 2127 <0x18000000 0x1000000>; 2128 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2130 interrupt-names = "stall", "nonstall"; 2131 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2132 <&bpmp TEGRA194_CLK_GPU_PWR>, 2133 <&bpmp TEGRA194_CLK_FUSE>; 2134 clock-names = "gpu", "pwr", "fuse"; 2135 resets = <&bpmp TEGRA194_RESET_GPU>; 2136 reset-names = "gpu"; 2137 dma-coherent; 2138 2139 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2140 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2141 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2142 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2143 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2144 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2145 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2146 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2147 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2148 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2149 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2150 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2151 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2152 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2153 "read-1", "read-1-hp", "write-1", 2154 "read-2", "read-2-hp", "write-2", 2155 "read-3", "read-3-hp", "write-3"; 2156 }; 2157 }; 2158 2159 pcie@14100000 { 2160 compatible = "nvidia,tegra194-pcie"; 2161 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2162 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2163 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2164 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2165 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2166 reg-names = "appl", "config", "atu_dma", "dbi"; 2167 2168 status = "disabled"; 2169 2170 #address-cells = <3>; 2171 #size-cells = <2>; 2172 device_type = "pci"; 2173 num-lanes = <1>; 2174 num-viewport = <8>; 2175 linux,pci-domain = <1>; 2176 2177 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2178 clock-names = "core"; 2179 2180 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2181 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2182 reset-names = "apb", "core"; 2183 2184 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2185 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2186 interrupt-names = "intr", "msi"; 2187 2188 #interrupt-cells = <1>; 2189 interrupt-map-mask = <0 0 0 0>; 2190 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2191 2192 nvidia,bpmp = <&bpmp 1>; 2193 2194 nvidia,aspm-cmrt-us = <60>; 2195 nvidia,aspm-pwr-on-t-us = <20>; 2196 nvidia,aspm-l0s-entrance-latency-us = <3>; 2197 2198 bus-range = <0x0 0xff>; 2199 2200 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2201 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2202 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2203 2204 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2205 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2206 interconnect-names = "dma-mem", "write"; 2207 iommus = <&smmu TEGRA194_SID_PCIE1>; 2208 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2209 iommu-map-mask = <0x0>; 2210 dma-coherent; 2211 }; 2212 2213 pcie@14120000 { 2214 compatible = "nvidia,tegra194-pcie"; 2215 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2216 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2217 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2218 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2219 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2220 reg-names = "appl", "config", "atu_dma", "dbi"; 2221 2222 status = "disabled"; 2223 2224 #address-cells = <3>; 2225 #size-cells = <2>; 2226 device_type = "pci"; 2227 num-lanes = <1>; 2228 num-viewport = <8>; 2229 linux,pci-domain = <2>; 2230 2231 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2232 clock-names = "core"; 2233 2234 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2235 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2236 reset-names = "apb", "core"; 2237 2238 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2239 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2240 interrupt-names = "intr", "msi"; 2241 2242 #interrupt-cells = <1>; 2243 interrupt-map-mask = <0 0 0 0>; 2244 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2245 2246 nvidia,bpmp = <&bpmp 2>; 2247 2248 nvidia,aspm-cmrt-us = <60>; 2249 nvidia,aspm-pwr-on-t-us = <20>; 2250 nvidia,aspm-l0s-entrance-latency-us = <3>; 2251 2252 bus-range = <0x0 0xff>; 2253 2254 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2255 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2256 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2257 2258 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2259 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2260 interconnect-names = "dma-mem", "write"; 2261 iommus = <&smmu TEGRA194_SID_PCIE2>; 2262 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2263 iommu-map-mask = <0x0>; 2264 dma-coherent; 2265 }; 2266 2267 pcie@14140000 { 2268 compatible = "nvidia,tegra194-pcie"; 2269 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2270 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2271 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2272 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2273 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2274 reg-names = "appl", "config", "atu_dma", "dbi"; 2275 2276 status = "disabled"; 2277 2278 #address-cells = <3>; 2279 #size-cells = <2>; 2280 device_type = "pci"; 2281 num-lanes = <1>; 2282 num-viewport = <8>; 2283 linux,pci-domain = <3>; 2284 2285 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2286 clock-names = "core"; 2287 2288 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2289 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2290 reset-names = "apb", "core"; 2291 2292 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2293 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2294 interrupt-names = "intr", "msi"; 2295 2296 #interrupt-cells = <1>; 2297 interrupt-map-mask = <0 0 0 0>; 2298 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2299 2300 nvidia,bpmp = <&bpmp 3>; 2301 2302 nvidia,aspm-cmrt-us = <60>; 2303 nvidia,aspm-pwr-on-t-us = <20>; 2304 nvidia,aspm-l0s-entrance-latency-us = <3>; 2305 2306 bus-range = <0x0 0xff>; 2307 2308 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2309 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2310 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2311 2312 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2313 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2314 interconnect-names = "dma-mem", "write"; 2315 iommus = <&smmu TEGRA194_SID_PCIE3>; 2316 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2317 iommu-map-mask = <0x0>; 2318 dma-coherent; 2319 }; 2320 2321 pcie@14160000 { 2322 compatible = "nvidia,tegra194-pcie"; 2323 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2324 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2325 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2326 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2327 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2328 reg-names = "appl", "config", "atu_dma", "dbi"; 2329 2330 status = "disabled"; 2331 2332 #address-cells = <3>; 2333 #size-cells = <2>; 2334 device_type = "pci"; 2335 num-lanes = <4>; 2336 num-viewport = <8>; 2337 linux,pci-domain = <4>; 2338 2339 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2340 clock-names = "core"; 2341 2342 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2343 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2344 reset-names = "apb", "core"; 2345 2346 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2347 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2348 interrupt-names = "intr", "msi"; 2349 2350 #interrupt-cells = <1>; 2351 interrupt-map-mask = <0 0 0 0>; 2352 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2353 2354 nvidia,bpmp = <&bpmp 4>; 2355 2356 nvidia,aspm-cmrt-us = <60>; 2357 nvidia,aspm-pwr-on-t-us = <20>; 2358 nvidia,aspm-l0s-entrance-latency-us = <3>; 2359 2360 bus-range = <0x0 0xff>; 2361 2362 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2363 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2364 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2365 2366 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2367 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2368 interconnect-names = "dma-mem", "write"; 2369 iommus = <&smmu TEGRA194_SID_PCIE4>; 2370 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2371 iommu-map-mask = <0x0>; 2372 dma-coherent; 2373 }; 2374 2375 pcie@14180000 { 2376 compatible = "nvidia,tegra194-pcie"; 2377 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2378 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2379 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2380 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2381 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2382 reg-names = "appl", "config", "atu_dma", "dbi"; 2383 2384 status = "disabled"; 2385 2386 #address-cells = <3>; 2387 #size-cells = <2>; 2388 device_type = "pci"; 2389 num-lanes = <8>; 2390 num-viewport = <8>; 2391 linux,pci-domain = <0>; 2392 2393 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2394 clock-names = "core"; 2395 2396 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2397 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2398 reset-names = "apb", "core"; 2399 2400 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2401 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2402 interrupt-names = "intr", "msi"; 2403 2404 #interrupt-cells = <1>; 2405 interrupt-map-mask = <0 0 0 0>; 2406 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2407 2408 nvidia,bpmp = <&bpmp 0>; 2409 2410 nvidia,aspm-cmrt-us = <60>; 2411 nvidia,aspm-pwr-on-t-us = <20>; 2412 nvidia,aspm-l0s-entrance-latency-us = <3>; 2413 2414 bus-range = <0x0 0xff>; 2415 2416 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2417 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2418 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2419 2420 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2421 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2422 interconnect-names = "dma-mem", "write"; 2423 iommus = <&smmu TEGRA194_SID_PCIE0>; 2424 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2425 iommu-map-mask = <0x0>; 2426 dma-coherent; 2427 }; 2428 2429 pcie@141a0000 { 2430 compatible = "nvidia,tegra194-pcie"; 2431 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2432 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2433 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2434 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2435 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2436 reg-names = "appl", "config", "atu_dma", "dbi"; 2437 2438 status = "disabled"; 2439 2440 #address-cells = <3>; 2441 #size-cells = <2>; 2442 device_type = "pci"; 2443 num-lanes = <8>; 2444 num-viewport = <8>; 2445 linux,pci-domain = <5>; 2446 2447 pinctrl-names = "default"; 2448 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2449 2450 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 2451 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 2452 clock-names = "core", "core_m"; 2453 2454 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2455 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2456 reset-names = "apb", "core"; 2457 2458 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2459 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2460 interrupt-names = "intr", "msi"; 2461 2462 nvidia,bpmp = <&bpmp 5>; 2463 2464 #interrupt-cells = <1>; 2465 interrupt-map-mask = <0 0 0 0>; 2466 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2467 2468 nvidia,aspm-cmrt-us = <60>; 2469 nvidia,aspm-pwr-on-t-us = <20>; 2470 nvidia,aspm-l0s-entrance-latency-us = <3>; 2471 2472 bus-range = <0x0 0xff>; 2473 2474 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2475 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2476 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2477 2478 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2479 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2480 interconnect-names = "dma-mem", "write"; 2481 iommus = <&smmu TEGRA194_SID_PCIE5>; 2482 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2483 iommu-map-mask = <0x0>; 2484 dma-coherent; 2485 }; 2486 2487 pcie-ep@14160000 { 2488 compatible = "nvidia,tegra194-pcie-ep"; 2489 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2490 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2491 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2492 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2493 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2494 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2495 2496 status = "disabled"; 2497 2498 num-lanes = <4>; 2499 num-ib-windows = <2>; 2500 num-ob-windows = <8>; 2501 2502 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2503 clock-names = "core"; 2504 2505 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2506 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2507 reset-names = "apb", "core"; 2508 2509 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2510 interrupt-names = "intr"; 2511 2512 nvidia,bpmp = <&bpmp 4>; 2513 2514 nvidia,aspm-cmrt-us = <60>; 2515 nvidia,aspm-pwr-on-t-us = <20>; 2516 nvidia,aspm-l0s-entrance-latency-us = <3>; 2517 2518 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2519 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2520 interconnect-names = "dma-mem", "write"; 2521 iommus = <&smmu TEGRA194_SID_PCIE4>; 2522 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2523 iommu-map-mask = <0x0>; 2524 dma-coherent; 2525 }; 2526 2527 pcie-ep@14180000 { 2528 compatible = "nvidia,tegra194-pcie-ep"; 2529 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2530 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2531 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2532 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2533 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2534 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2535 2536 status = "disabled"; 2537 2538 num-lanes = <8>; 2539 num-ib-windows = <2>; 2540 num-ob-windows = <8>; 2541 2542 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2543 clock-names = "core"; 2544 2545 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2546 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2547 reset-names = "apb", "core"; 2548 2549 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2550 interrupt-names = "intr"; 2551 2552 nvidia,bpmp = <&bpmp 0>; 2553 2554 nvidia,aspm-cmrt-us = <60>; 2555 nvidia,aspm-pwr-on-t-us = <20>; 2556 nvidia,aspm-l0s-entrance-latency-us = <3>; 2557 2558 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2559 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2560 interconnect-names = "dma-mem", "write"; 2561 iommus = <&smmu TEGRA194_SID_PCIE0>; 2562 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2563 iommu-map-mask = <0x0>; 2564 dma-coherent; 2565 }; 2566 2567 pcie-ep@141a0000 { 2568 compatible = "nvidia,tegra194-pcie-ep"; 2569 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2570 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2571 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2572 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2573 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2574 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2575 2576 status = "disabled"; 2577 2578 num-lanes = <8>; 2579 num-ib-windows = <2>; 2580 num-ob-windows = <8>; 2581 2582 pinctrl-names = "default"; 2583 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2584 2585 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2586 clock-names = "core"; 2587 2588 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2589 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2590 reset-names = "apb", "core"; 2591 2592 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2593 interrupt-names = "intr"; 2594 2595 nvidia,bpmp = <&bpmp 5>; 2596 2597 nvidia,aspm-cmrt-us = <60>; 2598 nvidia,aspm-pwr-on-t-us = <20>; 2599 nvidia,aspm-l0s-entrance-latency-us = <3>; 2600 2601 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2602 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2603 interconnect-names = "dma-mem", "write"; 2604 iommus = <&smmu TEGRA194_SID_PCIE5>; 2605 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2606 iommu-map-mask = <0x0>; 2607 dma-coherent; 2608 }; 2609 2610 sram@40000000 { 2611 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2612 reg = <0x0 0x40000000 0x0 0x50000>; 2613 #address-cells = <1>; 2614 #size-cells = <1>; 2615 ranges = <0x0 0x0 0x40000000 0x50000>; 2616 2617 cpu_bpmp_tx: sram@4e000 { 2618 reg = <0x4e000 0x1000>; 2619 label = "cpu-bpmp-tx"; 2620 pool; 2621 }; 2622 2623 cpu_bpmp_rx: sram@4f000 { 2624 reg = <0x4f000 0x1000>; 2625 label = "cpu-bpmp-rx"; 2626 pool; 2627 }; 2628 }; 2629 2630 bpmp: bpmp { 2631 compatible = "nvidia,tegra186-bpmp"; 2632 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2633 TEGRA_HSP_DB_MASTER_BPMP>; 2634 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2635 #clock-cells = <1>; 2636 #reset-cells = <1>; 2637 #power-domain-cells = <1>; 2638 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2639 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2640 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2641 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2642 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2643 iommus = <&smmu TEGRA194_SID_BPMP>; 2644 2645 bpmp_i2c: i2c { 2646 compatible = "nvidia,tegra186-bpmp-i2c"; 2647 nvidia,bpmp-bus-id = <5>; 2648 #address-cells = <1>; 2649 #size-cells = <0>; 2650 }; 2651 2652 bpmp_thermal: thermal { 2653 compatible = "nvidia,tegra186-bpmp-thermal"; 2654 #thermal-sensor-cells = <1>; 2655 }; 2656 }; 2657 2658 cpus { 2659 compatible = "nvidia,tegra194-ccplex"; 2660 nvidia,bpmp = <&bpmp>; 2661 #address-cells = <1>; 2662 #size-cells = <0>; 2663 2664 cpu0_0: cpu@0 { 2665 compatible = "nvidia,tegra194-carmel"; 2666 device_type = "cpu"; 2667 reg = <0x000>; 2668 enable-method = "psci"; 2669 i-cache-size = <131072>; 2670 i-cache-line-size = <64>; 2671 i-cache-sets = <512>; 2672 d-cache-size = <65536>; 2673 d-cache-line-size = <64>; 2674 d-cache-sets = <256>; 2675 next-level-cache = <&l2c_0>; 2676 }; 2677 2678 cpu0_1: cpu@1 { 2679 compatible = "nvidia,tegra194-carmel"; 2680 device_type = "cpu"; 2681 reg = <0x001>; 2682 enable-method = "psci"; 2683 i-cache-size = <131072>; 2684 i-cache-line-size = <64>; 2685 i-cache-sets = <512>; 2686 d-cache-size = <65536>; 2687 d-cache-line-size = <64>; 2688 d-cache-sets = <256>; 2689 next-level-cache = <&l2c_0>; 2690 }; 2691 2692 cpu1_0: cpu@100 { 2693 compatible = "nvidia,tegra194-carmel"; 2694 device_type = "cpu"; 2695 reg = <0x100>; 2696 enable-method = "psci"; 2697 i-cache-size = <131072>; 2698 i-cache-line-size = <64>; 2699 i-cache-sets = <512>; 2700 d-cache-size = <65536>; 2701 d-cache-line-size = <64>; 2702 d-cache-sets = <256>; 2703 next-level-cache = <&l2c_1>; 2704 }; 2705 2706 cpu1_1: cpu@101 { 2707 compatible = "nvidia,tegra194-carmel"; 2708 device_type = "cpu"; 2709 reg = <0x101>; 2710 enable-method = "psci"; 2711 i-cache-size = <131072>; 2712 i-cache-line-size = <64>; 2713 i-cache-sets = <512>; 2714 d-cache-size = <65536>; 2715 d-cache-line-size = <64>; 2716 d-cache-sets = <256>; 2717 next-level-cache = <&l2c_1>; 2718 }; 2719 2720 cpu2_0: cpu@200 { 2721 compatible = "nvidia,tegra194-carmel"; 2722 device_type = "cpu"; 2723 reg = <0x200>; 2724 enable-method = "psci"; 2725 i-cache-size = <131072>; 2726 i-cache-line-size = <64>; 2727 i-cache-sets = <512>; 2728 d-cache-size = <65536>; 2729 d-cache-line-size = <64>; 2730 d-cache-sets = <256>; 2731 next-level-cache = <&l2c_2>; 2732 }; 2733 2734 cpu2_1: cpu@201 { 2735 compatible = "nvidia,tegra194-carmel"; 2736 device_type = "cpu"; 2737 reg = <0x201>; 2738 enable-method = "psci"; 2739 i-cache-size = <131072>; 2740 i-cache-line-size = <64>; 2741 i-cache-sets = <512>; 2742 d-cache-size = <65536>; 2743 d-cache-line-size = <64>; 2744 d-cache-sets = <256>; 2745 next-level-cache = <&l2c_2>; 2746 }; 2747 2748 cpu3_0: cpu@300 { 2749 compatible = "nvidia,tegra194-carmel"; 2750 device_type = "cpu"; 2751 reg = <0x300>; 2752 enable-method = "psci"; 2753 i-cache-size = <131072>; 2754 i-cache-line-size = <64>; 2755 i-cache-sets = <512>; 2756 d-cache-size = <65536>; 2757 d-cache-line-size = <64>; 2758 d-cache-sets = <256>; 2759 next-level-cache = <&l2c_3>; 2760 }; 2761 2762 cpu3_1: cpu@301 { 2763 compatible = "nvidia,tegra194-carmel"; 2764 device_type = "cpu"; 2765 reg = <0x301>; 2766 enable-method = "psci"; 2767 i-cache-size = <131072>; 2768 i-cache-line-size = <64>; 2769 i-cache-sets = <512>; 2770 d-cache-size = <65536>; 2771 d-cache-line-size = <64>; 2772 d-cache-sets = <256>; 2773 next-level-cache = <&l2c_3>; 2774 }; 2775 2776 cpu-map { 2777 cluster0 { 2778 core0 { 2779 cpu = <&cpu0_0>; 2780 }; 2781 2782 core1 { 2783 cpu = <&cpu0_1>; 2784 }; 2785 }; 2786 2787 cluster1 { 2788 core0 { 2789 cpu = <&cpu1_0>; 2790 }; 2791 2792 core1 { 2793 cpu = <&cpu1_1>; 2794 }; 2795 }; 2796 2797 cluster2 { 2798 core0 { 2799 cpu = <&cpu2_0>; 2800 }; 2801 2802 core1 { 2803 cpu = <&cpu2_1>; 2804 }; 2805 }; 2806 2807 cluster3 { 2808 core0 { 2809 cpu = <&cpu3_0>; 2810 }; 2811 2812 core1 { 2813 cpu = <&cpu3_1>; 2814 }; 2815 }; 2816 }; 2817 2818 l2c_0: l2-cache0 { 2819 cache-size = <2097152>; 2820 cache-line-size = <64>; 2821 cache-sets = <2048>; 2822 next-level-cache = <&l3c>; 2823 }; 2824 2825 l2c_1: l2-cache1 { 2826 cache-size = <2097152>; 2827 cache-line-size = <64>; 2828 cache-sets = <2048>; 2829 next-level-cache = <&l3c>; 2830 }; 2831 2832 l2c_2: l2-cache2 { 2833 cache-size = <2097152>; 2834 cache-line-size = <64>; 2835 cache-sets = <2048>; 2836 next-level-cache = <&l3c>; 2837 }; 2838 2839 l2c_3: l2-cache3 { 2840 cache-size = <2097152>; 2841 cache-line-size = <64>; 2842 cache-sets = <2048>; 2843 next-level-cache = <&l3c>; 2844 }; 2845 2846 l3c: l3-cache { 2847 cache-size = <4194304>; 2848 cache-line-size = <64>; 2849 cache-sets = <4096>; 2850 }; 2851 }; 2852 2853 pmu { 2854 compatible = "arm,armv8-pmuv3"; 2855 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2856 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2857 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2858 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 2859 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 2860 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 2861 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 2862 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 2863 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 2864 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 2865 }; 2866 2867 psci { 2868 compatible = "arm,psci-1.0"; 2869 status = "okay"; 2870 method = "smc"; 2871 }; 2872 2873 sound { 2874 status = "disabled"; 2875 2876 clocks = <&bpmp TEGRA194_CLK_PLLA>, 2877 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2878 clock-names = "pll_a", "plla_out0"; 2879 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 2880 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 2881 <&bpmp TEGRA194_CLK_AUD_MCLK>; 2882 assigned-clock-parents = <0>, 2883 <&bpmp TEGRA194_CLK_PLLA>, 2884 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2885 /* 2886 * PLLA supports dynamic ramp. Below initial rate is chosen 2887 * for this to work and oscillate between base rates required 2888 * for 8x and 11.025x sample rate streams. 2889 */ 2890 assigned-clock-rates = <258000000>; 2891 2892 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 2893 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 2894 interconnect-names = "dma-mem", "write"; 2895 iommus = <&smmu TEGRA194_SID_APE>; 2896 }; 2897 2898 tcu: tcu { 2899 compatible = "nvidia,tegra194-tcu"; 2900 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2901 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2902 mbox-names = "rx", "tx"; 2903 }; 2904 2905 thermal-zones { 2906 cpu { 2907 thermal-sensors = <&{/bpmp/thermal} 2908 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2909 status = "disabled"; 2910 }; 2911 2912 gpu { 2913 thermal-sensors = <&{/bpmp/thermal} 2914 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2915 status = "disabled"; 2916 }; 2917 2918 aux { 2919 thermal-sensors = <&{/bpmp/thermal} 2920 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2921 status = "disabled"; 2922 }; 2923 2924 pllx { 2925 thermal-sensors = <&{/bpmp/thermal} 2926 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2927 status = "disabled"; 2928 }; 2929 2930 ao { 2931 thermal-sensors = <&{/bpmp/thermal} 2932 TEGRA194_BPMP_THERMAL_ZONE_AO>; 2933 status = "disabled"; 2934 }; 2935 2936 tj { 2937 thermal-sensors = <&{/bpmp/thermal} 2938 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2939 status = "disabled"; 2940 }; 2941 }; 2942 2943 timer { 2944 compatible = "arm,armv8-timer"; 2945 interrupts = <GIC_PPI 13 2946 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2947 <GIC_PPI 14 2948 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2949 <GIC_PPI 11 2950 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2951 <GIC_PPI 10 2952 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2953 interrupt-parent = <&gic>; 2954 always-on; 2955 }; 2956}; 2957