1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra194-clock.h>
3#include <dt-bindings/gpio/tegra194-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7#include <dt-bindings/pinctrl/pinctrl-tegra.h>
8#include <dt-bindings/power/tegra194-powergate.h>
9#include <dt-bindings/reset/tegra194-reset.h>
10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
11#include <dt-bindings/memory/tegra194-mc.h>
12
13/ {
14	compatible = "nvidia,tegra194";
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	/* control backbone */
20	bus@0 {
21		compatible = "simple-bus";
22		#address-cells = <1>;
23		#size-cells = <1>;
24		ranges = <0x0 0x0 0x0 0x40000000>;
25
26		misc@100000 {
27			compatible = "nvidia,tegra194-misc";
28			reg = <0x00100000 0xf000>,
29			      <0x0010f000 0x1000>;
30		};
31
32		gpio: gpio@2200000 {
33			compatible = "nvidia,tegra194-gpio";
34			reg-names = "security", "gpio";
35			reg = <0x2200000 0x10000>,
36			      <0x2210000 0x10000>;
37			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
38				     <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
39				     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
40				     <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
41				     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
42				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
43				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
44				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
45				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
46				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
47				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
48				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
49				     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
50				     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
51				     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
52				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
53				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
54				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
55				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
56				     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
57				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
58				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
59				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
60				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
61				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
62				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
63				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
64				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
65				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
66				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
67				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
68				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
69				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
70				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
71				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
72				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
73				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
74				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
75				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
76				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
77				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
78				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
79				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
80				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
81				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
82				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
83				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
84				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
85			#interrupt-cells = <2>;
86			interrupt-controller;
87			#gpio-cells = <2>;
88			gpio-controller;
89		};
90
91		ethernet@2490000 {
92			compatible = "nvidia,tegra194-eqos",
93				     "nvidia,tegra186-eqos",
94				     "snps,dwc-qos-ethernet-4.10";
95			reg = <0x02490000 0x10000>;
96			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
97			clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
98				 <&bpmp TEGRA194_CLK_EQOS_AXI>,
99				 <&bpmp TEGRA194_CLK_EQOS_RX>,
100				 <&bpmp TEGRA194_CLK_EQOS_TX>,
101				 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
102			clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
103			resets = <&bpmp TEGRA194_RESET_EQOS>;
104			reset-names = "eqos";
105			interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
106					<&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
107			interconnect-names = "dma-mem", "write";
108			iommus = <&smmu TEGRA194_SID_EQOS>;
109			status = "disabled";
110
111			snps,write-requests = <1>;
112			snps,read-requests = <3>;
113			snps,burst-map = <0x7>;
114			snps,txpbl = <16>;
115			snps,rxpbl = <8>;
116		};
117
118		aconnect@2900000 {
119			compatible = "nvidia,tegra194-aconnect",
120				     "nvidia,tegra210-aconnect";
121			clocks = <&bpmp TEGRA194_CLK_APE>,
122				 <&bpmp TEGRA194_CLK_APB2APE>;
123			clock-names = "ape", "apb2ape";
124			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
125			#address-cells = <1>;
126			#size-cells = <1>;
127			ranges = <0x02900000 0x02900000 0x200000>;
128			status = "disabled";
129
130			adma: dma-controller@2930000 {
131				compatible = "nvidia,tegra194-adma",
132					     "nvidia,tegra186-adma";
133				reg = <0x02930000 0x20000>;
134				interrupt-parent = <&agic>;
135				interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
136					      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
137					      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
138					      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
139					      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
140					      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
141					      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
142					      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
143					      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
144					      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
145					      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
146					      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
147					      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
148					      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
149					      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
150					      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
151					      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
152					      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
153					      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
154					      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
155					      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
156					      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
157					      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
158					      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
159					      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
160					      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
161					      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
162					      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
163					      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
164					      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
165					      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
166					      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
167				#dma-cells = <1>;
168				clocks = <&bpmp TEGRA194_CLK_AHUB>;
169				clock-names = "d_audio";
170				status = "disabled";
171			};
172
173			agic: interrupt-controller@2a40000 {
174				compatible = "nvidia,tegra194-agic",
175					     "nvidia,tegra210-agic";
176				#interrupt-cells = <3>;
177				interrupt-controller;
178				reg = <0x02a41000 0x1000>,
179				      <0x02a42000 0x2000>;
180				interrupts = <GIC_SPI 145
181					      (GIC_CPU_MASK_SIMPLE(4) |
182					       IRQ_TYPE_LEVEL_HIGH)>;
183				clocks = <&bpmp TEGRA194_CLK_APE>;
184				clock-names = "clk";
185				status = "disabled";
186			};
187
188			tegra_ahub: ahub@2900800 {
189				compatible = "nvidia,tegra194-ahub",
190					     "nvidia,tegra186-ahub";
191				reg = <0x02900800 0x800>;
192				clocks = <&bpmp TEGRA194_CLK_AHUB>;
193				clock-names = "ahub";
194				assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
195				assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
196				#address-cells = <1>;
197				#size-cells = <1>;
198				ranges = <0x02900800 0x02900800 0x11800>;
199				status = "disabled";
200
201				tegra_admaif: admaif@290f000 {
202					compatible = "nvidia,tegra194-admaif",
203						     "nvidia,tegra186-admaif";
204					reg = <0x0290f000 0x1000>;
205					dmas = <&adma 1>, <&adma 1>,
206					       <&adma 2>, <&adma 2>,
207					       <&adma 3>, <&adma 3>,
208					       <&adma 4>, <&adma 4>,
209					       <&adma 5>, <&adma 5>,
210					       <&adma 6>, <&adma 6>,
211					       <&adma 7>, <&adma 7>,
212					       <&adma 8>, <&adma 8>,
213					       <&adma 9>, <&adma 9>,
214					       <&adma 10>, <&adma 10>,
215					       <&adma 11>, <&adma 11>,
216					       <&adma 12>, <&adma 12>,
217					       <&adma 13>, <&adma 13>,
218					       <&adma 14>, <&adma 14>,
219					       <&adma 15>, <&adma 15>,
220					       <&adma 16>, <&adma 16>,
221					       <&adma 17>, <&adma 17>,
222					       <&adma 18>, <&adma 18>,
223					       <&adma 19>, <&adma 19>,
224					       <&adma 20>, <&adma 20>;
225					dma-names = "rx1", "tx1",
226						    "rx2", "tx2",
227						    "rx3", "tx3",
228						    "rx4", "tx4",
229						    "rx5", "tx5",
230						    "rx6", "tx6",
231						    "rx7", "tx7",
232						    "rx8", "tx8",
233						    "rx9", "tx9",
234						    "rx10", "tx10",
235						    "rx11", "tx11",
236						    "rx12", "tx12",
237						    "rx13", "tx13",
238						    "rx14", "tx14",
239						    "rx15", "tx15",
240						    "rx16", "tx16",
241						    "rx17", "tx17",
242						    "rx18", "tx18",
243						    "rx19", "tx19",
244						    "rx20", "tx20";
245					status = "disabled";
246				};
247
248				tegra_i2s1: i2s@2901000 {
249					compatible = "nvidia,tegra194-i2s",
250						     "nvidia,tegra210-i2s";
251					reg = <0x2901000 0x100>;
252					clocks = <&bpmp TEGRA194_CLK_I2S1>,
253						 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
254					clock-names = "i2s", "sync_input";
255					assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
256					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
257					assigned-clock-rates = <1536000>;
258					sound-name-prefix = "I2S1";
259					status = "disabled";
260				};
261
262				tegra_i2s2: i2s@2901100 {
263					compatible = "nvidia,tegra194-i2s",
264						     "nvidia,tegra210-i2s";
265					reg = <0x2901100 0x100>;
266					clocks = <&bpmp TEGRA194_CLK_I2S2>,
267						 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
268					clock-names = "i2s", "sync_input";
269					assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
270					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
271					assigned-clock-rates = <1536000>;
272					sound-name-prefix = "I2S2";
273					status = "disabled";
274				};
275
276				tegra_i2s3: i2s@2901200 {
277					compatible = "nvidia,tegra194-i2s",
278						     "nvidia,tegra210-i2s";
279					reg = <0x2901200 0x100>;
280					clocks = <&bpmp TEGRA194_CLK_I2S3>,
281						 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
282					clock-names = "i2s", "sync_input";
283					assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
284					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
285					assigned-clock-rates = <1536000>;
286					sound-name-prefix = "I2S3";
287					status = "disabled";
288				};
289
290				tegra_i2s4: i2s@2901300 {
291					compatible = "nvidia,tegra194-i2s",
292						     "nvidia,tegra210-i2s";
293					reg = <0x2901300 0x100>;
294					clocks = <&bpmp TEGRA194_CLK_I2S4>,
295						 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
296					clock-names = "i2s", "sync_input";
297					assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
298					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
299					assigned-clock-rates = <1536000>;
300					sound-name-prefix = "I2S4";
301					status = "disabled";
302				};
303
304				tegra_i2s5: i2s@2901400 {
305					compatible = "nvidia,tegra194-i2s",
306						     "nvidia,tegra210-i2s";
307					reg = <0x2901400 0x100>;
308					clocks = <&bpmp TEGRA194_CLK_I2S5>,
309						 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
310					clock-names = "i2s", "sync_input";
311					assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
312					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
313					assigned-clock-rates = <1536000>;
314					sound-name-prefix = "I2S5";
315					status = "disabled";
316				};
317
318				tegra_i2s6: i2s@2901500 {
319					compatible = "nvidia,tegra194-i2s",
320						     "nvidia,tegra210-i2s";
321					reg = <0x2901500 0x100>;
322					clocks = <&bpmp TEGRA194_CLK_I2S6>,
323						 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
324					clock-names = "i2s", "sync_input";
325					assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
326					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
327					assigned-clock-rates = <1536000>;
328					sound-name-prefix = "I2S6";
329					status = "disabled";
330				};
331
332				tegra_dmic1: dmic@2904000 {
333					compatible = "nvidia,tegra194-dmic",
334						     "nvidia,tegra210-dmic";
335					reg = <0x2904000 0x100>;
336					clocks = <&bpmp TEGRA194_CLK_DMIC1>;
337					clock-names = "dmic";
338					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
339					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
340					assigned-clock-rates = <3072000>;
341					sound-name-prefix = "DMIC1";
342					status = "disabled";
343				};
344
345				tegra_dmic2: dmic@2904100 {
346					compatible = "nvidia,tegra194-dmic",
347						     "nvidia,tegra210-dmic";
348					reg = <0x2904100 0x100>;
349					clocks = <&bpmp TEGRA194_CLK_DMIC2>;
350					clock-names = "dmic";
351					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
352					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
353					assigned-clock-rates = <3072000>;
354					sound-name-prefix = "DMIC2";
355					status = "disabled";
356				};
357
358				tegra_dmic3: dmic@2904200 {
359					compatible = "nvidia,tegra194-dmic",
360						     "nvidia,tegra210-dmic";
361					reg = <0x2904200 0x100>;
362					clocks = <&bpmp TEGRA194_CLK_DMIC3>;
363					clock-names = "dmic";
364					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
365					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
366					assigned-clock-rates = <3072000>;
367					sound-name-prefix = "DMIC3";
368					status = "disabled";
369				};
370
371				tegra_dmic4: dmic@2904300 {
372					compatible = "nvidia,tegra194-dmic",
373						     "nvidia,tegra210-dmic";
374					reg = <0x2904300 0x100>;
375					clocks = <&bpmp TEGRA194_CLK_DMIC4>;
376					clock-names = "dmic";
377					assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
378					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
379					assigned-clock-rates = <3072000>;
380					sound-name-prefix = "DMIC4";
381					status = "disabled";
382				};
383
384				tegra_dspk1: dspk@2905000 {
385					compatible = "nvidia,tegra194-dspk",
386						     "nvidia,tegra186-dspk";
387					reg = <0x2905000 0x100>;
388					clocks = <&bpmp TEGRA194_CLK_DSPK1>;
389					clock-names = "dspk";
390					assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
391					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
392					assigned-clock-rates = <12288000>;
393					sound-name-prefix = "DSPK1";
394					status = "disabled";
395				};
396
397				tegra_dspk2: dspk@2905100 {
398					compatible = "nvidia,tegra194-dspk",
399						     "nvidia,tegra186-dspk";
400					reg = <0x2905100 0x100>;
401					clocks = <&bpmp TEGRA194_CLK_DSPK2>;
402					clock-names = "dspk";
403					assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
404					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
405					assigned-clock-rates = <12288000>;
406					sound-name-prefix = "DSPK2";
407					status = "disabled";
408				};
409
410				tegra_sfc1: sfc@2902000 {
411					compatible = "nvidia,tegra194-sfc",
412						     "nvidia,tegra210-sfc";
413					reg = <0x2902000 0x200>;
414					sound-name-prefix = "SFC1";
415					status = "disabled";
416				};
417
418				tegra_sfc2: sfc@2902200 {
419					compatible = "nvidia,tegra194-sfc",
420						     "nvidia,tegra210-sfc";
421					reg = <0x2902200 0x200>;
422					sound-name-prefix = "SFC2";
423					status = "disabled";
424				};
425
426				tegra_sfc3: sfc@2902400 {
427					compatible = "nvidia,tegra194-sfc",
428						     "nvidia,tegra210-sfc";
429					reg = <0x2902400 0x200>;
430					sound-name-prefix = "SFC3";
431					status = "disabled";
432				};
433
434				tegra_sfc4: sfc@2902600 {
435					compatible = "nvidia,tegra194-sfc",
436						     "nvidia,tegra210-sfc";
437					reg = <0x2902600 0x200>;
438					sound-name-prefix = "SFC4";
439					status = "disabled";
440				};
441
442				tegra_mvc1: mvc@290a000 {
443					compatible = "nvidia,tegra194-mvc",
444						     "nvidia,tegra210-mvc";
445					reg = <0x290a000 0x200>;
446					sound-name-prefix = "MVC1";
447					status = "disabled";
448				};
449
450				tegra_mvc2: mvc@290a200 {
451					compatible = "nvidia,tegra194-mvc",
452						     "nvidia,tegra210-mvc";
453					reg = <0x290a200 0x200>;
454					sound-name-prefix = "MVC2";
455					status = "disabled";
456				};
457
458				tegra_amx1: amx@2903000 {
459					compatible = "nvidia,tegra194-amx";
460					reg = <0x2903000 0x100>;
461					sound-name-prefix = "AMX1";
462					status = "disabled";
463				};
464
465				tegra_amx2: amx@2903100 {
466					compatible = "nvidia,tegra194-amx";
467					reg = <0x2903100 0x100>;
468					sound-name-prefix = "AMX2";
469					status = "disabled";
470				};
471
472				tegra_amx3: amx@2903200 {
473					compatible = "nvidia,tegra194-amx";
474					reg = <0x2903200 0x100>;
475					sound-name-prefix = "AMX3";
476					status = "disabled";
477				};
478
479				tegra_amx4: amx@2903300 {
480					compatible = "nvidia,tegra194-amx";
481					reg = <0x2903300 0x100>;
482					sound-name-prefix = "AMX4";
483					status = "disabled";
484				};
485
486				tegra_adx1: adx@2903800 {
487					compatible = "nvidia,tegra194-adx",
488						     "nvidia,tegra210-adx";
489					reg = <0x2903800 0x100>;
490					sound-name-prefix = "ADX1";
491					status = "disabled";
492				};
493
494				tegra_adx2: adx@2903900 {
495					compatible = "nvidia,tegra194-adx",
496						     "nvidia,tegra210-adx";
497					reg = <0x2903900 0x100>;
498					sound-name-prefix = "ADX2";
499					status = "disabled";
500				};
501
502				tegra_adx3: adx@2903a00 {
503					compatible = "nvidia,tegra194-adx",
504						     "nvidia,tegra210-adx";
505					reg = <0x2903a00 0x100>;
506					sound-name-prefix = "ADX3";
507					status = "disabled";
508				};
509
510				tegra_adx4: adx@2903b00 {
511					compatible = "nvidia,tegra194-adx",
512						     "nvidia,tegra210-adx";
513					reg = <0x2903b00 0x100>;
514					sound-name-prefix = "ADX4";
515					status = "disabled";
516				};
517
518				tegra_amixer: amixer@290bb00 {
519					compatible = "nvidia,tegra194-amixer",
520						     "nvidia,tegra210-amixer";
521					reg = <0x290bb00 0x800>;
522					sound-name-prefix = "MIXER1";
523					status = "disabled";
524				};
525			};
526		};
527
528		pinmux: pinmux@2430000 {
529			compatible = "nvidia,tegra194-pinmux";
530			reg = <0x2430000 0x17000>,
531			      <0xc300000 0x4000>;
532
533			status = "okay";
534
535			pex_rst_c5_out_state: pex_rst_c5_out {
536				pex_rst {
537					nvidia,pins = "pex_l5_rst_n_pgg1";
538					nvidia,schmitt = <TEGRA_PIN_DISABLE>;
539					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
540					nvidia,io-hv = <TEGRA_PIN_ENABLE>;
541					nvidia,tristate = <TEGRA_PIN_DISABLE>;
542					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
543				};
544			};
545
546			clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
547				clkreq {
548					nvidia,pins = "pex_l5_clkreq_n_pgg0";
549					nvidia,schmitt = <TEGRA_PIN_DISABLE>;
550					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
551					nvidia,io-hv = <TEGRA_PIN_ENABLE>;
552					nvidia,tristate = <TEGRA_PIN_DISABLE>;
553					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
554				};
555			};
556		};
557
558		mc: memory-controller@2c00000 {
559			compatible = "nvidia,tegra194-mc";
560			reg = <0x02c00000 0x100000>,
561			      <0x02b80000 0x040000>,
562			      <0x01700000 0x100000>;
563			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
564			#interconnect-cells = <1>;
565			status = "disabled";
566
567			#address-cells = <2>;
568			#size-cells = <2>;
569
570			ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
571				 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
572				 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
573
574			/*
575			 * Bit 39 of addresses passing through the memory
576			 * controller selects the XBAR format used when memory
577			 * is accessed. This is used to transparently access
578			 * memory in the XBAR format used by the discrete GPU
579			 * (bit 39 set) or Tegra (bit 39 clear).
580			 *
581			 * As a consequence, the operating system must ensure
582			 * that bit 39 is never used implicitly, for example
583			 * via an I/O virtual address mapping of an IOMMU. If
584			 * devices require access to the XBAR switch, their
585			 * drivers must set this bit explicitly.
586			 *
587			 * Limit the DMA range for memory clients to [38:0].
588			 */
589			dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
590
591			emc: external-memory-controller@2c60000 {
592				compatible = "nvidia,tegra194-emc";
593				reg = <0x0 0x02c60000 0x0 0x90000>,
594				      <0x0 0x01780000 0x0 0x80000>;
595				clocks = <&bpmp TEGRA194_CLK_EMC>;
596				clock-names = "emc";
597
598				#interconnect-cells = <0>;
599
600				nvidia,bpmp = <&bpmp>;
601			};
602		};
603
604		uarta: serial@3100000 {
605			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
606			reg = <0x03100000 0x40>;
607			reg-shift = <2>;
608			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
609			clocks = <&bpmp TEGRA194_CLK_UARTA>;
610			clock-names = "serial";
611			resets = <&bpmp TEGRA194_RESET_UARTA>;
612			reset-names = "serial";
613			status = "disabled";
614		};
615
616		uartb: serial@3110000 {
617			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
618			reg = <0x03110000 0x40>;
619			reg-shift = <2>;
620			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
621			clocks = <&bpmp TEGRA194_CLK_UARTB>;
622			clock-names = "serial";
623			resets = <&bpmp TEGRA194_RESET_UARTB>;
624			reset-names = "serial";
625			status = "disabled";
626		};
627
628		uartd: serial@3130000 {
629			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
630			reg = <0x03130000 0x40>;
631			reg-shift = <2>;
632			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
633			clocks = <&bpmp TEGRA194_CLK_UARTD>;
634			clock-names = "serial";
635			resets = <&bpmp TEGRA194_RESET_UARTD>;
636			reset-names = "serial";
637			status = "disabled";
638		};
639
640		uarte: serial@3140000 {
641			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
642			reg = <0x03140000 0x40>;
643			reg-shift = <2>;
644			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
645			clocks = <&bpmp TEGRA194_CLK_UARTE>;
646			clock-names = "serial";
647			resets = <&bpmp TEGRA194_RESET_UARTE>;
648			reset-names = "serial";
649			status = "disabled";
650		};
651
652		uartf: serial@3150000 {
653			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
654			reg = <0x03150000 0x40>;
655			reg-shift = <2>;
656			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
657			clocks = <&bpmp TEGRA194_CLK_UARTF>;
658			clock-names = "serial";
659			resets = <&bpmp TEGRA194_RESET_UARTF>;
660			reset-names = "serial";
661			status = "disabled";
662		};
663
664		gen1_i2c: i2c@3160000 {
665			compatible = "nvidia,tegra194-i2c";
666			reg = <0x03160000 0x10000>;
667			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
668			#address-cells = <1>;
669			#size-cells = <0>;
670			clocks = <&bpmp TEGRA194_CLK_I2C1>;
671			clock-names = "div-clk";
672			resets = <&bpmp TEGRA194_RESET_I2C1>;
673			reset-names = "i2c";
674			status = "disabled";
675		};
676
677		uarth: serial@3170000 {
678			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
679			reg = <0x03170000 0x40>;
680			reg-shift = <2>;
681			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
682			clocks = <&bpmp TEGRA194_CLK_UARTH>;
683			clock-names = "serial";
684			resets = <&bpmp TEGRA194_RESET_UARTH>;
685			reset-names = "serial";
686			status = "disabled";
687		};
688
689		cam_i2c: i2c@3180000 {
690			compatible = "nvidia,tegra194-i2c";
691			reg = <0x03180000 0x10000>;
692			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
693			#address-cells = <1>;
694			#size-cells = <0>;
695			clocks = <&bpmp TEGRA194_CLK_I2C3>;
696			clock-names = "div-clk";
697			resets = <&bpmp TEGRA194_RESET_I2C3>;
698			reset-names = "i2c";
699			status = "disabled";
700		};
701
702		/* shares pads with dpaux1 */
703		dp_aux_ch1_i2c: i2c@3190000 {
704			compatible = "nvidia,tegra194-i2c";
705			reg = <0x03190000 0x10000>;
706			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
707			#address-cells = <1>;
708			#size-cells = <0>;
709			clocks = <&bpmp TEGRA194_CLK_I2C4>;
710			clock-names = "div-clk";
711			resets = <&bpmp TEGRA194_RESET_I2C4>;
712			reset-names = "i2c";
713			pinctrl-0 = <&state_dpaux1_i2c>;
714			pinctrl-1 = <&state_dpaux1_off>;
715			pinctrl-names = "default", "idle";
716			status = "disabled";
717		};
718
719		/* shares pads with dpaux0 */
720		dp_aux_ch0_i2c: i2c@31b0000 {
721			compatible = "nvidia,tegra194-i2c";
722			reg = <0x031b0000 0x10000>;
723			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
724			#address-cells = <1>;
725			#size-cells = <0>;
726			clocks = <&bpmp TEGRA194_CLK_I2C6>;
727			clock-names = "div-clk";
728			resets = <&bpmp TEGRA194_RESET_I2C6>;
729			reset-names = "i2c";
730			pinctrl-0 = <&state_dpaux0_i2c>;
731			pinctrl-1 = <&state_dpaux0_off>;
732			pinctrl-names = "default", "idle";
733			status = "disabled";
734		};
735
736		/* shares pads with dpaux2 */
737		dp_aux_ch2_i2c: i2c@31c0000 {
738			compatible = "nvidia,tegra194-i2c";
739			reg = <0x031c0000 0x10000>;
740			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
741			#address-cells = <1>;
742			#size-cells = <0>;
743			clocks = <&bpmp TEGRA194_CLK_I2C7>;
744			clock-names = "div-clk";
745			resets = <&bpmp TEGRA194_RESET_I2C7>;
746			reset-names = "i2c";
747			pinctrl-0 = <&state_dpaux2_i2c>;
748			pinctrl-1 = <&state_dpaux2_off>;
749			pinctrl-names = "default", "idle";
750			status = "disabled";
751		};
752
753		/* shares pads with dpaux3 */
754		dp_aux_ch3_i2c: i2c@31e0000 {
755			compatible = "nvidia,tegra194-i2c";
756			reg = <0x031e0000 0x10000>;
757			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
758			#address-cells = <1>;
759			#size-cells = <0>;
760			clocks = <&bpmp TEGRA194_CLK_I2C9>;
761			clock-names = "div-clk";
762			resets = <&bpmp TEGRA194_RESET_I2C9>;
763			reset-names = "i2c";
764			pinctrl-0 = <&state_dpaux3_i2c>;
765			pinctrl-1 = <&state_dpaux3_off>;
766			pinctrl-names = "default", "idle";
767			status = "disabled";
768		};
769
770		spi@3270000 {
771			compatible = "nvidia,tegra194-qspi";
772			reg = <0x3270000 0x1000>;
773			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
774			#address-cells = <1>;
775			#size-cells = <0>;
776			clocks = <&bpmp TEGRA194_CLK_QSPI0>,
777				 <&bpmp TEGRA194_CLK_QSPI0_PM>;
778			clock-names = "qspi", "qspi_out";
779			resets = <&bpmp TEGRA194_RESET_QSPI0>;
780			reset-names = "qspi";
781			status = "disabled";
782		};
783
784		spi@3300000 {
785			compatible = "nvidia,tegra194-qspi";
786			reg = <0x3300000 0x1000>;
787			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
788			#address-cells = <1>;
789			#size-cells = <0>;
790			clocks = <&bpmp TEGRA194_CLK_QSPI1>,
791				 <&bpmp TEGRA194_CLK_QSPI1_PM>;
792			clock-names = "qspi", "qspi_out";
793			resets = <&bpmp TEGRA194_RESET_QSPI1>;
794			reset-names = "qspi";
795			status = "disabled";
796		};
797
798		pwm1: pwm@3280000 {
799			compatible = "nvidia,tegra194-pwm",
800				     "nvidia,tegra186-pwm";
801			reg = <0x3280000 0x10000>;
802			clocks = <&bpmp TEGRA194_CLK_PWM1>;
803			clock-names = "pwm";
804			resets = <&bpmp TEGRA194_RESET_PWM1>;
805			reset-names = "pwm";
806			status = "disabled";
807			#pwm-cells = <2>;
808		};
809
810		pwm2: pwm@3290000 {
811			compatible = "nvidia,tegra194-pwm",
812				     "nvidia,tegra186-pwm";
813			reg = <0x3290000 0x10000>;
814			clocks = <&bpmp TEGRA194_CLK_PWM2>;
815			clock-names = "pwm";
816			resets = <&bpmp TEGRA194_RESET_PWM2>;
817			reset-names = "pwm";
818			status = "disabled";
819			#pwm-cells = <2>;
820		};
821
822		pwm3: pwm@32a0000 {
823			compatible = "nvidia,tegra194-pwm",
824				     "nvidia,tegra186-pwm";
825			reg = <0x32a0000 0x10000>;
826			clocks = <&bpmp TEGRA194_CLK_PWM3>;
827			clock-names = "pwm";
828			resets = <&bpmp TEGRA194_RESET_PWM3>;
829			reset-names = "pwm";
830			status = "disabled";
831			#pwm-cells = <2>;
832		};
833
834		pwm5: pwm@32c0000 {
835			compatible = "nvidia,tegra194-pwm",
836				     "nvidia,tegra186-pwm";
837			reg = <0x32c0000 0x10000>;
838			clocks = <&bpmp TEGRA194_CLK_PWM5>;
839			clock-names = "pwm";
840			resets = <&bpmp TEGRA194_RESET_PWM5>;
841			reset-names = "pwm";
842			status = "disabled";
843			#pwm-cells = <2>;
844		};
845
846		pwm6: pwm@32d0000 {
847			compatible = "nvidia,tegra194-pwm",
848				     "nvidia,tegra186-pwm";
849			reg = <0x32d0000 0x10000>;
850			clocks = <&bpmp TEGRA194_CLK_PWM6>;
851			clock-names = "pwm";
852			resets = <&bpmp TEGRA194_RESET_PWM6>;
853			reset-names = "pwm";
854			status = "disabled";
855			#pwm-cells = <2>;
856		};
857
858		pwm7: pwm@32e0000 {
859			compatible = "nvidia,tegra194-pwm",
860				     "nvidia,tegra186-pwm";
861			reg = <0x32e0000 0x10000>;
862			clocks = <&bpmp TEGRA194_CLK_PWM7>;
863			clock-names = "pwm";
864			resets = <&bpmp TEGRA194_RESET_PWM7>;
865			reset-names = "pwm";
866			status = "disabled";
867			#pwm-cells = <2>;
868		};
869
870		pwm8: pwm@32f0000 {
871			compatible = "nvidia,tegra194-pwm",
872				     "nvidia,tegra186-pwm";
873			reg = <0x32f0000 0x10000>;
874			clocks = <&bpmp TEGRA194_CLK_PWM8>;
875			clock-names = "pwm";
876			resets = <&bpmp TEGRA194_RESET_PWM8>;
877			reset-names = "pwm";
878			status = "disabled";
879			#pwm-cells = <2>;
880		};
881
882		sdmmc1: mmc@3400000 {
883			compatible = "nvidia,tegra194-sdhci";
884			reg = <0x03400000 0x10000>;
885			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
886			clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
887				 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
888			clock-names = "sdhci", "tmclk";
889			resets = <&bpmp TEGRA194_RESET_SDMMC1>;
890			reset-names = "sdhci";
891			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
892					<&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
893			interconnect-names = "dma-mem", "write";
894			iommus = <&smmu TEGRA194_SID_SDMMC1>;
895			pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
896			pinctrl-0 = <&sdmmc1_3v3>;
897			pinctrl-1 = <&sdmmc1_1v8>;
898			nvidia,pad-autocal-pull-up-offset-3v3-timeout =
899									<0x07>;
900			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
901									<0x07>;
902			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
903			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
904									<0x07>;
905			nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
906			nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
907			nvidia,default-tap = <0x9>;
908			nvidia,default-trim = <0x5>;
909			sd-uhs-sdr25;
910			sd-uhs-sdr50;
911			sd-uhs-ddr50;
912			sd-uhs-sdr104;
913			status = "disabled";
914		};
915
916		sdmmc3: mmc@3440000 {
917			compatible = "nvidia,tegra194-sdhci";
918			reg = <0x03440000 0x10000>;
919			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
920			clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
921				 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
922			clock-names = "sdhci", "tmclk";
923			resets = <&bpmp TEGRA194_RESET_SDMMC3>;
924			reset-names = "sdhci";
925			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
926					<&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
927			interconnect-names = "dma-mem", "write";
928			iommus = <&smmu TEGRA194_SID_SDMMC3>;
929			pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
930			pinctrl-0 = <&sdmmc3_3v3>;
931			pinctrl-1 = <&sdmmc3_1v8>;
932			nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
933			nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
934			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
935			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
936									<0x07>;
937			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
938			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
939									<0x07>;
940			nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
941			nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
942			nvidia,default-tap = <0x9>;
943			nvidia,default-trim = <0x5>;
944			sd-uhs-sdr25;
945			sd-uhs-sdr50;
946			sd-uhs-ddr50;
947			sd-uhs-sdr104;
948			status = "disabled";
949		};
950
951		sdmmc4: mmc@3460000 {
952			compatible = "nvidia,tegra194-sdhci";
953			reg = <0x03460000 0x10000>;
954			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
955			clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
956				 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
957			clock-names = "sdhci", "tmclk";
958			assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
959					  <&bpmp TEGRA194_CLK_PLLC4>;
960			assigned-clock-parents =
961					  <&bpmp TEGRA194_CLK_PLLC4>;
962			resets = <&bpmp TEGRA194_RESET_SDMMC4>;
963			reset-names = "sdhci";
964			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
965					<&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
966			interconnect-names = "dma-mem", "write";
967			iommus = <&smmu TEGRA194_SID_SDMMC4>;
968			nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
969			nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
970			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
971			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
972									<0x0a>;
973			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
974			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
975									<0x0a>;
976			nvidia,default-tap = <0x8>;
977			nvidia,default-trim = <0x14>;
978			nvidia,dqs-trim = <40>;
979			supports-cqe;
980			status = "disabled";
981		};
982
983		hda@3510000 {
984			compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
985			reg = <0x3510000 0x10000>;
986			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
987			clocks = <&bpmp TEGRA194_CLK_HDA>,
988				 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
989				 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
990			clock-names = "hda", "hda2hdmi", "hda2codec_2x";
991			resets = <&bpmp TEGRA194_RESET_HDA>,
992				 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>,
993				 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>;
994			reset-names = "hda", "hda2hdmi", "hda2codec_2x";
995			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
996			interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
997					<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
998			interconnect-names = "dma-mem", "write";
999			iommus = <&smmu TEGRA194_SID_HDA>;
1000			status = "disabled";
1001		};
1002
1003		xusb_padctl: padctl@3520000 {
1004			compatible = "nvidia,tegra194-xusb-padctl";
1005			reg = <0x03520000 0x1000>,
1006			      <0x03540000 0x1000>;
1007			reg-names = "padctl", "ao";
1008			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1009
1010			resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
1011			reset-names = "padctl";
1012
1013			status = "disabled";
1014
1015			pads {
1016				usb2 {
1017					clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
1018					clock-names = "trk";
1019
1020					lanes {
1021						usb2-0 {
1022							nvidia,function = "xusb";
1023							status = "disabled";
1024							#phy-cells = <0>;
1025						};
1026
1027						usb2-1 {
1028							nvidia,function = "xusb";
1029							status = "disabled";
1030							#phy-cells = <0>;
1031						};
1032
1033						usb2-2 {
1034							nvidia,function = "xusb";
1035							status = "disabled";
1036							#phy-cells = <0>;
1037						};
1038
1039						usb2-3 {
1040							nvidia,function = "xusb";
1041							status = "disabled";
1042							#phy-cells = <0>;
1043						};
1044					};
1045				};
1046
1047				usb3 {
1048					lanes {
1049						usb3-0 {
1050							nvidia,function = "xusb";
1051							status = "disabled";
1052							#phy-cells = <0>;
1053						};
1054
1055						usb3-1 {
1056							nvidia,function = "xusb";
1057							status = "disabled";
1058							#phy-cells = <0>;
1059						};
1060
1061						usb3-2 {
1062							nvidia,function = "xusb";
1063							status = "disabled";
1064							#phy-cells = <0>;
1065						};
1066
1067						usb3-3 {
1068							nvidia,function = "xusb";
1069							status = "disabled";
1070							#phy-cells = <0>;
1071						};
1072					};
1073				};
1074			};
1075
1076			ports {
1077				usb2-0 {
1078					status = "disabled";
1079				};
1080
1081				usb2-1 {
1082					status = "disabled";
1083				};
1084
1085				usb2-2 {
1086					status = "disabled";
1087				};
1088
1089				usb2-3 {
1090					status = "disabled";
1091				};
1092
1093				usb3-0 {
1094					status = "disabled";
1095				};
1096
1097				usb3-1 {
1098					status = "disabled";
1099				};
1100
1101				usb3-2 {
1102					status = "disabled";
1103				};
1104
1105				usb3-3 {
1106					status = "disabled";
1107				};
1108			};
1109		};
1110
1111		usb@3550000 {
1112			compatible = "nvidia,tegra194-xudc";
1113			reg = <0x03550000 0x8000>,
1114			      <0x03558000 0x1000>;
1115			reg-names = "base", "fpci";
1116			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1117			clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
1118				 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1119				 <&bpmp TEGRA194_CLK_XUSB_SS>,
1120				 <&bpmp TEGRA194_CLK_XUSB_FS>;
1121			clock-names = "dev", "ss", "ss_src", "fs_src";
1122			interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>,
1123					<&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>;
1124			interconnect-names = "dma-mem", "write";
1125			iommus = <&smmu TEGRA194_SID_XUSB_DEV>;
1126			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1127					<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1128			power-domain-names = "dev", "ss";
1129			nvidia,xusb-padctl = <&xusb_padctl>;
1130			status = "disabled";
1131		};
1132
1133		usb@3610000 {
1134			compatible = "nvidia,tegra194-xusb";
1135			reg = <0x03610000 0x40000>,
1136			      <0x03600000 0x10000>;
1137			reg-names = "hcd", "fpci";
1138
1139			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1140				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1141
1142			clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
1143				 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
1144				 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1145				 <&bpmp TEGRA194_CLK_XUSB_SS>,
1146				 <&bpmp TEGRA194_CLK_CLK_M>,
1147				 <&bpmp TEGRA194_CLK_XUSB_FS>,
1148				 <&bpmp TEGRA194_CLK_UTMIPLL>,
1149				 <&bpmp TEGRA194_CLK_CLK_M>,
1150				 <&bpmp TEGRA194_CLK_PLLE>;
1151			clock-names = "xusb_host", "xusb_falcon_src",
1152				      "xusb_ss", "xusb_ss_src", "xusb_hs_src",
1153				      "xusb_fs_src", "pll_u_480m", "clk_m",
1154				      "pll_e";
1155			interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1156					<&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1157			interconnect-names = "dma-mem", "write";
1158			iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
1159
1160			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1161					<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1162			power-domain-names = "xusb_host", "xusb_ss";
1163
1164			nvidia,xusb-padctl = <&xusb_padctl>;
1165			status = "disabled";
1166		};
1167
1168		fuse@3820000 {
1169			compatible = "nvidia,tegra194-efuse";
1170			reg = <0x03820000 0x10000>;
1171			clocks = <&bpmp TEGRA194_CLK_FUSE>;
1172			clock-names = "fuse";
1173		};
1174
1175		gic: interrupt-controller@3881000 {
1176			compatible = "arm,gic-400";
1177			#interrupt-cells = <3>;
1178			interrupt-controller;
1179			reg = <0x03881000 0x1000>,
1180			      <0x03882000 0x2000>,
1181			      <0x03884000 0x2000>,
1182			      <0x03886000 0x2000>;
1183			interrupts = <GIC_PPI 9
1184				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1185			interrupt-parent = <&gic>;
1186		};
1187
1188		cec@3960000 {
1189			compatible = "nvidia,tegra194-cec";
1190			reg = <0x03960000 0x10000>;
1191			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1192			clocks = <&bpmp TEGRA194_CLK_CEC>;
1193			clock-names = "cec";
1194			status = "disabled";
1195		};
1196
1197		hsp_top0: hsp@3c00000 {
1198			compatible = "nvidia,tegra194-hsp";
1199			reg = <0x03c00000 0xa0000>;
1200			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1201			             <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1202			             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1203			             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1204			             <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1205			             <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1206			             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1207			             <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1208			             <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1209			interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1210			                  "shared3", "shared4", "shared5", "shared6",
1211			                  "shared7";
1212			#mbox-cells = <2>;
1213		};
1214
1215		p2u_hsio_0: phy@3e10000 {
1216			compatible = "nvidia,tegra194-p2u";
1217			reg = <0x03e10000 0x10000>;
1218			reg-names = "ctl";
1219
1220			#phy-cells = <0>;
1221		};
1222
1223		p2u_hsio_1: phy@3e20000 {
1224			compatible = "nvidia,tegra194-p2u";
1225			reg = <0x03e20000 0x10000>;
1226			reg-names = "ctl";
1227
1228			#phy-cells = <0>;
1229		};
1230
1231		p2u_hsio_2: phy@3e30000 {
1232			compatible = "nvidia,tegra194-p2u";
1233			reg = <0x03e30000 0x10000>;
1234			reg-names = "ctl";
1235
1236			#phy-cells = <0>;
1237		};
1238
1239		p2u_hsio_3: phy@3e40000 {
1240			compatible = "nvidia,tegra194-p2u";
1241			reg = <0x03e40000 0x10000>;
1242			reg-names = "ctl";
1243
1244			#phy-cells = <0>;
1245		};
1246
1247		p2u_hsio_4: phy@3e50000 {
1248			compatible = "nvidia,tegra194-p2u";
1249			reg = <0x03e50000 0x10000>;
1250			reg-names = "ctl";
1251
1252			#phy-cells = <0>;
1253		};
1254
1255		p2u_hsio_5: phy@3e60000 {
1256			compatible = "nvidia,tegra194-p2u";
1257			reg = <0x03e60000 0x10000>;
1258			reg-names = "ctl";
1259
1260			#phy-cells = <0>;
1261		};
1262
1263		p2u_hsio_6: phy@3e70000 {
1264			compatible = "nvidia,tegra194-p2u";
1265			reg = <0x03e70000 0x10000>;
1266			reg-names = "ctl";
1267
1268			#phy-cells = <0>;
1269		};
1270
1271		p2u_hsio_7: phy@3e80000 {
1272			compatible = "nvidia,tegra194-p2u";
1273			reg = <0x03e80000 0x10000>;
1274			reg-names = "ctl";
1275
1276			#phy-cells = <0>;
1277		};
1278
1279		p2u_hsio_8: phy@3e90000 {
1280			compatible = "nvidia,tegra194-p2u";
1281			reg = <0x03e90000 0x10000>;
1282			reg-names = "ctl";
1283
1284			#phy-cells = <0>;
1285		};
1286
1287		p2u_hsio_9: phy@3ea0000 {
1288			compatible = "nvidia,tegra194-p2u";
1289			reg = <0x03ea0000 0x10000>;
1290			reg-names = "ctl";
1291
1292			#phy-cells = <0>;
1293		};
1294
1295		p2u_nvhs_0: phy@3eb0000 {
1296			compatible = "nvidia,tegra194-p2u";
1297			reg = <0x03eb0000 0x10000>;
1298			reg-names = "ctl";
1299
1300			#phy-cells = <0>;
1301		};
1302
1303		p2u_nvhs_1: phy@3ec0000 {
1304			compatible = "nvidia,tegra194-p2u";
1305			reg = <0x03ec0000 0x10000>;
1306			reg-names = "ctl";
1307
1308			#phy-cells = <0>;
1309		};
1310
1311		p2u_nvhs_2: phy@3ed0000 {
1312			compatible = "nvidia,tegra194-p2u";
1313			reg = <0x03ed0000 0x10000>;
1314			reg-names = "ctl";
1315
1316			#phy-cells = <0>;
1317		};
1318
1319		p2u_nvhs_3: phy@3ee0000 {
1320			compatible = "nvidia,tegra194-p2u";
1321			reg = <0x03ee0000 0x10000>;
1322			reg-names = "ctl";
1323
1324			#phy-cells = <0>;
1325		};
1326
1327		p2u_nvhs_4: phy@3ef0000 {
1328			compatible = "nvidia,tegra194-p2u";
1329			reg = <0x03ef0000 0x10000>;
1330			reg-names = "ctl";
1331
1332			#phy-cells = <0>;
1333		};
1334
1335		p2u_nvhs_5: phy@3f00000 {
1336			compatible = "nvidia,tegra194-p2u";
1337			reg = <0x03f00000 0x10000>;
1338			reg-names = "ctl";
1339
1340			#phy-cells = <0>;
1341		};
1342
1343		p2u_nvhs_6: phy@3f10000 {
1344			compatible = "nvidia,tegra194-p2u";
1345			reg = <0x03f10000 0x10000>;
1346			reg-names = "ctl";
1347
1348			#phy-cells = <0>;
1349		};
1350
1351		p2u_nvhs_7: phy@3f20000 {
1352			compatible = "nvidia,tegra194-p2u";
1353			reg = <0x03f20000 0x10000>;
1354			reg-names = "ctl";
1355
1356			#phy-cells = <0>;
1357		};
1358
1359		p2u_hsio_10: phy@3f30000 {
1360			compatible = "nvidia,tegra194-p2u";
1361			reg = <0x03f30000 0x10000>;
1362			reg-names = "ctl";
1363
1364			#phy-cells = <0>;
1365		};
1366
1367		p2u_hsio_11: phy@3f40000 {
1368			compatible = "nvidia,tegra194-p2u";
1369			reg = <0x03f40000 0x10000>;
1370			reg-names = "ctl";
1371
1372			#phy-cells = <0>;
1373		};
1374
1375		hsp_aon: hsp@c150000 {
1376			compatible = "nvidia,tegra194-hsp";
1377			reg = <0x0c150000 0x90000>;
1378			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1379			             <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1380			             <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1381			             <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1382			/*
1383			 * Shared interrupt 0 is routed only to AON/SPE, so
1384			 * we only have 4 shared interrupts for the CCPLEX.
1385			 */
1386			interrupt-names = "shared1", "shared2", "shared3", "shared4";
1387			#mbox-cells = <2>;
1388		};
1389
1390		gen2_i2c: i2c@c240000 {
1391			compatible = "nvidia,tegra194-i2c";
1392			reg = <0x0c240000 0x10000>;
1393			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1394			#address-cells = <1>;
1395			#size-cells = <0>;
1396			clocks = <&bpmp TEGRA194_CLK_I2C2>;
1397			clock-names = "div-clk";
1398			resets = <&bpmp TEGRA194_RESET_I2C2>;
1399			reset-names = "i2c";
1400			status = "disabled";
1401		};
1402
1403		gen8_i2c: i2c@c250000 {
1404			compatible = "nvidia,tegra194-i2c";
1405			reg = <0x0c250000 0x10000>;
1406			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1407			#address-cells = <1>;
1408			#size-cells = <0>;
1409			clocks = <&bpmp TEGRA194_CLK_I2C8>;
1410			clock-names = "div-clk";
1411			resets = <&bpmp TEGRA194_RESET_I2C8>;
1412			reset-names = "i2c";
1413			status = "disabled";
1414		};
1415
1416		uartc: serial@c280000 {
1417			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1418			reg = <0x0c280000 0x40>;
1419			reg-shift = <2>;
1420			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1421			clocks = <&bpmp TEGRA194_CLK_UARTC>;
1422			clock-names = "serial";
1423			resets = <&bpmp TEGRA194_RESET_UARTC>;
1424			reset-names = "serial";
1425			status = "disabled";
1426		};
1427
1428		uartg: serial@c290000 {
1429			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1430			reg = <0x0c290000 0x40>;
1431			reg-shift = <2>;
1432			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1433			clocks = <&bpmp TEGRA194_CLK_UARTG>;
1434			clock-names = "serial";
1435			resets = <&bpmp TEGRA194_RESET_UARTG>;
1436			reset-names = "serial";
1437			status = "disabled";
1438		};
1439
1440		rtc: rtc@c2a0000 {
1441			compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1442			reg = <0x0c2a0000 0x10000>;
1443			interrupt-parent = <&pmc>;
1444			interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1445			clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1446			clock-names = "rtc";
1447			status = "disabled";
1448		};
1449
1450		gpio_aon: gpio@c2f0000 {
1451			compatible = "nvidia,tegra194-gpio-aon";
1452			reg-names = "security", "gpio";
1453			reg = <0xc2f0000 0x1000>,
1454			      <0xc2f1000 0x1000>;
1455			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1456				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1457				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1458				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1459			gpio-controller;
1460			#gpio-cells = <2>;
1461			interrupt-controller;
1462			#interrupt-cells = <2>;
1463		};
1464
1465		pwm4: pwm@c340000 {
1466			compatible = "nvidia,tegra194-pwm",
1467				     "nvidia,tegra186-pwm";
1468			reg = <0xc340000 0x10000>;
1469			clocks = <&bpmp TEGRA194_CLK_PWM4>;
1470			clock-names = "pwm";
1471			resets = <&bpmp TEGRA194_RESET_PWM4>;
1472			reset-names = "pwm";
1473			status = "disabled";
1474			#pwm-cells = <2>;
1475		};
1476
1477		pmc: pmc@c360000 {
1478			compatible = "nvidia,tegra194-pmc";
1479			reg = <0x0c360000 0x10000>,
1480			      <0x0c370000 0x10000>,
1481			      <0x0c380000 0x10000>,
1482			      <0x0c390000 0x10000>,
1483			      <0x0c3a0000 0x10000>;
1484			reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1485
1486			#interrupt-cells = <2>;
1487			interrupt-controller;
1488			sdmmc1_3v3: sdmmc1-3v3 {
1489				pins = "sdmmc1-hv";
1490				power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1491			};
1492
1493			sdmmc1_1v8: sdmmc1-1v8 {
1494				pins = "sdmmc1-hv";
1495				power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1496			};
1497			sdmmc3_3v3: sdmmc3-3v3 {
1498				pins = "sdmmc3-hv";
1499				power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1500			};
1501
1502			sdmmc3_1v8: sdmmc3-1v8 {
1503				pins = "sdmmc3-hv";
1504				power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1505			};
1506
1507		};
1508
1509		iommu@10000000 {
1510			compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1511			reg = <0x10000000 0x800000>;
1512			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1513				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1514				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1515				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1516				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1517				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1518				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1519				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1520				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1521				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1522				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1523				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1524				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1525				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1526				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1527				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1528				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1529				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1530				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1531				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1532				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1533				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1534				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1535				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1536				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1537				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1538				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1539				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1540				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1541				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1542				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1543				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1544				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1545				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1546				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1547				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1548				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1549				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1550				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1551				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1552				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1553				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1554				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1555				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1556				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1557				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1558				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1559				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1560				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1561				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1562				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1563				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1564				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1565				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1566				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1567				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1568				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1569				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1570				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1571				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1572				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1573				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1574				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1575				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1576				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1577			stream-match-mask = <0x7f80>;
1578			#global-interrupts = <1>;
1579			#iommu-cells = <1>;
1580
1581			nvidia,memory-controller = <&mc>;
1582			status = "okay";
1583		};
1584
1585		smmu: iommu@12000000 {
1586			compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1587			reg = <0x12000000 0x800000>,
1588			      <0x11000000 0x800000>;
1589			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1590				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1591				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1592				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1593				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1594				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1595				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1596				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1597				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1598				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1599				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1600				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1601				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1602				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1603				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1604				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1605				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1606				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1607				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1608				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1609				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1610				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1611				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1612				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1613				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1614				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1615				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1616				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1617				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1618				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1619				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1620				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1621				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1622				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1623				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1624				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1625				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1626				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1627				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1628				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1629				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1630				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1631				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1632				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1633				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1634				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1635				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1636				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1637				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1638				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1639				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1640				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1641				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1642				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1643				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1644				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1645				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1646				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1647				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1648				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1649				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1650				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1651				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1652				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1653				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1654				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1655			stream-match-mask = <0x7f80>;
1656			#global-interrupts = <2>;
1657			#iommu-cells = <1>;
1658
1659			nvidia,memory-controller = <&mc>;
1660			status = "okay";
1661		};
1662
1663		host1x@13e00000 {
1664			compatible = "nvidia,tegra194-host1x";
1665			reg = <0x13e00000 0x10000>,
1666			      <0x13e10000 0x10000>;
1667			reg-names = "hypervisor", "vm";
1668			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1669				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1670			interrupt-names = "syncpt", "host1x";
1671			clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1672			clock-names = "host1x";
1673			resets = <&bpmp TEGRA194_RESET_HOST1X>;
1674			reset-names = "host1x";
1675
1676			#address-cells = <1>;
1677			#size-cells = <1>;
1678
1679			ranges = <0x15000000 0x15000000 0x01000000>;
1680			interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
1681			interconnect-names = "dma-mem";
1682			iommus = <&smmu TEGRA194_SID_HOST1X>;
1683
1684			nvdec@15140000 {
1685				compatible = "nvidia,tegra194-nvdec";
1686				reg = <0x15140000 0x00040000>;
1687				clocks = <&bpmp TEGRA194_CLK_NVDEC1>;
1688				clock-names = "nvdec";
1689				resets = <&bpmp TEGRA194_RESET_NVDEC1>;
1690				reset-names = "nvdec";
1691
1692				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
1693				interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>,
1694						<&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>,
1695						<&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>;
1696				interconnect-names = "dma-mem", "read-1", "write";
1697				iommus = <&smmu TEGRA194_SID_NVDEC1>;
1698				dma-coherent;
1699
1700				nvidia,host1x-class = <0xf5>;
1701			};
1702
1703			display-hub@15200000 {
1704				compatible = "nvidia,tegra194-display";
1705				reg = <0x15200000 0x00040000>;
1706				resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1707					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1708					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1709					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1710					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1711					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1712					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1713				reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1714					      "wgrp3", "wgrp4", "wgrp5";
1715				clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1716					 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1717				clock-names = "disp", "hub";
1718				status = "disabled";
1719
1720				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1721
1722				#address-cells = <1>;
1723				#size-cells = <1>;
1724
1725				ranges = <0x15200000 0x15200000 0x40000>;
1726
1727				display@15200000 {
1728					compatible = "nvidia,tegra194-dc";
1729					reg = <0x15200000 0x10000>;
1730					interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1731					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1732					clock-names = "dc";
1733					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1734					reset-names = "dc";
1735
1736					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1737					interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1738							<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1739					interconnect-names = "dma-mem", "read-1";
1740
1741					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1742					nvidia,head = <0>;
1743				};
1744
1745				display@15210000 {
1746					compatible = "nvidia,tegra194-dc";
1747					reg = <0x15210000 0x10000>;
1748					interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1749					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1750					clock-names = "dc";
1751					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1752					reset-names = "dc";
1753
1754					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1755					interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1756							<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1757					interconnect-names = "dma-mem", "read-1";
1758
1759					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1760					nvidia,head = <1>;
1761				};
1762
1763				display@15220000 {
1764					compatible = "nvidia,tegra194-dc";
1765					reg = <0x15220000 0x10000>;
1766					interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1767					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
1768					clock-names = "dc";
1769					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
1770					reset-names = "dc";
1771
1772					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1773					interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1774							<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1775					interconnect-names = "dma-mem", "read-1";
1776
1777					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1778					nvidia,head = <2>;
1779				};
1780
1781				display@15230000 {
1782					compatible = "nvidia,tegra194-dc";
1783					reg = <0x15230000 0x10000>;
1784					interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1785					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
1786					clock-names = "dc";
1787					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
1788					reset-names = "dc";
1789
1790					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1791					interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1792							<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1793					interconnect-names = "dma-mem", "read-1";
1794
1795					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1796					nvidia,head = <3>;
1797				};
1798			};
1799
1800			vic@15340000 {
1801				compatible = "nvidia,tegra194-vic";
1802				reg = <0x15340000 0x00040000>;
1803				interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1804				clocks = <&bpmp TEGRA194_CLK_VIC>;
1805				clock-names = "vic";
1806				resets = <&bpmp TEGRA194_RESET_VIC>;
1807				reset-names = "vic";
1808
1809				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
1810				interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
1811						<&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
1812				interconnect-names = "dma-mem", "write";
1813				iommus = <&smmu TEGRA194_SID_VIC>;
1814			};
1815
1816			nvjpg@15380000 {
1817				compatible = "nvidia,tegra194-nvjpg";
1818				reg = <0x15380000 0x40000>;
1819				clocks = <&bpmp TEGRA194_CLK_NVJPG>;
1820				clock-names = "nvjpg";
1821				resets = <&bpmp TEGRA194_RESET_NVJPG>;
1822				reset-names = "nvjpg";
1823
1824				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
1825				interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>,
1826						<&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>;
1827				interconnect-names = "dma-mem", "write";
1828				iommus = <&smmu TEGRA194_SID_NVJPG>;
1829				dma-coherent;
1830			};
1831
1832			nvdec@15480000 {
1833				compatible = "nvidia,tegra194-nvdec";
1834				reg = <0x15480000 0x00040000>;
1835				clocks = <&bpmp TEGRA194_CLK_NVDEC>;
1836				clock-names = "nvdec";
1837				resets = <&bpmp TEGRA194_RESET_NVDEC>;
1838				reset-names = "nvdec";
1839
1840				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
1841				interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>,
1842						<&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>,
1843						<&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>;
1844				interconnect-names = "dma-mem", "read-1", "write";
1845				iommus = <&smmu TEGRA194_SID_NVDEC>;
1846				dma-coherent;
1847
1848				nvidia,host1x-class = <0xf0>;
1849			};
1850
1851			nvenc@154c0000 {
1852				compatible = "nvidia,tegra194-nvenc";
1853				reg = <0x154c0000 0x40000>;
1854				clocks = <&bpmp TEGRA194_CLK_NVENC>;
1855				clock-names = "nvenc";
1856				resets = <&bpmp TEGRA194_RESET_NVENC>;
1857				reset-names = "nvenc";
1858
1859				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
1860				interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>,
1861						<&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>,
1862						<&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>;
1863				interconnect-names = "dma-mem", "read-1", "write";
1864				iommus = <&smmu TEGRA194_SID_NVENC>;
1865				dma-coherent;
1866
1867				nvidia,host1x-class = <0x21>;
1868			};
1869
1870			dpaux0: dpaux@155c0000 {
1871				compatible = "nvidia,tegra194-dpaux";
1872				reg = <0x155c0000 0x10000>;
1873				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1874				clocks = <&bpmp TEGRA194_CLK_DPAUX>,
1875					 <&bpmp TEGRA194_CLK_PLLDP>;
1876				clock-names = "dpaux", "parent";
1877				resets = <&bpmp TEGRA194_RESET_DPAUX>;
1878				reset-names = "dpaux";
1879				status = "disabled";
1880
1881				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1882
1883				state_dpaux0_aux: pinmux-aux {
1884					groups = "dpaux-io";
1885					function = "aux";
1886				};
1887
1888				state_dpaux0_i2c: pinmux-i2c {
1889					groups = "dpaux-io";
1890					function = "i2c";
1891				};
1892
1893				state_dpaux0_off: pinmux-off {
1894					groups = "dpaux-io";
1895					function = "off";
1896				};
1897
1898				i2c-bus {
1899					#address-cells = <1>;
1900					#size-cells = <0>;
1901				};
1902			};
1903
1904			dpaux1: dpaux@155d0000 {
1905				compatible = "nvidia,tegra194-dpaux";
1906				reg = <0x155d0000 0x10000>;
1907				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1908				clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
1909					 <&bpmp TEGRA194_CLK_PLLDP>;
1910				clock-names = "dpaux", "parent";
1911				resets = <&bpmp TEGRA194_RESET_DPAUX1>;
1912				reset-names = "dpaux";
1913				status = "disabled";
1914
1915				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1916
1917				state_dpaux1_aux: pinmux-aux {
1918					groups = "dpaux-io";
1919					function = "aux";
1920				};
1921
1922				state_dpaux1_i2c: pinmux-i2c {
1923					groups = "dpaux-io";
1924					function = "i2c";
1925				};
1926
1927				state_dpaux1_off: pinmux-off {
1928					groups = "dpaux-io";
1929					function = "off";
1930				};
1931
1932				i2c-bus {
1933					#address-cells = <1>;
1934					#size-cells = <0>;
1935				};
1936			};
1937
1938			dpaux2: dpaux@155e0000 {
1939				compatible = "nvidia,tegra194-dpaux";
1940				reg = <0x155e0000 0x10000>;
1941				interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1942				clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
1943					 <&bpmp TEGRA194_CLK_PLLDP>;
1944				clock-names = "dpaux", "parent";
1945				resets = <&bpmp TEGRA194_RESET_DPAUX2>;
1946				reset-names = "dpaux";
1947				status = "disabled";
1948
1949				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1950
1951				state_dpaux2_aux: pinmux-aux {
1952					groups = "dpaux-io";
1953					function = "aux";
1954				};
1955
1956				state_dpaux2_i2c: pinmux-i2c {
1957					groups = "dpaux-io";
1958					function = "i2c";
1959				};
1960
1961				state_dpaux2_off: pinmux-off {
1962					groups = "dpaux-io";
1963					function = "off";
1964				};
1965
1966				i2c-bus {
1967					#address-cells = <1>;
1968					#size-cells = <0>;
1969				};
1970			};
1971
1972			dpaux3: dpaux@155f0000 {
1973				compatible = "nvidia,tegra194-dpaux";
1974				reg = <0x155f0000 0x10000>;
1975				interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1976				clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
1977					 <&bpmp TEGRA194_CLK_PLLDP>;
1978				clock-names = "dpaux", "parent";
1979				resets = <&bpmp TEGRA194_RESET_DPAUX3>;
1980				reset-names = "dpaux";
1981				status = "disabled";
1982
1983				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1984
1985				state_dpaux3_aux: pinmux-aux {
1986					groups = "dpaux-io";
1987					function = "aux";
1988				};
1989
1990				state_dpaux3_i2c: pinmux-i2c {
1991					groups = "dpaux-io";
1992					function = "i2c";
1993				};
1994
1995				state_dpaux3_off: pinmux-off {
1996					groups = "dpaux-io";
1997					function = "off";
1998				};
1999
2000				i2c-bus {
2001					#address-cells = <1>;
2002					#size-cells = <0>;
2003				};
2004			};
2005
2006			nvenc@15a80000 {
2007				compatible = "nvidia,tegra194-nvenc";
2008				reg = <0x15a80000 0x00040000>;
2009				clocks = <&bpmp TEGRA194_CLK_NVENC1>;
2010				clock-names = "nvenc";
2011				resets = <&bpmp TEGRA194_RESET_NVENC1>;
2012				reset-names = "nvenc";
2013
2014				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
2015				interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>,
2016						<&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>,
2017						<&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>;
2018				interconnect-names = "dma-mem", "read-1", "write";
2019				iommus = <&smmu TEGRA194_SID_NVENC1>;
2020				dma-coherent;
2021
2022				nvidia,host1x-class = <0x22>;
2023			};
2024
2025			sor0: sor@15b00000 {
2026				compatible = "nvidia,tegra194-sor";
2027				reg = <0x15b00000 0x40000>;
2028				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
2029				clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
2030					 <&bpmp TEGRA194_CLK_SOR0_OUT>,
2031					 <&bpmp TEGRA194_CLK_PLLD>,
2032					 <&bpmp TEGRA194_CLK_PLLDP>,
2033					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2034					 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
2035				clock-names = "sor", "out", "parent", "dp", "safe",
2036					      "pad";
2037				resets = <&bpmp TEGRA194_RESET_SOR0>;
2038				reset-names = "sor";
2039				pinctrl-0 = <&state_dpaux0_aux>;
2040				pinctrl-1 = <&state_dpaux0_i2c>;
2041				pinctrl-2 = <&state_dpaux0_off>;
2042				pinctrl-names = "aux", "i2c", "off";
2043				status = "disabled";
2044
2045				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2046				nvidia,interface = <0>;
2047			};
2048
2049			sor1: sor@15b40000 {
2050				compatible = "nvidia,tegra194-sor";
2051				reg = <0x15b40000 0x40000>;
2052				interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2053				clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
2054					 <&bpmp TEGRA194_CLK_SOR1_OUT>,
2055					 <&bpmp TEGRA194_CLK_PLLD2>,
2056					 <&bpmp TEGRA194_CLK_PLLDP>,
2057					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2058					 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
2059				clock-names = "sor", "out", "parent", "dp", "safe",
2060					      "pad";
2061				resets = <&bpmp TEGRA194_RESET_SOR1>;
2062				reset-names = "sor";
2063				pinctrl-0 = <&state_dpaux1_aux>;
2064				pinctrl-1 = <&state_dpaux1_i2c>;
2065				pinctrl-2 = <&state_dpaux1_off>;
2066				pinctrl-names = "aux", "i2c", "off";
2067				status = "disabled";
2068
2069				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2070				nvidia,interface = <1>;
2071			};
2072
2073			sor2: sor@15b80000 {
2074				compatible = "nvidia,tegra194-sor";
2075				reg = <0x15b80000 0x40000>;
2076				interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2077				clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
2078					 <&bpmp TEGRA194_CLK_SOR2_OUT>,
2079					 <&bpmp TEGRA194_CLK_PLLD3>,
2080					 <&bpmp TEGRA194_CLK_PLLDP>,
2081					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2082					 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
2083				clock-names = "sor", "out", "parent", "dp", "safe",
2084					      "pad";
2085				resets = <&bpmp TEGRA194_RESET_SOR2>;
2086				reset-names = "sor";
2087				pinctrl-0 = <&state_dpaux2_aux>;
2088				pinctrl-1 = <&state_dpaux2_i2c>;
2089				pinctrl-2 = <&state_dpaux2_off>;
2090				pinctrl-names = "aux", "i2c", "off";
2091				status = "disabled";
2092
2093				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2094				nvidia,interface = <2>;
2095			};
2096
2097			sor3: sor@15bc0000 {
2098				compatible = "nvidia,tegra194-sor";
2099				reg = <0x15bc0000 0x40000>;
2100				interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
2101				clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
2102					 <&bpmp TEGRA194_CLK_SOR3_OUT>,
2103					 <&bpmp TEGRA194_CLK_PLLD4>,
2104					 <&bpmp TEGRA194_CLK_PLLDP>,
2105					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2106					 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
2107				clock-names = "sor", "out", "parent", "dp", "safe",
2108					      "pad";
2109				resets = <&bpmp TEGRA194_RESET_SOR3>;
2110				reset-names = "sor";
2111				pinctrl-0 = <&state_dpaux3_aux>;
2112				pinctrl-1 = <&state_dpaux3_i2c>;
2113				pinctrl-2 = <&state_dpaux3_off>;
2114				pinctrl-names = "aux", "i2c", "off";
2115				status = "disabled";
2116
2117				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2118				nvidia,interface = <3>;
2119			};
2120		};
2121
2122		gpu@17000000 {
2123			compatible = "nvidia,gv11b";
2124			reg = <0x17000000 0x1000000>,
2125			      <0x18000000 0x1000000>;
2126			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
2127				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
2128			interrupt-names = "stall", "nonstall";
2129			clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
2130				 <&bpmp TEGRA194_CLK_GPU_PWR>,
2131				 <&bpmp TEGRA194_CLK_FUSE>;
2132			clock-names = "gpu", "pwr", "fuse";
2133			resets = <&bpmp TEGRA194_RESET_GPU>;
2134			reset-names = "gpu";
2135			dma-coherent;
2136
2137			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2138			interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
2139					<&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
2140					<&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
2141					<&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
2142					<&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
2143					<&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
2144					<&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
2145					<&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
2146					<&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
2147					<&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
2148					<&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
2149					<&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
2150			interconnect-names = "dma-mem", "read-0-hp", "write-0",
2151					     "read-1", "read-1-hp", "write-1",
2152					     "read-2", "read-2-hp", "write-2",
2153					     "read-3", "read-3-hp", "write-3";
2154		};
2155	};
2156
2157	pcie@14100000 {
2158		compatible = "nvidia,tegra194-pcie";
2159		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2160		reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K)      */
2161		      <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2162		      <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2163		      <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2164		reg-names = "appl", "config", "atu_dma", "dbi";
2165
2166		status = "disabled";
2167
2168		#address-cells = <3>;
2169		#size-cells = <2>;
2170		device_type = "pci";
2171		num-lanes = <1>;
2172		num-viewport = <8>;
2173		linux,pci-domain = <1>;
2174
2175		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
2176		clock-names = "core";
2177
2178		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
2179			 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
2180		reset-names = "apb", "core";
2181
2182		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2183			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2184		interrupt-names = "intr", "msi";
2185
2186		#interrupt-cells = <1>;
2187		interrupt-map-mask = <0 0 0 0>;
2188		interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2189
2190		nvidia,bpmp = <&bpmp 1>;
2191
2192		nvidia,aspm-cmrt-us = <60>;
2193		nvidia,aspm-pwr-on-t-us = <20>;
2194		nvidia,aspm-l0s-entrance-latency-us = <3>;
2195
2196		bus-range = <0x0 0xff>;
2197
2198		ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2199			 <0x02000000 0x0  0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
2200			 <0x01000000 0x0  0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2201
2202		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
2203				<&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
2204		interconnect-names = "dma-mem", "write";
2205		iommus = <&smmu TEGRA194_SID_PCIE1>;
2206		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
2207		iommu-map-mask = <0x0>;
2208		dma-coherent;
2209	};
2210
2211	pcie@14120000 {
2212		compatible = "nvidia,tegra194-pcie";
2213		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2214		reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K)      */
2215		      <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2216		      <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2217		      <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2218		reg-names = "appl", "config", "atu_dma", "dbi";
2219
2220		status = "disabled";
2221
2222		#address-cells = <3>;
2223		#size-cells = <2>;
2224		device_type = "pci";
2225		num-lanes = <1>;
2226		num-viewport = <8>;
2227		linux,pci-domain = <2>;
2228
2229		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
2230		clock-names = "core";
2231
2232		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
2233			 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
2234		reset-names = "apb", "core";
2235
2236		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2237			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2238		interrupt-names = "intr", "msi";
2239
2240		#interrupt-cells = <1>;
2241		interrupt-map-mask = <0 0 0 0>;
2242		interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2243
2244		nvidia,bpmp = <&bpmp 2>;
2245
2246		nvidia,aspm-cmrt-us = <60>;
2247		nvidia,aspm-pwr-on-t-us = <20>;
2248		nvidia,aspm-l0s-entrance-latency-us = <3>;
2249
2250		bus-range = <0x0 0xff>;
2251
2252		ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2253			 <0x02000000 0x0  0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
2254			 <0x01000000 0x0  0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2255
2256		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
2257				<&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
2258		interconnect-names = "dma-mem", "write";
2259		iommus = <&smmu TEGRA194_SID_PCIE2>;
2260		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
2261		iommu-map-mask = <0x0>;
2262		dma-coherent;
2263	};
2264
2265	pcie@14140000 {
2266		compatible = "nvidia,tegra194-pcie";
2267		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2268		reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K)      */
2269		      <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2270		      <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2271		      <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2272		reg-names = "appl", "config", "atu_dma", "dbi";
2273
2274		status = "disabled";
2275
2276		#address-cells = <3>;
2277		#size-cells = <2>;
2278		device_type = "pci";
2279		num-lanes = <1>;
2280		num-viewport = <8>;
2281		linux,pci-domain = <3>;
2282
2283		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
2284		clock-names = "core";
2285
2286		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
2287			 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
2288		reset-names = "apb", "core";
2289
2290		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2291			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2292		interrupt-names = "intr", "msi";
2293
2294		#interrupt-cells = <1>;
2295		interrupt-map-mask = <0 0 0 0>;
2296		interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2297
2298		nvidia,bpmp = <&bpmp 3>;
2299
2300		nvidia,aspm-cmrt-us = <60>;
2301		nvidia,aspm-pwr-on-t-us = <20>;
2302		nvidia,aspm-l0s-entrance-latency-us = <3>;
2303
2304		bus-range = <0x0 0xff>;
2305
2306		ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2307			 <0x02000000 0x0  0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
2308			 <0x01000000 0x0  0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2309
2310		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
2311				<&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
2312		interconnect-names = "dma-mem", "write";
2313		iommus = <&smmu TEGRA194_SID_PCIE3>;
2314		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
2315		iommu-map-mask = <0x0>;
2316		dma-coherent;
2317	};
2318
2319	pcie@14160000 {
2320		compatible = "nvidia,tegra194-pcie";
2321		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2322		reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
2323		      <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2324		      <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2325		      <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2326		reg-names = "appl", "config", "atu_dma", "dbi";
2327
2328		status = "disabled";
2329
2330		#address-cells = <3>;
2331		#size-cells = <2>;
2332		device_type = "pci";
2333		num-lanes = <4>;
2334		num-viewport = <8>;
2335		linux,pci-domain = <4>;
2336
2337		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2338		clock-names = "core";
2339
2340		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2341			 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2342		reset-names = "apb", "core";
2343
2344		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2345			     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2346		interrupt-names = "intr", "msi";
2347
2348		#interrupt-cells = <1>;
2349		interrupt-map-mask = <0 0 0 0>;
2350		interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2351
2352		nvidia,bpmp = <&bpmp 4>;
2353
2354		nvidia,aspm-cmrt-us = <60>;
2355		nvidia,aspm-pwr-on-t-us = <20>;
2356		nvidia,aspm-l0s-entrance-latency-us = <3>;
2357
2358		bus-range = <0x0 0xff>;
2359
2360		ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2361			 <0x02000000 0x0  0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2362			 <0x01000000 0x0  0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2363
2364		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
2365				<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
2366		interconnect-names = "dma-mem", "write";
2367		iommus = <&smmu TEGRA194_SID_PCIE4>;
2368		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2369		iommu-map-mask = <0x0>;
2370		dma-coherent;
2371	};
2372
2373	pcie@14180000 {
2374		compatible = "nvidia,tegra194-pcie";
2375		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2376		reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
2377		      <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2378		      <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2379		      <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2380		reg-names = "appl", "config", "atu_dma", "dbi";
2381
2382		status = "disabled";
2383
2384		#address-cells = <3>;
2385		#size-cells = <2>;
2386		device_type = "pci";
2387		num-lanes = <8>;
2388		num-viewport = <8>;
2389		linux,pci-domain = <0>;
2390
2391		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2392		clock-names = "core";
2393
2394		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2395			 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2396		reset-names = "apb", "core";
2397
2398		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2399			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2400		interrupt-names = "intr", "msi";
2401
2402		#interrupt-cells = <1>;
2403		interrupt-map-mask = <0 0 0 0>;
2404		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2405
2406		nvidia,bpmp = <&bpmp 0>;
2407
2408		nvidia,aspm-cmrt-us = <60>;
2409		nvidia,aspm-pwr-on-t-us = <20>;
2410		nvidia,aspm-l0s-entrance-latency-us = <3>;
2411
2412		bus-range = <0x0 0xff>;
2413
2414		ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2415			 <0x02000000 0x0  0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2416			 <0x01000000 0x0  0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2417
2418		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
2419				<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
2420		interconnect-names = "dma-mem", "write";
2421		iommus = <&smmu TEGRA194_SID_PCIE0>;
2422		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2423		iommu-map-mask = <0x0>;
2424		dma-coherent;
2425	};
2426
2427	pcie@141a0000 {
2428		compatible = "nvidia,tegra194-pcie";
2429		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2430		reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2431		      <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2432		      <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2433		      <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2434		reg-names = "appl", "config", "atu_dma", "dbi";
2435
2436		status = "disabled";
2437
2438		#address-cells = <3>;
2439		#size-cells = <2>;
2440		device_type = "pci";
2441		num-lanes = <8>;
2442		num-viewport = <8>;
2443		linux,pci-domain = <5>;
2444
2445		pinctrl-names = "default";
2446		pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
2447
2448		clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
2449			 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
2450		clock-names = "core", "core_m";
2451
2452		resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2453			 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2454		reset-names = "apb", "core";
2455
2456		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2457			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2458		interrupt-names = "intr", "msi";
2459
2460		nvidia,bpmp = <&bpmp 5>;
2461
2462		#interrupt-cells = <1>;
2463		interrupt-map-mask = <0 0 0 0>;
2464		interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2465
2466		nvidia,aspm-cmrt-us = <60>;
2467		nvidia,aspm-pwr-on-t-us = <20>;
2468		nvidia,aspm-l0s-entrance-latency-us = <3>;
2469
2470		bus-range = <0x0 0xff>;
2471
2472		ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2473			 <0x02000000 0x0  0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2474			 <0x01000000 0x0  0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2475
2476		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2477				<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2478		interconnect-names = "dma-mem", "write";
2479		iommus = <&smmu TEGRA194_SID_PCIE5>;
2480		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2481		iommu-map-mask = <0x0>;
2482		dma-coherent;
2483	};
2484
2485	pcie-ep@14160000 {
2486		compatible = "nvidia,tegra194-pcie-ep";
2487		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2488		reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
2489		      <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2490		      <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2491		      <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2492		reg-names = "appl", "atu_dma", "dbi", "addr_space";
2493
2494		status = "disabled";
2495
2496		num-lanes = <4>;
2497		num-ib-windows = <2>;
2498		num-ob-windows = <8>;
2499
2500		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2501		clock-names = "core";
2502
2503		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2504			 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2505		reset-names = "apb", "core";
2506
2507		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
2508		interrupt-names = "intr";
2509
2510		nvidia,bpmp = <&bpmp 4>;
2511
2512		nvidia,aspm-cmrt-us = <60>;
2513		nvidia,aspm-pwr-on-t-us = <20>;
2514		nvidia,aspm-l0s-entrance-latency-us = <3>;
2515
2516		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
2517				<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
2518		interconnect-names = "dma-mem", "write";
2519		iommus = <&smmu TEGRA194_SID_PCIE4>;
2520		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2521		iommu-map-mask = <0x0>;
2522		dma-coherent;
2523	};
2524
2525	pcie-ep@14180000 {
2526		compatible = "nvidia,tegra194-pcie-ep";
2527		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2528		reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
2529		      <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2530		      <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2531		      <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2532		reg-names = "appl", "atu_dma", "dbi", "addr_space";
2533
2534		status = "disabled";
2535
2536		num-lanes = <8>;
2537		num-ib-windows = <2>;
2538		num-ob-windows = <8>;
2539
2540		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2541		clock-names = "core";
2542
2543		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2544			 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2545		reset-names = "apb", "core";
2546
2547		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
2548		interrupt-names = "intr";
2549
2550		nvidia,bpmp = <&bpmp 0>;
2551
2552		nvidia,aspm-cmrt-us = <60>;
2553		nvidia,aspm-pwr-on-t-us = <20>;
2554		nvidia,aspm-l0s-entrance-latency-us = <3>;
2555
2556		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
2557				<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
2558		interconnect-names = "dma-mem", "write";
2559		iommus = <&smmu TEGRA194_SID_PCIE0>;
2560		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2561		iommu-map-mask = <0x0>;
2562		dma-coherent;
2563	};
2564
2565	pcie-ep@141a0000 {
2566		compatible = "nvidia,tegra194-pcie-ep";
2567		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2568		reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2569		      <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2570		      <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2571		      <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2572		reg-names = "appl", "atu_dma", "dbi", "addr_space";
2573
2574		status = "disabled";
2575
2576		num-lanes = <8>;
2577		num-ib-windows = <2>;
2578		num-ob-windows = <8>;
2579
2580		pinctrl-names = "default";
2581		pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2582
2583		clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2584		clock-names = "core";
2585
2586		resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2587			 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2588		reset-names = "apb", "core";
2589
2590		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
2591		interrupt-names = "intr";
2592
2593		nvidia,bpmp = <&bpmp 5>;
2594
2595		nvidia,aspm-cmrt-us = <60>;
2596		nvidia,aspm-pwr-on-t-us = <20>;
2597		nvidia,aspm-l0s-entrance-latency-us = <3>;
2598
2599		interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2600				<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2601		interconnect-names = "dma-mem", "write";
2602		iommus = <&smmu TEGRA194_SID_PCIE5>;
2603		iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2604		iommu-map-mask = <0x0>;
2605		dma-coherent;
2606	};
2607
2608	sram@40000000 {
2609		compatible = "nvidia,tegra194-sysram", "mmio-sram";
2610		reg = <0x0 0x40000000 0x0 0x50000>;
2611		#address-cells = <1>;
2612		#size-cells = <1>;
2613		ranges = <0x0 0x0 0x40000000 0x50000>;
2614
2615		cpu_bpmp_tx: sram@4e000 {
2616			reg = <0x4e000 0x1000>;
2617			label = "cpu-bpmp-tx";
2618			pool;
2619		};
2620
2621		cpu_bpmp_rx: sram@4f000 {
2622			reg = <0x4f000 0x1000>;
2623			label = "cpu-bpmp-rx";
2624			pool;
2625		};
2626	};
2627
2628	bpmp: bpmp {
2629		compatible = "nvidia,tegra186-bpmp";
2630		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2631				    TEGRA_HSP_DB_MASTER_BPMP>;
2632		shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
2633		#clock-cells = <1>;
2634		#reset-cells = <1>;
2635		#power-domain-cells = <1>;
2636		interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
2637				<&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
2638				<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
2639				<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
2640		interconnect-names = "read", "write", "dma-mem", "dma-write";
2641		iommus = <&smmu TEGRA194_SID_BPMP>;
2642
2643		bpmp_i2c: i2c {
2644			compatible = "nvidia,tegra186-bpmp-i2c";
2645			nvidia,bpmp-bus-id = <5>;
2646			#address-cells = <1>;
2647			#size-cells = <0>;
2648		};
2649
2650		bpmp_thermal: thermal {
2651			compatible = "nvidia,tegra186-bpmp-thermal";
2652			#thermal-sensor-cells = <1>;
2653		};
2654	};
2655
2656	cpus {
2657		compatible = "nvidia,tegra194-ccplex";
2658		nvidia,bpmp = <&bpmp>;
2659		#address-cells = <1>;
2660		#size-cells = <0>;
2661
2662		cpu0_0: cpu@0 {
2663			compatible = "nvidia,tegra194-carmel";
2664			device_type = "cpu";
2665			reg = <0x000>;
2666			enable-method = "psci";
2667			i-cache-size = <131072>;
2668			i-cache-line-size = <64>;
2669			i-cache-sets = <512>;
2670			d-cache-size = <65536>;
2671			d-cache-line-size = <64>;
2672			d-cache-sets = <256>;
2673			next-level-cache = <&l2c_0>;
2674		};
2675
2676		cpu0_1: cpu@1 {
2677			compatible = "nvidia,tegra194-carmel";
2678			device_type = "cpu";
2679			reg = <0x001>;
2680			enable-method = "psci";
2681			i-cache-size = <131072>;
2682			i-cache-line-size = <64>;
2683			i-cache-sets = <512>;
2684			d-cache-size = <65536>;
2685			d-cache-line-size = <64>;
2686			d-cache-sets = <256>;
2687			next-level-cache = <&l2c_0>;
2688		};
2689
2690		cpu1_0: cpu@100 {
2691			compatible = "nvidia,tegra194-carmel";
2692			device_type = "cpu";
2693			reg = <0x100>;
2694			enable-method = "psci";
2695			i-cache-size = <131072>;
2696			i-cache-line-size = <64>;
2697			i-cache-sets = <512>;
2698			d-cache-size = <65536>;
2699			d-cache-line-size = <64>;
2700			d-cache-sets = <256>;
2701			next-level-cache = <&l2c_1>;
2702		};
2703
2704		cpu1_1: cpu@101 {
2705			compatible = "nvidia,tegra194-carmel";
2706			device_type = "cpu";
2707			reg = <0x101>;
2708			enable-method = "psci";
2709			i-cache-size = <131072>;
2710			i-cache-line-size = <64>;
2711			i-cache-sets = <512>;
2712			d-cache-size = <65536>;
2713			d-cache-line-size = <64>;
2714			d-cache-sets = <256>;
2715			next-level-cache = <&l2c_1>;
2716		};
2717
2718		cpu2_0: cpu@200 {
2719			compatible = "nvidia,tegra194-carmel";
2720			device_type = "cpu";
2721			reg = <0x200>;
2722			enable-method = "psci";
2723			i-cache-size = <131072>;
2724			i-cache-line-size = <64>;
2725			i-cache-sets = <512>;
2726			d-cache-size = <65536>;
2727			d-cache-line-size = <64>;
2728			d-cache-sets = <256>;
2729			next-level-cache = <&l2c_2>;
2730		};
2731
2732		cpu2_1: cpu@201 {
2733			compatible = "nvidia,tegra194-carmel";
2734			device_type = "cpu";
2735			reg = <0x201>;
2736			enable-method = "psci";
2737			i-cache-size = <131072>;
2738			i-cache-line-size = <64>;
2739			i-cache-sets = <512>;
2740			d-cache-size = <65536>;
2741			d-cache-line-size = <64>;
2742			d-cache-sets = <256>;
2743			next-level-cache = <&l2c_2>;
2744		};
2745
2746		cpu3_0: cpu@300 {
2747			compatible = "nvidia,tegra194-carmel";
2748			device_type = "cpu";
2749			reg = <0x300>;
2750			enable-method = "psci";
2751			i-cache-size = <131072>;
2752			i-cache-line-size = <64>;
2753			i-cache-sets = <512>;
2754			d-cache-size = <65536>;
2755			d-cache-line-size = <64>;
2756			d-cache-sets = <256>;
2757			next-level-cache = <&l2c_3>;
2758		};
2759
2760		cpu3_1: cpu@301 {
2761			compatible = "nvidia,tegra194-carmel";
2762			device_type = "cpu";
2763			reg = <0x301>;
2764			enable-method = "psci";
2765			i-cache-size = <131072>;
2766			i-cache-line-size = <64>;
2767			i-cache-sets = <512>;
2768			d-cache-size = <65536>;
2769			d-cache-line-size = <64>;
2770			d-cache-sets = <256>;
2771			next-level-cache = <&l2c_3>;
2772		};
2773
2774		cpu-map {
2775			cluster0 {
2776				core0 {
2777					cpu = <&cpu0_0>;
2778				};
2779
2780				core1 {
2781					cpu = <&cpu0_1>;
2782				};
2783			};
2784
2785			cluster1 {
2786				core0 {
2787					cpu = <&cpu1_0>;
2788				};
2789
2790				core1 {
2791					cpu = <&cpu1_1>;
2792				};
2793			};
2794
2795			cluster2 {
2796				core0 {
2797					cpu = <&cpu2_0>;
2798				};
2799
2800				core1 {
2801					cpu = <&cpu2_1>;
2802				};
2803			};
2804
2805			cluster3 {
2806				core0 {
2807					cpu = <&cpu3_0>;
2808				};
2809
2810				core1 {
2811					cpu = <&cpu3_1>;
2812				};
2813			};
2814		};
2815
2816		l2c_0: l2-cache0 {
2817			cache-size = <2097152>;
2818			cache-line-size = <64>;
2819			cache-sets = <2048>;
2820			next-level-cache = <&l3c>;
2821		};
2822
2823		l2c_1: l2-cache1 {
2824			cache-size = <2097152>;
2825			cache-line-size = <64>;
2826			cache-sets = <2048>;
2827			next-level-cache = <&l3c>;
2828		};
2829
2830		l2c_2: l2-cache2 {
2831			cache-size = <2097152>;
2832			cache-line-size = <64>;
2833			cache-sets = <2048>;
2834			next-level-cache = <&l3c>;
2835		};
2836
2837		l2c_3: l2-cache3 {
2838			cache-size = <2097152>;
2839			cache-line-size = <64>;
2840			cache-sets = <2048>;
2841			next-level-cache = <&l3c>;
2842		};
2843
2844		l3c: l3-cache {
2845			cache-size = <4194304>;
2846			cache-line-size = <64>;
2847			cache-sets = <4096>;
2848		};
2849	};
2850
2851	pmu {
2852		compatible = "arm,armv8-pmuv3";
2853		interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
2854			     <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
2855			     <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
2856			     <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
2857			     <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
2858			     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
2859			     <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
2860			     <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
2861		interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
2862				      &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
2863	};
2864
2865	psci {
2866		compatible = "arm,psci-1.0";
2867		status = "okay";
2868		method = "smc";
2869	};
2870
2871	sound {
2872		status = "disabled";
2873
2874		clocks = <&bpmp TEGRA194_CLK_PLLA>,
2875			 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
2876		clock-names = "pll_a", "plla_out0";
2877		assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
2878				  <&bpmp TEGRA194_CLK_PLLA_OUT0>,
2879				  <&bpmp TEGRA194_CLK_AUD_MCLK>;
2880		assigned-clock-parents = <0>,
2881					 <&bpmp TEGRA194_CLK_PLLA>,
2882					 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
2883		/*
2884		 * PLLA supports dynamic ramp. Below initial rate is chosen
2885		 * for this to work and oscillate between base rates required
2886		 * for 8x and 11.025x sample rate streams.
2887		 */
2888		assigned-clock-rates = <258000000>;
2889
2890		interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>,
2891				<&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>;
2892		interconnect-names = "dma-mem", "write";
2893		iommus = <&smmu TEGRA194_SID_APE>;
2894	};
2895
2896	tcu: tcu {
2897		compatible = "nvidia,tegra194-tcu";
2898		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
2899		         <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
2900		mbox-names = "rx", "tx";
2901	};
2902
2903	thermal-zones {
2904		cpu-thermal {
2905			thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>;
2906			status = "disabled";
2907		};
2908
2909		gpu-thermal {
2910			thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>;
2911			status = "disabled";
2912		};
2913
2914		aux-thermal {
2915			thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>;
2916			status = "disabled";
2917		};
2918
2919		pllx-thermal {
2920			thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
2921			status = "disabled";
2922		};
2923
2924		ao-thermal {
2925			thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>;
2926			status = "disabled";
2927		};
2928
2929		tj-thermal {
2930			thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
2931			status = "disabled";
2932		};
2933	};
2934
2935	timer {
2936		compatible = "arm,armv8-timer";
2937		interrupts = <GIC_PPI 13
2938				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2939			     <GIC_PPI 14
2940				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2941			     <GIC_PPI 11
2942				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2943			     <GIC_PPI 10
2944				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2945		interrupt-parent = <&gic>;
2946		always-on;
2947	};
2948};
2949