1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 }; 90 91 ethernet@2490000 { 92 compatible = "nvidia,tegra194-eqos", 93 "nvidia,tegra186-eqos", 94 "snps,dwc-qos-ethernet-4.10"; 95 reg = <0x02490000 0x10000>; 96 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 98 <&bpmp TEGRA194_CLK_EQOS_AXI>, 99 <&bpmp TEGRA194_CLK_EQOS_RX>, 100 <&bpmp TEGRA194_CLK_EQOS_TX>, 101 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 102 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 103 resets = <&bpmp TEGRA194_RESET_EQOS>; 104 reset-names = "eqos"; 105 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 106 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 107 interconnect-names = "dma-mem", "write"; 108 iommus = <&smmu TEGRA194_SID_EQOS>; 109 status = "disabled"; 110 111 snps,write-requests = <1>; 112 snps,read-requests = <3>; 113 snps,burst-map = <0x7>; 114 snps,txpbl = <16>; 115 snps,rxpbl = <8>; 116 }; 117 118 gpcdma: dma-controller@2600000 { 119 compatible = "nvidia,tegra194-gpcdma", 120 "nvidia,tegra186-gpcdma"; 121 reg = <0x2600000 0x210000>; 122 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 123 reset-names = "gpcdma"; 124 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 155 #dma-cells = <1>; 156 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 157 dma-coherent; 158 status = "okay"; 159 }; 160 161 aconnect@2900000 { 162 compatible = "nvidia,tegra194-aconnect", 163 "nvidia,tegra210-aconnect"; 164 clocks = <&bpmp TEGRA194_CLK_APE>, 165 <&bpmp TEGRA194_CLK_APB2APE>; 166 clock-names = "ape", "apb2ape"; 167 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 168 #address-cells = <1>; 169 #size-cells = <1>; 170 ranges = <0x02900000 0x02900000 0x200000>; 171 status = "disabled"; 172 173 adma: dma-controller@2930000 { 174 compatible = "nvidia,tegra194-adma", 175 "nvidia,tegra186-adma"; 176 reg = <0x02930000 0x20000>; 177 interrupt-parent = <&agic>; 178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #dma-cells = <1>; 211 clocks = <&bpmp TEGRA194_CLK_AHUB>; 212 clock-names = "d_audio"; 213 status = "disabled"; 214 }; 215 216 agic: interrupt-controller@2a40000 { 217 compatible = "nvidia,tegra194-agic", 218 "nvidia,tegra210-agic"; 219 #interrupt-cells = <3>; 220 interrupt-controller; 221 reg = <0x02a41000 0x1000>, 222 <0x02a42000 0x2000>; 223 interrupts = <GIC_SPI 145 224 (GIC_CPU_MASK_SIMPLE(4) | 225 IRQ_TYPE_LEVEL_HIGH)>; 226 clocks = <&bpmp TEGRA194_CLK_APE>; 227 clock-names = "clk"; 228 status = "disabled"; 229 }; 230 231 tegra_ahub: ahub@2900800 { 232 compatible = "nvidia,tegra194-ahub", 233 "nvidia,tegra186-ahub"; 234 reg = <0x02900800 0x800>; 235 clocks = <&bpmp TEGRA194_CLK_AHUB>; 236 clock-names = "ahub"; 237 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 238 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 239 #address-cells = <1>; 240 #size-cells = <1>; 241 ranges = <0x02900800 0x02900800 0x11800>; 242 status = "disabled"; 243 244 tegra_admaif: admaif@290f000 { 245 compatible = "nvidia,tegra194-admaif", 246 "nvidia,tegra186-admaif"; 247 reg = <0x0290f000 0x1000>; 248 dmas = <&adma 1>, <&adma 1>, 249 <&adma 2>, <&adma 2>, 250 <&adma 3>, <&adma 3>, 251 <&adma 4>, <&adma 4>, 252 <&adma 5>, <&adma 5>, 253 <&adma 6>, <&adma 6>, 254 <&adma 7>, <&adma 7>, 255 <&adma 8>, <&adma 8>, 256 <&adma 9>, <&adma 9>, 257 <&adma 10>, <&adma 10>, 258 <&adma 11>, <&adma 11>, 259 <&adma 12>, <&adma 12>, 260 <&adma 13>, <&adma 13>, 261 <&adma 14>, <&adma 14>, 262 <&adma 15>, <&adma 15>, 263 <&adma 16>, <&adma 16>, 264 <&adma 17>, <&adma 17>, 265 <&adma 18>, <&adma 18>, 266 <&adma 19>, <&adma 19>, 267 <&adma 20>, <&adma 20>; 268 dma-names = "rx1", "tx1", 269 "rx2", "tx2", 270 "rx3", "tx3", 271 "rx4", "tx4", 272 "rx5", "tx5", 273 "rx6", "tx6", 274 "rx7", "tx7", 275 "rx8", "tx8", 276 "rx9", "tx9", 277 "rx10", "tx10", 278 "rx11", "tx11", 279 "rx12", "tx12", 280 "rx13", "tx13", 281 "rx14", "tx14", 282 "rx15", "tx15", 283 "rx16", "tx16", 284 "rx17", "tx17", 285 "rx18", "tx18", 286 "rx19", "tx19", 287 "rx20", "tx20"; 288 status = "disabled"; 289 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 290 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 291 interconnect-names = "dma-mem", "write"; 292 iommus = <&smmu TEGRA194_SID_APE>; 293 }; 294 295 tegra_i2s1: i2s@2901000 { 296 compatible = "nvidia,tegra194-i2s", 297 "nvidia,tegra210-i2s"; 298 reg = <0x2901000 0x100>; 299 clocks = <&bpmp TEGRA194_CLK_I2S1>, 300 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 301 clock-names = "i2s", "sync_input"; 302 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 303 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 304 assigned-clock-rates = <1536000>; 305 sound-name-prefix = "I2S1"; 306 status = "disabled"; 307 }; 308 309 tegra_i2s2: i2s@2901100 { 310 compatible = "nvidia,tegra194-i2s", 311 "nvidia,tegra210-i2s"; 312 reg = <0x2901100 0x100>; 313 clocks = <&bpmp TEGRA194_CLK_I2S2>, 314 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 315 clock-names = "i2s", "sync_input"; 316 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 317 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 318 assigned-clock-rates = <1536000>; 319 sound-name-prefix = "I2S2"; 320 status = "disabled"; 321 }; 322 323 tegra_i2s3: i2s@2901200 { 324 compatible = "nvidia,tegra194-i2s", 325 "nvidia,tegra210-i2s"; 326 reg = <0x2901200 0x100>; 327 clocks = <&bpmp TEGRA194_CLK_I2S3>, 328 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 329 clock-names = "i2s", "sync_input"; 330 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 331 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 332 assigned-clock-rates = <1536000>; 333 sound-name-prefix = "I2S3"; 334 status = "disabled"; 335 }; 336 337 tegra_i2s4: i2s@2901300 { 338 compatible = "nvidia,tegra194-i2s", 339 "nvidia,tegra210-i2s"; 340 reg = <0x2901300 0x100>; 341 clocks = <&bpmp TEGRA194_CLK_I2S4>, 342 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 343 clock-names = "i2s", "sync_input"; 344 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 345 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 346 assigned-clock-rates = <1536000>; 347 sound-name-prefix = "I2S4"; 348 status = "disabled"; 349 }; 350 351 tegra_i2s5: i2s@2901400 { 352 compatible = "nvidia,tegra194-i2s", 353 "nvidia,tegra210-i2s"; 354 reg = <0x2901400 0x100>; 355 clocks = <&bpmp TEGRA194_CLK_I2S5>, 356 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 357 clock-names = "i2s", "sync_input"; 358 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 359 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 360 assigned-clock-rates = <1536000>; 361 sound-name-prefix = "I2S5"; 362 status = "disabled"; 363 }; 364 365 tegra_i2s6: i2s@2901500 { 366 compatible = "nvidia,tegra194-i2s", 367 "nvidia,tegra210-i2s"; 368 reg = <0x2901500 0x100>; 369 clocks = <&bpmp TEGRA194_CLK_I2S6>, 370 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 371 clock-names = "i2s", "sync_input"; 372 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 373 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 374 assigned-clock-rates = <1536000>; 375 sound-name-prefix = "I2S6"; 376 status = "disabled"; 377 }; 378 379 tegra_dmic1: dmic@2904000 { 380 compatible = "nvidia,tegra194-dmic", 381 "nvidia,tegra210-dmic"; 382 reg = <0x2904000 0x100>; 383 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 384 clock-names = "dmic"; 385 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 386 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 387 assigned-clock-rates = <3072000>; 388 sound-name-prefix = "DMIC1"; 389 status = "disabled"; 390 }; 391 392 tegra_dmic2: dmic@2904100 { 393 compatible = "nvidia,tegra194-dmic", 394 "nvidia,tegra210-dmic"; 395 reg = <0x2904100 0x100>; 396 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 397 clock-names = "dmic"; 398 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 399 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 400 assigned-clock-rates = <3072000>; 401 sound-name-prefix = "DMIC2"; 402 status = "disabled"; 403 }; 404 405 tegra_dmic3: dmic@2904200 { 406 compatible = "nvidia,tegra194-dmic", 407 "nvidia,tegra210-dmic"; 408 reg = <0x2904200 0x100>; 409 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 410 clock-names = "dmic"; 411 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 412 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 413 assigned-clock-rates = <3072000>; 414 sound-name-prefix = "DMIC3"; 415 status = "disabled"; 416 }; 417 418 tegra_dmic4: dmic@2904300 { 419 compatible = "nvidia,tegra194-dmic", 420 "nvidia,tegra210-dmic"; 421 reg = <0x2904300 0x100>; 422 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 423 clock-names = "dmic"; 424 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 425 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 426 assigned-clock-rates = <3072000>; 427 sound-name-prefix = "DMIC4"; 428 status = "disabled"; 429 }; 430 431 tegra_dspk1: dspk@2905000 { 432 compatible = "nvidia,tegra194-dspk", 433 "nvidia,tegra186-dspk"; 434 reg = <0x2905000 0x100>; 435 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 436 clock-names = "dspk"; 437 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 438 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 439 assigned-clock-rates = <12288000>; 440 sound-name-prefix = "DSPK1"; 441 status = "disabled"; 442 }; 443 444 tegra_dspk2: dspk@2905100 { 445 compatible = "nvidia,tegra194-dspk", 446 "nvidia,tegra186-dspk"; 447 reg = <0x2905100 0x100>; 448 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 449 clock-names = "dspk"; 450 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 451 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 452 assigned-clock-rates = <12288000>; 453 sound-name-prefix = "DSPK2"; 454 status = "disabled"; 455 }; 456 457 tegra_sfc1: sfc@2902000 { 458 compatible = "nvidia,tegra194-sfc", 459 "nvidia,tegra210-sfc"; 460 reg = <0x2902000 0x200>; 461 sound-name-prefix = "SFC1"; 462 status = "disabled"; 463 }; 464 465 tegra_sfc2: sfc@2902200 { 466 compatible = "nvidia,tegra194-sfc", 467 "nvidia,tegra210-sfc"; 468 reg = <0x2902200 0x200>; 469 sound-name-prefix = "SFC2"; 470 status = "disabled"; 471 }; 472 473 tegra_sfc3: sfc@2902400 { 474 compatible = "nvidia,tegra194-sfc", 475 "nvidia,tegra210-sfc"; 476 reg = <0x2902400 0x200>; 477 sound-name-prefix = "SFC3"; 478 status = "disabled"; 479 }; 480 481 tegra_sfc4: sfc@2902600 { 482 compatible = "nvidia,tegra194-sfc", 483 "nvidia,tegra210-sfc"; 484 reg = <0x2902600 0x200>; 485 sound-name-prefix = "SFC4"; 486 status = "disabled"; 487 }; 488 489 tegra_mvc1: mvc@290a000 { 490 compatible = "nvidia,tegra194-mvc", 491 "nvidia,tegra210-mvc"; 492 reg = <0x290a000 0x200>; 493 sound-name-prefix = "MVC1"; 494 status = "disabled"; 495 }; 496 497 tegra_mvc2: mvc@290a200 { 498 compatible = "nvidia,tegra194-mvc", 499 "nvidia,tegra210-mvc"; 500 reg = <0x290a200 0x200>; 501 sound-name-prefix = "MVC2"; 502 status = "disabled"; 503 }; 504 505 tegra_amx1: amx@2903000 { 506 compatible = "nvidia,tegra194-amx"; 507 reg = <0x2903000 0x100>; 508 sound-name-prefix = "AMX1"; 509 status = "disabled"; 510 }; 511 512 tegra_amx2: amx@2903100 { 513 compatible = "nvidia,tegra194-amx"; 514 reg = <0x2903100 0x100>; 515 sound-name-prefix = "AMX2"; 516 status = "disabled"; 517 }; 518 519 tegra_amx3: amx@2903200 { 520 compatible = "nvidia,tegra194-amx"; 521 reg = <0x2903200 0x100>; 522 sound-name-prefix = "AMX3"; 523 status = "disabled"; 524 }; 525 526 tegra_amx4: amx@2903300 { 527 compatible = "nvidia,tegra194-amx"; 528 reg = <0x2903300 0x100>; 529 sound-name-prefix = "AMX4"; 530 status = "disabled"; 531 }; 532 533 tegra_adx1: adx@2903800 { 534 compatible = "nvidia,tegra194-adx", 535 "nvidia,tegra210-adx"; 536 reg = <0x2903800 0x100>; 537 sound-name-prefix = "ADX1"; 538 status = "disabled"; 539 }; 540 541 tegra_adx2: adx@2903900 { 542 compatible = "nvidia,tegra194-adx", 543 "nvidia,tegra210-adx"; 544 reg = <0x2903900 0x100>; 545 sound-name-prefix = "ADX2"; 546 status = "disabled"; 547 }; 548 549 tegra_adx3: adx@2903a00 { 550 compatible = "nvidia,tegra194-adx", 551 "nvidia,tegra210-adx"; 552 reg = <0x2903a00 0x100>; 553 sound-name-prefix = "ADX3"; 554 status = "disabled"; 555 }; 556 557 tegra_adx4: adx@2903b00 { 558 compatible = "nvidia,tegra194-adx", 559 "nvidia,tegra210-adx"; 560 reg = <0x2903b00 0x100>; 561 sound-name-prefix = "ADX4"; 562 status = "disabled"; 563 }; 564 565 tegra_amixer: amixer@290bb00 { 566 compatible = "nvidia,tegra194-amixer", 567 "nvidia,tegra210-amixer"; 568 reg = <0x290bb00 0x800>; 569 sound-name-prefix = "MIXER1"; 570 status = "disabled"; 571 }; 572 }; 573 }; 574 575 pinmux: pinmux@2430000 { 576 compatible = "nvidia,tegra194-pinmux"; 577 reg = <0x2430000 0x17000>, 578 <0xc300000 0x4000>; 579 580 status = "okay"; 581 582 pex_rst_c5_out_state: pex_rst_c5_out { 583 pex_rst { 584 nvidia,pins = "pex_l5_rst_n_pgg1"; 585 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 586 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 587 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 588 nvidia,tristate = <TEGRA_PIN_DISABLE>; 589 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 590 }; 591 }; 592 593 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 594 clkreq { 595 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 596 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 597 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 598 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 599 nvidia,tristate = <TEGRA_PIN_DISABLE>; 600 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 601 }; 602 }; 603 }; 604 605 mc: memory-controller@2c00000 { 606 compatible = "nvidia,tegra194-mc"; 607 reg = <0x02c00000 0x100000>, 608 <0x02b80000 0x040000>, 609 <0x01700000 0x100000>; 610 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 611 #interconnect-cells = <1>; 612 status = "disabled"; 613 614 #address-cells = <2>; 615 #size-cells = <2>; 616 617 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 618 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 619 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 620 621 /* 622 * Bit 39 of addresses passing through the memory 623 * controller selects the XBAR format used when memory 624 * is accessed. This is used to transparently access 625 * memory in the XBAR format used by the discrete GPU 626 * (bit 39 set) or Tegra (bit 39 clear). 627 * 628 * As a consequence, the operating system must ensure 629 * that bit 39 is never used implicitly, for example 630 * via an I/O virtual address mapping of an IOMMU. If 631 * devices require access to the XBAR switch, their 632 * drivers must set this bit explicitly. 633 * 634 * Limit the DMA range for memory clients to [38:0]. 635 */ 636 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 637 638 emc: external-memory-controller@2c60000 { 639 compatible = "nvidia,tegra194-emc"; 640 reg = <0x0 0x02c60000 0x0 0x90000>, 641 <0x0 0x01780000 0x0 0x80000>; 642 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&bpmp TEGRA194_CLK_EMC>; 644 clock-names = "emc"; 645 646 #interconnect-cells = <0>; 647 648 nvidia,bpmp = <&bpmp>; 649 }; 650 }; 651 652 uarta: serial@3100000 { 653 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 654 reg = <0x03100000 0x40>; 655 reg-shift = <2>; 656 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&bpmp TEGRA194_CLK_UARTA>; 658 clock-names = "serial"; 659 resets = <&bpmp TEGRA194_RESET_UARTA>; 660 reset-names = "serial"; 661 status = "disabled"; 662 }; 663 664 uartb: serial@3110000 { 665 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 666 reg = <0x03110000 0x40>; 667 reg-shift = <2>; 668 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&bpmp TEGRA194_CLK_UARTB>; 670 clock-names = "serial"; 671 resets = <&bpmp TEGRA194_RESET_UARTB>; 672 reset-names = "serial"; 673 status = "disabled"; 674 }; 675 676 uartd: serial@3130000 { 677 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 678 reg = <0x03130000 0x40>; 679 reg-shift = <2>; 680 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&bpmp TEGRA194_CLK_UARTD>; 682 clock-names = "serial"; 683 resets = <&bpmp TEGRA194_RESET_UARTD>; 684 reset-names = "serial"; 685 status = "disabled"; 686 }; 687 688 uarte: serial@3140000 { 689 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 690 reg = <0x03140000 0x40>; 691 reg-shift = <2>; 692 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&bpmp TEGRA194_CLK_UARTE>; 694 clock-names = "serial"; 695 resets = <&bpmp TEGRA194_RESET_UARTE>; 696 reset-names = "serial"; 697 status = "disabled"; 698 }; 699 700 uartf: serial@3150000 { 701 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 702 reg = <0x03150000 0x40>; 703 reg-shift = <2>; 704 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&bpmp TEGRA194_CLK_UARTF>; 706 clock-names = "serial"; 707 resets = <&bpmp TEGRA194_RESET_UARTF>; 708 reset-names = "serial"; 709 status = "disabled"; 710 }; 711 712 gen1_i2c: i2c@3160000 { 713 compatible = "nvidia,tegra194-i2c"; 714 reg = <0x03160000 0x10000>; 715 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 clocks = <&bpmp TEGRA194_CLK_I2C1>; 719 clock-names = "div-clk"; 720 resets = <&bpmp TEGRA194_RESET_I2C1>; 721 reset-names = "i2c"; 722 status = "disabled"; 723 }; 724 725 uarth: serial@3170000 { 726 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 727 reg = <0x03170000 0x40>; 728 reg-shift = <2>; 729 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&bpmp TEGRA194_CLK_UARTH>; 731 clock-names = "serial"; 732 resets = <&bpmp TEGRA194_RESET_UARTH>; 733 reset-names = "serial"; 734 status = "disabled"; 735 }; 736 737 cam_i2c: i2c@3180000 { 738 compatible = "nvidia,tegra194-i2c"; 739 reg = <0x03180000 0x10000>; 740 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 clocks = <&bpmp TEGRA194_CLK_I2C3>; 744 clock-names = "div-clk"; 745 resets = <&bpmp TEGRA194_RESET_I2C3>; 746 reset-names = "i2c"; 747 status = "disabled"; 748 }; 749 750 /* shares pads with dpaux1 */ 751 dp_aux_ch1_i2c: i2c@3190000 { 752 compatible = "nvidia,tegra194-i2c"; 753 reg = <0x03190000 0x10000>; 754 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 clocks = <&bpmp TEGRA194_CLK_I2C4>; 758 clock-names = "div-clk"; 759 resets = <&bpmp TEGRA194_RESET_I2C4>; 760 reset-names = "i2c"; 761 pinctrl-0 = <&state_dpaux1_i2c>; 762 pinctrl-1 = <&state_dpaux1_off>; 763 pinctrl-names = "default", "idle"; 764 status = "disabled"; 765 }; 766 767 /* shares pads with dpaux0 */ 768 dp_aux_ch0_i2c: i2c@31b0000 { 769 compatible = "nvidia,tegra194-i2c"; 770 reg = <0x031b0000 0x10000>; 771 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 clocks = <&bpmp TEGRA194_CLK_I2C6>; 775 clock-names = "div-clk"; 776 resets = <&bpmp TEGRA194_RESET_I2C6>; 777 reset-names = "i2c"; 778 pinctrl-0 = <&state_dpaux0_i2c>; 779 pinctrl-1 = <&state_dpaux0_off>; 780 pinctrl-names = "default", "idle"; 781 status = "disabled"; 782 }; 783 784 /* shares pads with dpaux2 */ 785 dp_aux_ch2_i2c: i2c@31c0000 { 786 compatible = "nvidia,tegra194-i2c"; 787 reg = <0x031c0000 0x10000>; 788 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 clocks = <&bpmp TEGRA194_CLK_I2C7>; 792 clock-names = "div-clk"; 793 resets = <&bpmp TEGRA194_RESET_I2C7>; 794 reset-names = "i2c"; 795 pinctrl-0 = <&state_dpaux2_i2c>; 796 pinctrl-1 = <&state_dpaux2_off>; 797 pinctrl-names = "default", "idle"; 798 status = "disabled"; 799 }; 800 801 /* shares pads with dpaux3 */ 802 dp_aux_ch3_i2c: i2c@31e0000 { 803 compatible = "nvidia,tegra194-i2c"; 804 reg = <0x031e0000 0x10000>; 805 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 clocks = <&bpmp TEGRA194_CLK_I2C9>; 809 clock-names = "div-clk"; 810 resets = <&bpmp TEGRA194_RESET_I2C9>; 811 reset-names = "i2c"; 812 pinctrl-0 = <&state_dpaux3_i2c>; 813 pinctrl-1 = <&state_dpaux3_off>; 814 pinctrl-names = "default", "idle"; 815 status = "disabled"; 816 }; 817 818 spi@3270000 { 819 compatible = "nvidia,tegra194-qspi"; 820 reg = <0x3270000 0x1000>; 821 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 825 <&bpmp TEGRA194_CLK_QSPI0_PM>; 826 clock-names = "qspi", "qspi_out"; 827 resets = <&bpmp TEGRA194_RESET_QSPI0>; 828 reset-names = "qspi"; 829 status = "disabled"; 830 }; 831 832 spi@3300000 { 833 compatible = "nvidia,tegra194-qspi"; 834 reg = <0x3300000 0x1000>; 835 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 839 <&bpmp TEGRA194_CLK_QSPI1_PM>; 840 clock-names = "qspi", "qspi_out"; 841 resets = <&bpmp TEGRA194_RESET_QSPI1>; 842 reset-names = "qspi"; 843 status = "disabled"; 844 }; 845 846 pwm1: pwm@3280000 { 847 compatible = "nvidia,tegra194-pwm", 848 "nvidia,tegra186-pwm"; 849 reg = <0x3280000 0x10000>; 850 clocks = <&bpmp TEGRA194_CLK_PWM1>; 851 clock-names = "pwm"; 852 resets = <&bpmp TEGRA194_RESET_PWM1>; 853 reset-names = "pwm"; 854 status = "disabled"; 855 #pwm-cells = <2>; 856 }; 857 858 pwm2: pwm@3290000 { 859 compatible = "nvidia,tegra194-pwm", 860 "nvidia,tegra186-pwm"; 861 reg = <0x3290000 0x10000>; 862 clocks = <&bpmp TEGRA194_CLK_PWM2>; 863 clock-names = "pwm"; 864 resets = <&bpmp TEGRA194_RESET_PWM2>; 865 reset-names = "pwm"; 866 status = "disabled"; 867 #pwm-cells = <2>; 868 }; 869 870 pwm3: pwm@32a0000 { 871 compatible = "nvidia,tegra194-pwm", 872 "nvidia,tegra186-pwm"; 873 reg = <0x32a0000 0x10000>; 874 clocks = <&bpmp TEGRA194_CLK_PWM3>; 875 clock-names = "pwm"; 876 resets = <&bpmp TEGRA194_RESET_PWM3>; 877 reset-names = "pwm"; 878 status = "disabled"; 879 #pwm-cells = <2>; 880 }; 881 882 pwm5: pwm@32c0000 { 883 compatible = "nvidia,tegra194-pwm", 884 "nvidia,tegra186-pwm"; 885 reg = <0x32c0000 0x10000>; 886 clocks = <&bpmp TEGRA194_CLK_PWM5>; 887 clock-names = "pwm"; 888 resets = <&bpmp TEGRA194_RESET_PWM5>; 889 reset-names = "pwm"; 890 status = "disabled"; 891 #pwm-cells = <2>; 892 }; 893 894 pwm6: pwm@32d0000 { 895 compatible = "nvidia,tegra194-pwm", 896 "nvidia,tegra186-pwm"; 897 reg = <0x32d0000 0x10000>; 898 clocks = <&bpmp TEGRA194_CLK_PWM6>; 899 clock-names = "pwm"; 900 resets = <&bpmp TEGRA194_RESET_PWM6>; 901 reset-names = "pwm"; 902 status = "disabled"; 903 #pwm-cells = <2>; 904 }; 905 906 pwm7: pwm@32e0000 { 907 compatible = "nvidia,tegra194-pwm", 908 "nvidia,tegra186-pwm"; 909 reg = <0x32e0000 0x10000>; 910 clocks = <&bpmp TEGRA194_CLK_PWM7>; 911 clock-names = "pwm"; 912 resets = <&bpmp TEGRA194_RESET_PWM7>; 913 reset-names = "pwm"; 914 status = "disabled"; 915 #pwm-cells = <2>; 916 }; 917 918 pwm8: pwm@32f0000 { 919 compatible = "nvidia,tegra194-pwm", 920 "nvidia,tegra186-pwm"; 921 reg = <0x32f0000 0x10000>; 922 clocks = <&bpmp TEGRA194_CLK_PWM8>; 923 clock-names = "pwm"; 924 resets = <&bpmp TEGRA194_RESET_PWM8>; 925 reset-names = "pwm"; 926 status = "disabled"; 927 #pwm-cells = <2>; 928 }; 929 930 sdmmc1: mmc@3400000 { 931 compatible = "nvidia,tegra194-sdhci"; 932 reg = <0x03400000 0x10000>; 933 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 935 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 936 clock-names = "sdhci", "tmclk"; 937 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 938 reset-names = "sdhci"; 939 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 940 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 941 interconnect-names = "dma-mem", "write"; 942 iommus = <&smmu TEGRA194_SID_SDMMC1>; 943 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 944 pinctrl-0 = <&sdmmc1_3v3>; 945 pinctrl-1 = <&sdmmc1_1v8>; 946 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 947 <0x07>; 948 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 949 <0x07>; 950 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 951 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 952 <0x07>; 953 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 954 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 955 nvidia,default-tap = <0x9>; 956 nvidia,default-trim = <0x5>; 957 sd-uhs-sdr25; 958 sd-uhs-sdr50; 959 sd-uhs-ddr50; 960 sd-uhs-sdr104; 961 status = "disabled"; 962 }; 963 964 sdmmc3: mmc@3440000 { 965 compatible = "nvidia,tegra194-sdhci"; 966 reg = <0x03440000 0x10000>; 967 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 969 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 970 clock-names = "sdhci", "tmclk"; 971 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 972 reset-names = "sdhci"; 973 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 974 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 975 interconnect-names = "dma-mem", "write"; 976 iommus = <&smmu TEGRA194_SID_SDMMC3>; 977 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 978 pinctrl-0 = <&sdmmc3_3v3>; 979 pinctrl-1 = <&sdmmc3_1v8>; 980 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 981 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 982 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 983 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 984 <0x07>; 985 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 986 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 987 <0x07>; 988 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 989 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 990 nvidia,default-tap = <0x9>; 991 nvidia,default-trim = <0x5>; 992 sd-uhs-sdr25; 993 sd-uhs-sdr50; 994 sd-uhs-ddr50; 995 sd-uhs-sdr104; 996 status = "disabled"; 997 }; 998 999 sdmmc4: mmc@3460000 { 1000 compatible = "nvidia,tegra194-sdhci"; 1001 reg = <0x03460000 0x10000>; 1002 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1003 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1004 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1005 clock-names = "sdhci", "tmclk"; 1006 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1007 <&bpmp TEGRA194_CLK_PLLC4>; 1008 assigned-clock-parents = 1009 <&bpmp TEGRA194_CLK_PLLC4>; 1010 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1011 reset-names = "sdhci"; 1012 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1013 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1014 interconnect-names = "dma-mem", "write"; 1015 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1016 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1017 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1018 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1019 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1020 <0x0a>; 1021 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1022 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1023 <0x0a>; 1024 nvidia,default-tap = <0x8>; 1025 nvidia,default-trim = <0x14>; 1026 nvidia,dqs-trim = <40>; 1027 cap-mmc-highspeed; 1028 mmc-ddr-1_8v; 1029 mmc-hs200-1_8v; 1030 mmc-hs400-1_8v; 1031 mmc-hs400-enhanced-strobe; 1032 supports-cqe; 1033 status = "disabled"; 1034 }; 1035 1036 hda@3510000 { 1037 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 1038 reg = <0x3510000 0x10000>; 1039 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1040 clocks = <&bpmp TEGRA194_CLK_HDA>, 1041 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1042 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1043 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1044 resets = <&bpmp TEGRA194_RESET_HDA>, 1045 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1046 reset-names = "hda", "hda2hdmi"; 1047 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1048 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1049 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1050 interconnect-names = "dma-mem", "write"; 1051 iommus = <&smmu TEGRA194_SID_HDA>; 1052 status = "disabled"; 1053 }; 1054 1055 xusb_padctl: padctl@3520000 { 1056 compatible = "nvidia,tegra194-xusb-padctl"; 1057 reg = <0x03520000 0x1000>, 1058 <0x03540000 0x1000>; 1059 reg-names = "padctl", "ao"; 1060 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1061 1062 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1063 reset-names = "padctl"; 1064 1065 status = "disabled"; 1066 1067 pads { 1068 usb2 { 1069 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1070 clock-names = "trk"; 1071 1072 lanes { 1073 usb2-0 { 1074 nvidia,function = "xusb"; 1075 status = "disabled"; 1076 #phy-cells = <0>; 1077 }; 1078 1079 usb2-1 { 1080 nvidia,function = "xusb"; 1081 status = "disabled"; 1082 #phy-cells = <0>; 1083 }; 1084 1085 usb2-2 { 1086 nvidia,function = "xusb"; 1087 status = "disabled"; 1088 #phy-cells = <0>; 1089 }; 1090 1091 usb2-3 { 1092 nvidia,function = "xusb"; 1093 status = "disabled"; 1094 #phy-cells = <0>; 1095 }; 1096 }; 1097 }; 1098 1099 usb3 { 1100 lanes { 1101 usb3-0 { 1102 nvidia,function = "xusb"; 1103 status = "disabled"; 1104 #phy-cells = <0>; 1105 }; 1106 1107 usb3-1 { 1108 nvidia,function = "xusb"; 1109 status = "disabled"; 1110 #phy-cells = <0>; 1111 }; 1112 1113 usb3-2 { 1114 nvidia,function = "xusb"; 1115 status = "disabled"; 1116 #phy-cells = <0>; 1117 }; 1118 1119 usb3-3 { 1120 nvidia,function = "xusb"; 1121 status = "disabled"; 1122 #phy-cells = <0>; 1123 }; 1124 }; 1125 }; 1126 }; 1127 1128 ports { 1129 usb2-0 { 1130 status = "disabled"; 1131 }; 1132 1133 usb2-1 { 1134 status = "disabled"; 1135 }; 1136 1137 usb2-2 { 1138 status = "disabled"; 1139 }; 1140 1141 usb2-3 { 1142 status = "disabled"; 1143 }; 1144 1145 usb3-0 { 1146 status = "disabled"; 1147 }; 1148 1149 usb3-1 { 1150 status = "disabled"; 1151 }; 1152 1153 usb3-2 { 1154 status = "disabled"; 1155 }; 1156 1157 usb3-3 { 1158 status = "disabled"; 1159 }; 1160 }; 1161 }; 1162 1163 usb@3550000 { 1164 compatible = "nvidia,tegra194-xudc"; 1165 reg = <0x03550000 0x8000>, 1166 <0x03558000 0x1000>; 1167 reg-names = "base", "fpci"; 1168 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1169 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1170 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1171 <&bpmp TEGRA194_CLK_XUSB_SS>, 1172 <&bpmp TEGRA194_CLK_XUSB_FS>; 1173 clock-names = "dev", "ss", "ss_src", "fs_src"; 1174 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1175 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1176 interconnect-names = "dma-mem", "write"; 1177 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1178 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1179 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1180 power-domain-names = "dev", "ss"; 1181 nvidia,xusb-padctl = <&xusb_padctl>; 1182 status = "disabled"; 1183 }; 1184 1185 usb@3610000 { 1186 compatible = "nvidia,tegra194-xusb"; 1187 reg = <0x03610000 0x40000>, 1188 <0x03600000 0x10000>; 1189 reg-names = "hcd", "fpci"; 1190 1191 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1193 1194 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1195 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1196 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1197 <&bpmp TEGRA194_CLK_XUSB_SS>, 1198 <&bpmp TEGRA194_CLK_CLK_M>, 1199 <&bpmp TEGRA194_CLK_XUSB_FS>, 1200 <&bpmp TEGRA194_CLK_UTMIPLL>, 1201 <&bpmp TEGRA194_CLK_CLK_M>, 1202 <&bpmp TEGRA194_CLK_PLLE>; 1203 clock-names = "xusb_host", "xusb_falcon_src", 1204 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1205 "xusb_fs_src", "pll_u_480m", "clk_m", 1206 "pll_e"; 1207 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1208 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1209 interconnect-names = "dma-mem", "write"; 1210 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1211 1212 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1213 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1214 power-domain-names = "xusb_host", "xusb_ss"; 1215 1216 nvidia,xusb-padctl = <&xusb_padctl>; 1217 status = "disabled"; 1218 }; 1219 1220 fuse@3820000 { 1221 compatible = "nvidia,tegra194-efuse"; 1222 reg = <0x03820000 0x10000>; 1223 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1224 clock-names = "fuse"; 1225 }; 1226 1227 gic: interrupt-controller@3881000 { 1228 compatible = "arm,gic-400"; 1229 #interrupt-cells = <3>; 1230 interrupt-controller; 1231 reg = <0x03881000 0x1000>, 1232 <0x03882000 0x2000>, 1233 <0x03884000 0x2000>, 1234 <0x03886000 0x2000>; 1235 interrupts = <GIC_PPI 9 1236 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1237 interrupt-parent = <&gic>; 1238 }; 1239 1240 cec@3960000 { 1241 compatible = "nvidia,tegra194-cec"; 1242 reg = <0x03960000 0x10000>; 1243 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1244 clocks = <&bpmp TEGRA194_CLK_CEC>; 1245 clock-names = "cec"; 1246 status = "disabled"; 1247 }; 1248 1249 hsp_top0: hsp@3c00000 { 1250 compatible = "nvidia,tegra194-hsp"; 1251 reg = <0x03c00000 0xa0000>; 1252 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1261 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1262 "shared3", "shared4", "shared5", "shared6", 1263 "shared7"; 1264 #mbox-cells = <2>; 1265 }; 1266 1267 p2u_hsio_0: phy@3e10000 { 1268 compatible = "nvidia,tegra194-p2u"; 1269 reg = <0x03e10000 0x10000>; 1270 reg-names = "ctl"; 1271 1272 #phy-cells = <0>; 1273 }; 1274 1275 p2u_hsio_1: phy@3e20000 { 1276 compatible = "nvidia,tegra194-p2u"; 1277 reg = <0x03e20000 0x10000>; 1278 reg-names = "ctl"; 1279 1280 #phy-cells = <0>; 1281 }; 1282 1283 p2u_hsio_2: phy@3e30000 { 1284 compatible = "nvidia,tegra194-p2u"; 1285 reg = <0x03e30000 0x10000>; 1286 reg-names = "ctl"; 1287 1288 #phy-cells = <0>; 1289 }; 1290 1291 p2u_hsio_3: phy@3e40000 { 1292 compatible = "nvidia,tegra194-p2u"; 1293 reg = <0x03e40000 0x10000>; 1294 reg-names = "ctl"; 1295 1296 #phy-cells = <0>; 1297 }; 1298 1299 p2u_hsio_4: phy@3e50000 { 1300 compatible = "nvidia,tegra194-p2u"; 1301 reg = <0x03e50000 0x10000>; 1302 reg-names = "ctl"; 1303 1304 #phy-cells = <0>; 1305 }; 1306 1307 p2u_hsio_5: phy@3e60000 { 1308 compatible = "nvidia,tegra194-p2u"; 1309 reg = <0x03e60000 0x10000>; 1310 reg-names = "ctl"; 1311 1312 #phy-cells = <0>; 1313 }; 1314 1315 p2u_hsio_6: phy@3e70000 { 1316 compatible = "nvidia,tegra194-p2u"; 1317 reg = <0x03e70000 0x10000>; 1318 reg-names = "ctl"; 1319 1320 #phy-cells = <0>; 1321 }; 1322 1323 p2u_hsio_7: phy@3e80000 { 1324 compatible = "nvidia,tegra194-p2u"; 1325 reg = <0x03e80000 0x10000>; 1326 reg-names = "ctl"; 1327 1328 #phy-cells = <0>; 1329 }; 1330 1331 p2u_hsio_8: phy@3e90000 { 1332 compatible = "nvidia,tegra194-p2u"; 1333 reg = <0x03e90000 0x10000>; 1334 reg-names = "ctl"; 1335 1336 #phy-cells = <0>; 1337 }; 1338 1339 p2u_hsio_9: phy@3ea0000 { 1340 compatible = "nvidia,tegra194-p2u"; 1341 reg = <0x03ea0000 0x10000>; 1342 reg-names = "ctl"; 1343 1344 #phy-cells = <0>; 1345 }; 1346 1347 p2u_nvhs_0: phy@3eb0000 { 1348 compatible = "nvidia,tegra194-p2u"; 1349 reg = <0x03eb0000 0x10000>; 1350 reg-names = "ctl"; 1351 1352 #phy-cells = <0>; 1353 }; 1354 1355 p2u_nvhs_1: phy@3ec0000 { 1356 compatible = "nvidia,tegra194-p2u"; 1357 reg = <0x03ec0000 0x10000>; 1358 reg-names = "ctl"; 1359 1360 #phy-cells = <0>; 1361 }; 1362 1363 p2u_nvhs_2: phy@3ed0000 { 1364 compatible = "nvidia,tegra194-p2u"; 1365 reg = <0x03ed0000 0x10000>; 1366 reg-names = "ctl"; 1367 1368 #phy-cells = <0>; 1369 }; 1370 1371 p2u_nvhs_3: phy@3ee0000 { 1372 compatible = "nvidia,tegra194-p2u"; 1373 reg = <0x03ee0000 0x10000>; 1374 reg-names = "ctl"; 1375 1376 #phy-cells = <0>; 1377 }; 1378 1379 p2u_nvhs_4: phy@3ef0000 { 1380 compatible = "nvidia,tegra194-p2u"; 1381 reg = <0x03ef0000 0x10000>; 1382 reg-names = "ctl"; 1383 1384 #phy-cells = <0>; 1385 }; 1386 1387 p2u_nvhs_5: phy@3f00000 { 1388 compatible = "nvidia,tegra194-p2u"; 1389 reg = <0x03f00000 0x10000>; 1390 reg-names = "ctl"; 1391 1392 #phy-cells = <0>; 1393 }; 1394 1395 p2u_nvhs_6: phy@3f10000 { 1396 compatible = "nvidia,tegra194-p2u"; 1397 reg = <0x03f10000 0x10000>; 1398 reg-names = "ctl"; 1399 1400 #phy-cells = <0>; 1401 }; 1402 1403 p2u_nvhs_7: phy@3f20000 { 1404 compatible = "nvidia,tegra194-p2u"; 1405 reg = <0x03f20000 0x10000>; 1406 reg-names = "ctl"; 1407 1408 #phy-cells = <0>; 1409 }; 1410 1411 p2u_hsio_10: phy@3f30000 { 1412 compatible = "nvidia,tegra194-p2u"; 1413 reg = <0x03f30000 0x10000>; 1414 reg-names = "ctl"; 1415 1416 #phy-cells = <0>; 1417 }; 1418 1419 p2u_hsio_11: phy@3f40000 { 1420 compatible = "nvidia,tegra194-p2u"; 1421 reg = <0x03f40000 0x10000>; 1422 reg-names = "ctl"; 1423 1424 #phy-cells = <0>; 1425 }; 1426 1427 hsp_aon: hsp@c150000 { 1428 compatible = "nvidia,tegra194-hsp"; 1429 reg = <0x0c150000 0x90000>; 1430 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1434 /* 1435 * Shared interrupt 0 is routed only to AON/SPE, so 1436 * we only have 4 shared interrupts for the CCPLEX. 1437 */ 1438 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1439 #mbox-cells = <2>; 1440 }; 1441 1442 gen2_i2c: i2c@c240000 { 1443 compatible = "nvidia,tegra194-i2c"; 1444 reg = <0x0c240000 0x10000>; 1445 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1446 #address-cells = <1>; 1447 #size-cells = <0>; 1448 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1449 clock-names = "div-clk"; 1450 resets = <&bpmp TEGRA194_RESET_I2C2>; 1451 reset-names = "i2c"; 1452 status = "disabled"; 1453 }; 1454 1455 gen8_i2c: i2c@c250000 { 1456 compatible = "nvidia,tegra194-i2c"; 1457 reg = <0x0c250000 0x10000>; 1458 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1462 clock-names = "div-clk"; 1463 resets = <&bpmp TEGRA194_RESET_I2C8>; 1464 reset-names = "i2c"; 1465 status = "disabled"; 1466 }; 1467 1468 uartc: serial@c280000 { 1469 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1470 reg = <0x0c280000 0x40>; 1471 reg-shift = <2>; 1472 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1473 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1474 clock-names = "serial"; 1475 resets = <&bpmp TEGRA194_RESET_UARTC>; 1476 reset-names = "serial"; 1477 status = "disabled"; 1478 }; 1479 1480 uartg: serial@c290000 { 1481 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1482 reg = <0x0c290000 0x40>; 1483 reg-shift = <2>; 1484 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1485 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1486 clock-names = "serial"; 1487 resets = <&bpmp TEGRA194_RESET_UARTG>; 1488 reset-names = "serial"; 1489 status = "disabled"; 1490 }; 1491 1492 rtc: rtc@c2a0000 { 1493 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1494 reg = <0x0c2a0000 0x10000>; 1495 interrupt-parent = <&pmc>; 1496 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1497 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1498 clock-names = "rtc"; 1499 status = "disabled"; 1500 }; 1501 1502 gpio_aon: gpio@c2f0000 { 1503 compatible = "nvidia,tegra194-gpio-aon"; 1504 reg-names = "security", "gpio"; 1505 reg = <0xc2f0000 0x1000>, 1506 <0xc2f1000 0x1000>; 1507 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1511 gpio-controller; 1512 #gpio-cells = <2>; 1513 interrupt-controller; 1514 #interrupt-cells = <2>; 1515 }; 1516 1517 pwm4: pwm@c340000 { 1518 compatible = "nvidia,tegra194-pwm", 1519 "nvidia,tegra186-pwm"; 1520 reg = <0xc340000 0x10000>; 1521 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1522 clock-names = "pwm"; 1523 resets = <&bpmp TEGRA194_RESET_PWM4>; 1524 reset-names = "pwm"; 1525 status = "disabled"; 1526 #pwm-cells = <2>; 1527 }; 1528 1529 pmc: pmc@c360000 { 1530 compatible = "nvidia,tegra194-pmc"; 1531 reg = <0x0c360000 0x10000>, 1532 <0x0c370000 0x10000>, 1533 <0x0c380000 0x10000>, 1534 <0x0c390000 0x10000>, 1535 <0x0c3a0000 0x10000>; 1536 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1537 1538 #interrupt-cells = <2>; 1539 interrupt-controller; 1540 sdmmc1_3v3: sdmmc1-3v3 { 1541 pins = "sdmmc1-hv"; 1542 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1543 }; 1544 1545 sdmmc1_1v8: sdmmc1-1v8 { 1546 pins = "sdmmc1-hv"; 1547 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1548 }; 1549 sdmmc3_3v3: sdmmc3-3v3 { 1550 pins = "sdmmc3-hv"; 1551 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1552 }; 1553 1554 sdmmc3_1v8: sdmmc3-1v8 { 1555 pins = "sdmmc3-hv"; 1556 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1557 }; 1558 1559 }; 1560 1561 iommu@10000000 { 1562 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1563 reg = <0x10000000 0x800000>; 1564 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1629 stream-match-mask = <0x7f80>; 1630 #global-interrupts = <1>; 1631 #iommu-cells = <1>; 1632 1633 nvidia,memory-controller = <&mc>; 1634 status = "okay"; 1635 }; 1636 1637 smmu: iommu@12000000 { 1638 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1639 reg = <0x12000000 0x800000>, 1640 <0x11000000 0x800000>; 1641 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1707 stream-match-mask = <0x7f80>; 1708 #global-interrupts = <2>; 1709 #iommu-cells = <1>; 1710 1711 nvidia,memory-controller = <&mc>; 1712 status = "okay"; 1713 }; 1714 1715 host1x@13e00000 { 1716 compatible = "nvidia,tegra194-host1x"; 1717 reg = <0x13e00000 0x10000>, 1718 <0x13e10000 0x10000>; 1719 reg-names = "hypervisor", "vm"; 1720 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1722 interrupt-names = "syncpt", "host1x"; 1723 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1724 clock-names = "host1x"; 1725 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1726 reset-names = "host1x"; 1727 1728 #address-cells = <1>; 1729 #size-cells = <1>; 1730 1731 ranges = <0x15000000 0x15000000 0x01000000>; 1732 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1733 interconnect-names = "dma-mem"; 1734 iommus = <&smmu TEGRA194_SID_HOST1X>; 1735 1736 nvdec@15140000 { 1737 compatible = "nvidia,tegra194-nvdec"; 1738 reg = <0x15140000 0x00040000>; 1739 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1740 clock-names = "nvdec"; 1741 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1742 reset-names = "nvdec"; 1743 1744 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1745 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1746 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1747 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1748 interconnect-names = "dma-mem", "read-1", "write"; 1749 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1750 dma-coherent; 1751 1752 nvidia,host1x-class = <0xf5>; 1753 }; 1754 1755 display-hub@15200000 { 1756 compatible = "nvidia,tegra194-display"; 1757 reg = <0x15200000 0x00040000>; 1758 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1759 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1760 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1761 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1762 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1763 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1764 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1765 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1766 "wgrp3", "wgrp4", "wgrp5"; 1767 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1768 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1769 clock-names = "disp", "hub"; 1770 status = "disabled"; 1771 1772 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1773 1774 #address-cells = <1>; 1775 #size-cells = <1>; 1776 1777 ranges = <0x15200000 0x15200000 0x40000>; 1778 1779 display@15200000 { 1780 compatible = "nvidia,tegra194-dc"; 1781 reg = <0x15200000 0x10000>; 1782 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1783 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1784 clock-names = "dc"; 1785 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1786 reset-names = "dc"; 1787 1788 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1789 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1790 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1791 interconnect-names = "dma-mem", "read-1"; 1792 1793 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1794 nvidia,head = <0>; 1795 }; 1796 1797 display@15210000 { 1798 compatible = "nvidia,tegra194-dc"; 1799 reg = <0x15210000 0x10000>; 1800 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1801 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1802 clock-names = "dc"; 1803 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1804 reset-names = "dc"; 1805 1806 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1807 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1808 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1809 interconnect-names = "dma-mem", "read-1"; 1810 1811 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1812 nvidia,head = <1>; 1813 }; 1814 1815 display@15220000 { 1816 compatible = "nvidia,tegra194-dc"; 1817 reg = <0x15220000 0x10000>; 1818 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1819 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1820 clock-names = "dc"; 1821 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1822 reset-names = "dc"; 1823 1824 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1825 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1826 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1827 interconnect-names = "dma-mem", "read-1"; 1828 1829 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1830 nvidia,head = <2>; 1831 }; 1832 1833 display@15230000 { 1834 compatible = "nvidia,tegra194-dc"; 1835 reg = <0x15230000 0x10000>; 1836 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1837 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1838 clock-names = "dc"; 1839 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1840 reset-names = "dc"; 1841 1842 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1843 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1844 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1845 interconnect-names = "dma-mem", "read-1"; 1846 1847 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1848 nvidia,head = <3>; 1849 }; 1850 }; 1851 1852 vic@15340000 { 1853 compatible = "nvidia,tegra194-vic"; 1854 reg = <0x15340000 0x00040000>; 1855 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1856 clocks = <&bpmp TEGRA194_CLK_VIC>; 1857 clock-names = "vic"; 1858 resets = <&bpmp TEGRA194_RESET_VIC>; 1859 reset-names = "vic"; 1860 1861 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1862 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1863 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1864 interconnect-names = "dma-mem", "write"; 1865 iommus = <&smmu TEGRA194_SID_VIC>; 1866 dma-coherent; 1867 }; 1868 1869 nvjpg@15380000 { 1870 compatible = "nvidia,tegra194-nvjpg"; 1871 reg = <0x15380000 0x40000>; 1872 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1873 clock-names = "nvjpg"; 1874 resets = <&bpmp TEGRA194_RESET_NVJPG>; 1875 reset-names = "nvjpg"; 1876 1877 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1878 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1879 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1880 interconnect-names = "dma-mem", "write"; 1881 iommus = <&smmu TEGRA194_SID_NVJPG>; 1882 dma-coherent; 1883 }; 1884 1885 nvdec@15480000 { 1886 compatible = "nvidia,tegra194-nvdec"; 1887 reg = <0x15480000 0x00040000>; 1888 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 1889 clock-names = "nvdec"; 1890 resets = <&bpmp TEGRA194_RESET_NVDEC>; 1891 reset-names = "nvdec"; 1892 1893 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 1894 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 1895 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 1896 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 1897 interconnect-names = "dma-mem", "read-1", "write"; 1898 iommus = <&smmu TEGRA194_SID_NVDEC>; 1899 dma-coherent; 1900 1901 nvidia,host1x-class = <0xf0>; 1902 }; 1903 1904 nvenc@154c0000 { 1905 compatible = "nvidia,tegra194-nvenc"; 1906 reg = <0x154c0000 0x40000>; 1907 clocks = <&bpmp TEGRA194_CLK_NVENC>; 1908 clock-names = "nvenc"; 1909 resets = <&bpmp TEGRA194_RESET_NVENC>; 1910 reset-names = "nvenc"; 1911 1912 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 1913 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 1914 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 1915 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 1916 interconnect-names = "dma-mem", "read-1", "write"; 1917 iommus = <&smmu TEGRA194_SID_NVENC>; 1918 dma-coherent; 1919 1920 nvidia,host1x-class = <0x21>; 1921 }; 1922 1923 dpaux0: dpaux@155c0000 { 1924 compatible = "nvidia,tegra194-dpaux"; 1925 reg = <0x155c0000 0x10000>; 1926 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1927 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1928 <&bpmp TEGRA194_CLK_PLLDP>; 1929 clock-names = "dpaux", "parent"; 1930 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1931 reset-names = "dpaux"; 1932 status = "disabled"; 1933 1934 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1935 1936 state_dpaux0_aux: pinmux-aux { 1937 groups = "dpaux-io"; 1938 function = "aux"; 1939 }; 1940 1941 state_dpaux0_i2c: pinmux-i2c { 1942 groups = "dpaux-io"; 1943 function = "i2c"; 1944 }; 1945 1946 state_dpaux0_off: pinmux-off { 1947 groups = "dpaux-io"; 1948 function = "off"; 1949 }; 1950 1951 i2c-bus { 1952 #address-cells = <1>; 1953 #size-cells = <0>; 1954 }; 1955 }; 1956 1957 dpaux1: dpaux@155d0000 { 1958 compatible = "nvidia,tegra194-dpaux"; 1959 reg = <0x155d0000 0x10000>; 1960 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1961 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1962 <&bpmp TEGRA194_CLK_PLLDP>; 1963 clock-names = "dpaux", "parent"; 1964 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1965 reset-names = "dpaux"; 1966 status = "disabled"; 1967 1968 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1969 1970 state_dpaux1_aux: pinmux-aux { 1971 groups = "dpaux-io"; 1972 function = "aux"; 1973 }; 1974 1975 state_dpaux1_i2c: pinmux-i2c { 1976 groups = "dpaux-io"; 1977 function = "i2c"; 1978 }; 1979 1980 state_dpaux1_off: pinmux-off { 1981 groups = "dpaux-io"; 1982 function = "off"; 1983 }; 1984 1985 i2c-bus { 1986 #address-cells = <1>; 1987 #size-cells = <0>; 1988 }; 1989 }; 1990 1991 dpaux2: dpaux@155e0000 { 1992 compatible = "nvidia,tegra194-dpaux"; 1993 reg = <0x155e0000 0x10000>; 1994 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1995 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1996 <&bpmp TEGRA194_CLK_PLLDP>; 1997 clock-names = "dpaux", "parent"; 1998 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1999 reset-names = "dpaux"; 2000 status = "disabled"; 2001 2002 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2003 2004 state_dpaux2_aux: pinmux-aux { 2005 groups = "dpaux-io"; 2006 function = "aux"; 2007 }; 2008 2009 state_dpaux2_i2c: pinmux-i2c { 2010 groups = "dpaux-io"; 2011 function = "i2c"; 2012 }; 2013 2014 state_dpaux2_off: pinmux-off { 2015 groups = "dpaux-io"; 2016 function = "off"; 2017 }; 2018 2019 i2c-bus { 2020 #address-cells = <1>; 2021 #size-cells = <0>; 2022 }; 2023 }; 2024 2025 dpaux3: dpaux@155f0000 { 2026 compatible = "nvidia,tegra194-dpaux"; 2027 reg = <0x155f0000 0x10000>; 2028 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2029 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2030 <&bpmp TEGRA194_CLK_PLLDP>; 2031 clock-names = "dpaux", "parent"; 2032 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2033 reset-names = "dpaux"; 2034 status = "disabled"; 2035 2036 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2037 2038 state_dpaux3_aux: pinmux-aux { 2039 groups = "dpaux-io"; 2040 function = "aux"; 2041 }; 2042 2043 state_dpaux3_i2c: pinmux-i2c { 2044 groups = "dpaux-io"; 2045 function = "i2c"; 2046 }; 2047 2048 state_dpaux3_off: pinmux-off { 2049 groups = "dpaux-io"; 2050 function = "off"; 2051 }; 2052 2053 i2c-bus { 2054 #address-cells = <1>; 2055 #size-cells = <0>; 2056 }; 2057 }; 2058 2059 nvenc@15a80000 { 2060 compatible = "nvidia,tegra194-nvenc"; 2061 reg = <0x15a80000 0x00040000>; 2062 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2063 clock-names = "nvenc"; 2064 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2065 reset-names = "nvenc"; 2066 2067 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2068 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2069 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2070 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2071 interconnect-names = "dma-mem", "read-1", "write"; 2072 iommus = <&smmu TEGRA194_SID_NVENC1>; 2073 dma-coherent; 2074 2075 nvidia,host1x-class = <0x22>; 2076 }; 2077 2078 sor0: sor@15b00000 { 2079 compatible = "nvidia,tegra194-sor"; 2080 reg = <0x15b00000 0x40000>; 2081 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2082 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2083 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2084 <&bpmp TEGRA194_CLK_PLLD>, 2085 <&bpmp TEGRA194_CLK_PLLDP>, 2086 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2087 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2088 clock-names = "sor", "out", "parent", "dp", "safe", 2089 "pad"; 2090 resets = <&bpmp TEGRA194_RESET_SOR0>; 2091 reset-names = "sor"; 2092 pinctrl-0 = <&state_dpaux0_aux>; 2093 pinctrl-1 = <&state_dpaux0_i2c>; 2094 pinctrl-2 = <&state_dpaux0_off>; 2095 pinctrl-names = "aux", "i2c", "off"; 2096 status = "disabled"; 2097 2098 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2099 nvidia,interface = <0>; 2100 }; 2101 2102 sor1: sor@15b40000 { 2103 compatible = "nvidia,tegra194-sor"; 2104 reg = <0x15b40000 0x40000>; 2105 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2106 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2107 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2108 <&bpmp TEGRA194_CLK_PLLD2>, 2109 <&bpmp TEGRA194_CLK_PLLDP>, 2110 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2111 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2112 clock-names = "sor", "out", "parent", "dp", "safe", 2113 "pad"; 2114 resets = <&bpmp TEGRA194_RESET_SOR1>; 2115 reset-names = "sor"; 2116 pinctrl-0 = <&state_dpaux1_aux>; 2117 pinctrl-1 = <&state_dpaux1_i2c>; 2118 pinctrl-2 = <&state_dpaux1_off>; 2119 pinctrl-names = "aux", "i2c", "off"; 2120 status = "disabled"; 2121 2122 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2123 nvidia,interface = <1>; 2124 }; 2125 2126 sor2: sor@15b80000 { 2127 compatible = "nvidia,tegra194-sor"; 2128 reg = <0x15b80000 0x40000>; 2129 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2130 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2131 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2132 <&bpmp TEGRA194_CLK_PLLD3>, 2133 <&bpmp TEGRA194_CLK_PLLDP>, 2134 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2135 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2136 clock-names = "sor", "out", "parent", "dp", "safe", 2137 "pad"; 2138 resets = <&bpmp TEGRA194_RESET_SOR2>; 2139 reset-names = "sor"; 2140 pinctrl-0 = <&state_dpaux2_aux>; 2141 pinctrl-1 = <&state_dpaux2_i2c>; 2142 pinctrl-2 = <&state_dpaux2_off>; 2143 pinctrl-names = "aux", "i2c", "off"; 2144 status = "disabled"; 2145 2146 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2147 nvidia,interface = <2>; 2148 }; 2149 2150 sor3: sor@15bc0000 { 2151 compatible = "nvidia,tegra194-sor"; 2152 reg = <0x15bc0000 0x40000>; 2153 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2154 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2155 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2156 <&bpmp TEGRA194_CLK_PLLD4>, 2157 <&bpmp TEGRA194_CLK_PLLDP>, 2158 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2159 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2160 clock-names = "sor", "out", "parent", "dp", "safe", 2161 "pad"; 2162 resets = <&bpmp TEGRA194_RESET_SOR3>; 2163 reset-names = "sor"; 2164 pinctrl-0 = <&state_dpaux3_aux>; 2165 pinctrl-1 = <&state_dpaux3_i2c>; 2166 pinctrl-2 = <&state_dpaux3_off>; 2167 pinctrl-names = "aux", "i2c", "off"; 2168 status = "disabled"; 2169 2170 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2171 nvidia,interface = <3>; 2172 }; 2173 }; 2174 2175 gpu@17000000 { 2176 compatible = "nvidia,gv11b"; 2177 reg = <0x17000000 0x1000000>, 2178 <0x18000000 0x1000000>; 2179 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2181 interrupt-names = "stall", "nonstall"; 2182 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2183 <&bpmp TEGRA194_CLK_GPU_PWR>, 2184 <&bpmp TEGRA194_CLK_FUSE>; 2185 clock-names = "gpu", "pwr", "fuse"; 2186 resets = <&bpmp TEGRA194_RESET_GPU>; 2187 reset-names = "gpu"; 2188 dma-coherent; 2189 2190 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2191 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2192 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2193 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2194 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2195 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2196 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2197 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2198 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2199 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2200 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2201 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2202 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2203 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2204 "read-1", "read-1-hp", "write-1", 2205 "read-2", "read-2-hp", "write-2", 2206 "read-3", "read-3-hp", "write-3"; 2207 }; 2208 }; 2209 2210 pcie@14100000 { 2211 compatible = "nvidia,tegra194-pcie"; 2212 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2213 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2214 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2215 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2216 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2217 reg-names = "appl", "config", "atu_dma", "dbi"; 2218 2219 status = "disabled"; 2220 2221 #address-cells = <3>; 2222 #size-cells = <2>; 2223 device_type = "pci"; 2224 num-lanes = <1>; 2225 linux,pci-domain = <1>; 2226 2227 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2228 clock-names = "core"; 2229 2230 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2231 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2232 reset-names = "apb", "core"; 2233 2234 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2235 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2236 interrupt-names = "intr", "msi"; 2237 2238 #interrupt-cells = <1>; 2239 interrupt-map-mask = <0 0 0 0>; 2240 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2241 2242 nvidia,bpmp = <&bpmp 1>; 2243 2244 nvidia,aspm-cmrt-us = <60>; 2245 nvidia,aspm-pwr-on-t-us = <20>; 2246 nvidia,aspm-l0s-entrance-latency-us = <3>; 2247 2248 bus-range = <0x0 0xff>; 2249 2250 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2251 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2252 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2253 2254 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2255 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2256 interconnect-names = "dma-mem", "write"; 2257 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2258 iommu-map-mask = <0x0>; 2259 dma-coherent; 2260 }; 2261 2262 pcie@14120000 { 2263 compatible = "nvidia,tegra194-pcie"; 2264 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2265 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2266 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2267 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2268 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2269 reg-names = "appl", "config", "atu_dma", "dbi"; 2270 2271 status = "disabled"; 2272 2273 #address-cells = <3>; 2274 #size-cells = <2>; 2275 device_type = "pci"; 2276 num-lanes = <1>; 2277 linux,pci-domain = <2>; 2278 2279 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2280 clock-names = "core"; 2281 2282 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2283 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2284 reset-names = "apb", "core"; 2285 2286 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2287 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2288 interrupt-names = "intr", "msi"; 2289 2290 #interrupt-cells = <1>; 2291 interrupt-map-mask = <0 0 0 0>; 2292 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2293 2294 nvidia,bpmp = <&bpmp 2>; 2295 2296 nvidia,aspm-cmrt-us = <60>; 2297 nvidia,aspm-pwr-on-t-us = <20>; 2298 nvidia,aspm-l0s-entrance-latency-us = <3>; 2299 2300 bus-range = <0x0 0xff>; 2301 2302 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2303 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2304 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2305 2306 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2307 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2308 interconnect-names = "dma-mem", "write"; 2309 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2310 iommu-map-mask = <0x0>; 2311 dma-coherent; 2312 }; 2313 2314 pcie@14140000 { 2315 compatible = "nvidia,tegra194-pcie"; 2316 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2317 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2318 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2319 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2320 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2321 reg-names = "appl", "config", "atu_dma", "dbi"; 2322 2323 status = "disabled"; 2324 2325 #address-cells = <3>; 2326 #size-cells = <2>; 2327 device_type = "pci"; 2328 num-lanes = <1>; 2329 linux,pci-domain = <3>; 2330 2331 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2332 clock-names = "core"; 2333 2334 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2335 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2336 reset-names = "apb", "core"; 2337 2338 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2339 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2340 interrupt-names = "intr", "msi"; 2341 2342 #interrupt-cells = <1>; 2343 interrupt-map-mask = <0 0 0 0>; 2344 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2345 2346 nvidia,bpmp = <&bpmp 3>; 2347 2348 nvidia,aspm-cmrt-us = <60>; 2349 nvidia,aspm-pwr-on-t-us = <20>; 2350 nvidia,aspm-l0s-entrance-latency-us = <3>; 2351 2352 bus-range = <0x0 0xff>; 2353 2354 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2355 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2356 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2357 2358 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2359 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2360 interconnect-names = "dma-mem", "write"; 2361 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2362 iommu-map-mask = <0x0>; 2363 dma-coherent; 2364 }; 2365 2366 pcie@14160000 { 2367 compatible = "nvidia,tegra194-pcie"; 2368 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2369 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2370 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2371 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2372 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2373 reg-names = "appl", "config", "atu_dma", "dbi"; 2374 2375 status = "disabled"; 2376 2377 #address-cells = <3>; 2378 #size-cells = <2>; 2379 device_type = "pci"; 2380 num-lanes = <4>; 2381 linux,pci-domain = <4>; 2382 2383 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2384 clock-names = "core"; 2385 2386 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2387 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2388 reset-names = "apb", "core"; 2389 2390 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2391 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2392 interrupt-names = "intr", "msi"; 2393 2394 #interrupt-cells = <1>; 2395 interrupt-map-mask = <0 0 0 0>; 2396 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2397 2398 nvidia,bpmp = <&bpmp 4>; 2399 2400 nvidia,aspm-cmrt-us = <60>; 2401 nvidia,aspm-pwr-on-t-us = <20>; 2402 nvidia,aspm-l0s-entrance-latency-us = <3>; 2403 2404 bus-range = <0x0 0xff>; 2405 2406 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2407 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2408 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2409 2410 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2411 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2412 interconnect-names = "dma-mem", "write"; 2413 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2414 iommu-map-mask = <0x0>; 2415 dma-coherent; 2416 }; 2417 2418 pcie@14180000 { 2419 compatible = "nvidia,tegra194-pcie"; 2420 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2421 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2422 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2423 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2424 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2425 reg-names = "appl", "config", "atu_dma", "dbi"; 2426 2427 status = "disabled"; 2428 2429 #address-cells = <3>; 2430 #size-cells = <2>; 2431 device_type = "pci"; 2432 num-lanes = <8>; 2433 linux,pci-domain = <0>; 2434 2435 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2436 clock-names = "core"; 2437 2438 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2439 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2440 reset-names = "apb", "core"; 2441 2442 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2443 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2444 interrupt-names = "intr", "msi"; 2445 2446 #interrupt-cells = <1>; 2447 interrupt-map-mask = <0 0 0 0>; 2448 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2449 2450 nvidia,bpmp = <&bpmp 0>; 2451 2452 nvidia,aspm-cmrt-us = <60>; 2453 nvidia,aspm-pwr-on-t-us = <20>; 2454 nvidia,aspm-l0s-entrance-latency-us = <3>; 2455 2456 bus-range = <0x0 0xff>; 2457 2458 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2459 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2460 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2461 2462 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2463 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2464 interconnect-names = "dma-mem", "write"; 2465 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2466 iommu-map-mask = <0x0>; 2467 dma-coherent; 2468 }; 2469 2470 pcie@141a0000 { 2471 compatible = "nvidia,tegra194-pcie"; 2472 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2473 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2474 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2475 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2476 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2477 reg-names = "appl", "config", "atu_dma", "dbi"; 2478 2479 status = "disabled"; 2480 2481 #address-cells = <3>; 2482 #size-cells = <2>; 2483 device_type = "pci"; 2484 num-lanes = <8>; 2485 linux,pci-domain = <5>; 2486 2487 pinctrl-names = "default"; 2488 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2489 2490 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2491 clock-names = "core"; 2492 2493 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2494 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2495 reset-names = "apb", "core"; 2496 2497 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2498 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2499 interrupt-names = "intr", "msi"; 2500 2501 nvidia,bpmp = <&bpmp 5>; 2502 2503 #interrupt-cells = <1>; 2504 interrupt-map-mask = <0 0 0 0>; 2505 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2506 2507 nvidia,aspm-cmrt-us = <60>; 2508 nvidia,aspm-pwr-on-t-us = <20>; 2509 nvidia,aspm-l0s-entrance-latency-us = <3>; 2510 2511 bus-range = <0x0 0xff>; 2512 2513 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2514 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2515 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2516 2517 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2518 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2519 interconnect-names = "dma-mem", "write"; 2520 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2521 iommu-map-mask = <0x0>; 2522 dma-coherent; 2523 }; 2524 2525 pcie-ep@14160000 { 2526 compatible = "nvidia,tegra194-pcie-ep"; 2527 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2528 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2529 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2530 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2531 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2532 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2533 2534 status = "disabled"; 2535 2536 num-lanes = <4>; 2537 num-ib-windows = <2>; 2538 num-ob-windows = <8>; 2539 2540 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2541 clock-names = "core"; 2542 2543 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2544 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2545 reset-names = "apb", "core"; 2546 2547 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2548 interrupt-names = "intr"; 2549 2550 nvidia,bpmp = <&bpmp 4>; 2551 2552 nvidia,aspm-cmrt-us = <60>; 2553 nvidia,aspm-pwr-on-t-us = <20>; 2554 nvidia,aspm-l0s-entrance-latency-us = <3>; 2555 2556 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2557 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2558 interconnect-names = "dma-mem", "write"; 2559 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2560 iommu-map-mask = <0x0>; 2561 dma-coherent; 2562 }; 2563 2564 pcie-ep@14180000 { 2565 compatible = "nvidia,tegra194-pcie-ep"; 2566 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2567 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2568 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2569 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2570 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2571 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2572 2573 status = "disabled"; 2574 2575 num-lanes = <8>; 2576 num-ib-windows = <2>; 2577 num-ob-windows = <8>; 2578 2579 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2580 clock-names = "core"; 2581 2582 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2583 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2584 reset-names = "apb", "core"; 2585 2586 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2587 interrupt-names = "intr"; 2588 2589 nvidia,bpmp = <&bpmp 0>; 2590 2591 nvidia,aspm-cmrt-us = <60>; 2592 nvidia,aspm-pwr-on-t-us = <20>; 2593 nvidia,aspm-l0s-entrance-latency-us = <3>; 2594 2595 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2596 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2597 interconnect-names = "dma-mem", "write"; 2598 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2599 iommu-map-mask = <0x0>; 2600 dma-coherent; 2601 }; 2602 2603 pcie-ep@141a0000 { 2604 compatible = "nvidia,tegra194-pcie-ep"; 2605 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2606 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2607 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2608 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2609 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2610 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2611 2612 status = "disabled"; 2613 2614 num-lanes = <8>; 2615 num-ib-windows = <2>; 2616 num-ob-windows = <8>; 2617 2618 pinctrl-names = "default"; 2619 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2620 2621 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2622 clock-names = "core"; 2623 2624 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2625 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2626 reset-names = "apb", "core"; 2627 2628 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2629 interrupt-names = "intr"; 2630 2631 nvidia,bpmp = <&bpmp 5>; 2632 2633 nvidia,aspm-cmrt-us = <60>; 2634 nvidia,aspm-pwr-on-t-us = <20>; 2635 nvidia,aspm-l0s-entrance-latency-us = <3>; 2636 2637 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2638 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2639 interconnect-names = "dma-mem", "write"; 2640 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2641 iommu-map-mask = <0x0>; 2642 dma-coherent; 2643 }; 2644 2645 sram@40000000 { 2646 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2647 reg = <0x0 0x40000000 0x0 0x50000>; 2648 #address-cells = <1>; 2649 #size-cells = <1>; 2650 ranges = <0x0 0x0 0x40000000 0x50000>; 2651 2652 cpu_bpmp_tx: sram@4e000 { 2653 reg = <0x4e000 0x1000>; 2654 label = "cpu-bpmp-tx"; 2655 pool; 2656 }; 2657 2658 cpu_bpmp_rx: sram@4f000 { 2659 reg = <0x4f000 0x1000>; 2660 label = "cpu-bpmp-rx"; 2661 pool; 2662 }; 2663 }; 2664 2665 bpmp: bpmp { 2666 compatible = "nvidia,tegra186-bpmp"; 2667 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2668 TEGRA_HSP_DB_MASTER_BPMP>; 2669 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2670 #clock-cells = <1>; 2671 #reset-cells = <1>; 2672 #power-domain-cells = <1>; 2673 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2674 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2675 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2676 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2677 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2678 iommus = <&smmu TEGRA194_SID_BPMP>; 2679 2680 bpmp_i2c: i2c { 2681 compatible = "nvidia,tegra186-bpmp-i2c"; 2682 nvidia,bpmp-bus-id = <5>; 2683 #address-cells = <1>; 2684 #size-cells = <0>; 2685 }; 2686 2687 bpmp_thermal: thermal { 2688 compatible = "nvidia,tegra186-bpmp-thermal"; 2689 #thermal-sensor-cells = <1>; 2690 }; 2691 }; 2692 2693 cpus { 2694 compatible = "nvidia,tegra194-ccplex"; 2695 nvidia,bpmp = <&bpmp>; 2696 #address-cells = <1>; 2697 #size-cells = <0>; 2698 2699 cpu0_0: cpu@0 { 2700 compatible = "nvidia,tegra194-carmel"; 2701 device_type = "cpu"; 2702 reg = <0x000>; 2703 enable-method = "psci"; 2704 i-cache-size = <131072>; 2705 i-cache-line-size = <64>; 2706 i-cache-sets = <512>; 2707 d-cache-size = <65536>; 2708 d-cache-line-size = <64>; 2709 d-cache-sets = <256>; 2710 next-level-cache = <&l2c_0>; 2711 }; 2712 2713 cpu0_1: cpu@1 { 2714 compatible = "nvidia,tegra194-carmel"; 2715 device_type = "cpu"; 2716 reg = <0x001>; 2717 enable-method = "psci"; 2718 i-cache-size = <131072>; 2719 i-cache-line-size = <64>; 2720 i-cache-sets = <512>; 2721 d-cache-size = <65536>; 2722 d-cache-line-size = <64>; 2723 d-cache-sets = <256>; 2724 next-level-cache = <&l2c_0>; 2725 }; 2726 2727 cpu1_0: cpu@100 { 2728 compatible = "nvidia,tegra194-carmel"; 2729 device_type = "cpu"; 2730 reg = <0x100>; 2731 enable-method = "psci"; 2732 i-cache-size = <131072>; 2733 i-cache-line-size = <64>; 2734 i-cache-sets = <512>; 2735 d-cache-size = <65536>; 2736 d-cache-line-size = <64>; 2737 d-cache-sets = <256>; 2738 next-level-cache = <&l2c_1>; 2739 }; 2740 2741 cpu1_1: cpu@101 { 2742 compatible = "nvidia,tegra194-carmel"; 2743 device_type = "cpu"; 2744 reg = <0x101>; 2745 enable-method = "psci"; 2746 i-cache-size = <131072>; 2747 i-cache-line-size = <64>; 2748 i-cache-sets = <512>; 2749 d-cache-size = <65536>; 2750 d-cache-line-size = <64>; 2751 d-cache-sets = <256>; 2752 next-level-cache = <&l2c_1>; 2753 }; 2754 2755 cpu2_0: cpu@200 { 2756 compatible = "nvidia,tegra194-carmel"; 2757 device_type = "cpu"; 2758 reg = <0x200>; 2759 enable-method = "psci"; 2760 i-cache-size = <131072>; 2761 i-cache-line-size = <64>; 2762 i-cache-sets = <512>; 2763 d-cache-size = <65536>; 2764 d-cache-line-size = <64>; 2765 d-cache-sets = <256>; 2766 next-level-cache = <&l2c_2>; 2767 }; 2768 2769 cpu2_1: cpu@201 { 2770 compatible = "nvidia,tegra194-carmel"; 2771 device_type = "cpu"; 2772 reg = <0x201>; 2773 enable-method = "psci"; 2774 i-cache-size = <131072>; 2775 i-cache-line-size = <64>; 2776 i-cache-sets = <512>; 2777 d-cache-size = <65536>; 2778 d-cache-line-size = <64>; 2779 d-cache-sets = <256>; 2780 next-level-cache = <&l2c_2>; 2781 }; 2782 2783 cpu3_0: cpu@300 { 2784 compatible = "nvidia,tegra194-carmel"; 2785 device_type = "cpu"; 2786 reg = <0x300>; 2787 enable-method = "psci"; 2788 i-cache-size = <131072>; 2789 i-cache-line-size = <64>; 2790 i-cache-sets = <512>; 2791 d-cache-size = <65536>; 2792 d-cache-line-size = <64>; 2793 d-cache-sets = <256>; 2794 next-level-cache = <&l2c_3>; 2795 }; 2796 2797 cpu3_1: cpu@301 { 2798 compatible = "nvidia,tegra194-carmel"; 2799 device_type = "cpu"; 2800 reg = <0x301>; 2801 enable-method = "psci"; 2802 i-cache-size = <131072>; 2803 i-cache-line-size = <64>; 2804 i-cache-sets = <512>; 2805 d-cache-size = <65536>; 2806 d-cache-line-size = <64>; 2807 d-cache-sets = <256>; 2808 next-level-cache = <&l2c_3>; 2809 }; 2810 2811 cpu-map { 2812 cluster0 { 2813 core0 { 2814 cpu = <&cpu0_0>; 2815 }; 2816 2817 core1 { 2818 cpu = <&cpu0_1>; 2819 }; 2820 }; 2821 2822 cluster1 { 2823 core0 { 2824 cpu = <&cpu1_0>; 2825 }; 2826 2827 core1 { 2828 cpu = <&cpu1_1>; 2829 }; 2830 }; 2831 2832 cluster2 { 2833 core0 { 2834 cpu = <&cpu2_0>; 2835 }; 2836 2837 core1 { 2838 cpu = <&cpu2_1>; 2839 }; 2840 }; 2841 2842 cluster3 { 2843 core0 { 2844 cpu = <&cpu3_0>; 2845 }; 2846 2847 core1 { 2848 cpu = <&cpu3_1>; 2849 }; 2850 }; 2851 }; 2852 2853 l2c_0: l2-cache0 { 2854 cache-size = <2097152>; 2855 cache-line-size = <64>; 2856 cache-sets = <2048>; 2857 next-level-cache = <&l3c>; 2858 }; 2859 2860 l2c_1: l2-cache1 { 2861 cache-size = <2097152>; 2862 cache-line-size = <64>; 2863 cache-sets = <2048>; 2864 next-level-cache = <&l3c>; 2865 }; 2866 2867 l2c_2: l2-cache2 { 2868 cache-size = <2097152>; 2869 cache-line-size = <64>; 2870 cache-sets = <2048>; 2871 next-level-cache = <&l3c>; 2872 }; 2873 2874 l2c_3: l2-cache3 { 2875 cache-size = <2097152>; 2876 cache-line-size = <64>; 2877 cache-sets = <2048>; 2878 next-level-cache = <&l3c>; 2879 }; 2880 2881 l3c: l3-cache { 2882 cache-size = <4194304>; 2883 cache-line-size = <64>; 2884 cache-sets = <4096>; 2885 }; 2886 }; 2887 2888 pmu { 2889 compatible = "arm,armv8-pmuv3"; 2890 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2891 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2892 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2893 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 2894 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 2895 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 2896 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 2897 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 2898 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 2899 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 2900 }; 2901 2902 psci { 2903 compatible = "arm,psci-1.0"; 2904 status = "okay"; 2905 method = "smc"; 2906 }; 2907 2908 sound { 2909 status = "disabled"; 2910 2911 clocks = <&bpmp TEGRA194_CLK_PLLA>, 2912 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2913 clock-names = "pll_a", "plla_out0"; 2914 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 2915 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 2916 <&bpmp TEGRA194_CLK_AUD_MCLK>; 2917 assigned-clock-parents = <0>, 2918 <&bpmp TEGRA194_CLK_PLLA>, 2919 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2920 /* 2921 * PLLA supports dynamic ramp. Below initial rate is chosen 2922 * for this to work and oscillate between base rates required 2923 * for 8x and 11.025x sample rate streams. 2924 */ 2925 assigned-clock-rates = <258000000>; 2926 }; 2927 2928 tcu: serial { 2929 compatible = "nvidia,tegra194-tcu"; 2930 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2931 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2932 mbox-names = "rx", "tx"; 2933 }; 2934 2935 thermal-zones { 2936 cpu-thermal { 2937 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2938 status = "disabled"; 2939 }; 2940 2941 gpu-thermal { 2942 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2943 status = "disabled"; 2944 }; 2945 2946 aux-thermal { 2947 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2948 status = "disabled"; 2949 }; 2950 2951 pllx-thermal { 2952 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2953 status = "disabled"; 2954 }; 2955 2956 ao-thermal { 2957 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 2958 status = "disabled"; 2959 }; 2960 2961 tj-thermal { 2962 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2963 status = "disabled"; 2964 }; 2965 }; 2966 2967 timer { 2968 compatible = "arm,armv8-timer"; 2969 interrupts = <GIC_PPI 13 2970 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2971 <GIC_PPI 14 2972 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2973 <GIC_PPI 11 2974 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2975 <GIC_PPI 10 2976 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2977 interrupt-parent = <&gic>; 2978 always-on; 2979 }; 2980}; 2981