1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/reset/tegra194-reset.h> 9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10#include <dt-bindings/memory/tegra194-mc.h> 11 12/ { 13 compatible = "nvidia,tegra194"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* control backbone */ 19 bus@0 { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra194-misc"; 27 reg = <0x00100000 0xf000>, 28 <0x0010f000 0x1000>; 29 }; 30 31 gpio: gpio@2200000 { 32 compatible = "nvidia,tegra194-gpio"; 33 reg-names = "security", "gpio"; 34 reg = <0x2200000 0x10000>, 35 <0x2210000 0x10000>; 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 84 #interrupt-cells = <2>; 85 interrupt-controller; 86 #gpio-cells = <2>; 87 gpio-controller; 88 }; 89 90 ethernet@2490000 { 91 compatible = "nvidia,tegra194-eqos", 92 "nvidia,tegra186-eqos", 93 "snps,dwc-qos-ethernet-4.10"; 94 reg = <0x02490000 0x10000>; 95 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 96 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 97 <&bpmp TEGRA194_CLK_EQOS_AXI>, 98 <&bpmp TEGRA194_CLK_EQOS_RX>, 99 <&bpmp TEGRA194_CLK_EQOS_TX>, 100 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 101 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 102 resets = <&bpmp TEGRA194_RESET_EQOS>; 103 reset-names = "eqos"; 104 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 105 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 106 interconnect-names = "dma-mem", "write"; 107 iommus = <&smmu TEGRA194_SID_EQOS>; 108 status = "disabled"; 109 110 snps,write-requests = <1>; 111 snps,read-requests = <3>; 112 snps,burst-map = <0x7>; 113 snps,txpbl = <16>; 114 snps,rxpbl = <8>; 115 }; 116 117 aconnect@2900000 { 118 compatible = "nvidia,tegra194-aconnect", 119 "nvidia,tegra210-aconnect"; 120 clocks = <&bpmp TEGRA194_CLK_APE>, 121 <&bpmp TEGRA194_CLK_APB2APE>; 122 clock-names = "ape", "apb2ape"; 123 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 ranges = <0x02900000 0x02900000 0x200000>; 127 status = "disabled"; 128 129 adma: dma-controller@2930000 { 130 compatible = "nvidia,tegra194-adma", 131 "nvidia,tegra186-adma"; 132 reg = <0x02930000 0x20000>; 133 interrupt-parent = <&agic>; 134 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 166 #dma-cells = <1>; 167 clocks = <&bpmp TEGRA194_CLK_AHUB>; 168 clock-names = "d_audio"; 169 status = "disabled"; 170 }; 171 172 agic: interrupt-controller@2a40000 { 173 compatible = "nvidia,tegra194-agic", 174 "nvidia,tegra210-agic"; 175 #interrupt-cells = <3>; 176 interrupt-controller; 177 reg = <0x02a41000 0x1000>, 178 <0x02a42000 0x2000>; 179 interrupts = <GIC_SPI 145 180 (GIC_CPU_MASK_SIMPLE(4) | 181 IRQ_TYPE_LEVEL_HIGH)>; 182 clocks = <&bpmp TEGRA194_CLK_APE>; 183 clock-names = "clk"; 184 status = "disabled"; 185 }; 186 187 tegra_ahub: ahub@2900800 { 188 compatible = "nvidia,tegra194-ahub", 189 "nvidia,tegra186-ahub"; 190 reg = <0x02900800 0x800>; 191 clocks = <&bpmp TEGRA194_CLK_AHUB>; 192 clock-names = "ahub"; 193 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 194 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 ranges = <0x02900800 0x02900800 0x11800>; 198 status = "disabled"; 199 200 tegra_admaif: admaif@290f000 { 201 compatible = "nvidia,tegra194-admaif", 202 "nvidia,tegra186-admaif"; 203 reg = <0x0290f000 0x1000>; 204 dmas = <&adma 1>, <&adma 1>, 205 <&adma 2>, <&adma 2>, 206 <&adma 3>, <&adma 3>, 207 <&adma 4>, <&adma 4>, 208 <&adma 5>, <&adma 5>, 209 <&adma 6>, <&adma 6>, 210 <&adma 7>, <&adma 7>, 211 <&adma 8>, <&adma 8>, 212 <&adma 9>, <&adma 9>, 213 <&adma 10>, <&adma 10>, 214 <&adma 11>, <&adma 11>, 215 <&adma 12>, <&adma 12>, 216 <&adma 13>, <&adma 13>, 217 <&adma 14>, <&adma 14>, 218 <&adma 15>, <&adma 15>, 219 <&adma 16>, <&adma 16>, 220 <&adma 17>, <&adma 17>, 221 <&adma 18>, <&adma 18>, 222 <&adma 19>, <&adma 19>, 223 <&adma 20>, <&adma 20>; 224 dma-names = "rx1", "tx1", 225 "rx2", "tx2", 226 "rx3", "tx3", 227 "rx4", "tx4", 228 "rx5", "tx5", 229 "rx6", "tx6", 230 "rx7", "tx7", 231 "rx8", "tx8", 232 "rx9", "tx9", 233 "rx10", "tx10", 234 "rx11", "tx11", 235 "rx12", "tx12", 236 "rx13", "tx13", 237 "rx14", "tx14", 238 "rx15", "tx15", 239 "rx16", "tx16", 240 "rx17", "tx17", 241 "rx18", "tx18", 242 "rx19", "tx19", 243 "rx20", "tx20"; 244 status = "disabled"; 245 }; 246 247 tegra_i2s1: i2s@2901000 { 248 compatible = "nvidia,tegra194-i2s", 249 "nvidia,tegra210-i2s"; 250 reg = <0x2901000 0x100>; 251 clocks = <&bpmp TEGRA194_CLK_I2S1>, 252 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 253 clock-names = "i2s", "sync_input"; 254 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 255 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 256 assigned-clock-rates = <1536000>; 257 sound-name-prefix = "I2S1"; 258 status = "disabled"; 259 }; 260 261 tegra_i2s2: i2s@2901100 { 262 compatible = "nvidia,tegra194-i2s", 263 "nvidia,tegra210-i2s"; 264 reg = <0x2901100 0x100>; 265 clocks = <&bpmp TEGRA194_CLK_I2S2>, 266 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 267 clock-names = "i2s", "sync_input"; 268 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 269 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 270 assigned-clock-rates = <1536000>; 271 sound-name-prefix = "I2S2"; 272 status = "disabled"; 273 }; 274 275 tegra_i2s3: i2s@2901200 { 276 compatible = "nvidia,tegra194-i2s", 277 "nvidia,tegra210-i2s"; 278 reg = <0x2901200 0x100>; 279 clocks = <&bpmp TEGRA194_CLK_I2S3>, 280 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 281 clock-names = "i2s", "sync_input"; 282 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 283 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 284 assigned-clock-rates = <1536000>; 285 sound-name-prefix = "I2S3"; 286 status = "disabled"; 287 }; 288 289 tegra_i2s4: i2s@2901300 { 290 compatible = "nvidia,tegra194-i2s", 291 "nvidia,tegra210-i2s"; 292 reg = <0x2901300 0x100>; 293 clocks = <&bpmp TEGRA194_CLK_I2S4>, 294 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 295 clock-names = "i2s", "sync_input"; 296 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 297 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 298 assigned-clock-rates = <1536000>; 299 sound-name-prefix = "I2S4"; 300 status = "disabled"; 301 }; 302 303 tegra_i2s5: i2s@2901400 { 304 compatible = "nvidia,tegra194-i2s", 305 "nvidia,tegra210-i2s"; 306 reg = <0x2901400 0x100>; 307 clocks = <&bpmp TEGRA194_CLK_I2S5>, 308 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 309 clock-names = "i2s", "sync_input"; 310 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 311 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 312 assigned-clock-rates = <1536000>; 313 sound-name-prefix = "I2S5"; 314 status = "disabled"; 315 }; 316 317 tegra_i2s6: i2s@2901500 { 318 compatible = "nvidia,tegra194-i2s", 319 "nvidia,tegra210-i2s"; 320 reg = <0x2901500 0x100>; 321 clocks = <&bpmp TEGRA194_CLK_I2S6>, 322 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 323 clock-names = "i2s", "sync_input"; 324 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 325 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 326 assigned-clock-rates = <1536000>; 327 sound-name-prefix = "I2S6"; 328 status = "disabled"; 329 }; 330 331 tegra_dmic1: dmic@2904000 { 332 compatible = "nvidia,tegra194-dmic", 333 "nvidia,tegra210-dmic"; 334 reg = <0x2904000 0x100>; 335 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 336 clock-names = "dmic"; 337 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 338 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 339 assigned-clock-rates = <3072000>; 340 sound-name-prefix = "DMIC1"; 341 status = "disabled"; 342 }; 343 344 tegra_dmic2: dmic@2904100 { 345 compatible = "nvidia,tegra194-dmic", 346 "nvidia,tegra210-dmic"; 347 reg = <0x2904100 0x100>; 348 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 349 clock-names = "dmic"; 350 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 351 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 352 assigned-clock-rates = <3072000>; 353 sound-name-prefix = "DMIC2"; 354 status = "disabled"; 355 }; 356 357 tegra_dmic3: dmic@2904200 { 358 compatible = "nvidia,tegra194-dmic", 359 "nvidia,tegra210-dmic"; 360 reg = <0x2904200 0x100>; 361 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 362 clock-names = "dmic"; 363 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 364 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 365 assigned-clock-rates = <3072000>; 366 sound-name-prefix = "DMIC3"; 367 status = "disabled"; 368 }; 369 370 tegra_dmic4: dmic@2904300 { 371 compatible = "nvidia,tegra194-dmic", 372 "nvidia,tegra210-dmic"; 373 reg = <0x2904300 0x100>; 374 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 375 clock-names = "dmic"; 376 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 377 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 378 assigned-clock-rates = <3072000>; 379 sound-name-prefix = "DMIC4"; 380 status = "disabled"; 381 }; 382 383 tegra_dspk1: dspk@2905000 { 384 compatible = "nvidia,tegra194-dspk", 385 "nvidia,tegra186-dspk"; 386 reg = <0x2905000 0x100>; 387 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 388 clock-names = "dspk"; 389 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 390 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 391 assigned-clock-rates = <12288000>; 392 sound-name-prefix = "DSPK1"; 393 status = "disabled"; 394 }; 395 396 tegra_dspk2: dspk@2905100 { 397 compatible = "nvidia,tegra194-dspk", 398 "nvidia,tegra186-dspk"; 399 reg = <0x2905100 0x100>; 400 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 401 clock-names = "dspk"; 402 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 403 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 404 assigned-clock-rates = <12288000>; 405 sound-name-prefix = "DSPK2"; 406 status = "disabled"; 407 }; 408 409 tegra_sfc1: sfc@2902000 { 410 compatible = "nvidia,tegra194-sfc", 411 "nvidia,tegra210-sfc"; 412 reg = <0x2902000 0x200>; 413 sound-name-prefix = "SFC1"; 414 status = "disabled"; 415 }; 416 417 tegra_sfc2: sfc@2902200 { 418 compatible = "nvidia,tegra194-sfc", 419 "nvidia,tegra210-sfc"; 420 reg = <0x2902200 0x200>; 421 sound-name-prefix = "SFC2"; 422 status = "disabled"; 423 }; 424 425 tegra_sfc3: sfc@2902400 { 426 compatible = "nvidia,tegra194-sfc", 427 "nvidia,tegra210-sfc"; 428 reg = <0x2902400 0x200>; 429 sound-name-prefix = "SFC3"; 430 status = "disabled"; 431 }; 432 433 tegra_sfc4: sfc@2902600 { 434 compatible = "nvidia,tegra194-sfc", 435 "nvidia,tegra210-sfc"; 436 reg = <0x2902600 0x200>; 437 sound-name-prefix = "SFC4"; 438 status = "disabled"; 439 }; 440 441 tegra_mvc1: mvc@290a000 { 442 compatible = "nvidia,tegra194-mvc", 443 "nvidia,tegra210-mvc"; 444 reg = <0x290a000 0x200>; 445 sound-name-prefix = "MVC1"; 446 status = "disabled"; 447 }; 448 449 tegra_mvc2: mvc@290a200 { 450 compatible = "nvidia,tegra194-mvc", 451 "nvidia,tegra210-mvc"; 452 reg = <0x290a200 0x200>; 453 sound-name-prefix = "MVC2"; 454 status = "disabled"; 455 }; 456 457 tegra_amx1: amx@2903000 { 458 compatible = "nvidia,tegra194-amx"; 459 reg = <0x2903000 0x100>; 460 sound-name-prefix = "AMX1"; 461 status = "disabled"; 462 }; 463 464 tegra_amx2: amx@2903100 { 465 compatible = "nvidia,tegra194-amx"; 466 reg = <0x2903100 0x100>; 467 sound-name-prefix = "AMX2"; 468 status = "disabled"; 469 }; 470 471 tegra_amx3: amx@2903200 { 472 compatible = "nvidia,tegra194-amx"; 473 reg = <0x2903200 0x100>; 474 sound-name-prefix = "AMX3"; 475 status = "disabled"; 476 }; 477 478 tegra_amx4: amx@2903300 { 479 compatible = "nvidia,tegra194-amx"; 480 reg = <0x2903300 0x100>; 481 sound-name-prefix = "AMX4"; 482 status = "disabled"; 483 }; 484 485 tegra_adx1: adx@2903800 { 486 compatible = "nvidia,tegra194-adx", 487 "nvidia,tegra210-adx"; 488 reg = <0x2903800 0x100>; 489 sound-name-prefix = "ADX1"; 490 status = "disabled"; 491 }; 492 493 tegra_adx2: adx@2903900 { 494 compatible = "nvidia,tegra194-adx", 495 "nvidia,tegra210-adx"; 496 reg = <0x2903900 0x100>; 497 sound-name-prefix = "ADX2"; 498 status = "disabled"; 499 }; 500 501 tegra_adx3: adx@2903a00 { 502 compatible = "nvidia,tegra194-adx", 503 "nvidia,tegra210-adx"; 504 reg = <0x2903a00 0x100>; 505 sound-name-prefix = "ADX3"; 506 status = "disabled"; 507 }; 508 509 tegra_adx4: adx@2903b00 { 510 compatible = "nvidia,tegra194-adx", 511 "nvidia,tegra210-adx"; 512 reg = <0x2903b00 0x100>; 513 sound-name-prefix = "ADX4"; 514 status = "disabled"; 515 }; 516 517 tegra_amixer: amixer@290bb00 { 518 compatible = "nvidia,tegra194-amixer", 519 "nvidia,tegra210-amixer"; 520 reg = <0x290bb00 0x800>; 521 sound-name-prefix = "MIXER1"; 522 status = "disabled"; 523 }; 524 }; 525 }; 526 527 pinmux: pinmux@2430000 { 528 compatible = "nvidia,tegra194-pinmux"; 529 reg = <0x2430000 0x17000>, 530 <0xc300000 0x4000>; 531 532 status = "okay"; 533 534 pex_rst_c5_out_state: pex_rst_c5_out { 535 pex_rst { 536 nvidia,pins = "pex_l5_rst_n_pgg1"; 537 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 538 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 539 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 540 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 541 nvidia,tristate = <TEGRA_PIN_DISABLE>; 542 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 543 }; 544 }; 545 546 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 547 clkreq { 548 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 549 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 550 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 551 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 552 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 553 nvidia,tristate = <TEGRA_PIN_DISABLE>; 554 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 555 }; 556 }; 557 }; 558 559 mc: memory-controller@2c00000 { 560 compatible = "nvidia,tegra194-mc"; 561 reg = <0x02c00000 0x100000>, 562 <0x02b80000 0x040000>, 563 <0x01700000 0x100000>; 564 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 565 #interconnect-cells = <1>; 566 status = "disabled"; 567 568 #address-cells = <2>; 569 #size-cells = <2>; 570 571 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 572 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 573 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 574 575 /* 576 * Bit 39 of addresses passing through the memory 577 * controller selects the XBAR format used when memory 578 * is accessed. This is used to transparently access 579 * memory in the XBAR format used by the discrete GPU 580 * (bit 39 set) or Tegra (bit 39 clear). 581 * 582 * As a consequence, the operating system must ensure 583 * that bit 39 is never used implicitly, for example 584 * via an I/O virtual address mapping of an IOMMU. If 585 * devices require access to the XBAR switch, their 586 * drivers must set this bit explicitly. 587 * 588 * Limit the DMA range for memory clients to [38:0]. 589 */ 590 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 591 592 emc: external-memory-controller@2c60000 { 593 compatible = "nvidia,tegra194-emc"; 594 reg = <0x0 0x02c60000 0x0 0x90000>, 595 <0x0 0x01780000 0x0 0x80000>; 596 clocks = <&bpmp TEGRA194_CLK_EMC>; 597 clock-names = "emc"; 598 599 #interconnect-cells = <0>; 600 601 nvidia,bpmp = <&bpmp>; 602 }; 603 }; 604 605 uarta: serial@3100000 { 606 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 607 reg = <0x03100000 0x40>; 608 reg-shift = <2>; 609 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&bpmp TEGRA194_CLK_UARTA>; 611 clock-names = "serial"; 612 resets = <&bpmp TEGRA194_RESET_UARTA>; 613 reset-names = "serial"; 614 status = "disabled"; 615 }; 616 617 uartb: serial@3110000 { 618 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 619 reg = <0x03110000 0x40>; 620 reg-shift = <2>; 621 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&bpmp TEGRA194_CLK_UARTB>; 623 clock-names = "serial"; 624 resets = <&bpmp TEGRA194_RESET_UARTB>; 625 reset-names = "serial"; 626 status = "disabled"; 627 }; 628 629 uartd: serial@3130000 { 630 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 631 reg = <0x03130000 0x40>; 632 reg-shift = <2>; 633 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&bpmp TEGRA194_CLK_UARTD>; 635 clock-names = "serial"; 636 resets = <&bpmp TEGRA194_RESET_UARTD>; 637 reset-names = "serial"; 638 status = "disabled"; 639 }; 640 641 uarte: serial@3140000 { 642 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 643 reg = <0x03140000 0x40>; 644 reg-shift = <2>; 645 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&bpmp TEGRA194_CLK_UARTE>; 647 clock-names = "serial"; 648 resets = <&bpmp TEGRA194_RESET_UARTE>; 649 reset-names = "serial"; 650 status = "disabled"; 651 }; 652 653 uartf: serial@3150000 { 654 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 655 reg = <0x03150000 0x40>; 656 reg-shift = <2>; 657 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&bpmp TEGRA194_CLK_UARTF>; 659 clock-names = "serial"; 660 resets = <&bpmp TEGRA194_RESET_UARTF>; 661 reset-names = "serial"; 662 status = "disabled"; 663 }; 664 665 gen1_i2c: i2c@3160000 { 666 compatible = "nvidia,tegra194-i2c"; 667 reg = <0x03160000 0x10000>; 668 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 clocks = <&bpmp TEGRA194_CLK_I2C1>; 672 clock-names = "div-clk"; 673 resets = <&bpmp TEGRA194_RESET_I2C1>; 674 reset-names = "i2c"; 675 status = "disabled"; 676 }; 677 678 uarth: serial@3170000 { 679 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 680 reg = <0x03170000 0x40>; 681 reg-shift = <2>; 682 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&bpmp TEGRA194_CLK_UARTH>; 684 clock-names = "serial"; 685 resets = <&bpmp TEGRA194_RESET_UARTH>; 686 reset-names = "serial"; 687 status = "disabled"; 688 }; 689 690 cam_i2c: i2c@3180000 { 691 compatible = "nvidia,tegra194-i2c"; 692 reg = <0x03180000 0x10000>; 693 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 clocks = <&bpmp TEGRA194_CLK_I2C3>; 697 clock-names = "div-clk"; 698 resets = <&bpmp TEGRA194_RESET_I2C3>; 699 reset-names = "i2c"; 700 status = "disabled"; 701 }; 702 703 /* shares pads with dpaux1 */ 704 dp_aux_ch1_i2c: i2c@3190000 { 705 compatible = "nvidia,tegra194-i2c"; 706 reg = <0x03190000 0x10000>; 707 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 clocks = <&bpmp TEGRA194_CLK_I2C4>; 711 clock-names = "div-clk"; 712 resets = <&bpmp TEGRA194_RESET_I2C4>; 713 reset-names = "i2c"; 714 pinctrl-0 = <&state_dpaux1_i2c>; 715 pinctrl-1 = <&state_dpaux1_off>; 716 pinctrl-names = "default", "idle"; 717 status = "disabled"; 718 }; 719 720 /* shares pads with dpaux0 */ 721 dp_aux_ch0_i2c: i2c@31b0000 { 722 compatible = "nvidia,tegra194-i2c"; 723 reg = <0x031b0000 0x10000>; 724 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 clocks = <&bpmp TEGRA194_CLK_I2C6>; 728 clock-names = "div-clk"; 729 resets = <&bpmp TEGRA194_RESET_I2C6>; 730 reset-names = "i2c"; 731 pinctrl-0 = <&state_dpaux0_i2c>; 732 pinctrl-1 = <&state_dpaux0_off>; 733 pinctrl-names = "default", "idle"; 734 status = "disabled"; 735 }; 736 737 /* shares pads with dpaux2 */ 738 dp_aux_ch2_i2c: i2c@31c0000 { 739 compatible = "nvidia,tegra194-i2c"; 740 reg = <0x031c0000 0x10000>; 741 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 clocks = <&bpmp TEGRA194_CLK_I2C7>; 745 clock-names = "div-clk"; 746 resets = <&bpmp TEGRA194_RESET_I2C7>; 747 reset-names = "i2c"; 748 pinctrl-0 = <&state_dpaux2_i2c>; 749 pinctrl-1 = <&state_dpaux2_off>; 750 pinctrl-names = "default", "idle"; 751 status = "disabled"; 752 }; 753 754 /* shares pads with dpaux3 */ 755 dp_aux_ch3_i2c: i2c@31e0000 { 756 compatible = "nvidia,tegra194-i2c"; 757 reg = <0x031e0000 0x10000>; 758 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 clocks = <&bpmp TEGRA194_CLK_I2C9>; 762 clock-names = "div-clk"; 763 resets = <&bpmp TEGRA194_RESET_I2C9>; 764 reset-names = "i2c"; 765 pinctrl-0 = <&state_dpaux3_i2c>; 766 pinctrl-1 = <&state_dpaux3_off>; 767 pinctrl-names = "default", "idle"; 768 status = "disabled"; 769 }; 770 771 spi@3270000 { 772 compatible = "nvidia,tegra194-qspi"; 773 reg = <0x3270000 0x1000>; 774 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 775 #address-cells = <1>; 776 #size-cells = <0>; 777 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 778 <&bpmp TEGRA194_CLK_QSPI0_PM>; 779 clock-names = "qspi", "qspi_out"; 780 resets = <&bpmp TEGRA194_RESET_QSPI0>; 781 reset-names = "qspi"; 782 status = "disabled"; 783 }; 784 785 spi@3300000 { 786 compatible = "nvidia,tegra194-qspi"; 787 reg = <0x3300000 0x1000>; 788 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 792 <&bpmp TEGRA194_CLK_QSPI1_PM>; 793 clock-names = "qspi", "qspi_out"; 794 resets = <&bpmp TEGRA194_RESET_QSPI1>; 795 reset-names = "qspi"; 796 status = "disabled"; 797 }; 798 799 pwm1: pwm@3280000 { 800 compatible = "nvidia,tegra194-pwm", 801 "nvidia,tegra186-pwm"; 802 reg = <0x3280000 0x10000>; 803 clocks = <&bpmp TEGRA194_CLK_PWM1>; 804 clock-names = "pwm"; 805 resets = <&bpmp TEGRA194_RESET_PWM1>; 806 reset-names = "pwm"; 807 status = "disabled"; 808 #pwm-cells = <2>; 809 }; 810 811 pwm2: pwm@3290000 { 812 compatible = "nvidia,tegra194-pwm", 813 "nvidia,tegra186-pwm"; 814 reg = <0x3290000 0x10000>; 815 clocks = <&bpmp TEGRA194_CLK_PWM2>; 816 clock-names = "pwm"; 817 resets = <&bpmp TEGRA194_RESET_PWM2>; 818 reset-names = "pwm"; 819 status = "disabled"; 820 #pwm-cells = <2>; 821 }; 822 823 pwm3: pwm@32a0000 { 824 compatible = "nvidia,tegra194-pwm", 825 "nvidia,tegra186-pwm"; 826 reg = <0x32a0000 0x10000>; 827 clocks = <&bpmp TEGRA194_CLK_PWM3>; 828 clock-names = "pwm"; 829 resets = <&bpmp TEGRA194_RESET_PWM3>; 830 reset-names = "pwm"; 831 status = "disabled"; 832 #pwm-cells = <2>; 833 }; 834 835 pwm5: pwm@32c0000 { 836 compatible = "nvidia,tegra194-pwm", 837 "nvidia,tegra186-pwm"; 838 reg = <0x32c0000 0x10000>; 839 clocks = <&bpmp TEGRA194_CLK_PWM5>; 840 clock-names = "pwm"; 841 resets = <&bpmp TEGRA194_RESET_PWM5>; 842 reset-names = "pwm"; 843 status = "disabled"; 844 #pwm-cells = <2>; 845 }; 846 847 pwm6: pwm@32d0000 { 848 compatible = "nvidia,tegra194-pwm", 849 "nvidia,tegra186-pwm"; 850 reg = <0x32d0000 0x10000>; 851 clocks = <&bpmp TEGRA194_CLK_PWM6>; 852 clock-names = "pwm"; 853 resets = <&bpmp TEGRA194_RESET_PWM6>; 854 reset-names = "pwm"; 855 status = "disabled"; 856 #pwm-cells = <2>; 857 }; 858 859 pwm7: pwm@32e0000 { 860 compatible = "nvidia,tegra194-pwm", 861 "nvidia,tegra186-pwm"; 862 reg = <0x32e0000 0x10000>; 863 clocks = <&bpmp TEGRA194_CLK_PWM7>; 864 clock-names = "pwm"; 865 resets = <&bpmp TEGRA194_RESET_PWM7>; 866 reset-names = "pwm"; 867 status = "disabled"; 868 #pwm-cells = <2>; 869 }; 870 871 pwm8: pwm@32f0000 { 872 compatible = "nvidia,tegra194-pwm", 873 "nvidia,tegra186-pwm"; 874 reg = <0x32f0000 0x10000>; 875 clocks = <&bpmp TEGRA194_CLK_PWM8>; 876 clock-names = "pwm"; 877 resets = <&bpmp TEGRA194_RESET_PWM8>; 878 reset-names = "pwm"; 879 status = "disabled"; 880 #pwm-cells = <2>; 881 }; 882 883 sdmmc1: mmc@3400000 { 884 compatible = "nvidia,tegra194-sdhci"; 885 reg = <0x03400000 0x10000>; 886 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 888 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 889 clock-names = "sdhci", "tmclk"; 890 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 891 reset-names = "sdhci"; 892 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 893 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 894 interconnect-names = "dma-mem", "write"; 895 iommus = <&smmu TEGRA194_SID_SDMMC1>; 896 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 897 <0x07>; 898 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 899 <0x07>; 900 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 901 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 902 <0x07>; 903 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 904 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 905 nvidia,default-tap = <0x9>; 906 nvidia,default-trim = <0x5>; 907 status = "disabled"; 908 }; 909 910 sdmmc3: mmc@3440000 { 911 compatible = "nvidia,tegra194-sdhci"; 912 reg = <0x03440000 0x10000>; 913 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 915 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 916 clock-names = "sdhci", "tmclk"; 917 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 918 reset-names = "sdhci"; 919 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 920 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 921 interconnect-names = "dma-mem", "write"; 922 iommus = <&smmu TEGRA194_SID_SDMMC3>; 923 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 924 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 925 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 926 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 927 <0x07>; 928 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 929 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 930 <0x07>; 931 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 932 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 933 nvidia,default-tap = <0x9>; 934 nvidia,default-trim = <0x5>; 935 status = "disabled"; 936 }; 937 938 sdmmc4: mmc@3460000 { 939 compatible = "nvidia,tegra194-sdhci"; 940 reg = <0x03460000 0x10000>; 941 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 942 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 943 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 944 clock-names = "sdhci", "tmclk"; 945 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 946 <&bpmp TEGRA194_CLK_PLLC4>; 947 assigned-clock-parents = 948 <&bpmp TEGRA194_CLK_PLLC4>; 949 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 950 reset-names = "sdhci"; 951 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 952 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 953 interconnect-names = "dma-mem", "write"; 954 iommus = <&smmu TEGRA194_SID_SDMMC4>; 955 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 956 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 957 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 958 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 959 <0x0a>; 960 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 961 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 962 <0x0a>; 963 nvidia,default-tap = <0x8>; 964 nvidia,default-trim = <0x14>; 965 nvidia,dqs-trim = <40>; 966 supports-cqe; 967 status = "disabled"; 968 }; 969 970 hda@3510000 { 971 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 972 reg = <0x3510000 0x10000>; 973 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&bpmp TEGRA194_CLK_HDA>, 975 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 976 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 977 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 978 resets = <&bpmp TEGRA194_RESET_HDA>, 979 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>, 980 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>; 981 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 982 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 983 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 984 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 985 interconnect-names = "dma-mem", "write"; 986 iommus = <&smmu TEGRA194_SID_HDA>; 987 status = "disabled"; 988 }; 989 990 xusb_padctl: padctl@3520000 { 991 compatible = "nvidia,tegra194-xusb-padctl"; 992 reg = <0x03520000 0x1000>, 993 <0x03540000 0x1000>; 994 reg-names = "padctl", "ao"; 995 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 996 997 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 998 reset-names = "padctl"; 999 1000 status = "disabled"; 1001 1002 pads { 1003 usb2 { 1004 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1005 clock-names = "trk"; 1006 1007 lanes { 1008 usb2-0 { 1009 nvidia,function = "xusb"; 1010 status = "disabled"; 1011 #phy-cells = <0>; 1012 }; 1013 1014 usb2-1 { 1015 nvidia,function = "xusb"; 1016 status = "disabled"; 1017 #phy-cells = <0>; 1018 }; 1019 1020 usb2-2 { 1021 nvidia,function = "xusb"; 1022 status = "disabled"; 1023 #phy-cells = <0>; 1024 }; 1025 1026 usb2-3 { 1027 nvidia,function = "xusb"; 1028 status = "disabled"; 1029 #phy-cells = <0>; 1030 }; 1031 }; 1032 }; 1033 1034 usb3 { 1035 lanes { 1036 usb3-0 { 1037 nvidia,function = "xusb"; 1038 status = "disabled"; 1039 #phy-cells = <0>; 1040 }; 1041 1042 usb3-1 { 1043 nvidia,function = "xusb"; 1044 status = "disabled"; 1045 #phy-cells = <0>; 1046 }; 1047 1048 usb3-2 { 1049 nvidia,function = "xusb"; 1050 status = "disabled"; 1051 #phy-cells = <0>; 1052 }; 1053 1054 usb3-3 { 1055 nvidia,function = "xusb"; 1056 status = "disabled"; 1057 #phy-cells = <0>; 1058 }; 1059 }; 1060 }; 1061 }; 1062 1063 ports { 1064 usb2-0 { 1065 status = "disabled"; 1066 }; 1067 1068 usb2-1 { 1069 status = "disabled"; 1070 }; 1071 1072 usb2-2 { 1073 status = "disabled"; 1074 }; 1075 1076 usb2-3 { 1077 status = "disabled"; 1078 }; 1079 1080 usb3-0 { 1081 status = "disabled"; 1082 }; 1083 1084 usb3-1 { 1085 status = "disabled"; 1086 }; 1087 1088 usb3-2 { 1089 status = "disabled"; 1090 }; 1091 1092 usb3-3 { 1093 status = "disabled"; 1094 }; 1095 }; 1096 }; 1097 1098 usb@3550000 { 1099 compatible = "nvidia,tegra194-xudc"; 1100 reg = <0x03550000 0x8000>, 1101 <0x03558000 0x1000>; 1102 reg-names = "base", "fpci"; 1103 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1105 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1106 <&bpmp TEGRA194_CLK_XUSB_SS>, 1107 <&bpmp TEGRA194_CLK_XUSB_FS>; 1108 clock-names = "dev", "ss", "ss_src", "fs_src"; 1109 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1110 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1111 interconnect-names = "dma-mem", "write"; 1112 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1113 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1114 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1115 power-domain-names = "dev", "ss"; 1116 nvidia,xusb-padctl = <&xusb_padctl>; 1117 status = "disabled"; 1118 }; 1119 1120 usb@3610000 { 1121 compatible = "nvidia,tegra194-xusb"; 1122 reg = <0x03610000 0x40000>, 1123 <0x03600000 0x10000>; 1124 reg-names = "hcd", "fpci"; 1125 1126 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1128 1129 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1130 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1131 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1132 <&bpmp TEGRA194_CLK_XUSB_SS>, 1133 <&bpmp TEGRA194_CLK_CLK_M>, 1134 <&bpmp TEGRA194_CLK_XUSB_FS>, 1135 <&bpmp TEGRA194_CLK_UTMIPLL>, 1136 <&bpmp TEGRA194_CLK_CLK_M>, 1137 <&bpmp TEGRA194_CLK_PLLE>; 1138 clock-names = "xusb_host", "xusb_falcon_src", 1139 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1140 "xusb_fs_src", "pll_u_480m", "clk_m", 1141 "pll_e"; 1142 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1143 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1144 interconnect-names = "dma-mem", "write"; 1145 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1146 1147 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1148 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1149 power-domain-names = "xusb_host", "xusb_ss"; 1150 1151 nvidia,xusb-padctl = <&xusb_padctl>; 1152 status = "disabled"; 1153 }; 1154 1155 fuse@3820000 { 1156 compatible = "nvidia,tegra194-efuse"; 1157 reg = <0x03820000 0x10000>; 1158 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1159 clock-names = "fuse"; 1160 }; 1161 1162 gic: interrupt-controller@3881000 { 1163 compatible = "arm,gic-400"; 1164 #interrupt-cells = <3>; 1165 interrupt-controller; 1166 reg = <0x03881000 0x1000>, 1167 <0x03882000 0x2000>, 1168 <0x03884000 0x2000>, 1169 <0x03886000 0x2000>; 1170 interrupts = <GIC_PPI 9 1171 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1172 interrupt-parent = <&gic>; 1173 }; 1174 1175 cec@3960000 { 1176 compatible = "nvidia,tegra194-cec"; 1177 reg = <0x03960000 0x10000>; 1178 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1179 clocks = <&bpmp TEGRA194_CLK_CEC>; 1180 clock-names = "cec"; 1181 status = "disabled"; 1182 }; 1183 1184 hsp_top0: hsp@3c00000 { 1185 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1186 reg = <0x03c00000 0xa0000>; 1187 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1196 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1197 "shared3", "shared4", "shared5", "shared6", 1198 "shared7"; 1199 #mbox-cells = <2>; 1200 }; 1201 1202 p2u_hsio_0: phy@3e10000 { 1203 compatible = "nvidia,tegra194-p2u"; 1204 reg = <0x03e10000 0x10000>; 1205 reg-names = "ctl"; 1206 1207 #phy-cells = <0>; 1208 }; 1209 1210 p2u_hsio_1: phy@3e20000 { 1211 compatible = "nvidia,tegra194-p2u"; 1212 reg = <0x03e20000 0x10000>; 1213 reg-names = "ctl"; 1214 1215 #phy-cells = <0>; 1216 }; 1217 1218 p2u_hsio_2: phy@3e30000 { 1219 compatible = "nvidia,tegra194-p2u"; 1220 reg = <0x03e30000 0x10000>; 1221 reg-names = "ctl"; 1222 1223 #phy-cells = <0>; 1224 }; 1225 1226 p2u_hsio_3: phy@3e40000 { 1227 compatible = "nvidia,tegra194-p2u"; 1228 reg = <0x03e40000 0x10000>; 1229 reg-names = "ctl"; 1230 1231 #phy-cells = <0>; 1232 }; 1233 1234 p2u_hsio_4: phy@3e50000 { 1235 compatible = "nvidia,tegra194-p2u"; 1236 reg = <0x03e50000 0x10000>; 1237 reg-names = "ctl"; 1238 1239 #phy-cells = <0>; 1240 }; 1241 1242 p2u_hsio_5: phy@3e60000 { 1243 compatible = "nvidia,tegra194-p2u"; 1244 reg = <0x03e60000 0x10000>; 1245 reg-names = "ctl"; 1246 1247 #phy-cells = <0>; 1248 }; 1249 1250 p2u_hsio_6: phy@3e70000 { 1251 compatible = "nvidia,tegra194-p2u"; 1252 reg = <0x03e70000 0x10000>; 1253 reg-names = "ctl"; 1254 1255 #phy-cells = <0>; 1256 }; 1257 1258 p2u_hsio_7: phy@3e80000 { 1259 compatible = "nvidia,tegra194-p2u"; 1260 reg = <0x03e80000 0x10000>; 1261 reg-names = "ctl"; 1262 1263 #phy-cells = <0>; 1264 }; 1265 1266 p2u_hsio_8: phy@3e90000 { 1267 compatible = "nvidia,tegra194-p2u"; 1268 reg = <0x03e90000 0x10000>; 1269 reg-names = "ctl"; 1270 1271 #phy-cells = <0>; 1272 }; 1273 1274 p2u_hsio_9: phy@3ea0000 { 1275 compatible = "nvidia,tegra194-p2u"; 1276 reg = <0x03ea0000 0x10000>; 1277 reg-names = "ctl"; 1278 1279 #phy-cells = <0>; 1280 }; 1281 1282 p2u_nvhs_0: phy@3eb0000 { 1283 compatible = "nvidia,tegra194-p2u"; 1284 reg = <0x03eb0000 0x10000>; 1285 reg-names = "ctl"; 1286 1287 #phy-cells = <0>; 1288 }; 1289 1290 p2u_nvhs_1: phy@3ec0000 { 1291 compatible = "nvidia,tegra194-p2u"; 1292 reg = <0x03ec0000 0x10000>; 1293 reg-names = "ctl"; 1294 1295 #phy-cells = <0>; 1296 }; 1297 1298 p2u_nvhs_2: phy@3ed0000 { 1299 compatible = "nvidia,tegra194-p2u"; 1300 reg = <0x03ed0000 0x10000>; 1301 reg-names = "ctl"; 1302 1303 #phy-cells = <0>; 1304 }; 1305 1306 p2u_nvhs_3: phy@3ee0000 { 1307 compatible = "nvidia,tegra194-p2u"; 1308 reg = <0x03ee0000 0x10000>; 1309 reg-names = "ctl"; 1310 1311 #phy-cells = <0>; 1312 }; 1313 1314 p2u_nvhs_4: phy@3ef0000 { 1315 compatible = "nvidia,tegra194-p2u"; 1316 reg = <0x03ef0000 0x10000>; 1317 reg-names = "ctl"; 1318 1319 #phy-cells = <0>; 1320 }; 1321 1322 p2u_nvhs_5: phy@3f00000 { 1323 compatible = "nvidia,tegra194-p2u"; 1324 reg = <0x03f00000 0x10000>; 1325 reg-names = "ctl"; 1326 1327 #phy-cells = <0>; 1328 }; 1329 1330 p2u_nvhs_6: phy@3f10000 { 1331 compatible = "nvidia,tegra194-p2u"; 1332 reg = <0x03f10000 0x10000>; 1333 reg-names = "ctl"; 1334 1335 #phy-cells = <0>; 1336 }; 1337 1338 p2u_nvhs_7: phy@3f20000 { 1339 compatible = "nvidia,tegra194-p2u"; 1340 reg = <0x03f20000 0x10000>; 1341 reg-names = "ctl"; 1342 1343 #phy-cells = <0>; 1344 }; 1345 1346 p2u_hsio_10: phy@3f30000 { 1347 compatible = "nvidia,tegra194-p2u"; 1348 reg = <0x03f30000 0x10000>; 1349 reg-names = "ctl"; 1350 1351 #phy-cells = <0>; 1352 }; 1353 1354 p2u_hsio_11: phy@3f40000 { 1355 compatible = "nvidia,tegra194-p2u"; 1356 reg = <0x03f40000 0x10000>; 1357 reg-names = "ctl"; 1358 1359 #phy-cells = <0>; 1360 }; 1361 1362 hsp_aon: hsp@c150000 { 1363 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1364 reg = <0x0c150000 0x90000>; 1365 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1369 /* 1370 * Shared interrupt 0 is routed only to AON/SPE, so 1371 * we only have 4 shared interrupts for the CCPLEX. 1372 */ 1373 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1374 #mbox-cells = <2>; 1375 }; 1376 1377 gen2_i2c: i2c@c240000 { 1378 compatible = "nvidia,tegra194-i2c"; 1379 reg = <0x0c240000 0x10000>; 1380 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1384 clock-names = "div-clk"; 1385 resets = <&bpmp TEGRA194_RESET_I2C2>; 1386 reset-names = "i2c"; 1387 status = "disabled"; 1388 }; 1389 1390 gen8_i2c: i2c@c250000 { 1391 compatible = "nvidia,tegra194-i2c"; 1392 reg = <0x0c250000 0x10000>; 1393 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1397 clock-names = "div-clk"; 1398 resets = <&bpmp TEGRA194_RESET_I2C8>; 1399 reset-names = "i2c"; 1400 status = "disabled"; 1401 }; 1402 1403 uartc: serial@c280000 { 1404 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1405 reg = <0x0c280000 0x40>; 1406 reg-shift = <2>; 1407 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1408 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1409 clock-names = "serial"; 1410 resets = <&bpmp TEGRA194_RESET_UARTC>; 1411 reset-names = "serial"; 1412 status = "disabled"; 1413 }; 1414 1415 uartg: serial@c290000 { 1416 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1417 reg = <0x0c290000 0x40>; 1418 reg-shift = <2>; 1419 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1420 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1421 clock-names = "serial"; 1422 resets = <&bpmp TEGRA194_RESET_UARTG>; 1423 reset-names = "serial"; 1424 status = "disabled"; 1425 }; 1426 1427 rtc: rtc@c2a0000 { 1428 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1429 reg = <0x0c2a0000 0x10000>; 1430 interrupt-parent = <&pmc>; 1431 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1432 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1433 clock-names = "rtc"; 1434 status = "disabled"; 1435 }; 1436 1437 gpio_aon: gpio@c2f0000 { 1438 compatible = "nvidia,tegra194-gpio-aon"; 1439 reg-names = "security", "gpio"; 1440 reg = <0xc2f0000 0x1000>, 1441 <0xc2f1000 0x1000>; 1442 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1446 gpio-controller; 1447 #gpio-cells = <2>; 1448 interrupt-controller; 1449 #interrupt-cells = <2>; 1450 }; 1451 1452 pwm4: pwm@c340000 { 1453 compatible = "nvidia,tegra194-pwm", 1454 "nvidia,tegra186-pwm"; 1455 reg = <0xc340000 0x10000>; 1456 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1457 clock-names = "pwm"; 1458 resets = <&bpmp TEGRA194_RESET_PWM4>; 1459 reset-names = "pwm"; 1460 status = "disabled"; 1461 #pwm-cells = <2>; 1462 }; 1463 1464 pmc: pmc@c360000 { 1465 compatible = "nvidia,tegra194-pmc"; 1466 reg = <0x0c360000 0x10000>, 1467 <0x0c370000 0x10000>, 1468 <0x0c380000 0x10000>, 1469 <0x0c390000 0x10000>, 1470 <0x0c3a0000 0x10000>; 1471 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1472 1473 #interrupt-cells = <2>; 1474 interrupt-controller; 1475 }; 1476 1477 smmu: iommu@12000000 { 1478 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1479 reg = <0x12000000 0x800000>, 1480 <0x11000000 0x800000>; 1481 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1547 stream-match-mask = <0x7f80>; 1548 #global-interrupts = <2>; 1549 #iommu-cells = <1>; 1550 1551 nvidia,memory-controller = <&mc>; 1552 status = "okay"; 1553 }; 1554 1555 host1x@13e00000 { 1556 compatible = "nvidia,tegra194-host1x"; 1557 reg = <0x13e00000 0x10000>, 1558 <0x13e10000 0x10000>; 1559 reg-names = "hypervisor", "vm"; 1560 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1562 interrupt-names = "syncpt", "host1x"; 1563 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1564 clock-names = "host1x"; 1565 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1566 reset-names = "host1x"; 1567 1568 #address-cells = <1>; 1569 #size-cells = <1>; 1570 1571 ranges = <0x15000000 0x15000000 0x01000000>; 1572 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1573 interconnect-names = "dma-mem"; 1574 iommus = <&smmu TEGRA194_SID_HOST1X>; 1575 1576 nvdec@15140000 { 1577 compatible = "nvidia,tegra194-nvdec"; 1578 reg = <0x15140000 0x00040000>; 1579 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1580 clock-names = "nvdec"; 1581 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1582 reset-names = "nvdec"; 1583 1584 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1585 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1586 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1587 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1588 interconnect-names = "dma-mem", "read-1", "write"; 1589 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1590 dma-coherent; 1591 1592 nvidia,host1x-class = <0xf5>; 1593 }; 1594 1595 display-hub@15200000 { 1596 compatible = "nvidia,tegra194-display"; 1597 reg = <0x15200000 0x00040000>; 1598 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1599 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1600 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1601 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1602 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1603 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1604 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1605 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1606 "wgrp3", "wgrp4", "wgrp5"; 1607 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1608 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1609 clock-names = "disp", "hub"; 1610 status = "disabled"; 1611 1612 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1613 1614 #address-cells = <1>; 1615 #size-cells = <1>; 1616 1617 ranges = <0x15200000 0x15200000 0x40000>; 1618 1619 display@15200000 { 1620 compatible = "nvidia,tegra194-dc"; 1621 reg = <0x15200000 0x10000>; 1622 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1623 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1624 clock-names = "dc"; 1625 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1626 reset-names = "dc"; 1627 1628 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1629 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1630 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1631 interconnect-names = "dma-mem", "read-1"; 1632 1633 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1634 nvidia,head = <0>; 1635 }; 1636 1637 display@15210000 { 1638 compatible = "nvidia,tegra194-dc"; 1639 reg = <0x15210000 0x10000>; 1640 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1641 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1642 clock-names = "dc"; 1643 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1644 reset-names = "dc"; 1645 1646 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1647 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1648 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1649 interconnect-names = "dma-mem", "read-1"; 1650 1651 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1652 nvidia,head = <1>; 1653 }; 1654 1655 display@15220000 { 1656 compatible = "nvidia,tegra194-dc"; 1657 reg = <0x15220000 0x10000>; 1658 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1659 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1660 clock-names = "dc"; 1661 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1662 reset-names = "dc"; 1663 1664 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1665 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1666 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1667 interconnect-names = "dma-mem", "read-1"; 1668 1669 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1670 nvidia,head = <2>; 1671 }; 1672 1673 display@15230000 { 1674 compatible = "nvidia,tegra194-dc"; 1675 reg = <0x15230000 0x10000>; 1676 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1677 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1678 clock-names = "dc"; 1679 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1680 reset-names = "dc"; 1681 1682 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1683 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1684 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1685 interconnect-names = "dma-mem", "read-1"; 1686 1687 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1688 nvidia,head = <3>; 1689 }; 1690 }; 1691 1692 vic@15340000 { 1693 compatible = "nvidia,tegra194-vic"; 1694 reg = <0x15340000 0x00040000>; 1695 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1696 clocks = <&bpmp TEGRA194_CLK_VIC>; 1697 clock-names = "vic"; 1698 resets = <&bpmp TEGRA194_RESET_VIC>; 1699 reset-names = "vic"; 1700 1701 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1702 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1703 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1704 interconnect-names = "dma-mem", "write"; 1705 iommus = <&smmu TEGRA194_SID_VIC>; 1706 }; 1707 1708 nvdec@15480000 { 1709 compatible = "nvidia,tegra194-nvdec"; 1710 reg = <0x15480000 0x00040000>; 1711 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 1712 clock-names = "nvdec"; 1713 resets = <&bpmp TEGRA194_RESET_NVDEC>; 1714 reset-names = "nvdec"; 1715 1716 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 1717 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 1718 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 1719 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 1720 interconnect-names = "dma-mem", "read-1", "write"; 1721 iommus = <&smmu TEGRA194_SID_NVDEC>; 1722 dma-coherent; 1723 1724 nvidia,host1x-class = <0xf0>; 1725 }; 1726 1727 dpaux0: dpaux@155c0000 { 1728 compatible = "nvidia,tegra194-dpaux"; 1729 reg = <0x155c0000 0x10000>; 1730 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1731 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1732 <&bpmp TEGRA194_CLK_PLLDP>; 1733 clock-names = "dpaux", "parent"; 1734 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1735 reset-names = "dpaux"; 1736 status = "disabled"; 1737 1738 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1739 1740 state_dpaux0_aux: pinmux-aux { 1741 groups = "dpaux-io"; 1742 function = "aux"; 1743 }; 1744 1745 state_dpaux0_i2c: pinmux-i2c { 1746 groups = "dpaux-io"; 1747 function = "i2c"; 1748 }; 1749 1750 state_dpaux0_off: pinmux-off { 1751 groups = "dpaux-io"; 1752 function = "off"; 1753 }; 1754 1755 i2c-bus { 1756 #address-cells = <1>; 1757 #size-cells = <0>; 1758 }; 1759 }; 1760 1761 dpaux1: dpaux@155d0000 { 1762 compatible = "nvidia,tegra194-dpaux"; 1763 reg = <0x155d0000 0x10000>; 1764 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1765 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1766 <&bpmp TEGRA194_CLK_PLLDP>; 1767 clock-names = "dpaux", "parent"; 1768 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1769 reset-names = "dpaux"; 1770 status = "disabled"; 1771 1772 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1773 1774 state_dpaux1_aux: pinmux-aux { 1775 groups = "dpaux-io"; 1776 function = "aux"; 1777 }; 1778 1779 state_dpaux1_i2c: pinmux-i2c { 1780 groups = "dpaux-io"; 1781 function = "i2c"; 1782 }; 1783 1784 state_dpaux1_off: pinmux-off { 1785 groups = "dpaux-io"; 1786 function = "off"; 1787 }; 1788 1789 i2c-bus { 1790 #address-cells = <1>; 1791 #size-cells = <0>; 1792 }; 1793 }; 1794 1795 dpaux2: dpaux@155e0000 { 1796 compatible = "nvidia,tegra194-dpaux"; 1797 reg = <0x155e0000 0x10000>; 1798 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1799 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1800 <&bpmp TEGRA194_CLK_PLLDP>; 1801 clock-names = "dpaux", "parent"; 1802 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1803 reset-names = "dpaux"; 1804 status = "disabled"; 1805 1806 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1807 1808 state_dpaux2_aux: pinmux-aux { 1809 groups = "dpaux-io"; 1810 function = "aux"; 1811 }; 1812 1813 state_dpaux2_i2c: pinmux-i2c { 1814 groups = "dpaux-io"; 1815 function = "i2c"; 1816 }; 1817 1818 state_dpaux2_off: pinmux-off { 1819 groups = "dpaux-io"; 1820 function = "off"; 1821 }; 1822 1823 i2c-bus { 1824 #address-cells = <1>; 1825 #size-cells = <0>; 1826 }; 1827 }; 1828 1829 dpaux3: dpaux@155f0000 { 1830 compatible = "nvidia,tegra194-dpaux"; 1831 reg = <0x155f0000 0x10000>; 1832 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1833 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1834 <&bpmp TEGRA194_CLK_PLLDP>; 1835 clock-names = "dpaux", "parent"; 1836 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1837 reset-names = "dpaux"; 1838 status = "disabled"; 1839 1840 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1841 1842 state_dpaux3_aux: pinmux-aux { 1843 groups = "dpaux-io"; 1844 function = "aux"; 1845 }; 1846 1847 state_dpaux3_i2c: pinmux-i2c { 1848 groups = "dpaux-io"; 1849 function = "i2c"; 1850 }; 1851 1852 state_dpaux3_off: pinmux-off { 1853 groups = "dpaux-io"; 1854 function = "off"; 1855 }; 1856 1857 i2c-bus { 1858 #address-cells = <1>; 1859 #size-cells = <0>; 1860 }; 1861 }; 1862 1863 sor0: sor@15b00000 { 1864 compatible = "nvidia,tegra194-sor"; 1865 reg = <0x15b00000 0x40000>; 1866 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1867 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1868 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1869 <&bpmp TEGRA194_CLK_PLLD>, 1870 <&bpmp TEGRA194_CLK_PLLDP>, 1871 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1872 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1873 clock-names = "sor", "out", "parent", "dp", "safe", 1874 "pad"; 1875 resets = <&bpmp TEGRA194_RESET_SOR0>; 1876 reset-names = "sor"; 1877 pinctrl-0 = <&state_dpaux0_aux>; 1878 pinctrl-1 = <&state_dpaux0_i2c>; 1879 pinctrl-2 = <&state_dpaux0_off>; 1880 pinctrl-names = "aux", "i2c", "off"; 1881 status = "disabled"; 1882 1883 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1884 nvidia,interface = <0>; 1885 }; 1886 1887 sor1: sor@15b40000 { 1888 compatible = "nvidia,tegra194-sor"; 1889 reg = <0x15b40000 0x40000>; 1890 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1891 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1892 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1893 <&bpmp TEGRA194_CLK_PLLD2>, 1894 <&bpmp TEGRA194_CLK_PLLDP>, 1895 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1896 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1897 clock-names = "sor", "out", "parent", "dp", "safe", 1898 "pad"; 1899 resets = <&bpmp TEGRA194_RESET_SOR1>; 1900 reset-names = "sor"; 1901 pinctrl-0 = <&state_dpaux1_aux>; 1902 pinctrl-1 = <&state_dpaux1_i2c>; 1903 pinctrl-2 = <&state_dpaux1_off>; 1904 pinctrl-names = "aux", "i2c", "off"; 1905 status = "disabled"; 1906 1907 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1908 nvidia,interface = <1>; 1909 }; 1910 1911 sor2: sor@15b80000 { 1912 compatible = "nvidia,tegra194-sor"; 1913 reg = <0x15b80000 0x40000>; 1914 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1915 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1916 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1917 <&bpmp TEGRA194_CLK_PLLD3>, 1918 <&bpmp TEGRA194_CLK_PLLDP>, 1919 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1920 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1921 clock-names = "sor", "out", "parent", "dp", "safe", 1922 "pad"; 1923 resets = <&bpmp TEGRA194_RESET_SOR2>; 1924 reset-names = "sor"; 1925 pinctrl-0 = <&state_dpaux2_aux>; 1926 pinctrl-1 = <&state_dpaux2_i2c>; 1927 pinctrl-2 = <&state_dpaux2_off>; 1928 pinctrl-names = "aux", "i2c", "off"; 1929 status = "disabled"; 1930 1931 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1932 nvidia,interface = <2>; 1933 }; 1934 1935 sor3: sor@15bc0000 { 1936 compatible = "nvidia,tegra194-sor"; 1937 reg = <0x15bc0000 0x40000>; 1938 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1939 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1940 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1941 <&bpmp TEGRA194_CLK_PLLD4>, 1942 <&bpmp TEGRA194_CLK_PLLDP>, 1943 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1944 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1945 clock-names = "sor", "out", "parent", "dp", "safe", 1946 "pad"; 1947 resets = <&bpmp TEGRA194_RESET_SOR3>; 1948 reset-names = "sor"; 1949 pinctrl-0 = <&state_dpaux3_aux>; 1950 pinctrl-1 = <&state_dpaux3_i2c>; 1951 pinctrl-2 = <&state_dpaux3_off>; 1952 pinctrl-names = "aux", "i2c", "off"; 1953 status = "disabled"; 1954 1955 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1956 nvidia,interface = <3>; 1957 }; 1958 }; 1959 1960 gpu@17000000 { 1961 compatible = "nvidia,gv11b"; 1962 reg = <0x17000000 0x1000000>, 1963 <0x18000000 0x1000000>; 1964 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1966 interrupt-names = "stall", "nonstall"; 1967 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 1968 <&bpmp TEGRA194_CLK_GPU_PWR>, 1969 <&bpmp TEGRA194_CLK_FUSE>; 1970 clock-names = "gpu", "pwr", "fuse"; 1971 resets = <&bpmp TEGRA194_RESET_GPU>; 1972 reset-names = "gpu"; 1973 dma-coherent; 1974 1975 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 1976 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 1977 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 1978 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 1979 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 1980 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 1981 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 1982 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 1983 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 1984 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 1985 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 1986 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 1987 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 1988 interconnect-names = "dma-mem", "read-0-hp", "write-0", 1989 "read-1", "read-1-hp", "write-1", 1990 "read-2", "read-2-hp", "write-2", 1991 "read-3", "read-3-hp", "write-3"; 1992 }; 1993 }; 1994 1995 pcie@14100000 { 1996 compatible = "nvidia,tegra194-pcie"; 1997 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1998 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1999 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2000 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2001 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2002 reg-names = "appl", "config", "atu_dma", "dbi"; 2003 2004 status = "disabled"; 2005 2006 #address-cells = <3>; 2007 #size-cells = <2>; 2008 device_type = "pci"; 2009 num-lanes = <1>; 2010 num-viewport = <8>; 2011 linux,pci-domain = <1>; 2012 2013 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2014 clock-names = "core"; 2015 2016 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2017 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2018 reset-names = "apb", "core"; 2019 2020 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2021 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2022 interrupt-names = "intr", "msi"; 2023 2024 #interrupt-cells = <1>; 2025 interrupt-map-mask = <0 0 0 0>; 2026 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2027 2028 nvidia,bpmp = <&bpmp 1>; 2029 2030 nvidia,aspm-cmrt-us = <60>; 2031 nvidia,aspm-pwr-on-t-us = <20>; 2032 nvidia,aspm-l0s-entrance-latency-us = <3>; 2033 2034 bus-range = <0x0 0xff>; 2035 2036 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2037 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2038 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2039 2040 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2041 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2042 interconnect-names = "dma-mem", "write"; 2043 iommus = <&smmu TEGRA194_SID_PCIE1>; 2044 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2045 iommu-map-mask = <0x0>; 2046 dma-coherent; 2047 }; 2048 2049 pcie@14120000 { 2050 compatible = "nvidia,tegra194-pcie"; 2051 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2052 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2053 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2054 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2055 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2056 reg-names = "appl", "config", "atu_dma", "dbi"; 2057 2058 status = "disabled"; 2059 2060 #address-cells = <3>; 2061 #size-cells = <2>; 2062 device_type = "pci"; 2063 num-lanes = <1>; 2064 num-viewport = <8>; 2065 linux,pci-domain = <2>; 2066 2067 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2068 clock-names = "core"; 2069 2070 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2071 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2072 reset-names = "apb", "core"; 2073 2074 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2075 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2076 interrupt-names = "intr", "msi"; 2077 2078 #interrupt-cells = <1>; 2079 interrupt-map-mask = <0 0 0 0>; 2080 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2081 2082 nvidia,bpmp = <&bpmp 2>; 2083 2084 nvidia,aspm-cmrt-us = <60>; 2085 nvidia,aspm-pwr-on-t-us = <20>; 2086 nvidia,aspm-l0s-entrance-latency-us = <3>; 2087 2088 bus-range = <0x0 0xff>; 2089 2090 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2091 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2092 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2093 2094 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2095 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2096 interconnect-names = "dma-mem", "write"; 2097 iommus = <&smmu TEGRA194_SID_PCIE2>; 2098 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2099 iommu-map-mask = <0x0>; 2100 dma-coherent; 2101 }; 2102 2103 pcie@14140000 { 2104 compatible = "nvidia,tegra194-pcie"; 2105 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2106 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2107 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2108 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2109 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2110 reg-names = "appl", "config", "atu_dma", "dbi"; 2111 2112 status = "disabled"; 2113 2114 #address-cells = <3>; 2115 #size-cells = <2>; 2116 device_type = "pci"; 2117 num-lanes = <1>; 2118 num-viewport = <8>; 2119 linux,pci-domain = <3>; 2120 2121 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2122 clock-names = "core"; 2123 2124 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2125 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2126 reset-names = "apb", "core"; 2127 2128 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2129 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2130 interrupt-names = "intr", "msi"; 2131 2132 #interrupt-cells = <1>; 2133 interrupt-map-mask = <0 0 0 0>; 2134 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2135 2136 nvidia,bpmp = <&bpmp 3>; 2137 2138 nvidia,aspm-cmrt-us = <60>; 2139 nvidia,aspm-pwr-on-t-us = <20>; 2140 nvidia,aspm-l0s-entrance-latency-us = <3>; 2141 2142 bus-range = <0x0 0xff>; 2143 2144 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2145 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2146 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2147 2148 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2149 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2150 interconnect-names = "dma-mem", "write"; 2151 iommus = <&smmu TEGRA194_SID_PCIE3>; 2152 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2153 iommu-map-mask = <0x0>; 2154 dma-coherent; 2155 }; 2156 2157 pcie@14160000 { 2158 compatible = "nvidia,tegra194-pcie"; 2159 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2160 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2161 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2162 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2163 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2164 reg-names = "appl", "config", "atu_dma", "dbi"; 2165 2166 status = "disabled"; 2167 2168 #address-cells = <3>; 2169 #size-cells = <2>; 2170 device_type = "pci"; 2171 num-lanes = <4>; 2172 num-viewport = <8>; 2173 linux,pci-domain = <4>; 2174 2175 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2176 clock-names = "core"; 2177 2178 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2179 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2180 reset-names = "apb", "core"; 2181 2182 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2183 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2184 interrupt-names = "intr", "msi"; 2185 2186 #interrupt-cells = <1>; 2187 interrupt-map-mask = <0 0 0 0>; 2188 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2189 2190 nvidia,bpmp = <&bpmp 4>; 2191 2192 nvidia,aspm-cmrt-us = <60>; 2193 nvidia,aspm-pwr-on-t-us = <20>; 2194 nvidia,aspm-l0s-entrance-latency-us = <3>; 2195 2196 bus-range = <0x0 0xff>; 2197 2198 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2199 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2200 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2201 2202 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2203 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2204 interconnect-names = "dma-mem", "write"; 2205 iommus = <&smmu TEGRA194_SID_PCIE4>; 2206 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2207 iommu-map-mask = <0x0>; 2208 dma-coherent; 2209 }; 2210 2211 pcie@14180000 { 2212 compatible = "nvidia,tegra194-pcie"; 2213 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2214 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2215 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2216 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2217 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2218 reg-names = "appl", "config", "atu_dma", "dbi"; 2219 2220 status = "disabled"; 2221 2222 #address-cells = <3>; 2223 #size-cells = <2>; 2224 device_type = "pci"; 2225 num-lanes = <8>; 2226 num-viewport = <8>; 2227 linux,pci-domain = <0>; 2228 2229 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2230 clock-names = "core"; 2231 2232 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2233 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2234 reset-names = "apb", "core"; 2235 2236 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2237 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2238 interrupt-names = "intr", "msi"; 2239 2240 #interrupt-cells = <1>; 2241 interrupt-map-mask = <0 0 0 0>; 2242 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2243 2244 nvidia,bpmp = <&bpmp 0>; 2245 2246 nvidia,aspm-cmrt-us = <60>; 2247 nvidia,aspm-pwr-on-t-us = <20>; 2248 nvidia,aspm-l0s-entrance-latency-us = <3>; 2249 2250 bus-range = <0x0 0xff>; 2251 2252 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2253 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2254 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2255 2256 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2257 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2258 interconnect-names = "dma-mem", "write"; 2259 iommus = <&smmu TEGRA194_SID_PCIE0>; 2260 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2261 iommu-map-mask = <0x0>; 2262 dma-coherent; 2263 }; 2264 2265 pcie@141a0000 { 2266 compatible = "nvidia,tegra194-pcie"; 2267 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2268 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2269 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2270 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2271 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2272 reg-names = "appl", "config", "atu_dma", "dbi"; 2273 2274 status = "disabled"; 2275 2276 #address-cells = <3>; 2277 #size-cells = <2>; 2278 device_type = "pci"; 2279 num-lanes = <8>; 2280 num-viewport = <8>; 2281 linux,pci-domain = <5>; 2282 2283 pinctrl-names = "default"; 2284 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2285 2286 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 2287 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 2288 clock-names = "core", "core_m"; 2289 2290 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2291 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2292 reset-names = "apb", "core"; 2293 2294 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2295 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2296 interrupt-names = "intr", "msi"; 2297 2298 nvidia,bpmp = <&bpmp 5>; 2299 2300 #interrupt-cells = <1>; 2301 interrupt-map-mask = <0 0 0 0>; 2302 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2303 2304 nvidia,aspm-cmrt-us = <60>; 2305 nvidia,aspm-pwr-on-t-us = <20>; 2306 nvidia,aspm-l0s-entrance-latency-us = <3>; 2307 2308 bus-range = <0x0 0xff>; 2309 2310 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2311 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2312 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2313 2314 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2315 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2316 interconnect-names = "dma-mem", "write"; 2317 iommus = <&smmu TEGRA194_SID_PCIE5>; 2318 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2319 iommu-map-mask = <0x0>; 2320 dma-coherent; 2321 }; 2322 2323 pcie_ep@14160000 { 2324 compatible = "nvidia,tegra194-pcie-ep"; 2325 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2326 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2327 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2328 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2329 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2330 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2331 2332 status = "disabled"; 2333 2334 num-lanes = <4>; 2335 num-ib-windows = <2>; 2336 num-ob-windows = <8>; 2337 2338 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2339 clock-names = "core"; 2340 2341 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2342 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2343 reset-names = "apb", "core"; 2344 2345 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2346 interrupt-names = "intr"; 2347 2348 nvidia,bpmp = <&bpmp 4>; 2349 2350 nvidia,aspm-cmrt-us = <60>; 2351 nvidia,aspm-pwr-on-t-us = <20>; 2352 nvidia,aspm-l0s-entrance-latency-us = <3>; 2353 2354 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2355 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2356 interconnect-names = "dma-mem", "write"; 2357 iommus = <&smmu TEGRA194_SID_PCIE4>; 2358 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2359 iommu-map-mask = <0x0>; 2360 dma-coherent; 2361 }; 2362 2363 pcie_ep@14180000 { 2364 compatible = "nvidia,tegra194-pcie-ep"; 2365 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2366 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2367 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2368 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2369 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2370 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2371 2372 status = "disabled"; 2373 2374 num-lanes = <8>; 2375 num-ib-windows = <2>; 2376 num-ob-windows = <8>; 2377 2378 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2379 clock-names = "core"; 2380 2381 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2382 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2383 reset-names = "apb", "core"; 2384 2385 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2386 interrupt-names = "intr"; 2387 2388 nvidia,bpmp = <&bpmp 0>; 2389 2390 nvidia,aspm-cmrt-us = <60>; 2391 nvidia,aspm-pwr-on-t-us = <20>; 2392 nvidia,aspm-l0s-entrance-latency-us = <3>; 2393 2394 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2395 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2396 interconnect-names = "dma-mem", "write"; 2397 iommus = <&smmu TEGRA194_SID_PCIE0>; 2398 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2399 iommu-map-mask = <0x0>; 2400 dma-coherent; 2401 }; 2402 2403 pcie_ep@141a0000 { 2404 compatible = "nvidia,tegra194-pcie-ep"; 2405 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2406 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2407 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2408 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2409 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2410 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2411 2412 status = "disabled"; 2413 2414 num-lanes = <8>; 2415 num-ib-windows = <2>; 2416 num-ob-windows = <8>; 2417 2418 pinctrl-names = "default"; 2419 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2420 2421 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2422 clock-names = "core"; 2423 2424 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2425 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2426 reset-names = "apb", "core"; 2427 2428 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2429 interrupt-names = "intr"; 2430 2431 nvidia,bpmp = <&bpmp 5>; 2432 2433 nvidia,aspm-cmrt-us = <60>; 2434 nvidia,aspm-pwr-on-t-us = <20>; 2435 nvidia,aspm-l0s-entrance-latency-us = <3>; 2436 2437 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2438 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2439 interconnect-names = "dma-mem", "write"; 2440 iommus = <&smmu TEGRA194_SID_PCIE5>; 2441 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2442 iommu-map-mask = <0x0>; 2443 dma-coherent; 2444 }; 2445 2446 sram@40000000 { 2447 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2448 reg = <0x0 0x40000000 0x0 0x50000>; 2449 #address-cells = <1>; 2450 #size-cells = <1>; 2451 ranges = <0x0 0x0 0x40000000 0x50000>; 2452 2453 cpu_bpmp_tx: sram@4e000 { 2454 reg = <0x4e000 0x1000>; 2455 label = "cpu-bpmp-tx"; 2456 pool; 2457 }; 2458 2459 cpu_bpmp_rx: sram@4f000 { 2460 reg = <0x4f000 0x1000>; 2461 label = "cpu-bpmp-rx"; 2462 pool; 2463 }; 2464 }; 2465 2466 bpmp: bpmp { 2467 compatible = "nvidia,tegra186-bpmp"; 2468 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2469 TEGRA_HSP_DB_MASTER_BPMP>; 2470 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 2471 #clock-cells = <1>; 2472 #reset-cells = <1>; 2473 #power-domain-cells = <1>; 2474 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2475 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2476 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2477 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2478 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2479 iommus = <&smmu TEGRA194_SID_BPMP>; 2480 2481 bpmp_i2c: i2c { 2482 compatible = "nvidia,tegra186-bpmp-i2c"; 2483 nvidia,bpmp-bus-id = <5>; 2484 #address-cells = <1>; 2485 #size-cells = <0>; 2486 }; 2487 2488 bpmp_thermal: thermal { 2489 compatible = "nvidia,tegra186-bpmp-thermal"; 2490 #thermal-sensor-cells = <1>; 2491 }; 2492 }; 2493 2494 cpus { 2495 compatible = "nvidia,tegra194-ccplex"; 2496 nvidia,bpmp = <&bpmp>; 2497 #address-cells = <1>; 2498 #size-cells = <0>; 2499 2500 cpu0_0: cpu@0 { 2501 compatible = "nvidia,tegra194-carmel"; 2502 device_type = "cpu"; 2503 reg = <0x000>; 2504 enable-method = "psci"; 2505 i-cache-size = <131072>; 2506 i-cache-line-size = <64>; 2507 i-cache-sets = <512>; 2508 d-cache-size = <65536>; 2509 d-cache-line-size = <64>; 2510 d-cache-sets = <256>; 2511 next-level-cache = <&l2c_0>; 2512 }; 2513 2514 cpu0_1: cpu@1 { 2515 compatible = "nvidia,tegra194-carmel"; 2516 device_type = "cpu"; 2517 reg = <0x001>; 2518 enable-method = "psci"; 2519 i-cache-size = <131072>; 2520 i-cache-line-size = <64>; 2521 i-cache-sets = <512>; 2522 d-cache-size = <65536>; 2523 d-cache-line-size = <64>; 2524 d-cache-sets = <256>; 2525 next-level-cache = <&l2c_0>; 2526 }; 2527 2528 cpu1_0: cpu@100 { 2529 compatible = "nvidia,tegra194-carmel"; 2530 device_type = "cpu"; 2531 reg = <0x100>; 2532 enable-method = "psci"; 2533 i-cache-size = <131072>; 2534 i-cache-line-size = <64>; 2535 i-cache-sets = <512>; 2536 d-cache-size = <65536>; 2537 d-cache-line-size = <64>; 2538 d-cache-sets = <256>; 2539 next-level-cache = <&l2c_1>; 2540 }; 2541 2542 cpu1_1: cpu@101 { 2543 compatible = "nvidia,tegra194-carmel"; 2544 device_type = "cpu"; 2545 reg = <0x101>; 2546 enable-method = "psci"; 2547 i-cache-size = <131072>; 2548 i-cache-line-size = <64>; 2549 i-cache-sets = <512>; 2550 d-cache-size = <65536>; 2551 d-cache-line-size = <64>; 2552 d-cache-sets = <256>; 2553 next-level-cache = <&l2c_1>; 2554 }; 2555 2556 cpu2_0: cpu@200 { 2557 compatible = "nvidia,tegra194-carmel"; 2558 device_type = "cpu"; 2559 reg = <0x200>; 2560 enable-method = "psci"; 2561 i-cache-size = <131072>; 2562 i-cache-line-size = <64>; 2563 i-cache-sets = <512>; 2564 d-cache-size = <65536>; 2565 d-cache-line-size = <64>; 2566 d-cache-sets = <256>; 2567 next-level-cache = <&l2c_2>; 2568 }; 2569 2570 cpu2_1: cpu@201 { 2571 compatible = "nvidia,tegra194-carmel"; 2572 device_type = "cpu"; 2573 reg = <0x201>; 2574 enable-method = "psci"; 2575 i-cache-size = <131072>; 2576 i-cache-line-size = <64>; 2577 i-cache-sets = <512>; 2578 d-cache-size = <65536>; 2579 d-cache-line-size = <64>; 2580 d-cache-sets = <256>; 2581 next-level-cache = <&l2c_2>; 2582 }; 2583 2584 cpu3_0: cpu@300 { 2585 compatible = "nvidia,tegra194-carmel"; 2586 device_type = "cpu"; 2587 reg = <0x300>; 2588 enable-method = "psci"; 2589 i-cache-size = <131072>; 2590 i-cache-line-size = <64>; 2591 i-cache-sets = <512>; 2592 d-cache-size = <65536>; 2593 d-cache-line-size = <64>; 2594 d-cache-sets = <256>; 2595 next-level-cache = <&l2c_3>; 2596 }; 2597 2598 cpu3_1: cpu@301 { 2599 compatible = "nvidia,tegra194-carmel"; 2600 device_type = "cpu"; 2601 reg = <0x301>; 2602 enable-method = "psci"; 2603 i-cache-size = <131072>; 2604 i-cache-line-size = <64>; 2605 i-cache-sets = <512>; 2606 d-cache-size = <65536>; 2607 d-cache-line-size = <64>; 2608 d-cache-sets = <256>; 2609 next-level-cache = <&l2c_3>; 2610 }; 2611 2612 cpu-map { 2613 cluster0 { 2614 core0 { 2615 cpu = <&cpu0_0>; 2616 }; 2617 2618 core1 { 2619 cpu = <&cpu0_1>; 2620 }; 2621 }; 2622 2623 cluster1 { 2624 core0 { 2625 cpu = <&cpu1_0>; 2626 }; 2627 2628 core1 { 2629 cpu = <&cpu1_1>; 2630 }; 2631 }; 2632 2633 cluster2 { 2634 core0 { 2635 cpu = <&cpu2_0>; 2636 }; 2637 2638 core1 { 2639 cpu = <&cpu2_1>; 2640 }; 2641 }; 2642 2643 cluster3 { 2644 core0 { 2645 cpu = <&cpu3_0>; 2646 }; 2647 2648 core1 { 2649 cpu = <&cpu3_1>; 2650 }; 2651 }; 2652 }; 2653 2654 l2c_0: l2-cache0 { 2655 cache-size = <2097152>; 2656 cache-line-size = <64>; 2657 cache-sets = <2048>; 2658 next-level-cache = <&l3c>; 2659 }; 2660 2661 l2c_1: l2-cache1 { 2662 cache-size = <2097152>; 2663 cache-line-size = <64>; 2664 cache-sets = <2048>; 2665 next-level-cache = <&l3c>; 2666 }; 2667 2668 l2c_2: l2-cache2 { 2669 cache-size = <2097152>; 2670 cache-line-size = <64>; 2671 cache-sets = <2048>; 2672 next-level-cache = <&l3c>; 2673 }; 2674 2675 l2c_3: l2-cache3 { 2676 cache-size = <2097152>; 2677 cache-line-size = <64>; 2678 cache-sets = <2048>; 2679 next-level-cache = <&l3c>; 2680 }; 2681 2682 l3c: l3-cache { 2683 cache-size = <4194304>; 2684 cache-line-size = <64>; 2685 cache-sets = <4096>; 2686 }; 2687 }; 2688 2689 pmu { 2690 compatible = "arm,armv8-pmuv3"; 2691 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2692 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2693 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2694 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 2695 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 2696 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 2697 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 2698 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 2699 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 2700 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 2701 }; 2702 2703 psci { 2704 compatible = "arm,psci-1.0"; 2705 status = "okay"; 2706 method = "smc"; 2707 }; 2708 2709 sound { 2710 status = "disabled"; 2711 2712 clocks = <&bpmp TEGRA194_CLK_PLLA>, 2713 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2714 clock-names = "pll_a", "plla_out0"; 2715 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 2716 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 2717 <&bpmp TEGRA194_CLK_AUD_MCLK>; 2718 assigned-clock-parents = <0>, 2719 <&bpmp TEGRA194_CLK_PLLA>, 2720 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2721 /* 2722 * PLLA supports dynamic ramp. Below initial rate is chosen 2723 * for this to work and oscillate between base rates required 2724 * for 8x and 11.025x sample rate streams. 2725 */ 2726 assigned-clock-rates = <258000000>; 2727 2728 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 2729 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 2730 interconnect-names = "dma-mem", "write"; 2731 iommus = <&smmu TEGRA194_SID_APE>; 2732 }; 2733 2734 tcu: tcu { 2735 compatible = "nvidia,tegra194-tcu"; 2736 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2737 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2738 mbox-names = "rx", "tx"; 2739 }; 2740 2741 thermal-zones { 2742 cpu { 2743 thermal-sensors = <&{/bpmp/thermal} 2744 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2745 status = "disabled"; 2746 }; 2747 2748 gpu { 2749 thermal-sensors = <&{/bpmp/thermal} 2750 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2751 status = "disabled"; 2752 }; 2753 2754 aux { 2755 thermal-sensors = <&{/bpmp/thermal} 2756 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2757 status = "disabled"; 2758 }; 2759 2760 pllx { 2761 thermal-sensors = <&{/bpmp/thermal} 2762 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2763 status = "disabled"; 2764 }; 2765 2766 ao { 2767 thermal-sensors = <&{/bpmp/thermal} 2768 TEGRA194_BPMP_THERMAL_ZONE_AO>; 2769 status = "disabled"; 2770 }; 2771 2772 tj { 2773 thermal-sensors = <&{/bpmp/thermal} 2774 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2775 status = "disabled"; 2776 }; 2777 }; 2778 2779 timer { 2780 compatible = "arm,armv8-timer"; 2781 interrupts = <GIC_PPI 13 2782 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2783 <GIC_PPI 14 2784 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2785 <GIC_PPI 11 2786 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2787 <GIC_PPI 10 2788 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2789 interrupt-parent = <&gic>; 2790 always-on; 2791 }; 2792}; 2793