1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 }; 90 91 ethernet@2490000 { 92 compatible = "nvidia,tegra194-eqos", 93 "nvidia,tegra186-eqos", 94 "snps,dwc-qos-ethernet-4.10"; 95 reg = <0x02490000 0x10000>; 96 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 98 <&bpmp TEGRA194_CLK_EQOS_AXI>, 99 <&bpmp TEGRA194_CLK_EQOS_RX>, 100 <&bpmp TEGRA194_CLK_EQOS_TX>, 101 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 102 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 103 resets = <&bpmp TEGRA194_RESET_EQOS>; 104 reset-names = "eqos"; 105 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 106 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 107 interconnect-names = "dma-mem", "write"; 108 iommus = <&smmu TEGRA194_SID_EQOS>; 109 status = "disabled"; 110 111 snps,write-requests = <1>; 112 snps,read-requests = <3>; 113 snps,burst-map = <0x7>; 114 snps,txpbl = <16>; 115 snps,rxpbl = <8>; 116 }; 117 118 gpcdma: dma-controller@2600000 { 119 compatible = "nvidia,tegra194-gpcdma", 120 "nvidia,tegra186-gpcdma"; 121 reg = <0x2600000 0x210000>; 122 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 123 reset-names = "gpcdma"; 124 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 155 #dma-cells = <1>; 156 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 157 dma-coherent; 158 status = "okay"; 159 }; 160 161 aconnect@2900000 { 162 compatible = "nvidia,tegra194-aconnect", 163 "nvidia,tegra210-aconnect"; 164 clocks = <&bpmp TEGRA194_CLK_APE>, 165 <&bpmp TEGRA194_CLK_APB2APE>; 166 clock-names = "ape", "apb2ape"; 167 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 168 #address-cells = <1>; 169 #size-cells = <1>; 170 ranges = <0x02900000 0x02900000 0x200000>; 171 status = "disabled"; 172 173 adma: dma-controller@2930000 { 174 compatible = "nvidia,tegra194-adma", 175 "nvidia,tegra186-adma"; 176 reg = <0x02930000 0x20000>; 177 interrupt-parent = <&agic>; 178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #dma-cells = <1>; 211 clocks = <&bpmp TEGRA194_CLK_AHUB>; 212 clock-names = "d_audio"; 213 status = "disabled"; 214 }; 215 216 agic: interrupt-controller@2a40000 { 217 compatible = "nvidia,tegra194-agic", 218 "nvidia,tegra210-agic"; 219 #interrupt-cells = <3>; 220 interrupt-controller; 221 reg = <0x02a41000 0x1000>, 222 <0x02a42000 0x2000>; 223 interrupts = <GIC_SPI 145 224 (GIC_CPU_MASK_SIMPLE(4) | 225 IRQ_TYPE_LEVEL_HIGH)>; 226 clocks = <&bpmp TEGRA194_CLK_APE>; 227 clock-names = "clk"; 228 status = "disabled"; 229 }; 230 231 tegra_ahub: ahub@2900800 { 232 compatible = "nvidia,tegra194-ahub", 233 "nvidia,tegra186-ahub"; 234 reg = <0x02900800 0x800>; 235 clocks = <&bpmp TEGRA194_CLK_AHUB>; 236 clock-names = "ahub"; 237 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 238 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 239 #address-cells = <1>; 240 #size-cells = <1>; 241 ranges = <0x02900800 0x02900800 0x11800>; 242 status = "disabled"; 243 244 tegra_admaif: admaif@290f000 { 245 compatible = "nvidia,tegra194-admaif", 246 "nvidia,tegra186-admaif"; 247 reg = <0x0290f000 0x1000>; 248 dmas = <&adma 1>, <&adma 1>, 249 <&adma 2>, <&adma 2>, 250 <&adma 3>, <&adma 3>, 251 <&adma 4>, <&adma 4>, 252 <&adma 5>, <&adma 5>, 253 <&adma 6>, <&adma 6>, 254 <&adma 7>, <&adma 7>, 255 <&adma 8>, <&adma 8>, 256 <&adma 9>, <&adma 9>, 257 <&adma 10>, <&adma 10>, 258 <&adma 11>, <&adma 11>, 259 <&adma 12>, <&adma 12>, 260 <&adma 13>, <&adma 13>, 261 <&adma 14>, <&adma 14>, 262 <&adma 15>, <&adma 15>, 263 <&adma 16>, <&adma 16>, 264 <&adma 17>, <&adma 17>, 265 <&adma 18>, <&adma 18>, 266 <&adma 19>, <&adma 19>, 267 <&adma 20>, <&adma 20>; 268 dma-names = "rx1", "tx1", 269 "rx2", "tx2", 270 "rx3", "tx3", 271 "rx4", "tx4", 272 "rx5", "tx5", 273 "rx6", "tx6", 274 "rx7", "tx7", 275 "rx8", "tx8", 276 "rx9", "tx9", 277 "rx10", "tx10", 278 "rx11", "tx11", 279 "rx12", "tx12", 280 "rx13", "tx13", 281 "rx14", "tx14", 282 "rx15", "tx15", 283 "rx16", "tx16", 284 "rx17", "tx17", 285 "rx18", "tx18", 286 "rx19", "tx19", 287 "rx20", "tx20"; 288 status = "disabled"; 289 }; 290 291 tegra_i2s1: i2s@2901000 { 292 compatible = "nvidia,tegra194-i2s", 293 "nvidia,tegra210-i2s"; 294 reg = <0x2901000 0x100>; 295 clocks = <&bpmp TEGRA194_CLK_I2S1>, 296 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 297 clock-names = "i2s", "sync_input"; 298 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 299 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 300 assigned-clock-rates = <1536000>; 301 sound-name-prefix = "I2S1"; 302 status = "disabled"; 303 }; 304 305 tegra_i2s2: i2s@2901100 { 306 compatible = "nvidia,tegra194-i2s", 307 "nvidia,tegra210-i2s"; 308 reg = <0x2901100 0x100>; 309 clocks = <&bpmp TEGRA194_CLK_I2S2>, 310 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 311 clock-names = "i2s", "sync_input"; 312 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 313 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 314 assigned-clock-rates = <1536000>; 315 sound-name-prefix = "I2S2"; 316 status = "disabled"; 317 }; 318 319 tegra_i2s3: i2s@2901200 { 320 compatible = "nvidia,tegra194-i2s", 321 "nvidia,tegra210-i2s"; 322 reg = <0x2901200 0x100>; 323 clocks = <&bpmp TEGRA194_CLK_I2S3>, 324 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 325 clock-names = "i2s", "sync_input"; 326 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 327 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 328 assigned-clock-rates = <1536000>; 329 sound-name-prefix = "I2S3"; 330 status = "disabled"; 331 }; 332 333 tegra_i2s4: i2s@2901300 { 334 compatible = "nvidia,tegra194-i2s", 335 "nvidia,tegra210-i2s"; 336 reg = <0x2901300 0x100>; 337 clocks = <&bpmp TEGRA194_CLK_I2S4>, 338 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 339 clock-names = "i2s", "sync_input"; 340 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 341 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 342 assigned-clock-rates = <1536000>; 343 sound-name-prefix = "I2S4"; 344 status = "disabled"; 345 }; 346 347 tegra_i2s5: i2s@2901400 { 348 compatible = "nvidia,tegra194-i2s", 349 "nvidia,tegra210-i2s"; 350 reg = <0x2901400 0x100>; 351 clocks = <&bpmp TEGRA194_CLK_I2S5>, 352 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 353 clock-names = "i2s", "sync_input"; 354 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 355 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 356 assigned-clock-rates = <1536000>; 357 sound-name-prefix = "I2S5"; 358 status = "disabled"; 359 }; 360 361 tegra_i2s6: i2s@2901500 { 362 compatible = "nvidia,tegra194-i2s", 363 "nvidia,tegra210-i2s"; 364 reg = <0x2901500 0x100>; 365 clocks = <&bpmp TEGRA194_CLK_I2S6>, 366 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 367 clock-names = "i2s", "sync_input"; 368 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 369 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 370 assigned-clock-rates = <1536000>; 371 sound-name-prefix = "I2S6"; 372 status = "disabled"; 373 }; 374 375 tegra_dmic1: dmic@2904000 { 376 compatible = "nvidia,tegra194-dmic", 377 "nvidia,tegra210-dmic"; 378 reg = <0x2904000 0x100>; 379 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 380 clock-names = "dmic"; 381 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 382 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 383 assigned-clock-rates = <3072000>; 384 sound-name-prefix = "DMIC1"; 385 status = "disabled"; 386 }; 387 388 tegra_dmic2: dmic@2904100 { 389 compatible = "nvidia,tegra194-dmic", 390 "nvidia,tegra210-dmic"; 391 reg = <0x2904100 0x100>; 392 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 393 clock-names = "dmic"; 394 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 395 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 396 assigned-clock-rates = <3072000>; 397 sound-name-prefix = "DMIC2"; 398 status = "disabled"; 399 }; 400 401 tegra_dmic3: dmic@2904200 { 402 compatible = "nvidia,tegra194-dmic", 403 "nvidia,tegra210-dmic"; 404 reg = <0x2904200 0x100>; 405 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 406 clock-names = "dmic"; 407 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 408 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 409 assigned-clock-rates = <3072000>; 410 sound-name-prefix = "DMIC3"; 411 status = "disabled"; 412 }; 413 414 tegra_dmic4: dmic@2904300 { 415 compatible = "nvidia,tegra194-dmic", 416 "nvidia,tegra210-dmic"; 417 reg = <0x2904300 0x100>; 418 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 419 clock-names = "dmic"; 420 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 421 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 422 assigned-clock-rates = <3072000>; 423 sound-name-prefix = "DMIC4"; 424 status = "disabled"; 425 }; 426 427 tegra_dspk1: dspk@2905000 { 428 compatible = "nvidia,tegra194-dspk", 429 "nvidia,tegra186-dspk"; 430 reg = <0x2905000 0x100>; 431 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 432 clock-names = "dspk"; 433 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 434 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 435 assigned-clock-rates = <12288000>; 436 sound-name-prefix = "DSPK1"; 437 status = "disabled"; 438 }; 439 440 tegra_dspk2: dspk@2905100 { 441 compatible = "nvidia,tegra194-dspk", 442 "nvidia,tegra186-dspk"; 443 reg = <0x2905100 0x100>; 444 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 445 clock-names = "dspk"; 446 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 447 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 448 assigned-clock-rates = <12288000>; 449 sound-name-prefix = "DSPK2"; 450 status = "disabled"; 451 }; 452 453 tegra_sfc1: sfc@2902000 { 454 compatible = "nvidia,tegra194-sfc", 455 "nvidia,tegra210-sfc"; 456 reg = <0x2902000 0x200>; 457 sound-name-prefix = "SFC1"; 458 status = "disabled"; 459 }; 460 461 tegra_sfc2: sfc@2902200 { 462 compatible = "nvidia,tegra194-sfc", 463 "nvidia,tegra210-sfc"; 464 reg = <0x2902200 0x200>; 465 sound-name-prefix = "SFC2"; 466 status = "disabled"; 467 }; 468 469 tegra_sfc3: sfc@2902400 { 470 compatible = "nvidia,tegra194-sfc", 471 "nvidia,tegra210-sfc"; 472 reg = <0x2902400 0x200>; 473 sound-name-prefix = "SFC3"; 474 status = "disabled"; 475 }; 476 477 tegra_sfc4: sfc@2902600 { 478 compatible = "nvidia,tegra194-sfc", 479 "nvidia,tegra210-sfc"; 480 reg = <0x2902600 0x200>; 481 sound-name-prefix = "SFC4"; 482 status = "disabled"; 483 }; 484 485 tegra_mvc1: mvc@290a000 { 486 compatible = "nvidia,tegra194-mvc", 487 "nvidia,tegra210-mvc"; 488 reg = <0x290a000 0x200>; 489 sound-name-prefix = "MVC1"; 490 status = "disabled"; 491 }; 492 493 tegra_mvc2: mvc@290a200 { 494 compatible = "nvidia,tegra194-mvc", 495 "nvidia,tegra210-mvc"; 496 reg = <0x290a200 0x200>; 497 sound-name-prefix = "MVC2"; 498 status = "disabled"; 499 }; 500 501 tegra_amx1: amx@2903000 { 502 compatible = "nvidia,tegra194-amx"; 503 reg = <0x2903000 0x100>; 504 sound-name-prefix = "AMX1"; 505 status = "disabled"; 506 }; 507 508 tegra_amx2: amx@2903100 { 509 compatible = "nvidia,tegra194-amx"; 510 reg = <0x2903100 0x100>; 511 sound-name-prefix = "AMX2"; 512 status = "disabled"; 513 }; 514 515 tegra_amx3: amx@2903200 { 516 compatible = "nvidia,tegra194-amx"; 517 reg = <0x2903200 0x100>; 518 sound-name-prefix = "AMX3"; 519 status = "disabled"; 520 }; 521 522 tegra_amx4: amx@2903300 { 523 compatible = "nvidia,tegra194-amx"; 524 reg = <0x2903300 0x100>; 525 sound-name-prefix = "AMX4"; 526 status = "disabled"; 527 }; 528 529 tegra_adx1: adx@2903800 { 530 compatible = "nvidia,tegra194-adx", 531 "nvidia,tegra210-adx"; 532 reg = <0x2903800 0x100>; 533 sound-name-prefix = "ADX1"; 534 status = "disabled"; 535 }; 536 537 tegra_adx2: adx@2903900 { 538 compatible = "nvidia,tegra194-adx", 539 "nvidia,tegra210-adx"; 540 reg = <0x2903900 0x100>; 541 sound-name-prefix = "ADX2"; 542 status = "disabled"; 543 }; 544 545 tegra_adx3: adx@2903a00 { 546 compatible = "nvidia,tegra194-adx", 547 "nvidia,tegra210-adx"; 548 reg = <0x2903a00 0x100>; 549 sound-name-prefix = "ADX3"; 550 status = "disabled"; 551 }; 552 553 tegra_adx4: adx@2903b00 { 554 compatible = "nvidia,tegra194-adx", 555 "nvidia,tegra210-adx"; 556 reg = <0x2903b00 0x100>; 557 sound-name-prefix = "ADX4"; 558 status = "disabled"; 559 }; 560 561 tegra_amixer: amixer@290bb00 { 562 compatible = "nvidia,tegra194-amixer", 563 "nvidia,tegra210-amixer"; 564 reg = <0x290bb00 0x800>; 565 sound-name-prefix = "MIXER1"; 566 status = "disabled"; 567 }; 568 }; 569 }; 570 571 pinmux: pinmux@2430000 { 572 compatible = "nvidia,tegra194-pinmux"; 573 reg = <0x2430000 0x17000>, 574 <0xc300000 0x4000>; 575 576 status = "okay"; 577 578 pex_rst_c5_out_state: pex_rst_c5_out { 579 pex_rst { 580 nvidia,pins = "pex_l5_rst_n_pgg1"; 581 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 582 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 583 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 584 nvidia,tristate = <TEGRA_PIN_DISABLE>; 585 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 586 }; 587 }; 588 589 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 590 clkreq { 591 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 592 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 593 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 594 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 595 nvidia,tristate = <TEGRA_PIN_DISABLE>; 596 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 597 }; 598 }; 599 }; 600 601 mc: memory-controller@2c00000 { 602 compatible = "nvidia,tegra194-mc"; 603 reg = <0x02c00000 0x100000>, 604 <0x02b80000 0x040000>, 605 <0x01700000 0x100000>; 606 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 607 #interconnect-cells = <1>; 608 status = "disabled"; 609 610 #address-cells = <2>; 611 #size-cells = <2>; 612 613 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 614 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 615 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 616 617 /* 618 * Bit 39 of addresses passing through the memory 619 * controller selects the XBAR format used when memory 620 * is accessed. This is used to transparently access 621 * memory in the XBAR format used by the discrete GPU 622 * (bit 39 set) or Tegra (bit 39 clear). 623 * 624 * As a consequence, the operating system must ensure 625 * that bit 39 is never used implicitly, for example 626 * via an I/O virtual address mapping of an IOMMU. If 627 * devices require access to the XBAR switch, their 628 * drivers must set this bit explicitly. 629 * 630 * Limit the DMA range for memory clients to [38:0]. 631 */ 632 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 633 634 emc: external-memory-controller@2c60000 { 635 compatible = "nvidia,tegra194-emc"; 636 reg = <0x0 0x02c60000 0x0 0x90000>, 637 <0x0 0x01780000 0x0 0x80000>; 638 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&bpmp TEGRA194_CLK_EMC>; 640 clock-names = "emc"; 641 642 #interconnect-cells = <0>; 643 644 nvidia,bpmp = <&bpmp>; 645 }; 646 }; 647 648 uarta: serial@3100000 { 649 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 650 reg = <0x03100000 0x40>; 651 reg-shift = <2>; 652 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&bpmp TEGRA194_CLK_UARTA>; 654 clock-names = "serial"; 655 resets = <&bpmp TEGRA194_RESET_UARTA>; 656 reset-names = "serial"; 657 status = "disabled"; 658 }; 659 660 uartb: serial@3110000 { 661 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 662 reg = <0x03110000 0x40>; 663 reg-shift = <2>; 664 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&bpmp TEGRA194_CLK_UARTB>; 666 clock-names = "serial"; 667 resets = <&bpmp TEGRA194_RESET_UARTB>; 668 reset-names = "serial"; 669 status = "disabled"; 670 }; 671 672 uartd: serial@3130000 { 673 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 674 reg = <0x03130000 0x40>; 675 reg-shift = <2>; 676 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&bpmp TEGRA194_CLK_UARTD>; 678 clock-names = "serial"; 679 resets = <&bpmp TEGRA194_RESET_UARTD>; 680 reset-names = "serial"; 681 status = "disabled"; 682 }; 683 684 uarte: serial@3140000 { 685 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 686 reg = <0x03140000 0x40>; 687 reg-shift = <2>; 688 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&bpmp TEGRA194_CLK_UARTE>; 690 clock-names = "serial"; 691 resets = <&bpmp TEGRA194_RESET_UARTE>; 692 reset-names = "serial"; 693 status = "disabled"; 694 }; 695 696 uartf: serial@3150000 { 697 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 698 reg = <0x03150000 0x40>; 699 reg-shift = <2>; 700 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&bpmp TEGRA194_CLK_UARTF>; 702 clock-names = "serial"; 703 resets = <&bpmp TEGRA194_RESET_UARTF>; 704 reset-names = "serial"; 705 status = "disabled"; 706 }; 707 708 gen1_i2c: i2c@3160000 { 709 compatible = "nvidia,tegra194-i2c"; 710 reg = <0x03160000 0x10000>; 711 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 clocks = <&bpmp TEGRA194_CLK_I2C1>; 715 clock-names = "div-clk"; 716 resets = <&bpmp TEGRA194_RESET_I2C1>; 717 reset-names = "i2c"; 718 status = "disabled"; 719 }; 720 721 uarth: serial@3170000 { 722 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 723 reg = <0x03170000 0x40>; 724 reg-shift = <2>; 725 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&bpmp TEGRA194_CLK_UARTH>; 727 clock-names = "serial"; 728 resets = <&bpmp TEGRA194_RESET_UARTH>; 729 reset-names = "serial"; 730 status = "disabled"; 731 }; 732 733 cam_i2c: i2c@3180000 { 734 compatible = "nvidia,tegra194-i2c"; 735 reg = <0x03180000 0x10000>; 736 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 737 #address-cells = <1>; 738 #size-cells = <0>; 739 clocks = <&bpmp TEGRA194_CLK_I2C3>; 740 clock-names = "div-clk"; 741 resets = <&bpmp TEGRA194_RESET_I2C3>; 742 reset-names = "i2c"; 743 status = "disabled"; 744 }; 745 746 /* shares pads with dpaux1 */ 747 dp_aux_ch1_i2c: i2c@3190000 { 748 compatible = "nvidia,tegra194-i2c"; 749 reg = <0x03190000 0x10000>; 750 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 clocks = <&bpmp TEGRA194_CLK_I2C4>; 754 clock-names = "div-clk"; 755 resets = <&bpmp TEGRA194_RESET_I2C4>; 756 reset-names = "i2c"; 757 pinctrl-0 = <&state_dpaux1_i2c>; 758 pinctrl-1 = <&state_dpaux1_off>; 759 pinctrl-names = "default", "idle"; 760 status = "disabled"; 761 }; 762 763 /* shares pads with dpaux0 */ 764 dp_aux_ch0_i2c: i2c@31b0000 { 765 compatible = "nvidia,tegra194-i2c"; 766 reg = <0x031b0000 0x10000>; 767 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 clocks = <&bpmp TEGRA194_CLK_I2C6>; 771 clock-names = "div-clk"; 772 resets = <&bpmp TEGRA194_RESET_I2C6>; 773 reset-names = "i2c"; 774 pinctrl-0 = <&state_dpaux0_i2c>; 775 pinctrl-1 = <&state_dpaux0_off>; 776 pinctrl-names = "default", "idle"; 777 status = "disabled"; 778 }; 779 780 /* shares pads with dpaux2 */ 781 dp_aux_ch2_i2c: i2c@31c0000 { 782 compatible = "nvidia,tegra194-i2c"; 783 reg = <0x031c0000 0x10000>; 784 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 clocks = <&bpmp TEGRA194_CLK_I2C7>; 788 clock-names = "div-clk"; 789 resets = <&bpmp TEGRA194_RESET_I2C7>; 790 reset-names = "i2c"; 791 pinctrl-0 = <&state_dpaux2_i2c>; 792 pinctrl-1 = <&state_dpaux2_off>; 793 pinctrl-names = "default", "idle"; 794 status = "disabled"; 795 }; 796 797 /* shares pads with dpaux3 */ 798 dp_aux_ch3_i2c: i2c@31e0000 { 799 compatible = "nvidia,tegra194-i2c"; 800 reg = <0x031e0000 0x10000>; 801 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 clocks = <&bpmp TEGRA194_CLK_I2C9>; 805 clock-names = "div-clk"; 806 resets = <&bpmp TEGRA194_RESET_I2C9>; 807 reset-names = "i2c"; 808 pinctrl-0 = <&state_dpaux3_i2c>; 809 pinctrl-1 = <&state_dpaux3_off>; 810 pinctrl-names = "default", "idle"; 811 status = "disabled"; 812 }; 813 814 spi@3270000 { 815 compatible = "nvidia,tegra194-qspi"; 816 reg = <0x3270000 0x1000>; 817 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 821 <&bpmp TEGRA194_CLK_QSPI0_PM>; 822 clock-names = "qspi", "qspi_out"; 823 resets = <&bpmp TEGRA194_RESET_QSPI0>; 824 reset-names = "qspi"; 825 status = "disabled"; 826 }; 827 828 spi@3300000 { 829 compatible = "nvidia,tegra194-qspi"; 830 reg = <0x3300000 0x1000>; 831 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 835 <&bpmp TEGRA194_CLK_QSPI1_PM>; 836 clock-names = "qspi", "qspi_out"; 837 resets = <&bpmp TEGRA194_RESET_QSPI1>; 838 reset-names = "qspi"; 839 status = "disabled"; 840 }; 841 842 pwm1: pwm@3280000 { 843 compatible = "nvidia,tegra194-pwm", 844 "nvidia,tegra186-pwm"; 845 reg = <0x3280000 0x10000>; 846 clocks = <&bpmp TEGRA194_CLK_PWM1>; 847 clock-names = "pwm"; 848 resets = <&bpmp TEGRA194_RESET_PWM1>; 849 reset-names = "pwm"; 850 status = "disabled"; 851 #pwm-cells = <2>; 852 }; 853 854 pwm2: pwm@3290000 { 855 compatible = "nvidia,tegra194-pwm", 856 "nvidia,tegra186-pwm"; 857 reg = <0x3290000 0x10000>; 858 clocks = <&bpmp TEGRA194_CLK_PWM2>; 859 clock-names = "pwm"; 860 resets = <&bpmp TEGRA194_RESET_PWM2>; 861 reset-names = "pwm"; 862 status = "disabled"; 863 #pwm-cells = <2>; 864 }; 865 866 pwm3: pwm@32a0000 { 867 compatible = "nvidia,tegra194-pwm", 868 "nvidia,tegra186-pwm"; 869 reg = <0x32a0000 0x10000>; 870 clocks = <&bpmp TEGRA194_CLK_PWM3>; 871 clock-names = "pwm"; 872 resets = <&bpmp TEGRA194_RESET_PWM3>; 873 reset-names = "pwm"; 874 status = "disabled"; 875 #pwm-cells = <2>; 876 }; 877 878 pwm5: pwm@32c0000 { 879 compatible = "nvidia,tegra194-pwm", 880 "nvidia,tegra186-pwm"; 881 reg = <0x32c0000 0x10000>; 882 clocks = <&bpmp TEGRA194_CLK_PWM5>; 883 clock-names = "pwm"; 884 resets = <&bpmp TEGRA194_RESET_PWM5>; 885 reset-names = "pwm"; 886 status = "disabled"; 887 #pwm-cells = <2>; 888 }; 889 890 pwm6: pwm@32d0000 { 891 compatible = "nvidia,tegra194-pwm", 892 "nvidia,tegra186-pwm"; 893 reg = <0x32d0000 0x10000>; 894 clocks = <&bpmp TEGRA194_CLK_PWM6>; 895 clock-names = "pwm"; 896 resets = <&bpmp TEGRA194_RESET_PWM6>; 897 reset-names = "pwm"; 898 status = "disabled"; 899 #pwm-cells = <2>; 900 }; 901 902 pwm7: pwm@32e0000 { 903 compatible = "nvidia,tegra194-pwm", 904 "nvidia,tegra186-pwm"; 905 reg = <0x32e0000 0x10000>; 906 clocks = <&bpmp TEGRA194_CLK_PWM7>; 907 clock-names = "pwm"; 908 resets = <&bpmp TEGRA194_RESET_PWM7>; 909 reset-names = "pwm"; 910 status = "disabled"; 911 #pwm-cells = <2>; 912 }; 913 914 pwm8: pwm@32f0000 { 915 compatible = "nvidia,tegra194-pwm", 916 "nvidia,tegra186-pwm"; 917 reg = <0x32f0000 0x10000>; 918 clocks = <&bpmp TEGRA194_CLK_PWM8>; 919 clock-names = "pwm"; 920 resets = <&bpmp TEGRA194_RESET_PWM8>; 921 reset-names = "pwm"; 922 status = "disabled"; 923 #pwm-cells = <2>; 924 }; 925 926 sdmmc1: mmc@3400000 { 927 compatible = "nvidia,tegra194-sdhci"; 928 reg = <0x03400000 0x10000>; 929 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 931 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 932 clock-names = "sdhci", "tmclk"; 933 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 934 reset-names = "sdhci"; 935 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 936 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 937 interconnect-names = "dma-mem", "write"; 938 iommus = <&smmu TEGRA194_SID_SDMMC1>; 939 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 940 pinctrl-0 = <&sdmmc1_3v3>; 941 pinctrl-1 = <&sdmmc1_1v8>; 942 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 943 <0x07>; 944 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 945 <0x07>; 946 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 947 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 948 <0x07>; 949 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 950 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 951 nvidia,default-tap = <0x9>; 952 nvidia,default-trim = <0x5>; 953 sd-uhs-sdr25; 954 sd-uhs-sdr50; 955 sd-uhs-ddr50; 956 sd-uhs-sdr104; 957 status = "disabled"; 958 }; 959 960 sdmmc3: mmc@3440000 { 961 compatible = "nvidia,tegra194-sdhci"; 962 reg = <0x03440000 0x10000>; 963 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 965 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 966 clock-names = "sdhci", "tmclk"; 967 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 968 reset-names = "sdhci"; 969 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 970 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 971 interconnect-names = "dma-mem", "write"; 972 iommus = <&smmu TEGRA194_SID_SDMMC3>; 973 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 974 pinctrl-0 = <&sdmmc3_3v3>; 975 pinctrl-1 = <&sdmmc3_1v8>; 976 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 977 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 978 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 979 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 980 <0x07>; 981 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 982 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 983 <0x07>; 984 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 985 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 986 nvidia,default-tap = <0x9>; 987 nvidia,default-trim = <0x5>; 988 sd-uhs-sdr25; 989 sd-uhs-sdr50; 990 sd-uhs-ddr50; 991 sd-uhs-sdr104; 992 status = "disabled"; 993 }; 994 995 sdmmc4: mmc@3460000 { 996 compatible = "nvidia,tegra194-sdhci"; 997 reg = <0x03460000 0x10000>; 998 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1000 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1001 clock-names = "sdhci", "tmclk"; 1002 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1003 <&bpmp TEGRA194_CLK_PLLC4>; 1004 assigned-clock-parents = 1005 <&bpmp TEGRA194_CLK_PLLC4>; 1006 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1007 reset-names = "sdhci"; 1008 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1009 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1010 interconnect-names = "dma-mem", "write"; 1011 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1012 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1013 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1014 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1015 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1016 <0x0a>; 1017 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1018 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1019 <0x0a>; 1020 nvidia,default-tap = <0x8>; 1021 nvidia,default-trim = <0x14>; 1022 nvidia,dqs-trim = <40>; 1023 cap-mmc-highspeed; 1024 mmc-ddr-1_8v; 1025 mmc-hs200-1_8v; 1026 mmc-hs400-1_8v; 1027 mmc-hs400-enhanced-strobe; 1028 supports-cqe; 1029 status = "disabled"; 1030 }; 1031 1032 hda@3510000 { 1033 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 1034 reg = <0x3510000 0x10000>; 1035 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1036 clocks = <&bpmp TEGRA194_CLK_HDA>, 1037 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1038 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1039 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1040 resets = <&bpmp TEGRA194_RESET_HDA>, 1041 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1042 reset-names = "hda", "hda2hdmi"; 1043 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1044 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1045 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1046 interconnect-names = "dma-mem", "write"; 1047 iommus = <&smmu TEGRA194_SID_HDA>; 1048 status = "disabled"; 1049 }; 1050 1051 xusb_padctl: padctl@3520000 { 1052 compatible = "nvidia,tegra194-xusb-padctl"; 1053 reg = <0x03520000 0x1000>, 1054 <0x03540000 0x1000>; 1055 reg-names = "padctl", "ao"; 1056 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1057 1058 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1059 reset-names = "padctl"; 1060 1061 status = "disabled"; 1062 1063 pads { 1064 usb2 { 1065 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1066 clock-names = "trk"; 1067 1068 lanes { 1069 usb2-0 { 1070 nvidia,function = "xusb"; 1071 status = "disabled"; 1072 #phy-cells = <0>; 1073 }; 1074 1075 usb2-1 { 1076 nvidia,function = "xusb"; 1077 status = "disabled"; 1078 #phy-cells = <0>; 1079 }; 1080 1081 usb2-2 { 1082 nvidia,function = "xusb"; 1083 status = "disabled"; 1084 #phy-cells = <0>; 1085 }; 1086 1087 usb2-3 { 1088 nvidia,function = "xusb"; 1089 status = "disabled"; 1090 #phy-cells = <0>; 1091 }; 1092 }; 1093 }; 1094 1095 usb3 { 1096 lanes { 1097 usb3-0 { 1098 nvidia,function = "xusb"; 1099 status = "disabled"; 1100 #phy-cells = <0>; 1101 }; 1102 1103 usb3-1 { 1104 nvidia,function = "xusb"; 1105 status = "disabled"; 1106 #phy-cells = <0>; 1107 }; 1108 1109 usb3-2 { 1110 nvidia,function = "xusb"; 1111 status = "disabled"; 1112 #phy-cells = <0>; 1113 }; 1114 1115 usb3-3 { 1116 nvidia,function = "xusb"; 1117 status = "disabled"; 1118 #phy-cells = <0>; 1119 }; 1120 }; 1121 }; 1122 }; 1123 1124 ports { 1125 usb2-0 { 1126 status = "disabled"; 1127 }; 1128 1129 usb2-1 { 1130 status = "disabled"; 1131 }; 1132 1133 usb2-2 { 1134 status = "disabled"; 1135 }; 1136 1137 usb2-3 { 1138 status = "disabled"; 1139 }; 1140 1141 usb3-0 { 1142 status = "disabled"; 1143 }; 1144 1145 usb3-1 { 1146 status = "disabled"; 1147 }; 1148 1149 usb3-2 { 1150 status = "disabled"; 1151 }; 1152 1153 usb3-3 { 1154 status = "disabled"; 1155 }; 1156 }; 1157 }; 1158 1159 usb@3550000 { 1160 compatible = "nvidia,tegra194-xudc"; 1161 reg = <0x03550000 0x8000>, 1162 <0x03558000 0x1000>; 1163 reg-names = "base", "fpci"; 1164 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1165 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1166 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1167 <&bpmp TEGRA194_CLK_XUSB_SS>, 1168 <&bpmp TEGRA194_CLK_XUSB_FS>; 1169 clock-names = "dev", "ss", "ss_src", "fs_src"; 1170 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1171 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1172 interconnect-names = "dma-mem", "write"; 1173 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1174 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1175 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1176 power-domain-names = "dev", "ss"; 1177 nvidia,xusb-padctl = <&xusb_padctl>; 1178 status = "disabled"; 1179 }; 1180 1181 usb@3610000 { 1182 compatible = "nvidia,tegra194-xusb"; 1183 reg = <0x03610000 0x40000>, 1184 <0x03600000 0x10000>; 1185 reg-names = "hcd", "fpci"; 1186 1187 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1189 1190 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1191 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1192 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1193 <&bpmp TEGRA194_CLK_XUSB_SS>, 1194 <&bpmp TEGRA194_CLK_CLK_M>, 1195 <&bpmp TEGRA194_CLK_XUSB_FS>, 1196 <&bpmp TEGRA194_CLK_UTMIPLL>, 1197 <&bpmp TEGRA194_CLK_CLK_M>, 1198 <&bpmp TEGRA194_CLK_PLLE>; 1199 clock-names = "xusb_host", "xusb_falcon_src", 1200 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1201 "xusb_fs_src", "pll_u_480m", "clk_m", 1202 "pll_e"; 1203 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1204 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1205 interconnect-names = "dma-mem", "write"; 1206 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1207 1208 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1209 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1210 power-domain-names = "xusb_host", "xusb_ss"; 1211 1212 nvidia,xusb-padctl = <&xusb_padctl>; 1213 status = "disabled"; 1214 }; 1215 1216 fuse@3820000 { 1217 compatible = "nvidia,tegra194-efuse"; 1218 reg = <0x03820000 0x10000>; 1219 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1220 clock-names = "fuse"; 1221 }; 1222 1223 gic: interrupt-controller@3881000 { 1224 compatible = "arm,gic-400"; 1225 #interrupt-cells = <3>; 1226 interrupt-controller; 1227 reg = <0x03881000 0x1000>, 1228 <0x03882000 0x2000>, 1229 <0x03884000 0x2000>, 1230 <0x03886000 0x2000>; 1231 interrupts = <GIC_PPI 9 1232 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1233 interrupt-parent = <&gic>; 1234 }; 1235 1236 cec@3960000 { 1237 compatible = "nvidia,tegra194-cec"; 1238 reg = <0x03960000 0x10000>; 1239 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&bpmp TEGRA194_CLK_CEC>; 1241 clock-names = "cec"; 1242 status = "disabled"; 1243 }; 1244 1245 hsp_top0: hsp@3c00000 { 1246 compatible = "nvidia,tegra194-hsp"; 1247 reg = <0x03c00000 0xa0000>; 1248 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1257 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1258 "shared3", "shared4", "shared5", "shared6", 1259 "shared7"; 1260 #mbox-cells = <2>; 1261 }; 1262 1263 p2u_hsio_0: phy@3e10000 { 1264 compatible = "nvidia,tegra194-p2u"; 1265 reg = <0x03e10000 0x10000>; 1266 reg-names = "ctl"; 1267 1268 #phy-cells = <0>; 1269 }; 1270 1271 p2u_hsio_1: phy@3e20000 { 1272 compatible = "nvidia,tegra194-p2u"; 1273 reg = <0x03e20000 0x10000>; 1274 reg-names = "ctl"; 1275 1276 #phy-cells = <0>; 1277 }; 1278 1279 p2u_hsio_2: phy@3e30000 { 1280 compatible = "nvidia,tegra194-p2u"; 1281 reg = <0x03e30000 0x10000>; 1282 reg-names = "ctl"; 1283 1284 #phy-cells = <0>; 1285 }; 1286 1287 p2u_hsio_3: phy@3e40000 { 1288 compatible = "nvidia,tegra194-p2u"; 1289 reg = <0x03e40000 0x10000>; 1290 reg-names = "ctl"; 1291 1292 #phy-cells = <0>; 1293 }; 1294 1295 p2u_hsio_4: phy@3e50000 { 1296 compatible = "nvidia,tegra194-p2u"; 1297 reg = <0x03e50000 0x10000>; 1298 reg-names = "ctl"; 1299 1300 #phy-cells = <0>; 1301 }; 1302 1303 p2u_hsio_5: phy@3e60000 { 1304 compatible = "nvidia,tegra194-p2u"; 1305 reg = <0x03e60000 0x10000>; 1306 reg-names = "ctl"; 1307 1308 #phy-cells = <0>; 1309 }; 1310 1311 p2u_hsio_6: phy@3e70000 { 1312 compatible = "nvidia,tegra194-p2u"; 1313 reg = <0x03e70000 0x10000>; 1314 reg-names = "ctl"; 1315 1316 #phy-cells = <0>; 1317 }; 1318 1319 p2u_hsio_7: phy@3e80000 { 1320 compatible = "nvidia,tegra194-p2u"; 1321 reg = <0x03e80000 0x10000>; 1322 reg-names = "ctl"; 1323 1324 #phy-cells = <0>; 1325 }; 1326 1327 p2u_hsio_8: phy@3e90000 { 1328 compatible = "nvidia,tegra194-p2u"; 1329 reg = <0x03e90000 0x10000>; 1330 reg-names = "ctl"; 1331 1332 #phy-cells = <0>; 1333 }; 1334 1335 p2u_hsio_9: phy@3ea0000 { 1336 compatible = "nvidia,tegra194-p2u"; 1337 reg = <0x03ea0000 0x10000>; 1338 reg-names = "ctl"; 1339 1340 #phy-cells = <0>; 1341 }; 1342 1343 p2u_nvhs_0: phy@3eb0000 { 1344 compatible = "nvidia,tegra194-p2u"; 1345 reg = <0x03eb0000 0x10000>; 1346 reg-names = "ctl"; 1347 1348 #phy-cells = <0>; 1349 }; 1350 1351 p2u_nvhs_1: phy@3ec0000 { 1352 compatible = "nvidia,tegra194-p2u"; 1353 reg = <0x03ec0000 0x10000>; 1354 reg-names = "ctl"; 1355 1356 #phy-cells = <0>; 1357 }; 1358 1359 p2u_nvhs_2: phy@3ed0000 { 1360 compatible = "nvidia,tegra194-p2u"; 1361 reg = <0x03ed0000 0x10000>; 1362 reg-names = "ctl"; 1363 1364 #phy-cells = <0>; 1365 }; 1366 1367 p2u_nvhs_3: phy@3ee0000 { 1368 compatible = "nvidia,tegra194-p2u"; 1369 reg = <0x03ee0000 0x10000>; 1370 reg-names = "ctl"; 1371 1372 #phy-cells = <0>; 1373 }; 1374 1375 p2u_nvhs_4: phy@3ef0000 { 1376 compatible = "nvidia,tegra194-p2u"; 1377 reg = <0x03ef0000 0x10000>; 1378 reg-names = "ctl"; 1379 1380 #phy-cells = <0>; 1381 }; 1382 1383 p2u_nvhs_5: phy@3f00000 { 1384 compatible = "nvidia,tegra194-p2u"; 1385 reg = <0x03f00000 0x10000>; 1386 reg-names = "ctl"; 1387 1388 #phy-cells = <0>; 1389 }; 1390 1391 p2u_nvhs_6: phy@3f10000 { 1392 compatible = "nvidia,tegra194-p2u"; 1393 reg = <0x03f10000 0x10000>; 1394 reg-names = "ctl"; 1395 1396 #phy-cells = <0>; 1397 }; 1398 1399 p2u_nvhs_7: phy@3f20000 { 1400 compatible = "nvidia,tegra194-p2u"; 1401 reg = <0x03f20000 0x10000>; 1402 reg-names = "ctl"; 1403 1404 #phy-cells = <0>; 1405 }; 1406 1407 p2u_hsio_10: phy@3f30000 { 1408 compatible = "nvidia,tegra194-p2u"; 1409 reg = <0x03f30000 0x10000>; 1410 reg-names = "ctl"; 1411 1412 #phy-cells = <0>; 1413 }; 1414 1415 p2u_hsio_11: phy@3f40000 { 1416 compatible = "nvidia,tegra194-p2u"; 1417 reg = <0x03f40000 0x10000>; 1418 reg-names = "ctl"; 1419 1420 #phy-cells = <0>; 1421 }; 1422 1423 hsp_aon: hsp@c150000 { 1424 compatible = "nvidia,tegra194-hsp"; 1425 reg = <0x0c150000 0x90000>; 1426 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1430 /* 1431 * Shared interrupt 0 is routed only to AON/SPE, so 1432 * we only have 4 shared interrupts for the CCPLEX. 1433 */ 1434 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1435 #mbox-cells = <2>; 1436 }; 1437 1438 gen2_i2c: i2c@c240000 { 1439 compatible = "nvidia,tegra194-i2c"; 1440 reg = <0x0c240000 0x10000>; 1441 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1445 clock-names = "div-clk"; 1446 resets = <&bpmp TEGRA194_RESET_I2C2>; 1447 reset-names = "i2c"; 1448 status = "disabled"; 1449 }; 1450 1451 gen8_i2c: i2c@c250000 { 1452 compatible = "nvidia,tegra194-i2c"; 1453 reg = <0x0c250000 0x10000>; 1454 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1455 #address-cells = <1>; 1456 #size-cells = <0>; 1457 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1458 clock-names = "div-clk"; 1459 resets = <&bpmp TEGRA194_RESET_I2C8>; 1460 reset-names = "i2c"; 1461 status = "disabled"; 1462 }; 1463 1464 uartc: serial@c280000 { 1465 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1466 reg = <0x0c280000 0x40>; 1467 reg-shift = <2>; 1468 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1469 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1470 clock-names = "serial"; 1471 resets = <&bpmp TEGRA194_RESET_UARTC>; 1472 reset-names = "serial"; 1473 status = "disabled"; 1474 }; 1475 1476 uartg: serial@c290000 { 1477 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1478 reg = <0x0c290000 0x40>; 1479 reg-shift = <2>; 1480 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1481 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1482 clock-names = "serial"; 1483 resets = <&bpmp TEGRA194_RESET_UARTG>; 1484 reset-names = "serial"; 1485 status = "disabled"; 1486 }; 1487 1488 rtc: rtc@c2a0000 { 1489 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1490 reg = <0x0c2a0000 0x10000>; 1491 interrupt-parent = <&pmc>; 1492 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1493 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1494 clock-names = "rtc"; 1495 status = "disabled"; 1496 }; 1497 1498 gpio_aon: gpio@c2f0000 { 1499 compatible = "nvidia,tegra194-gpio-aon"; 1500 reg-names = "security", "gpio"; 1501 reg = <0xc2f0000 0x1000>, 1502 <0xc2f1000 0x1000>; 1503 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1507 gpio-controller; 1508 #gpio-cells = <2>; 1509 interrupt-controller; 1510 #interrupt-cells = <2>; 1511 }; 1512 1513 pwm4: pwm@c340000 { 1514 compatible = "nvidia,tegra194-pwm", 1515 "nvidia,tegra186-pwm"; 1516 reg = <0xc340000 0x10000>; 1517 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1518 clock-names = "pwm"; 1519 resets = <&bpmp TEGRA194_RESET_PWM4>; 1520 reset-names = "pwm"; 1521 status = "disabled"; 1522 #pwm-cells = <2>; 1523 }; 1524 1525 pmc: pmc@c360000 { 1526 compatible = "nvidia,tegra194-pmc"; 1527 reg = <0x0c360000 0x10000>, 1528 <0x0c370000 0x10000>, 1529 <0x0c380000 0x10000>, 1530 <0x0c390000 0x10000>, 1531 <0x0c3a0000 0x10000>; 1532 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1533 1534 #interrupt-cells = <2>; 1535 interrupt-controller; 1536 sdmmc1_3v3: sdmmc1-3v3 { 1537 pins = "sdmmc1-hv"; 1538 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1539 }; 1540 1541 sdmmc1_1v8: sdmmc1-1v8 { 1542 pins = "sdmmc1-hv"; 1543 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1544 }; 1545 sdmmc3_3v3: sdmmc3-3v3 { 1546 pins = "sdmmc3-hv"; 1547 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1548 }; 1549 1550 sdmmc3_1v8: sdmmc3-1v8 { 1551 pins = "sdmmc3-hv"; 1552 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1553 }; 1554 1555 }; 1556 1557 iommu@10000000 { 1558 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1559 reg = <0x10000000 0x800000>; 1560 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1625 stream-match-mask = <0x7f80>; 1626 #global-interrupts = <1>; 1627 #iommu-cells = <1>; 1628 1629 nvidia,memory-controller = <&mc>; 1630 status = "okay"; 1631 }; 1632 1633 smmu: iommu@12000000 { 1634 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1635 reg = <0x12000000 0x800000>, 1636 <0x11000000 0x800000>; 1637 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1703 stream-match-mask = <0x7f80>; 1704 #global-interrupts = <2>; 1705 #iommu-cells = <1>; 1706 1707 nvidia,memory-controller = <&mc>; 1708 status = "okay"; 1709 }; 1710 1711 host1x@13e00000 { 1712 compatible = "nvidia,tegra194-host1x"; 1713 reg = <0x13e00000 0x10000>, 1714 <0x13e10000 0x10000>; 1715 reg-names = "hypervisor", "vm"; 1716 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1718 interrupt-names = "syncpt", "host1x"; 1719 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1720 clock-names = "host1x"; 1721 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1722 reset-names = "host1x"; 1723 1724 #address-cells = <1>; 1725 #size-cells = <1>; 1726 1727 ranges = <0x15000000 0x15000000 0x01000000>; 1728 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1729 interconnect-names = "dma-mem"; 1730 iommus = <&smmu TEGRA194_SID_HOST1X>; 1731 1732 nvdec@15140000 { 1733 compatible = "nvidia,tegra194-nvdec"; 1734 reg = <0x15140000 0x00040000>; 1735 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1736 clock-names = "nvdec"; 1737 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1738 reset-names = "nvdec"; 1739 1740 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1741 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1742 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1743 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1744 interconnect-names = "dma-mem", "read-1", "write"; 1745 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1746 dma-coherent; 1747 1748 nvidia,host1x-class = <0xf5>; 1749 }; 1750 1751 display-hub@15200000 { 1752 compatible = "nvidia,tegra194-display"; 1753 reg = <0x15200000 0x00040000>; 1754 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1755 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1756 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1757 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1758 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1759 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1760 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1761 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1762 "wgrp3", "wgrp4", "wgrp5"; 1763 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1764 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1765 clock-names = "disp", "hub"; 1766 status = "disabled"; 1767 1768 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1769 1770 #address-cells = <1>; 1771 #size-cells = <1>; 1772 1773 ranges = <0x15200000 0x15200000 0x40000>; 1774 1775 display@15200000 { 1776 compatible = "nvidia,tegra194-dc"; 1777 reg = <0x15200000 0x10000>; 1778 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1779 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1780 clock-names = "dc"; 1781 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1782 reset-names = "dc"; 1783 1784 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1785 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1786 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1787 interconnect-names = "dma-mem", "read-1"; 1788 1789 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1790 nvidia,head = <0>; 1791 }; 1792 1793 display@15210000 { 1794 compatible = "nvidia,tegra194-dc"; 1795 reg = <0x15210000 0x10000>; 1796 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1797 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1798 clock-names = "dc"; 1799 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1800 reset-names = "dc"; 1801 1802 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1803 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1804 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1805 interconnect-names = "dma-mem", "read-1"; 1806 1807 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1808 nvidia,head = <1>; 1809 }; 1810 1811 display@15220000 { 1812 compatible = "nvidia,tegra194-dc"; 1813 reg = <0x15220000 0x10000>; 1814 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1815 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1816 clock-names = "dc"; 1817 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1818 reset-names = "dc"; 1819 1820 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1821 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1822 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1823 interconnect-names = "dma-mem", "read-1"; 1824 1825 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1826 nvidia,head = <2>; 1827 }; 1828 1829 display@15230000 { 1830 compatible = "nvidia,tegra194-dc"; 1831 reg = <0x15230000 0x10000>; 1832 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1833 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1834 clock-names = "dc"; 1835 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1836 reset-names = "dc"; 1837 1838 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1839 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1840 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1841 interconnect-names = "dma-mem", "read-1"; 1842 1843 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1844 nvidia,head = <3>; 1845 }; 1846 }; 1847 1848 vic@15340000 { 1849 compatible = "nvidia,tegra194-vic"; 1850 reg = <0x15340000 0x00040000>; 1851 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1852 clocks = <&bpmp TEGRA194_CLK_VIC>; 1853 clock-names = "vic"; 1854 resets = <&bpmp TEGRA194_RESET_VIC>; 1855 reset-names = "vic"; 1856 1857 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1858 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1859 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1860 interconnect-names = "dma-mem", "write"; 1861 iommus = <&smmu TEGRA194_SID_VIC>; 1862 dma-coherent; 1863 }; 1864 1865 nvjpg@15380000 { 1866 compatible = "nvidia,tegra194-nvjpg"; 1867 reg = <0x15380000 0x40000>; 1868 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1869 clock-names = "nvjpg"; 1870 resets = <&bpmp TEGRA194_RESET_NVJPG>; 1871 reset-names = "nvjpg"; 1872 1873 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1874 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1875 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1876 interconnect-names = "dma-mem", "write"; 1877 iommus = <&smmu TEGRA194_SID_NVJPG>; 1878 dma-coherent; 1879 }; 1880 1881 nvdec@15480000 { 1882 compatible = "nvidia,tegra194-nvdec"; 1883 reg = <0x15480000 0x00040000>; 1884 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 1885 clock-names = "nvdec"; 1886 resets = <&bpmp TEGRA194_RESET_NVDEC>; 1887 reset-names = "nvdec"; 1888 1889 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 1890 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 1891 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 1892 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 1893 interconnect-names = "dma-mem", "read-1", "write"; 1894 iommus = <&smmu TEGRA194_SID_NVDEC>; 1895 dma-coherent; 1896 1897 nvidia,host1x-class = <0xf0>; 1898 }; 1899 1900 nvenc@154c0000 { 1901 compatible = "nvidia,tegra194-nvenc"; 1902 reg = <0x154c0000 0x40000>; 1903 clocks = <&bpmp TEGRA194_CLK_NVENC>; 1904 clock-names = "nvenc"; 1905 resets = <&bpmp TEGRA194_RESET_NVENC>; 1906 reset-names = "nvenc"; 1907 1908 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 1909 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 1910 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 1911 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 1912 interconnect-names = "dma-mem", "read-1", "write"; 1913 iommus = <&smmu TEGRA194_SID_NVENC>; 1914 dma-coherent; 1915 1916 nvidia,host1x-class = <0x21>; 1917 }; 1918 1919 dpaux0: dpaux@155c0000 { 1920 compatible = "nvidia,tegra194-dpaux"; 1921 reg = <0x155c0000 0x10000>; 1922 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1923 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1924 <&bpmp TEGRA194_CLK_PLLDP>; 1925 clock-names = "dpaux", "parent"; 1926 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1927 reset-names = "dpaux"; 1928 status = "disabled"; 1929 1930 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1931 1932 state_dpaux0_aux: pinmux-aux { 1933 groups = "dpaux-io"; 1934 function = "aux"; 1935 }; 1936 1937 state_dpaux0_i2c: pinmux-i2c { 1938 groups = "dpaux-io"; 1939 function = "i2c"; 1940 }; 1941 1942 state_dpaux0_off: pinmux-off { 1943 groups = "dpaux-io"; 1944 function = "off"; 1945 }; 1946 1947 i2c-bus { 1948 #address-cells = <1>; 1949 #size-cells = <0>; 1950 }; 1951 }; 1952 1953 dpaux1: dpaux@155d0000 { 1954 compatible = "nvidia,tegra194-dpaux"; 1955 reg = <0x155d0000 0x10000>; 1956 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1957 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1958 <&bpmp TEGRA194_CLK_PLLDP>; 1959 clock-names = "dpaux", "parent"; 1960 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1961 reset-names = "dpaux"; 1962 status = "disabled"; 1963 1964 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1965 1966 state_dpaux1_aux: pinmux-aux { 1967 groups = "dpaux-io"; 1968 function = "aux"; 1969 }; 1970 1971 state_dpaux1_i2c: pinmux-i2c { 1972 groups = "dpaux-io"; 1973 function = "i2c"; 1974 }; 1975 1976 state_dpaux1_off: pinmux-off { 1977 groups = "dpaux-io"; 1978 function = "off"; 1979 }; 1980 1981 i2c-bus { 1982 #address-cells = <1>; 1983 #size-cells = <0>; 1984 }; 1985 }; 1986 1987 dpaux2: dpaux@155e0000 { 1988 compatible = "nvidia,tegra194-dpaux"; 1989 reg = <0x155e0000 0x10000>; 1990 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1991 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1992 <&bpmp TEGRA194_CLK_PLLDP>; 1993 clock-names = "dpaux", "parent"; 1994 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1995 reset-names = "dpaux"; 1996 status = "disabled"; 1997 1998 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1999 2000 state_dpaux2_aux: pinmux-aux { 2001 groups = "dpaux-io"; 2002 function = "aux"; 2003 }; 2004 2005 state_dpaux2_i2c: pinmux-i2c { 2006 groups = "dpaux-io"; 2007 function = "i2c"; 2008 }; 2009 2010 state_dpaux2_off: pinmux-off { 2011 groups = "dpaux-io"; 2012 function = "off"; 2013 }; 2014 2015 i2c-bus { 2016 #address-cells = <1>; 2017 #size-cells = <0>; 2018 }; 2019 }; 2020 2021 dpaux3: dpaux@155f0000 { 2022 compatible = "nvidia,tegra194-dpaux"; 2023 reg = <0x155f0000 0x10000>; 2024 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2025 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2026 <&bpmp TEGRA194_CLK_PLLDP>; 2027 clock-names = "dpaux", "parent"; 2028 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2029 reset-names = "dpaux"; 2030 status = "disabled"; 2031 2032 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2033 2034 state_dpaux3_aux: pinmux-aux { 2035 groups = "dpaux-io"; 2036 function = "aux"; 2037 }; 2038 2039 state_dpaux3_i2c: pinmux-i2c { 2040 groups = "dpaux-io"; 2041 function = "i2c"; 2042 }; 2043 2044 state_dpaux3_off: pinmux-off { 2045 groups = "dpaux-io"; 2046 function = "off"; 2047 }; 2048 2049 i2c-bus { 2050 #address-cells = <1>; 2051 #size-cells = <0>; 2052 }; 2053 }; 2054 2055 nvenc@15a80000 { 2056 compatible = "nvidia,tegra194-nvenc"; 2057 reg = <0x15a80000 0x00040000>; 2058 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2059 clock-names = "nvenc"; 2060 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2061 reset-names = "nvenc"; 2062 2063 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2064 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2065 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2066 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2067 interconnect-names = "dma-mem", "read-1", "write"; 2068 iommus = <&smmu TEGRA194_SID_NVENC1>; 2069 dma-coherent; 2070 2071 nvidia,host1x-class = <0x22>; 2072 }; 2073 2074 sor0: sor@15b00000 { 2075 compatible = "nvidia,tegra194-sor"; 2076 reg = <0x15b00000 0x40000>; 2077 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2078 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2079 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2080 <&bpmp TEGRA194_CLK_PLLD>, 2081 <&bpmp TEGRA194_CLK_PLLDP>, 2082 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2083 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2084 clock-names = "sor", "out", "parent", "dp", "safe", 2085 "pad"; 2086 resets = <&bpmp TEGRA194_RESET_SOR0>; 2087 reset-names = "sor"; 2088 pinctrl-0 = <&state_dpaux0_aux>; 2089 pinctrl-1 = <&state_dpaux0_i2c>; 2090 pinctrl-2 = <&state_dpaux0_off>; 2091 pinctrl-names = "aux", "i2c", "off"; 2092 status = "disabled"; 2093 2094 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2095 nvidia,interface = <0>; 2096 }; 2097 2098 sor1: sor@15b40000 { 2099 compatible = "nvidia,tegra194-sor"; 2100 reg = <0x15b40000 0x40000>; 2101 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2102 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2103 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2104 <&bpmp TEGRA194_CLK_PLLD2>, 2105 <&bpmp TEGRA194_CLK_PLLDP>, 2106 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2107 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2108 clock-names = "sor", "out", "parent", "dp", "safe", 2109 "pad"; 2110 resets = <&bpmp TEGRA194_RESET_SOR1>; 2111 reset-names = "sor"; 2112 pinctrl-0 = <&state_dpaux1_aux>; 2113 pinctrl-1 = <&state_dpaux1_i2c>; 2114 pinctrl-2 = <&state_dpaux1_off>; 2115 pinctrl-names = "aux", "i2c", "off"; 2116 status = "disabled"; 2117 2118 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2119 nvidia,interface = <1>; 2120 }; 2121 2122 sor2: sor@15b80000 { 2123 compatible = "nvidia,tegra194-sor"; 2124 reg = <0x15b80000 0x40000>; 2125 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2126 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2127 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2128 <&bpmp TEGRA194_CLK_PLLD3>, 2129 <&bpmp TEGRA194_CLK_PLLDP>, 2130 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2131 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2132 clock-names = "sor", "out", "parent", "dp", "safe", 2133 "pad"; 2134 resets = <&bpmp TEGRA194_RESET_SOR2>; 2135 reset-names = "sor"; 2136 pinctrl-0 = <&state_dpaux2_aux>; 2137 pinctrl-1 = <&state_dpaux2_i2c>; 2138 pinctrl-2 = <&state_dpaux2_off>; 2139 pinctrl-names = "aux", "i2c", "off"; 2140 status = "disabled"; 2141 2142 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2143 nvidia,interface = <2>; 2144 }; 2145 2146 sor3: sor@15bc0000 { 2147 compatible = "nvidia,tegra194-sor"; 2148 reg = <0x15bc0000 0x40000>; 2149 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2150 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2151 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2152 <&bpmp TEGRA194_CLK_PLLD4>, 2153 <&bpmp TEGRA194_CLK_PLLDP>, 2154 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2155 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2156 clock-names = "sor", "out", "parent", "dp", "safe", 2157 "pad"; 2158 resets = <&bpmp TEGRA194_RESET_SOR3>; 2159 reset-names = "sor"; 2160 pinctrl-0 = <&state_dpaux3_aux>; 2161 pinctrl-1 = <&state_dpaux3_i2c>; 2162 pinctrl-2 = <&state_dpaux3_off>; 2163 pinctrl-names = "aux", "i2c", "off"; 2164 status = "disabled"; 2165 2166 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2167 nvidia,interface = <3>; 2168 }; 2169 }; 2170 2171 gpu@17000000 { 2172 compatible = "nvidia,gv11b"; 2173 reg = <0x17000000 0x1000000>, 2174 <0x18000000 0x1000000>; 2175 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2177 interrupt-names = "stall", "nonstall"; 2178 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2179 <&bpmp TEGRA194_CLK_GPU_PWR>, 2180 <&bpmp TEGRA194_CLK_FUSE>; 2181 clock-names = "gpu", "pwr", "fuse"; 2182 resets = <&bpmp TEGRA194_RESET_GPU>; 2183 reset-names = "gpu"; 2184 dma-coherent; 2185 2186 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2187 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2188 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2189 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2190 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2191 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2192 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2193 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2194 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2195 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2196 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2197 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2198 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2199 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2200 "read-1", "read-1-hp", "write-1", 2201 "read-2", "read-2-hp", "write-2", 2202 "read-3", "read-3-hp", "write-3"; 2203 }; 2204 }; 2205 2206 pcie@14100000 { 2207 compatible = "nvidia,tegra194-pcie"; 2208 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2209 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2210 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2211 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2212 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2213 reg-names = "appl", "config", "atu_dma", "dbi"; 2214 2215 status = "disabled"; 2216 2217 #address-cells = <3>; 2218 #size-cells = <2>; 2219 device_type = "pci"; 2220 num-lanes = <1>; 2221 linux,pci-domain = <1>; 2222 2223 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2224 clock-names = "core"; 2225 2226 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2227 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2228 reset-names = "apb", "core"; 2229 2230 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2231 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2232 interrupt-names = "intr", "msi"; 2233 2234 #interrupt-cells = <1>; 2235 interrupt-map-mask = <0 0 0 0>; 2236 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2237 2238 nvidia,bpmp = <&bpmp 1>; 2239 2240 nvidia,aspm-cmrt-us = <60>; 2241 nvidia,aspm-pwr-on-t-us = <20>; 2242 nvidia,aspm-l0s-entrance-latency-us = <3>; 2243 2244 bus-range = <0x0 0xff>; 2245 2246 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2247 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2248 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2249 2250 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2251 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2252 interconnect-names = "dma-mem", "write"; 2253 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2254 iommu-map-mask = <0x0>; 2255 dma-coherent; 2256 }; 2257 2258 pcie@14120000 { 2259 compatible = "nvidia,tegra194-pcie"; 2260 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2261 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2262 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2263 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2264 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2265 reg-names = "appl", "config", "atu_dma", "dbi"; 2266 2267 status = "disabled"; 2268 2269 #address-cells = <3>; 2270 #size-cells = <2>; 2271 device_type = "pci"; 2272 num-lanes = <1>; 2273 linux,pci-domain = <2>; 2274 2275 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2276 clock-names = "core"; 2277 2278 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2279 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2280 reset-names = "apb", "core"; 2281 2282 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2283 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2284 interrupt-names = "intr", "msi"; 2285 2286 #interrupt-cells = <1>; 2287 interrupt-map-mask = <0 0 0 0>; 2288 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2289 2290 nvidia,bpmp = <&bpmp 2>; 2291 2292 nvidia,aspm-cmrt-us = <60>; 2293 nvidia,aspm-pwr-on-t-us = <20>; 2294 nvidia,aspm-l0s-entrance-latency-us = <3>; 2295 2296 bus-range = <0x0 0xff>; 2297 2298 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2299 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2300 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2301 2302 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2303 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2304 interconnect-names = "dma-mem", "write"; 2305 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2306 iommu-map-mask = <0x0>; 2307 dma-coherent; 2308 }; 2309 2310 pcie@14140000 { 2311 compatible = "nvidia,tegra194-pcie"; 2312 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2313 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2314 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2315 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2316 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2317 reg-names = "appl", "config", "atu_dma", "dbi"; 2318 2319 status = "disabled"; 2320 2321 #address-cells = <3>; 2322 #size-cells = <2>; 2323 device_type = "pci"; 2324 num-lanes = <1>; 2325 linux,pci-domain = <3>; 2326 2327 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2328 clock-names = "core"; 2329 2330 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2331 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2332 reset-names = "apb", "core"; 2333 2334 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2335 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2336 interrupt-names = "intr", "msi"; 2337 2338 #interrupt-cells = <1>; 2339 interrupt-map-mask = <0 0 0 0>; 2340 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2341 2342 nvidia,bpmp = <&bpmp 3>; 2343 2344 nvidia,aspm-cmrt-us = <60>; 2345 nvidia,aspm-pwr-on-t-us = <20>; 2346 nvidia,aspm-l0s-entrance-latency-us = <3>; 2347 2348 bus-range = <0x0 0xff>; 2349 2350 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2351 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2352 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2353 2354 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2355 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2356 interconnect-names = "dma-mem", "write"; 2357 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2358 iommu-map-mask = <0x0>; 2359 dma-coherent; 2360 }; 2361 2362 pcie@14160000 { 2363 compatible = "nvidia,tegra194-pcie"; 2364 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2365 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2366 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2367 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2368 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2369 reg-names = "appl", "config", "atu_dma", "dbi"; 2370 2371 status = "disabled"; 2372 2373 #address-cells = <3>; 2374 #size-cells = <2>; 2375 device_type = "pci"; 2376 num-lanes = <4>; 2377 linux,pci-domain = <4>; 2378 2379 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2380 clock-names = "core"; 2381 2382 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2383 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2384 reset-names = "apb", "core"; 2385 2386 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2387 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2388 interrupt-names = "intr", "msi"; 2389 2390 #interrupt-cells = <1>; 2391 interrupt-map-mask = <0 0 0 0>; 2392 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2393 2394 nvidia,bpmp = <&bpmp 4>; 2395 2396 nvidia,aspm-cmrt-us = <60>; 2397 nvidia,aspm-pwr-on-t-us = <20>; 2398 nvidia,aspm-l0s-entrance-latency-us = <3>; 2399 2400 bus-range = <0x0 0xff>; 2401 2402 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2403 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2404 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2405 2406 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2407 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2408 interconnect-names = "dma-mem", "write"; 2409 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2410 iommu-map-mask = <0x0>; 2411 dma-coherent; 2412 }; 2413 2414 pcie@14180000 { 2415 compatible = "nvidia,tegra194-pcie"; 2416 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2417 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2418 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2419 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2420 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2421 reg-names = "appl", "config", "atu_dma", "dbi"; 2422 2423 status = "disabled"; 2424 2425 #address-cells = <3>; 2426 #size-cells = <2>; 2427 device_type = "pci"; 2428 num-lanes = <8>; 2429 linux,pci-domain = <0>; 2430 2431 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2432 clock-names = "core"; 2433 2434 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2435 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2436 reset-names = "apb", "core"; 2437 2438 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2439 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2440 interrupt-names = "intr", "msi"; 2441 2442 #interrupt-cells = <1>; 2443 interrupt-map-mask = <0 0 0 0>; 2444 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2445 2446 nvidia,bpmp = <&bpmp 0>; 2447 2448 nvidia,aspm-cmrt-us = <60>; 2449 nvidia,aspm-pwr-on-t-us = <20>; 2450 nvidia,aspm-l0s-entrance-latency-us = <3>; 2451 2452 bus-range = <0x0 0xff>; 2453 2454 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2455 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2456 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2457 2458 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2459 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2460 interconnect-names = "dma-mem", "write"; 2461 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2462 iommu-map-mask = <0x0>; 2463 dma-coherent; 2464 }; 2465 2466 pcie@141a0000 { 2467 compatible = "nvidia,tegra194-pcie"; 2468 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2469 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2470 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2471 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2472 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2473 reg-names = "appl", "config", "atu_dma", "dbi"; 2474 2475 status = "disabled"; 2476 2477 #address-cells = <3>; 2478 #size-cells = <2>; 2479 device_type = "pci"; 2480 num-lanes = <8>; 2481 linux,pci-domain = <5>; 2482 2483 pinctrl-names = "default"; 2484 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2485 2486 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2487 clock-names = "core"; 2488 2489 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2490 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2491 reset-names = "apb", "core"; 2492 2493 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2494 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2495 interrupt-names = "intr", "msi"; 2496 2497 nvidia,bpmp = <&bpmp 5>; 2498 2499 #interrupt-cells = <1>; 2500 interrupt-map-mask = <0 0 0 0>; 2501 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2502 2503 nvidia,aspm-cmrt-us = <60>; 2504 nvidia,aspm-pwr-on-t-us = <20>; 2505 nvidia,aspm-l0s-entrance-latency-us = <3>; 2506 2507 bus-range = <0x0 0xff>; 2508 2509 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2510 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2511 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2512 2513 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2514 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2515 interconnect-names = "dma-mem", "write"; 2516 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2517 iommu-map-mask = <0x0>; 2518 dma-coherent; 2519 }; 2520 2521 pcie-ep@14160000 { 2522 compatible = "nvidia,tegra194-pcie-ep"; 2523 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2524 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2525 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2526 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2527 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2528 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2529 2530 status = "disabled"; 2531 2532 num-lanes = <4>; 2533 num-ib-windows = <2>; 2534 num-ob-windows = <8>; 2535 2536 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2537 clock-names = "core"; 2538 2539 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2540 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2541 reset-names = "apb", "core"; 2542 2543 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2544 interrupt-names = "intr"; 2545 2546 nvidia,bpmp = <&bpmp 4>; 2547 2548 nvidia,aspm-cmrt-us = <60>; 2549 nvidia,aspm-pwr-on-t-us = <20>; 2550 nvidia,aspm-l0s-entrance-latency-us = <3>; 2551 2552 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2553 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2554 interconnect-names = "dma-mem", "write"; 2555 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2556 iommu-map-mask = <0x0>; 2557 dma-coherent; 2558 }; 2559 2560 pcie-ep@14180000 { 2561 compatible = "nvidia,tegra194-pcie-ep"; 2562 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2563 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2564 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2565 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2566 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2567 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2568 2569 status = "disabled"; 2570 2571 num-lanes = <8>; 2572 num-ib-windows = <2>; 2573 num-ob-windows = <8>; 2574 2575 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2576 clock-names = "core"; 2577 2578 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2579 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2580 reset-names = "apb", "core"; 2581 2582 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2583 interrupt-names = "intr"; 2584 2585 nvidia,bpmp = <&bpmp 0>; 2586 2587 nvidia,aspm-cmrt-us = <60>; 2588 nvidia,aspm-pwr-on-t-us = <20>; 2589 nvidia,aspm-l0s-entrance-latency-us = <3>; 2590 2591 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2592 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2593 interconnect-names = "dma-mem", "write"; 2594 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2595 iommu-map-mask = <0x0>; 2596 dma-coherent; 2597 }; 2598 2599 pcie-ep@141a0000 { 2600 compatible = "nvidia,tegra194-pcie-ep"; 2601 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2602 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2603 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2604 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2605 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2606 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2607 2608 status = "disabled"; 2609 2610 num-lanes = <8>; 2611 num-ib-windows = <2>; 2612 num-ob-windows = <8>; 2613 2614 pinctrl-names = "default"; 2615 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2616 2617 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2618 clock-names = "core"; 2619 2620 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2621 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2622 reset-names = "apb", "core"; 2623 2624 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2625 interrupt-names = "intr"; 2626 2627 nvidia,bpmp = <&bpmp 5>; 2628 2629 nvidia,aspm-cmrt-us = <60>; 2630 nvidia,aspm-pwr-on-t-us = <20>; 2631 nvidia,aspm-l0s-entrance-latency-us = <3>; 2632 2633 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2634 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2635 interconnect-names = "dma-mem", "write"; 2636 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2637 iommu-map-mask = <0x0>; 2638 dma-coherent; 2639 }; 2640 2641 sram@40000000 { 2642 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2643 reg = <0x0 0x40000000 0x0 0x50000>; 2644 #address-cells = <1>; 2645 #size-cells = <1>; 2646 ranges = <0x0 0x0 0x40000000 0x50000>; 2647 2648 cpu_bpmp_tx: sram@4e000 { 2649 reg = <0x4e000 0x1000>; 2650 label = "cpu-bpmp-tx"; 2651 pool; 2652 }; 2653 2654 cpu_bpmp_rx: sram@4f000 { 2655 reg = <0x4f000 0x1000>; 2656 label = "cpu-bpmp-rx"; 2657 pool; 2658 }; 2659 }; 2660 2661 bpmp: bpmp { 2662 compatible = "nvidia,tegra186-bpmp"; 2663 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2664 TEGRA_HSP_DB_MASTER_BPMP>; 2665 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2666 #clock-cells = <1>; 2667 #reset-cells = <1>; 2668 #power-domain-cells = <1>; 2669 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2670 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2671 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2672 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2673 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2674 iommus = <&smmu TEGRA194_SID_BPMP>; 2675 2676 bpmp_i2c: i2c { 2677 compatible = "nvidia,tegra186-bpmp-i2c"; 2678 nvidia,bpmp-bus-id = <5>; 2679 #address-cells = <1>; 2680 #size-cells = <0>; 2681 }; 2682 2683 bpmp_thermal: thermal { 2684 compatible = "nvidia,tegra186-bpmp-thermal"; 2685 #thermal-sensor-cells = <1>; 2686 }; 2687 }; 2688 2689 cpus { 2690 compatible = "nvidia,tegra194-ccplex"; 2691 nvidia,bpmp = <&bpmp>; 2692 #address-cells = <1>; 2693 #size-cells = <0>; 2694 2695 cpu0_0: cpu@0 { 2696 compatible = "nvidia,tegra194-carmel"; 2697 device_type = "cpu"; 2698 reg = <0x000>; 2699 enable-method = "psci"; 2700 i-cache-size = <131072>; 2701 i-cache-line-size = <64>; 2702 i-cache-sets = <512>; 2703 d-cache-size = <65536>; 2704 d-cache-line-size = <64>; 2705 d-cache-sets = <256>; 2706 next-level-cache = <&l2c_0>; 2707 }; 2708 2709 cpu0_1: cpu@1 { 2710 compatible = "nvidia,tegra194-carmel"; 2711 device_type = "cpu"; 2712 reg = <0x001>; 2713 enable-method = "psci"; 2714 i-cache-size = <131072>; 2715 i-cache-line-size = <64>; 2716 i-cache-sets = <512>; 2717 d-cache-size = <65536>; 2718 d-cache-line-size = <64>; 2719 d-cache-sets = <256>; 2720 next-level-cache = <&l2c_0>; 2721 }; 2722 2723 cpu1_0: cpu@100 { 2724 compatible = "nvidia,tegra194-carmel"; 2725 device_type = "cpu"; 2726 reg = <0x100>; 2727 enable-method = "psci"; 2728 i-cache-size = <131072>; 2729 i-cache-line-size = <64>; 2730 i-cache-sets = <512>; 2731 d-cache-size = <65536>; 2732 d-cache-line-size = <64>; 2733 d-cache-sets = <256>; 2734 next-level-cache = <&l2c_1>; 2735 }; 2736 2737 cpu1_1: cpu@101 { 2738 compatible = "nvidia,tegra194-carmel"; 2739 device_type = "cpu"; 2740 reg = <0x101>; 2741 enable-method = "psci"; 2742 i-cache-size = <131072>; 2743 i-cache-line-size = <64>; 2744 i-cache-sets = <512>; 2745 d-cache-size = <65536>; 2746 d-cache-line-size = <64>; 2747 d-cache-sets = <256>; 2748 next-level-cache = <&l2c_1>; 2749 }; 2750 2751 cpu2_0: cpu@200 { 2752 compatible = "nvidia,tegra194-carmel"; 2753 device_type = "cpu"; 2754 reg = <0x200>; 2755 enable-method = "psci"; 2756 i-cache-size = <131072>; 2757 i-cache-line-size = <64>; 2758 i-cache-sets = <512>; 2759 d-cache-size = <65536>; 2760 d-cache-line-size = <64>; 2761 d-cache-sets = <256>; 2762 next-level-cache = <&l2c_2>; 2763 }; 2764 2765 cpu2_1: cpu@201 { 2766 compatible = "nvidia,tegra194-carmel"; 2767 device_type = "cpu"; 2768 reg = <0x201>; 2769 enable-method = "psci"; 2770 i-cache-size = <131072>; 2771 i-cache-line-size = <64>; 2772 i-cache-sets = <512>; 2773 d-cache-size = <65536>; 2774 d-cache-line-size = <64>; 2775 d-cache-sets = <256>; 2776 next-level-cache = <&l2c_2>; 2777 }; 2778 2779 cpu3_0: cpu@300 { 2780 compatible = "nvidia,tegra194-carmel"; 2781 device_type = "cpu"; 2782 reg = <0x300>; 2783 enable-method = "psci"; 2784 i-cache-size = <131072>; 2785 i-cache-line-size = <64>; 2786 i-cache-sets = <512>; 2787 d-cache-size = <65536>; 2788 d-cache-line-size = <64>; 2789 d-cache-sets = <256>; 2790 next-level-cache = <&l2c_3>; 2791 }; 2792 2793 cpu3_1: cpu@301 { 2794 compatible = "nvidia,tegra194-carmel"; 2795 device_type = "cpu"; 2796 reg = <0x301>; 2797 enable-method = "psci"; 2798 i-cache-size = <131072>; 2799 i-cache-line-size = <64>; 2800 i-cache-sets = <512>; 2801 d-cache-size = <65536>; 2802 d-cache-line-size = <64>; 2803 d-cache-sets = <256>; 2804 next-level-cache = <&l2c_3>; 2805 }; 2806 2807 cpu-map { 2808 cluster0 { 2809 core0 { 2810 cpu = <&cpu0_0>; 2811 }; 2812 2813 core1 { 2814 cpu = <&cpu0_1>; 2815 }; 2816 }; 2817 2818 cluster1 { 2819 core0 { 2820 cpu = <&cpu1_0>; 2821 }; 2822 2823 core1 { 2824 cpu = <&cpu1_1>; 2825 }; 2826 }; 2827 2828 cluster2 { 2829 core0 { 2830 cpu = <&cpu2_0>; 2831 }; 2832 2833 core1 { 2834 cpu = <&cpu2_1>; 2835 }; 2836 }; 2837 2838 cluster3 { 2839 core0 { 2840 cpu = <&cpu3_0>; 2841 }; 2842 2843 core1 { 2844 cpu = <&cpu3_1>; 2845 }; 2846 }; 2847 }; 2848 2849 l2c_0: l2-cache0 { 2850 cache-size = <2097152>; 2851 cache-line-size = <64>; 2852 cache-sets = <2048>; 2853 next-level-cache = <&l3c>; 2854 }; 2855 2856 l2c_1: l2-cache1 { 2857 cache-size = <2097152>; 2858 cache-line-size = <64>; 2859 cache-sets = <2048>; 2860 next-level-cache = <&l3c>; 2861 }; 2862 2863 l2c_2: l2-cache2 { 2864 cache-size = <2097152>; 2865 cache-line-size = <64>; 2866 cache-sets = <2048>; 2867 next-level-cache = <&l3c>; 2868 }; 2869 2870 l2c_3: l2-cache3 { 2871 cache-size = <2097152>; 2872 cache-line-size = <64>; 2873 cache-sets = <2048>; 2874 next-level-cache = <&l3c>; 2875 }; 2876 2877 l3c: l3-cache { 2878 cache-size = <4194304>; 2879 cache-line-size = <64>; 2880 cache-sets = <4096>; 2881 }; 2882 }; 2883 2884 pmu { 2885 compatible = "arm,armv8-pmuv3"; 2886 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2887 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2888 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2889 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 2890 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 2891 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 2892 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 2893 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 2894 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 2895 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 2896 }; 2897 2898 psci { 2899 compatible = "arm,psci-1.0"; 2900 status = "okay"; 2901 method = "smc"; 2902 }; 2903 2904 sound { 2905 status = "disabled"; 2906 2907 clocks = <&bpmp TEGRA194_CLK_PLLA>, 2908 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2909 clock-names = "pll_a", "plla_out0"; 2910 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 2911 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 2912 <&bpmp TEGRA194_CLK_AUD_MCLK>; 2913 assigned-clock-parents = <0>, 2914 <&bpmp TEGRA194_CLK_PLLA>, 2915 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2916 /* 2917 * PLLA supports dynamic ramp. Below initial rate is chosen 2918 * for this to work and oscillate between base rates required 2919 * for 8x and 11.025x sample rate streams. 2920 */ 2921 assigned-clock-rates = <258000000>; 2922 2923 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 2924 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 2925 interconnect-names = "dma-mem", "write"; 2926 iommus = <&smmu TEGRA194_SID_APE>; 2927 }; 2928 2929 tcu: serial { 2930 compatible = "nvidia,tegra194-tcu"; 2931 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2932 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2933 mbox-names = "rx", "tx"; 2934 }; 2935 2936 thermal-zones { 2937 cpu-thermal { 2938 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2939 status = "disabled"; 2940 }; 2941 2942 gpu-thermal { 2943 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2944 status = "disabled"; 2945 }; 2946 2947 aux-thermal { 2948 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2949 status = "disabled"; 2950 }; 2951 2952 pllx-thermal { 2953 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2954 status = "disabled"; 2955 }; 2956 2957 ao-thermal { 2958 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 2959 status = "disabled"; 2960 }; 2961 2962 tj-thermal { 2963 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2964 status = "disabled"; 2965 }; 2966 }; 2967 2968 timer { 2969 compatible = "arm,armv8-timer"; 2970 interrupts = <GIC_PPI 13 2971 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2972 <GIC_PPI 14 2973 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2974 <GIC_PPI 11 2975 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2976 <GIC_PPI 10 2977 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2978 interrupt-parent = <&gic>; 2979 always-on; 2980 }; 2981}; 2982