1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 }; 90 91 ethernet@2490000 { 92 compatible = "nvidia,tegra194-eqos", 93 "nvidia,tegra186-eqos", 94 "snps,dwc-qos-ethernet-4.10"; 95 reg = <0x02490000 0x10000>; 96 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 98 <&bpmp TEGRA194_CLK_EQOS_AXI>, 99 <&bpmp TEGRA194_CLK_EQOS_RX>, 100 <&bpmp TEGRA194_CLK_EQOS_TX>, 101 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 102 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 103 resets = <&bpmp TEGRA194_RESET_EQOS>; 104 reset-names = "eqos"; 105 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 106 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 107 interconnect-names = "dma-mem", "write"; 108 iommus = <&smmu TEGRA194_SID_EQOS>; 109 status = "disabled"; 110 111 snps,write-requests = <1>; 112 snps,read-requests = <3>; 113 snps,burst-map = <0x7>; 114 snps,txpbl = <16>; 115 snps,rxpbl = <8>; 116 }; 117 118 gpcdma: dma-controller@2600000 { 119 compatible = "nvidia,tegra194-gpcdma", 120 "nvidia,tegra186-gpcdma"; 121 reg = <0x2600000 0x210000>; 122 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 123 reset-names = "gpcdma"; 124 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 155 #dma-cells = <1>; 156 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 157 dma-coherent; 158 status = "okay"; 159 }; 160 161 aconnect@2900000 { 162 compatible = "nvidia,tegra194-aconnect", 163 "nvidia,tegra210-aconnect"; 164 clocks = <&bpmp TEGRA194_CLK_APE>, 165 <&bpmp TEGRA194_CLK_APB2APE>; 166 clock-names = "ape", "apb2ape"; 167 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 168 #address-cells = <1>; 169 #size-cells = <1>; 170 ranges = <0x02900000 0x02900000 0x200000>; 171 status = "disabled"; 172 173 adma: dma-controller@2930000 { 174 compatible = "nvidia,tegra194-adma", 175 "nvidia,tegra186-adma"; 176 reg = <0x02930000 0x20000>; 177 interrupt-parent = <&agic>; 178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #dma-cells = <1>; 211 clocks = <&bpmp TEGRA194_CLK_AHUB>; 212 clock-names = "d_audio"; 213 status = "disabled"; 214 }; 215 216 agic: interrupt-controller@2a40000 { 217 compatible = "nvidia,tegra194-agic", 218 "nvidia,tegra210-agic"; 219 #interrupt-cells = <3>; 220 interrupt-controller; 221 reg = <0x02a41000 0x1000>, 222 <0x02a42000 0x2000>; 223 interrupts = <GIC_SPI 145 224 (GIC_CPU_MASK_SIMPLE(4) | 225 IRQ_TYPE_LEVEL_HIGH)>; 226 clocks = <&bpmp TEGRA194_CLK_APE>; 227 clock-names = "clk"; 228 status = "disabled"; 229 }; 230 231 tegra_ahub: ahub@2900800 { 232 compatible = "nvidia,tegra194-ahub", 233 "nvidia,tegra186-ahub"; 234 reg = <0x02900800 0x800>; 235 clocks = <&bpmp TEGRA194_CLK_AHUB>; 236 clock-names = "ahub"; 237 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 238 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 239 #address-cells = <1>; 240 #size-cells = <1>; 241 ranges = <0x02900800 0x02900800 0x11800>; 242 status = "disabled"; 243 244 tegra_admaif: admaif@290f000 { 245 compatible = "nvidia,tegra194-admaif", 246 "nvidia,tegra186-admaif"; 247 reg = <0x0290f000 0x1000>; 248 dmas = <&adma 1>, <&adma 1>, 249 <&adma 2>, <&adma 2>, 250 <&adma 3>, <&adma 3>, 251 <&adma 4>, <&adma 4>, 252 <&adma 5>, <&adma 5>, 253 <&adma 6>, <&adma 6>, 254 <&adma 7>, <&adma 7>, 255 <&adma 8>, <&adma 8>, 256 <&adma 9>, <&adma 9>, 257 <&adma 10>, <&adma 10>, 258 <&adma 11>, <&adma 11>, 259 <&adma 12>, <&adma 12>, 260 <&adma 13>, <&adma 13>, 261 <&adma 14>, <&adma 14>, 262 <&adma 15>, <&adma 15>, 263 <&adma 16>, <&adma 16>, 264 <&adma 17>, <&adma 17>, 265 <&adma 18>, <&adma 18>, 266 <&adma 19>, <&adma 19>, 267 <&adma 20>, <&adma 20>; 268 dma-names = "rx1", "tx1", 269 "rx2", "tx2", 270 "rx3", "tx3", 271 "rx4", "tx4", 272 "rx5", "tx5", 273 "rx6", "tx6", 274 "rx7", "tx7", 275 "rx8", "tx8", 276 "rx9", "tx9", 277 "rx10", "tx10", 278 "rx11", "tx11", 279 "rx12", "tx12", 280 "rx13", "tx13", 281 "rx14", "tx14", 282 "rx15", "tx15", 283 "rx16", "tx16", 284 "rx17", "tx17", 285 "rx18", "tx18", 286 "rx19", "tx19", 287 "rx20", "tx20"; 288 status = "disabled"; 289 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 290 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 291 interconnect-names = "dma-mem", "write"; 292 iommus = <&smmu TEGRA194_SID_APE>; 293 }; 294 295 tegra_i2s1: i2s@2901000 { 296 compatible = "nvidia,tegra194-i2s", 297 "nvidia,tegra210-i2s"; 298 reg = <0x2901000 0x100>; 299 clocks = <&bpmp TEGRA194_CLK_I2S1>, 300 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 301 clock-names = "i2s", "sync_input"; 302 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 303 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 304 assigned-clock-rates = <1536000>; 305 sound-name-prefix = "I2S1"; 306 status = "disabled"; 307 }; 308 309 tegra_i2s2: i2s@2901100 { 310 compatible = "nvidia,tegra194-i2s", 311 "nvidia,tegra210-i2s"; 312 reg = <0x2901100 0x100>; 313 clocks = <&bpmp TEGRA194_CLK_I2S2>, 314 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 315 clock-names = "i2s", "sync_input"; 316 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 317 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 318 assigned-clock-rates = <1536000>; 319 sound-name-prefix = "I2S2"; 320 status = "disabled"; 321 }; 322 323 tegra_i2s3: i2s@2901200 { 324 compatible = "nvidia,tegra194-i2s", 325 "nvidia,tegra210-i2s"; 326 reg = <0x2901200 0x100>; 327 clocks = <&bpmp TEGRA194_CLK_I2S3>, 328 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 329 clock-names = "i2s", "sync_input"; 330 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 331 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 332 assigned-clock-rates = <1536000>; 333 sound-name-prefix = "I2S3"; 334 status = "disabled"; 335 }; 336 337 tegra_i2s4: i2s@2901300 { 338 compatible = "nvidia,tegra194-i2s", 339 "nvidia,tegra210-i2s"; 340 reg = <0x2901300 0x100>; 341 clocks = <&bpmp TEGRA194_CLK_I2S4>, 342 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 343 clock-names = "i2s", "sync_input"; 344 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 345 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 346 assigned-clock-rates = <1536000>; 347 sound-name-prefix = "I2S4"; 348 status = "disabled"; 349 }; 350 351 tegra_i2s5: i2s@2901400 { 352 compatible = "nvidia,tegra194-i2s", 353 "nvidia,tegra210-i2s"; 354 reg = <0x2901400 0x100>; 355 clocks = <&bpmp TEGRA194_CLK_I2S5>, 356 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 357 clock-names = "i2s", "sync_input"; 358 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 359 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 360 assigned-clock-rates = <1536000>; 361 sound-name-prefix = "I2S5"; 362 status = "disabled"; 363 }; 364 365 tegra_i2s6: i2s@2901500 { 366 compatible = "nvidia,tegra194-i2s", 367 "nvidia,tegra210-i2s"; 368 reg = <0x2901500 0x100>; 369 clocks = <&bpmp TEGRA194_CLK_I2S6>, 370 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 371 clock-names = "i2s", "sync_input"; 372 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 373 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 374 assigned-clock-rates = <1536000>; 375 sound-name-prefix = "I2S6"; 376 status = "disabled"; 377 }; 378 379 tegra_dmic1: dmic@2904000 { 380 compatible = "nvidia,tegra194-dmic", 381 "nvidia,tegra210-dmic"; 382 reg = <0x2904000 0x100>; 383 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 384 clock-names = "dmic"; 385 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 386 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 387 assigned-clock-rates = <3072000>; 388 sound-name-prefix = "DMIC1"; 389 status = "disabled"; 390 }; 391 392 tegra_dmic2: dmic@2904100 { 393 compatible = "nvidia,tegra194-dmic", 394 "nvidia,tegra210-dmic"; 395 reg = <0x2904100 0x100>; 396 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 397 clock-names = "dmic"; 398 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 399 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 400 assigned-clock-rates = <3072000>; 401 sound-name-prefix = "DMIC2"; 402 status = "disabled"; 403 }; 404 405 tegra_dmic3: dmic@2904200 { 406 compatible = "nvidia,tegra194-dmic", 407 "nvidia,tegra210-dmic"; 408 reg = <0x2904200 0x100>; 409 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 410 clock-names = "dmic"; 411 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 412 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 413 assigned-clock-rates = <3072000>; 414 sound-name-prefix = "DMIC3"; 415 status = "disabled"; 416 }; 417 418 tegra_dmic4: dmic@2904300 { 419 compatible = "nvidia,tegra194-dmic", 420 "nvidia,tegra210-dmic"; 421 reg = <0x2904300 0x100>; 422 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 423 clock-names = "dmic"; 424 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 425 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 426 assigned-clock-rates = <3072000>; 427 sound-name-prefix = "DMIC4"; 428 status = "disabled"; 429 }; 430 431 tegra_dspk1: dspk@2905000 { 432 compatible = "nvidia,tegra194-dspk", 433 "nvidia,tegra186-dspk"; 434 reg = <0x2905000 0x100>; 435 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 436 clock-names = "dspk"; 437 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 438 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 439 assigned-clock-rates = <12288000>; 440 sound-name-prefix = "DSPK1"; 441 status = "disabled"; 442 }; 443 444 tegra_dspk2: dspk@2905100 { 445 compatible = "nvidia,tegra194-dspk", 446 "nvidia,tegra186-dspk"; 447 reg = <0x2905100 0x100>; 448 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 449 clock-names = "dspk"; 450 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 451 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 452 assigned-clock-rates = <12288000>; 453 sound-name-prefix = "DSPK2"; 454 status = "disabled"; 455 }; 456 457 tegra_sfc1: sfc@2902000 { 458 compatible = "nvidia,tegra194-sfc", 459 "nvidia,tegra210-sfc"; 460 reg = <0x2902000 0x200>; 461 sound-name-prefix = "SFC1"; 462 status = "disabled"; 463 }; 464 465 tegra_sfc2: sfc@2902200 { 466 compatible = "nvidia,tegra194-sfc", 467 "nvidia,tegra210-sfc"; 468 reg = <0x2902200 0x200>; 469 sound-name-prefix = "SFC2"; 470 status = "disabled"; 471 }; 472 473 tegra_sfc3: sfc@2902400 { 474 compatible = "nvidia,tegra194-sfc", 475 "nvidia,tegra210-sfc"; 476 reg = <0x2902400 0x200>; 477 sound-name-prefix = "SFC3"; 478 status = "disabled"; 479 }; 480 481 tegra_sfc4: sfc@2902600 { 482 compatible = "nvidia,tegra194-sfc", 483 "nvidia,tegra210-sfc"; 484 reg = <0x2902600 0x200>; 485 sound-name-prefix = "SFC4"; 486 status = "disabled"; 487 }; 488 489 tegra_mvc1: mvc@290a000 { 490 compatible = "nvidia,tegra194-mvc", 491 "nvidia,tegra210-mvc"; 492 reg = <0x290a000 0x200>; 493 sound-name-prefix = "MVC1"; 494 status = "disabled"; 495 }; 496 497 tegra_mvc2: mvc@290a200 { 498 compatible = "nvidia,tegra194-mvc", 499 "nvidia,tegra210-mvc"; 500 reg = <0x290a200 0x200>; 501 sound-name-prefix = "MVC2"; 502 status = "disabled"; 503 }; 504 505 tegra_amx1: amx@2903000 { 506 compatible = "nvidia,tegra194-amx"; 507 reg = <0x2903000 0x100>; 508 sound-name-prefix = "AMX1"; 509 status = "disabled"; 510 }; 511 512 tegra_amx2: amx@2903100 { 513 compatible = "nvidia,tegra194-amx"; 514 reg = <0x2903100 0x100>; 515 sound-name-prefix = "AMX2"; 516 status = "disabled"; 517 }; 518 519 tegra_amx3: amx@2903200 { 520 compatible = "nvidia,tegra194-amx"; 521 reg = <0x2903200 0x100>; 522 sound-name-prefix = "AMX3"; 523 status = "disabled"; 524 }; 525 526 tegra_amx4: amx@2903300 { 527 compatible = "nvidia,tegra194-amx"; 528 reg = <0x2903300 0x100>; 529 sound-name-prefix = "AMX4"; 530 status = "disabled"; 531 }; 532 533 tegra_adx1: adx@2903800 { 534 compatible = "nvidia,tegra194-adx", 535 "nvidia,tegra210-adx"; 536 reg = <0x2903800 0x100>; 537 sound-name-prefix = "ADX1"; 538 status = "disabled"; 539 }; 540 541 tegra_adx2: adx@2903900 { 542 compatible = "nvidia,tegra194-adx", 543 "nvidia,tegra210-adx"; 544 reg = <0x2903900 0x100>; 545 sound-name-prefix = "ADX2"; 546 status = "disabled"; 547 }; 548 549 tegra_adx3: adx@2903a00 { 550 compatible = "nvidia,tegra194-adx", 551 "nvidia,tegra210-adx"; 552 reg = <0x2903a00 0x100>; 553 sound-name-prefix = "ADX3"; 554 status = "disabled"; 555 }; 556 557 tegra_adx4: adx@2903b00 { 558 compatible = "nvidia,tegra194-adx", 559 "nvidia,tegra210-adx"; 560 reg = <0x2903b00 0x100>; 561 sound-name-prefix = "ADX4"; 562 status = "disabled"; 563 }; 564 565 tegra_amixer: amixer@290bb00 { 566 compatible = "nvidia,tegra194-amixer", 567 "nvidia,tegra210-amixer"; 568 reg = <0x290bb00 0x800>; 569 sound-name-prefix = "MIXER1"; 570 status = "disabled"; 571 }; 572 }; 573 }; 574 575 pinmux: pinmux@2430000 { 576 compatible = "nvidia,tegra194-pinmux"; 577 reg = <0x2430000 0x17000>, 578 <0xc300000 0x4000>; 579 580 status = "okay"; 581 582 pex_rst_c5_out_state: pex_rst_c5_out { 583 pex_rst { 584 nvidia,pins = "pex_l5_rst_n_pgg1"; 585 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 586 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 587 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 588 nvidia,tristate = <TEGRA_PIN_DISABLE>; 589 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 590 }; 591 }; 592 593 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 594 clkreq { 595 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 596 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 597 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 598 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 599 nvidia,tristate = <TEGRA_PIN_DISABLE>; 600 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 601 }; 602 }; 603 }; 604 605 mc: memory-controller@2c00000 { 606 compatible = "nvidia,tegra194-mc"; 607 reg = <0x02c00000 0x100000>, 608 <0x02b80000 0x040000>, 609 <0x01700000 0x100000>; 610 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 611 #interconnect-cells = <1>; 612 status = "disabled"; 613 614 #address-cells = <2>; 615 #size-cells = <2>; 616 617 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 618 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 619 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 620 621 /* 622 * Bit 39 of addresses passing through the memory 623 * controller selects the XBAR format used when memory 624 * is accessed. This is used to transparently access 625 * memory in the XBAR format used by the discrete GPU 626 * (bit 39 set) or Tegra (bit 39 clear). 627 * 628 * As a consequence, the operating system must ensure 629 * that bit 39 is never used implicitly, for example 630 * via an I/O virtual address mapping of an IOMMU. If 631 * devices require access to the XBAR switch, their 632 * drivers must set this bit explicitly. 633 * 634 * Limit the DMA range for memory clients to [38:0]. 635 */ 636 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 637 638 emc: external-memory-controller@2c60000 { 639 compatible = "nvidia,tegra194-emc"; 640 reg = <0x0 0x02c60000 0x0 0x90000>, 641 <0x0 0x01780000 0x0 0x80000>; 642 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&bpmp TEGRA194_CLK_EMC>; 644 clock-names = "emc"; 645 646 #interconnect-cells = <0>; 647 648 nvidia,bpmp = <&bpmp>; 649 }; 650 }; 651 652 uarta: serial@3100000 { 653 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 654 reg = <0x03100000 0x40>; 655 reg-shift = <2>; 656 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&bpmp TEGRA194_CLK_UARTA>; 658 clock-names = "serial"; 659 resets = <&bpmp TEGRA194_RESET_UARTA>; 660 reset-names = "serial"; 661 status = "disabled"; 662 }; 663 664 uartb: serial@3110000 { 665 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 666 reg = <0x03110000 0x40>; 667 reg-shift = <2>; 668 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&bpmp TEGRA194_CLK_UARTB>; 670 clock-names = "serial"; 671 resets = <&bpmp TEGRA194_RESET_UARTB>; 672 reset-names = "serial"; 673 status = "disabled"; 674 }; 675 676 uartd: serial@3130000 { 677 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 678 reg = <0x03130000 0x40>; 679 reg-shift = <2>; 680 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&bpmp TEGRA194_CLK_UARTD>; 682 clock-names = "serial"; 683 resets = <&bpmp TEGRA194_RESET_UARTD>; 684 reset-names = "serial"; 685 status = "disabled"; 686 }; 687 688 uarte: serial@3140000 { 689 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 690 reg = <0x03140000 0x40>; 691 reg-shift = <2>; 692 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&bpmp TEGRA194_CLK_UARTE>; 694 clock-names = "serial"; 695 resets = <&bpmp TEGRA194_RESET_UARTE>; 696 reset-names = "serial"; 697 status = "disabled"; 698 }; 699 700 uartf: serial@3150000 { 701 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 702 reg = <0x03150000 0x40>; 703 reg-shift = <2>; 704 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&bpmp TEGRA194_CLK_UARTF>; 706 clock-names = "serial"; 707 resets = <&bpmp TEGRA194_RESET_UARTF>; 708 reset-names = "serial"; 709 status = "disabled"; 710 }; 711 712 gen1_i2c: i2c@3160000 { 713 compatible = "nvidia,tegra194-i2c"; 714 reg = <0x03160000 0x10000>; 715 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 clocks = <&bpmp TEGRA194_CLK_I2C1>; 719 clock-names = "div-clk"; 720 resets = <&bpmp TEGRA194_RESET_I2C1>; 721 reset-names = "i2c"; 722 status = "disabled"; 723 }; 724 725 uarth: serial@3170000 { 726 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 727 reg = <0x03170000 0x40>; 728 reg-shift = <2>; 729 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&bpmp TEGRA194_CLK_UARTH>; 731 clock-names = "serial"; 732 resets = <&bpmp TEGRA194_RESET_UARTH>; 733 reset-names = "serial"; 734 status = "disabled"; 735 }; 736 737 cam_i2c: i2c@3180000 { 738 compatible = "nvidia,tegra194-i2c"; 739 reg = <0x03180000 0x10000>; 740 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 clocks = <&bpmp TEGRA194_CLK_I2C3>; 744 clock-names = "div-clk"; 745 resets = <&bpmp TEGRA194_RESET_I2C3>; 746 reset-names = "i2c"; 747 status = "disabled"; 748 }; 749 750 /* shares pads with dpaux1 */ 751 dp_aux_ch1_i2c: i2c@3190000 { 752 compatible = "nvidia,tegra194-i2c"; 753 reg = <0x03190000 0x10000>; 754 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 clocks = <&bpmp TEGRA194_CLK_I2C4>; 758 clock-names = "div-clk"; 759 resets = <&bpmp TEGRA194_RESET_I2C4>; 760 reset-names = "i2c"; 761 pinctrl-0 = <&state_dpaux1_i2c>; 762 pinctrl-1 = <&state_dpaux1_off>; 763 pinctrl-names = "default", "idle"; 764 status = "disabled"; 765 }; 766 767 /* shares pads with dpaux0 */ 768 dp_aux_ch0_i2c: i2c@31b0000 { 769 compatible = "nvidia,tegra194-i2c"; 770 reg = <0x031b0000 0x10000>; 771 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 clocks = <&bpmp TEGRA194_CLK_I2C6>; 775 clock-names = "div-clk"; 776 resets = <&bpmp TEGRA194_RESET_I2C6>; 777 reset-names = "i2c"; 778 pinctrl-0 = <&state_dpaux0_i2c>; 779 pinctrl-1 = <&state_dpaux0_off>; 780 pinctrl-names = "default", "idle"; 781 status = "disabled"; 782 }; 783 784 /* shares pads with dpaux2 */ 785 dp_aux_ch2_i2c: i2c@31c0000 { 786 compatible = "nvidia,tegra194-i2c"; 787 reg = <0x031c0000 0x10000>; 788 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 clocks = <&bpmp TEGRA194_CLK_I2C7>; 792 clock-names = "div-clk"; 793 resets = <&bpmp TEGRA194_RESET_I2C7>; 794 reset-names = "i2c"; 795 pinctrl-0 = <&state_dpaux2_i2c>; 796 pinctrl-1 = <&state_dpaux2_off>; 797 pinctrl-names = "default", "idle"; 798 status = "disabled"; 799 }; 800 801 /* shares pads with dpaux3 */ 802 dp_aux_ch3_i2c: i2c@31e0000 { 803 compatible = "nvidia,tegra194-i2c"; 804 reg = <0x031e0000 0x10000>; 805 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 clocks = <&bpmp TEGRA194_CLK_I2C9>; 809 clock-names = "div-clk"; 810 resets = <&bpmp TEGRA194_RESET_I2C9>; 811 reset-names = "i2c"; 812 pinctrl-0 = <&state_dpaux3_i2c>; 813 pinctrl-1 = <&state_dpaux3_off>; 814 pinctrl-names = "default", "idle"; 815 status = "disabled"; 816 }; 817 818 spi@3270000 { 819 compatible = "nvidia,tegra194-qspi"; 820 reg = <0x3270000 0x1000>; 821 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 825 <&bpmp TEGRA194_CLK_QSPI0_PM>; 826 clock-names = "qspi", "qspi_out"; 827 resets = <&bpmp TEGRA194_RESET_QSPI0>; 828 reset-names = "qspi"; 829 status = "disabled"; 830 }; 831 832 spi@3300000 { 833 compatible = "nvidia,tegra194-qspi"; 834 reg = <0x3300000 0x1000>; 835 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 839 <&bpmp TEGRA194_CLK_QSPI1_PM>; 840 clock-names = "qspi", "qspi_out"; 841 resets = <&bpmp TEGRA194_RESET_QSPI1>; 842 reset-names = "qspi"; 843 status = "disabled"; 844 }; 845 846 pwm1: pwm@3280000 { 847 compatible = "nvidia,tegra194-pwm", 848 "nvidia,tegra186-pwm"; 849 reg = <0x3280000 0x10000>; 850 clocks = <&bpmp TEGRA194_CLK_PWM1>; 851 clock-names = "pwm"; 852 resets = <&bpmp TEGRA194_RESET_PWM1>; 853 reset-names = "pwm"; 854 status = "disabled"; 855 #pwm-cells = <2>; 856 }; 857 858 pwm2: pwm@3290000 { 859 compatible = "nvidia,tegra194-pwm", 860 "nvidia,tegra186-pwm"; 861 reg = <0x3290000 0x10000>; 862 clocks = <&bpmp TEGRA194_CLK_PWM2>; 863 clock-names = "pwm"; 864 resets = <&bpmp TEGRA194_RESET_PWM2>; 865 reset-names = "pwm"; 866 status = "disabled"; 867 #pwm-cells = <2>; 868 }; 869 870 pwm3: pwm@32a0000 { 871 compatible = "nvidia,tegra194-pwm", 872 "nvidia,tegra186-pwm"; 873 reg = <0x32a0000 0x10000>; 874 clocks = <&bpmp TEGRA194_CLK_PWM3>; 875 clock-names = "pwm"; 876 resets = <&bpmp TEGRA194_RESET_PWM3>; 877 reset-names = "pwm"; 878 status = "disabled"; 879 #pwm-cells = <2>; 880 }; 881 882 pwm5: pwm@32c0000 { 883 compatible = "nvidia,tegra194-pwm", 884 "nvidia,tegra186-pwm"; 885 reg = <0x32c0000 0x10000>; 886 clocks = <&bpmp TEGRA194_CLK_PWM5>; 887 clock-names = "pwm"; 888 resets = <&bpmp TEGRA194_RESET_PWM5>; 889 reset-names = "pwm"; 890 status = "disabled"; 891 #pwm-cells = <2>; 892 }; 893 894 pwm6: pwm@32d0000 { 895 compatible = "nvidia,tegra194-pwm", 896 "nvidia,tegra186-pwm"; 897 reg = <0x32d0000 0x10000>; 898 clocks = <&bpmp TEGRA194_CLK_PWM6>; 899 clock-names = "pwm"; 900 resets = <&bpmp TEGRA194_RESET_PWM6>; 901 reset-names = "pwm"; 902 status = "disabled"; 903 #pwm-cells = <2>; 904 }; 905 906 pwm7: pwm@32e0000 { 907 compatible = "nvidia,tegra194-pwm", 908 "nvidia,tegra186-pwm"; 909 reg = <0x32e0000 0x10000>; 910 clocks = <&bpmp TEGRA194_CLK_PWM7>; 911 clock-names = "pwm"; 912 resets = <&bpmp TEGRA194_RESET_PWM7>; 913 reset-names = "pwm"; 914 status = "disabled"; 915 #pwm-cells = <2>; 916 }; 917 918 pwm8: pwm@32f0000 { 919 compatible = "nvidia,tegra194-pwm", 920 "nvidia,tegra186-pwm"; 921 reg = <0x32f0000 0x10000>; 922 clocks = <&bpmp TEGRA194_CLK_PWM8>; 923 clock-names = "pwm"; 924 resets = <&bpmp TEGRA194_RESET_PWM8>; 925 reset-names = "pwm"; 926 status = "disabled"; 927 #pwm-cells = <2>; 928 }; 929 930 sdmmc1: mmc@3400000 { 931 compatible = "nvidia,tegra194-sdhci"; 932 reg = <0x03400000 0x10000>; 933 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 935 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 936 clock-names = "sdhci", "tmclk"; 937 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 938 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 939 assigned-clock-parents = 940 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 941 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 942 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 943 reset-names = "sdhci"; 944 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 945 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 946 interconnect-names = "dma-mem", "write"; 947 iommus = <&smmu TEGRA194_SID_SDMMC1>; 948 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 949 pinctrl-0 = <&sdmmc1_3v3>; 950 pinctrl-1 = <&sdmmc1_1v8>; 951 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 952 <0x07>; 953 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 954 <0x07>; 955 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 956 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 957 <0x07>; 958 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 959 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 960 nvidia,default-tap = <0x9>; 961 nvidia,default-trim = <0x5>; 962 sd-uhs-sdr25; 963 sd-uhs-sdr50; 964 sd-uhs-ddr50; 965 sd-uhs-sdr104; 966 status = "disabled"; 967 }; 968 969 sdmmc3: mmc@3440000 { 970 compatible = "nvidia,tegra194-sdhci"; 971 reg = <0x03440000 0x10000>; 972 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 974 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 975 clock-names = "sdhci", "tmclk"; 976 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 977 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 978 assigned-clock-parents = 979 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 980 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 981 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 982 reset-names = "sdhci"; 983 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 984 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 985 interconnect-names = "dma-mem", "write"; 986 iommus = <&smmu TEGRA194_SID_SDMMC3>; 987 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 988 pinctrl-0 = <&sdmmc3_3v3>; 989 pinctrl-1 = <&sdmmc3_1v8>; 990 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 991 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 992 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 993 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 994 <0x07>; 995 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 996 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 997 <0x07>; 998 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 999 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1000 nvidia,default-tap = <0x9>; 1001 nvidia,default-trim = <0x5>; 1002 sd-uhs-sdr25; 1003 sd-uhs-sdr50; 1004 sd-uhs-ddr50; 1005 sd-uhs-sdr104; 1006 status = "disabled"; 1007 }; 1008 1009 sdmmc4: mmc@3460000 { 1010 compatible = "nvidia,tegra194-sdhci"; 1011 reg = <0x03460000 0x10000>; 1012 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1014 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1015 clock-names = "sdhci", "tmclk"; 1016 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1017 <&bpmp TEGRA194_CLK_PLLC4>; 1018 assigned-clock-parents = 1019 <&bpmp TEGRA194_CLK_PLLC4>; 1020 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1021 reset-names = "sdhci"; 1022 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1023 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1024 interconnect-names = "dma-mem", "write"; 1025 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1026 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1027 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1028 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1029 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1030 <0x0a>; 1031 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1032 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1033 <0x0a>; 1034 nvidia,default-tap = <0x8>; 1035 nvidia,default-trim = <0x14>; 1036 nvidia,dqs-trim = <40>; 1037 cap-mmc-highspeed; 1038 mmc-ddr-1_8v; 1039 mmc-hs200-1_8v; 1040 mmc-hs400-1_8v; 1041 mmc-hs400-enhanced-strobe; 1042 supports-cqe; 1043 status = "disabled"; 1044 }; 1045 1046 hda@3510000 { 1047 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 1048 reg = <0x3510000 0x10000>; 1049 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&bpmp TEGRA194_CLK_HDA>, 1051 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1052 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1053 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1054 resets = <&bpmp TEGRA194_RESET_HDA>, 1055 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1056 reset-names = "hda", "hda2hdmi"; 1057 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1058 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1059 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1060 interconnect-names = "dma-mem", "write"; 1061 iommus = <&smmu TEGRA194_SID_HDA>; 1062 status = "disabled"; 1063 }; 1064 1065 xusb_padctl: padctl@3520000 { 1066 compatible = "nvidia,tegra194-xusb-padctl"; 1067 reg = <0x03520000 0x1000>, 1068 <0x03540000 0x1000>; 1069 reg-names = "padctl", "ao"; 1070 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1071 1072 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1073 reset-names = "padctl"; 1074 1075 status = "disabled"; 1076 1077 pads { 1078 usb2 { 1079 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1080 clock-names = "trk"; 1081 1082 lanes { 1083 usb2-0 { 1084 nvidia,function = "xusb"; 1085 status = "disabled"; 1086 #phy-cells = <0>; 1087 }; 1088 1089 usb2-1 { 1090 nvidia,function = "xusb"; 1091 status = "disabled"; 1092 #phy-cells = <0>; 1093 }; 1094 1095 usb2-2 { 1096 nvidia,function = "xusb"; 1097 status = "disabled"; 1098 #phy-cells = <0>; 1099 }; 1100 1101 usb2-3 { 1102 nvidia,function = "xusb"; 1103 status = "disabled"; 1104 #phy-cells = <0>; 1105 }; 1106 }; 1107 }; 1108 1109 usb3 { 1110 lanes { 1111 usb3-0 { 1112 nvidia,function = "xusb"; 1113 status = "disabled"; 1114 #phy-cells = <0>; 1115 }; 1116 1117 usb3-1 { 1118 nvidia,function = "xusb"; 1119 status = "disabled"; 1120 #phy-cells = <0>; 1121 }; 1122 1123 usb3-2 { 1124 nvidia,function = "xusb"; 1125 status = "disabled"; 1126 #phy-cells = <0>; 1127 }; 1128 1129 usb3-3 { 1130 nvidia,function = "xusb"; 1131 status = "disabled"; 1132 #phy-cells = <0>; 1133 }; 1134 }; 1135 }; 1136 }; 1137 1138 ports { 1139 usb2-0 { 1140 status = "disabled"; 1141 }; 1142 1143 usb2-1 { 1144 status = "disabled"; 1145 }; 1146 1147 usb2-2 { 1148 status = "disabled"; 1149 }; 1150 1151 usb2-3 { 1152 status = "disabled"; 1153 }; 1154 1155 usb3-0 { 1156 status = "disabled"; 1157 }; 1158 1159 usb3-1 { 1160 status = "disabled"; 1161 }; 1162 1163 usb3-2 { 1164 status = "disabled"; 1165 }; 1166 1167 usb3-3 { 1168 status = "disabled"; 1169 }; 1170 }; 1171 }; 1172 1173 usb@3550000 { 1174 compatible = "nvidia,tegra194-xudc"; 1175 reg = <0x03550000 0x8000>, 1176 <0x03558000 0x1000>; 1177 reg-names = "base", "fpci"; 1178 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1179 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1180 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1181 <&bpmp TEGRA194_CLK_XUSB_SS>, 1182 <&bpmp TEGRA194_CLK_XUSB_FS>; 1183 clock-names = "dev", "ss", "ss_src", "fs_src"; 1184 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1185 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1186 interconnect-names = "dma-mem", "write"; 1187 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1188 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1189 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1190 power-domain-names = "dev", "ss"; 1191 nvidia,xusb-padctl = <&xusb_padctl>; 1192 status = "disabled"; 1193 }; 1194 1195 usb@3610000 { 1196 compatible = "nvidia,tegra194-xusb"; 1197 reg = <0x03610000 0x40000>, 1198 <0x03600000 0x10000>; 1199 reg-names = "hcd", "fpci"; 1200 1201 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1203 1204 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1205 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1206 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1207 <&bpmp TEGRA194_CLK_XUSB_SS>, 1208 <&bpmp TEGRA194_CLK_CLK_M>, 1209 <&bpmp TEGRA194_CLK_XUSB_FS>, 1210 <&bpmp TEGRA194_CLK_UTMIPLL>, 1211 <&bpmp TEGRA194_CLK_CLK_M>, 1212 <&bpmp TEGRA194_CLK_PLLE>; 1213 clock-names = "xusb_host", "xusb_falcon_src", 1214 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1215 "xusb_fs_src", "pll_u_480m", "clk_m", 1216 "pll_e"; 1217 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1218 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1219 interconnect-names = "dma-mem", "write"; 1220 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1221 1222 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1223 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1224 power-domain-names = "xusb_host", "xusb_ss"; 1225 1226 nvidia,xusb-padctl = <&xusb_padctl>; 1227 status = "disabled"; 1228 }; 1229 1230 fuse@3820000 { 1231 compatible = "nvidia,tegra194-efuse"; 1232 reg = <0x03820000 0x10000>; 1233 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1234 clock-names = "fuse"; 1235 }; 1236 1237 gic: interrupt-controller@3881000 { 1238 compatible = "arm,gic-400"; 1239 #interrupt-cells = <3>; 1240 interrupt-controller; 1241 reg = <0x03881000 0x1000>, 1242 <0x03882000 0x2000>, 1243 <0x03884000 0x2000>, 1244 <0x03886000 0x2000>; 1245 interrupts = <GIC_PPI 9 1246 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1247 interrupt-parent = <&gic>; 1248 }; 1249 1250 cec@3960000 { 1251 compatible = "nvidia,tegra194-cec"; 1252 reg = <0x03960000 0x10000>; 1253 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1254 clocks = <&bpmp TEGRA194_CLK_CEC>; 1255 clock-names = "cec"; 1256 status = "disabled"; 1257 }; 1258 1259 hsp_top0: hsp@3c00000 { 1260 compatible = "nvidia,tegra194-hsp"; 1261 reg = <0x03c00000 0xa0000>; 1262 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1271 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1272 "shared3", "shared4", "shared5", "shared6", 1273 "shared7"; 1274 #mbox-cells = <2>; 1275 }; 1276 1277 p2u_hsio_0: phy@3e10000 { 1278 compatible = "nvidia,tegra194-p2u"; 1279 reg = <0x03e10000 0x10000>; 1280 reg-names = "ctl"; 1281 1282 #phy-cells = <0>; 1283 }; 1284 1285 p2u_hsio_1: phy@3e20000 { 1286 compatible = "nvidia,tegra194-p2u"; 1287 reg = <0x03e20000 0x10000>; 1288 reg-names = "ctl"; 1289 1290 #phy-cells = <0>; 1291 }; 1292 1293 p2u_hsio_2: phy@3e30000 { 1294 compatible = "nvidia,tegra194-p2u"; 1295 reg = <0x03e30000 0x10000>; 1296 reg-names = "ctl"; 1297 1298 #phy-cells = <0>; 1299 }; 1300 1301 p2u_hsio_3: phy@3e40000 { 1302 compatible = "nvidia,tegra194-p2u"; 1303 reg = <0x03e40000 0x10000>; 1304 reg-names = "ctl"; 1305 1306 #phy-cells = <0>; 1307 }; 1308 1309 p2u_hsio_4: phy@3e50000 { 1310 compatible = "nvidia,tegra194-p2u"; 1311 reg = <0x03e50000 0x10000>; 1312 reg-names = "ctl"; 1313 1314 #phy-cells = <0>; 1315 }; 1316 1317 p2u_hsio_5: phy@3e60000 { 1318 compatible = "nvidia,tegra194-p2u"; 1319 reg = <0x03e60000 0x10000>; 1320 reg-names = "ctl"; 1321 1322 #phy-cells = <0>; 1323 }; 1324 1325 p2u_hsio_6: phy@3e70000 { 1326 compatible = "nvidia,tegra194-p2u"; 1327 reg = <0x03e70000 0x10000>; 1328 reg-names = "ctl"; 1329 1330 #phy-cells = <0>; 1331 }; 1332 1333 p2u_hsio_7: phy@3e80000 { 1334 compatible = "nvidia,tegra194-p2u"; 1335 reg = <0x03e80000 0x10000>; 1336 reg-names = "ctl"; 1337 1338 #phy-cells = <0>; 1339 }; 1340 1341 p2u_hsio_8: phy@3e90000 { 1342 compatible = "nvidia,tegra194-p2u"; 1343 reg = <0x03e90000 0x10000>; 1344 reg-names = "ctl"; 1345 1346 #phy-cells = <0>; 1347 }; 1348 1349 p2u_hsio_9: phy@3ea0000 { 1350 compatible = "nvidia,tegra194-p2u"; 1351 reg = <0x03ea0000 0x10000>; 1352 reg-names = "ctl"; 1353 1354 #phy-cells = <0>; 1355 }; 1356 1357 p2u_nvhs_0: phy@3eb0000 { 1358 compatible = "nvidia,tegra194-p2u"; 1359 reg = <0x03eb0000 0x10000>; 1360 reg-names = "ctl"; 1361 1362 #phy-cells = <0>; 1363 }; 1364 1365 p2u_nvhs_1: phy@3ec0000 { 1366 compatible = "nvidia,tegra194-p2u"; 1367 reg = <0x03ec0000 0x10000>; 1368 reg-names = "ctl"; 1369 1370 #phy-cells = <0>; 1371 }; 1372 1373 p2u_nvhs_2: phy@3ed0000 { 1374 compatible = "nvidia,tegra194-p2u"; 1375 reg = <0x03ed0000 0x10000>; 1376 reg-names = "ctl"; 1377 1378 #phy-cells = <0>; 1379 }; 1380 1381 p2u_nvhs_3: phy@3ee0000 { 1382 compatible = "nvidia,tegra194-p2u"; 1383 reg = <0x03ee0000 0x10000>; 1384 reg-names = "ctl"; 1385 1386 #phy-cells = <0>; 1387 }; 1388 1389 p2u_nvhs_4: phy@3ef0000 { 1390 compatible = "nvidia,tegra194-p2u"; 1391 reg = <0x03ef0000 0x10000>; 1392 reg-names = "ctl"; 1393 1394 #phy-cells = <0>; 1395 }; 1396 1397 p2u_nvhs_5: phy@3f00000 { 1398 compatible = "nvidia,tegra194-p2u"; 1399 reg = <0x03f00000 0x10000>; 1400 reg-names = "ctl"; 1401 1402 #phy-cells = <0>; 1403 }; 1404 1405 p2u_nvhs_6: phy@3f10000 { 1406 compatible = "nvidia,tegra194-p2u"; 1407 reg = <0x03f10000 0x10000>; 1408 reg-names = "ctl"; 1409 1410 #phy-cells = <0>; 1411 }; 1412 1413 p2u_nvhs_7: phy@3f20000 { 1414 compatible = "nvidia,tegra194-p2u"; 1415 reg = <0x03f20000 0x10000>; 1416 reg-names = "ctl"; 1417 1418 #phy-cells = <0>; 1419 }; 1420 1421 p2u_hsio_10: phy@3f30000 { 1422 compatible = "nvidia,tegra194-p2u"; 1423 reg = <0x03f30000 0x10000>; 1424 reg-names = "ctl"; 1425 1426 #phy-cells = <0>; 1427 }; 1428 1429 p2u_hsio_11: phy@3f40000 { 1430 compatible = "nvidia,tegra194-p2u"; 1431 reg = <0x03f40000 0x10000>; 1432 reg-names = "ctl"; 1433 1434 #phy-cells = <0>; 1435 }; 1436 1437 hsp_aon: hsp@c150000 { 1438 compatible = "nvidia,tegra194-hsp"; 1439 reg = <0x0c150000 0x90000>; 1440 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1444 /* 1445 * Shared interrupt 0 is routed only to AON/SPE, so 1446 * we only have 4 shared interrupts for the CCPLEX. 1447 */ 1448 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1449 #mbox-cells = <2>; 1450 }; 1451 1452 gen2_i2c: i2c@c240000 { 1453 compatible = "nvidia,tegra194-i2c"; 1454 reg = <0x0c240000 0x10000>; 1455 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1459 clock-names = "div-clk"; 1460 resets = <&bpmp TEGRA194_RESET_I2C2>; 1461 reset-names = "i2c"; 1462 status = "disabled"; 1463 }; 1464 1465 gen8_i2c: i2c@c250000 { 1466 compatible = "nvidia,tegra194-i2c"; 1467 reg = <0x0c250000 0x10000>; 1468 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1472 clock-names = "div-clk"; 1473 resets = <&bpmp TEGRA194_RESET_I2C8>; 1474 reset-names = "i2c"; 1475 status = "disabled"; 1476 }; 1477 1478 uartc: serial@c280000 { 1479 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1480 reg = <0x0c280000 0x40>; 1481 reg-shift = <2>; 1482 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1483 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1484 clock-names = "serial"; 1485 resets = <&bpmp TEGRA194_RESET_UARTC>; 1486 reset-names = "serial"; 1487 status = "disabled"; 1488 }; 1489 1490 uartg: serial@c290000 { 1491 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1492 reg = <0x0c290000 0x40>; 1493 reg-shift = <2>; 1494 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1495 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1496 clock-names = "serial"; 1497 resets = <&bpmp TEGRA194_RESET_UARTG>; 1498 reset-names = "serial"; 1499 status = "disabled"; 1500 }; 1501 1502 rtc: rtc@c2a0000 { 1503 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1504 reg = <0x0c2a0000 0x10000>; 1505 interrupt-parent = <&pmc>; 1506 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1507 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1508 clock-names = "rtc"; 1509 status = "disabled"; 1510 }; 1511 1512 gpio_aon: gpio@c2f0000 { 1513 compatible = "nvidia,tegra194-gpio-aon"; 1514 reg-names = "security", "gpio"; 1515 reg = <0xc2f0000 0x1000>, 1516 <0xc2f1000 0x1000>; 1517 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1521 gpio-controller; 1522 #gpio-cells = <2>; 1523 interrupt-controller; 1524 #interrupt-cells = <2>; 1525 }; 1526 1527 pwm4: pwm@c340000 { 1528 compatible = "nvidia,tegra194-pwm", 1529 "nvidia,tegra186-pwm"; 1530 reg = <0xc340000 0x10000>; 1531 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1532 clock-names = "pwm"; 1533 resets = <&bpmp TEGRA194_RESET_PWM4>; 1534 reset-names = "pwm"; 1535 status = "disabled"; 1536 #pwm-cells = <2>; 1537 }; 1538 1539 pmc: pmc@c360000 { 1540 compatible = "nvidia,tegra194-pmc"; 1541 reg = <0x0c360000 0x10000>, 1542 <0x0c370000 0x10000>, 1543 <0x0c380000 0x10000>, 1544 <0x0c390000 0x10000>, 1545 <0x0c3a0000 0x10000>; 1546 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1547 1548 #interrupt-cells = <2>; 1549 interrupt-controller; 1550 sdmmc1_3v3: sdmmc1-3v3 { 1551 pins = "sdmmc1-hv"; 1552 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1553 }; 1554 1555 sdmmc1_1v8: sdmmc1-1v8 { 1556 pins = "sdmmc1-hv"; 1557 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1558 }; 1559 sdmmc3_3v3: sdmmc3-3v3 { 1560 pins = "sdmmc3-hv"; 1561 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1562 }; 1563 1564 sdmmc3_1v8: sdmmc3-1v8 { 1565 pins = "sdmmc3-hv"; 1566 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1567 }; 1568 1569 }; 1570 1571 iommu@10000000 { 1572 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1573 reg = <0x10000000 0x800000>; 1574 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1639 stream-match-mask = <0x7f80>; 1640 #global-interrupts = <1>; 1641 #iommu-cells = <1>; 1642 1643 nvidia,memory-controller = <&mc>; 1644 status = "disabled"; 1645 }; 1646 1647 smmu: iommu@12000000 { 1648 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1649 reg = <0x12000000 0x800000>, 1650 <0x11000000 0x800000>; 1651 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1717 stream-match-mask = <0x7f80>; 1718 #global-interrupts = <2>; 1719 #iommu-cells = <1>; 1720 1721 nvidia,memory-controller = <&mc>; 1722 status = "okay"; 1723 }; 1724 1725 host1x@13e00000 { 1726 compatible = "nvidia,tegra194-host1x"; 1727 reg = <0x13e00000 0x10000>, 1728 <0x13e10000 0x10000>; 1729 reg-names = "hypervisor", "vm"; 1730 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1732 interrupt-names = "syncpt", "host1x"; 1733 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1734 clock-names = "host1x"; 1735 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1736 reset-names = "host1x"; 1737 1738 #address-cells = <1>; 1739 #size-cells = <1>; 1740 1741 ranges = <0x15000000 0x15000000 0x01000000>; 1742 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1743 interconnect-names = "dma-mem"; 1744 iommus = <&smmu TEGRA194_SID_HOST1X>; 1745 1746 nvdec@15140000 { 1747 compatible = "nvidia,tegra194-nvdec"; 1748 reg = <0x15140000 0x00040000>; 1749 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1750 clock-names = "nvdec"; 1751 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1752 reset-names = "nvdec"; 1753 1754 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1755 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1756 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1757 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1758 interconnect-names = "dma-mem", "read-1", "write"; 1759 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1760 dma-coherent; 1761 1762 nvidia,host1x-class = <0xf5>; 1763 }; 1764 1765 display-hub@15200000 { 1766 compatible = "nvidia,tegra194-display"; 1767 reg = <0x15200000 0x00040000>; 1768 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1769 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1770 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1771 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1772 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1773 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1774 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1775 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1776 "wgrp3", "wgrp4", "wgrp5"; 1777 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1778 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1779 clock-names = "disp", "hub"; 1780 status = "disabled"; 1781 1782 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1783 1784 #address-cells = <1>; 1785 #size-cells = <1>; 1786 1787 ranges = <0x15200000 0x15200000 0x40000>; 1788 1789 display@15200000 { 1790 compatible = "nvidia,tegra194-dc"; 1791 reg = <0x15200000 0x10000>; 1792 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1793 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1794 clock-names = "dc"; 1795 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1796 reset-names = "dc"; 1797 1798 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1799 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1800 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1801 interconnect-names = "dma-mem", "read-1"; 1802 1803 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1804 nvidia,head = <0>; 1805 }; 1806 1807 display@15210000 { 1808 compatible = "nvidia,tegra194-dc"; 1809 reg = <0x15210000 0x10000>; 1810 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1811 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1812 clock-names = "dc"; 1813 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1814 reset-names = "dc"; 1815 1816 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1817 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1818 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1819 interconnect-names = "dma-mem", "read-1"; 1820 1821 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1822 nvidia,head = <1>; 1823 }; 1824 1825 display@15220000 { 1826 compatible = "nvidia,tegra194-dc"; 1827 reg = <0x15220000 0x10000>; 1828 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1829 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1830 clock-names = "dc"; 1831 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1832 reset-names = "dc"; 1833 1834 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1835 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1836 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1837 interconnect-names = "dma-mem", "read-1"; 1838 1839 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1840 nvidia,head = <2>; 1841 }; 1842 1843 display@15230000 { 1844 compatible = "nvidia,tegra194-dc"; 1845 reg = <0x15230000 0x10000>; 1846 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1847 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1848 clock-names = "dc"; 1849 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1850 reset-names = "dc"; 1851 1852 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1853 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1854 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1855 interconnect-names = "dma-mem", "read-1"; 1856 1857 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1858 nvidia,head = <3>; 1859 }; 1860 }; 1861 1862 vic@15340000 { 1863 compatible = "nvidia,tegra194-vic"; 1864 reg = <0x15340000 0x00040000>; 1865 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1866 clocks = <&bpmp TEGRA194_CLK_VIC>; 1867 clock-names = "vic"; 1868 resets = <&bpmp TEGRA194_RESET_VIC>; 1869 reset-names = "vic"; 1870 1871 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1872 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1873 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1874 interconnect-names = "dma-mem", "write"; 1875 iommus = <&smmu TEGRA194_SID_VIC>; 1876 dma-coherent; 1877 }; 1878 1879 nvjpg@15380000 { 1880 compatible = "nvidia,tegra194-nvjpg"; 1881 reg = <0x15380000 0x40000>; 1882 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1883 clock-names = "nvjpg"; 1884 resets = <&bpmp TEGRA194_RESET_NVJPG>; 1885 reset-names = "nvjpg"; 1886 1887 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1888 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1889 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1890 interconnect-names = "dma-mem", "write"; 1891 iommus = <&smmu TEGRA194_SID_NVJPG>; 1892 dma-coherent; 1893 }; 1894 1895 nvdec@15480000 { 1896 compatible = "nvidia,tegra194-nvdec"; 1897 reg = <0x15480000 0x00040000>; 1898 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 1899 clock-names = "nvdec"; 1900 resets = <&bpmp TEGRA194_RESET_NVDEC>; 1901 reset-names = "nvdec"; 1902 1903 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 1904 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 1905 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 1906 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 1907 interconnect-names = "dma-mem", "read-1", "write"; 1908 iommus = <&smmu TEGRA194_SID_NVDEC>; 1909 dma-coherent; 1910 1911 nvidia,host1x-class = <0xf0>; 1912 }; 1913 1914 nvenc@154c0000 { 1915 compatible = "nvidia,tegra194-nvenc"; 1916 reg = <0x154c0000 0x40000>; 1917 clocks = <&bpmp TEGRA194_CLK_NVENC>; 1918 clock-names = "nvenc"; 1919 resets = <&bpmp TEGRA194_RESET_NVENC>; 1920 reset-names = "nvenc"; 1921 1922 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 1923 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 1924 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 1925 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 1926 interconnect-names = "dma-mem", "read-1", "write"; 1927 iommus = <&smmu TEGRA194_SID_NVENC>; 1928 dma-coherent; 1929 1930 nvidia,host1x-class = <0x21>; 1931 }; 1932 1933 dpaux0: dpaux@155c0000 { 1934 compatible = "nvidia,tegra194-dpaux"; 1935 reg = <0x155c0000 0x10000>; 1936 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1937 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1938 <&bpmp TEGRA194_CLK_PLLDP>; 1939 clock-names = "dpaux", "parent"; 1940 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1941 reset-names = "dpaux"; 1942 status = "disabled"; 1943 1944 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1945 1946 state_dpaux0_aux: pinmux-aux { 1947 groups = "dpaux-io"; 1948 function = "aux"; 1949 }; 1950 1951 state_dpaux0_i2c: pinmux-i2c { 1952 groups = "dpaux-io"; 1953 function = "i2c"; 1954 }; 1955 1956 state_dpaux0_off: pinmux-off { 1957 groups = "dpaux-io"; 1958 function = "off"; 1959 }; 1960 1961 i2c-bus { 1962 #address-cells = <1>; 1963 #size-cells = <0>; 1964 }; 1965 }; 1966 1967 dpaux1: dpaux@155d0000 { 1968 compatible = "nvidia,tegra194-dpaux"; 1969 reg = <0x155d0000 0x10000>; 1970 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1971 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1972 <&bpmp TEGRA194_CLK_PLLDP>; 1973 clock-names = "dpaux", "parent"; 1974 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1975 reset-names = "dpaux"; 1976 status = "disabled"; 1977 1978 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1979 1980 state_dpaux1_aux: pinmux-aux { 1981 groups = "dpaux-io"; 1982 function = "aux"; 1983 }; 1984 1985 state_dpaux1_i2c: pinmux-i2c { 1986 groups = "dpaux-io"; 1987 function = "i2c"; 1988 }; 1989 1990 state_dpaux1_off: pinmux-off { 1991 groups = "dpaux-io"; 1992 function = "off"; 1993 }; 1994 1995 i2c-bus { 1996 #address-cells = <1>; 1997 #size-cells = <0>; 1998 }; 1999 }; 2000 2001 dpaux2: dpaux@155e0000 { 2002 compatible = "nvidia,tegra194-dpaux"; 2003 reg = <0x155e0000 0x10000>; 2004 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2005 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2006 <&bpmp TEGRA194_CLK_PLLDP>; 2007 clock-names = "dpaux", "parent"; 2008 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2009 reset-names = "dpaux"; 2010 status = "disabled"; 2011 2012 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2013 2014 state_dpaux2_aux: pinmux-aux { 2015 groups = "dpaux-io"; 2016 function = "aux"; 2017 }; 2018 2019 state_dpaux2_i2c: pinmux-i2c { 2020 groups = "dpaux-io"; 2021 function = "i2c"; 2022 }; 2023 2024 state_dpaux2_off: pinmux-off { 2025 groups = "dpaux-io"; 2026 function = "off"; 2027 }; 2028 2029 i2c-bus { 2030 #address-cells = <1>; 2031 #size-cells = <0>; 2032 }; 2033 }; 2034 2035 dpaux3: dpaux@155f0000 { 2036 compatible = "nvidia,tegra194-dpaux"; 2037 reg = <0x155f0000 0x10000>; 2038 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2039 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2040 <&bpmp TEGRA194_CLK_PLLDP>; 2041 clock-names = "dpaux", "parent"; 2042 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2043 reset-names = "dpaux"; 2044 status = "disabled"; 2045 2046 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2047 2048 state_dpaux3_aux: pinmux-aux { 2049 groups = "dpaux-io"; 2050 function = "aux"; 2051 }; 2052 2053 state_dpaux3_i2c: pinmux-i2c { 2054 groups = "dpaux-io"; 2055 function = "i2c"; 2056 }; 2057 2058 state_dpaux3_off: pinmux-off { 2059 groups = "dpaux-io"; 2060 function = "off"; 2061 }; 2062 2063 i2c-bus { 2064 #address-cells = <1>; 2065 #size-cells = <0>; 2066 }; 2067 }; 2068 2069 nvenc@15a80000 { 2070 compatible = "nvidia,tegra194-nvenc"; 2071 reg = <0x15a80000 0x00040000>; 2072 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2073 clock-names = "nvenc"; 2074 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2075 reset-names = "nvenc"; 2076 2077 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2078 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2079 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2080 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2081 interconnect-names = "dma-mem", "read-1", "write"; 2082 iommus = <&smmu TEGRA194_SID_NVENC1>; 2083 dma-coherent; 2084 2085 nvidia,host1x-class = <0x22>; 2086 }; 2087 2088 sor0: sor@15b00000 { 2089 compatible = "nvidia,tegra194-sor"; 2090 reg = <0x15b00000 0x40000>; 2091 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2092 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2093 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2094 <&bpmp TEGRA194_CLK_PLLD>, 2095 <&bpmp TEGRA194_CLK_PLLDP>, 2096 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2097 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2098 clock-names = "sor", "out", "parent", "dp", "safe", 2099 "pad"; 2100 resets = <&bpmp TEGRA194_RESET_SOR0>; 2101 reset-names = "sor"; 2102 pinctrl-0 = <&state_dpaux0_aux>; 2103 pinctrl-1 = <&state_dpaux0_i2c>; 2104 pinctrl-2 = <&state_dpaux0_off>; 2105 pinctrl-names = "aux", "i2c", "off"; 2106 status = "disabled"; 2107 2108 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2109 nvidia,interface = <0>; 2110 }; 2111 2112 sor1: sor@15b40000 { 2113 compatible = "nvidia,tegra194-sor"; 2114 reg = <0x15b40000 0x40000>; 2115 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2116 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2117 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2118 <&bpmp TEGRA194_CLK_PLLD2>, 2119 <&bpmp TEGRA194_CLK_PLLDP>, 2120 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2121 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2122 clock-names = "sor", "out", "parent", "dp", "safe", 2123 "pad"; 2124 resets = <&bpmp TEGRA194_RESET_SOR1>; 2125 reset-names = "sor"; 2126 pinctrl-0 = <&state_dpaux1_aux>; 2127 pinctrl-1 = <&state_dpaux1_i2c>; 2128 pinctrl-2 = <&state_dpaux1_off>; 2129 pinctrl-names = "aux", "i2c", "off"; 2130 status = "disabled"; 2131 2132 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2133 nvidia,interface = <1>; 2134 }; 2135 2136 sor2: sor@15b80000 { 2137 compatible = "nvidia,tegra194-sor"; 2138 reg = <0x15b80000 0x40000>; 2139 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2140 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2141 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2142 <&bpmp TEGRA194_CLK_PLLD3>, 2143 <&bpmp TEGRA194_CLK_PLLDP>, 2144 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2145 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2146 clock-names = "sor", "out", "parent", "dp", "safe", 2147 "pad"; 2148 resets = <&bpmp TEGRA194_RESET_SOR2>; 2149 reset-names = "sor"; 2150 pinctrl-0 = <&state_dpaux2_aux>; 2151 pinctrl-1 = <&state_dpaux2_i2c>; 2152 pinctrl-2 = <&state_dpaux2_off>; 2153 pinctrl-names = "aux", "i2c", "off"; 2154 status = "disabled"; 2155 2156 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2157 nvidia,interface = <2>; 2158 }; 2159 2160 sor3: sor@15bc0000 { 2161 compatible = "nvidia,tegra194-sor"; 2162 reg = <0x15bc0000 0x40000>; 2163 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2164 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2165 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2166 <&bpmp TEGRA194_CLK_PLLD4>, 2167 <&bpmp TEGRA194_CLK_PLLDP>, 2168 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2169 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2170 clock-names = "sor", "out", "parent", "dp", "safe", 2171 "pad"; 2172 resets = <&bpmp TEGRA194_RESET_SOR3>; 2173 reset-names = "sor"; 2174 pinctrl-0 = <&state_dpaux3_aux>; 2175 pinctrl-1 = <&state_dpaux3_i2c>; 2176 pinctrl-2 = <&state_dpaux3_off>; 2177 pinctrl-names = "aux", "i2c", "off"; 2178 status = "disabled"; 2179 2180 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2181 nvidia,interface = <3>; 2182 }; 2183 }; 2184 2185 gpu@17000000 { 2186 compatible = "nvidia,gv11b"; 2187 reg = <0x17000000 0x1000000>, 2188 <0x18000000 0x1000000>; 2189 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2190 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2191 interrupt-names = "stall", "nonstall"; 2192 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2193 <&bpmp TEGRA194_CLK_GPU_PWR>, 2194 <&bpmp TEGRA194_CLK_FUSE>; 2195 clock-names = "gpu", "pwr", "fuse"; 2196 resets = <&bpmp TEGRA194_RESET_GPU>; 2197 reset-names = "gpu"; 2198 dma-coherent; 2199 2200 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2201 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2202 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2203 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2204 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2205 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2206 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2207 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2208 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2209 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2210 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2211 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2212 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2213 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2214 "read-1", "read-1-hp", "write-1", 2215 "read-2", "read-2-hp", "write-2", 2216 "read-3", "read-3-hp", "write-3"; 2217 }; 2218 }; 2219 2220 pcie@14100000 { 2221 compatible = "nvidia,tegra194-pcie"; 2222 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2223 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2224 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2225 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2226 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2227 reg-names = "appl", "config", "atu_dma", "dbi"; 2228 2229 status = "disabled"; 2230 2231 #address-cells = <3>; 2232 #size-cells = <2>; 2233 device_type = "pci"; 2234 num-lanes = <1>; 2235 linux,pci-domain = <1>; 2236 2237 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2238 clock-names = "core"; 2239 2240 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2241 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2242 reset-names = "apb", "core"; 2243 2244 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2245 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2246 interrupt-names = "intr", "msi"; 2247 2248 #interrupt-cells = <1>; 2249 interrupt-map-mask = <0 0 0 0>; 2250 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2251 2252 nvidia,bpmp = <&bpmp 1>; 2253 2254 nvidia,aspm-cmrt-us = <60>; 2255 nvidia,aspm-pwr-on-t-us = <20>; 2256 nvidia,aspm-l0s-entrance-latency-us = <3>; 2257 2258 bus-range = <0x0 0xff>; 2259 2260 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2261 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2262 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2263 2264 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2265 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2266 interconnect-names = "dma-mem", "write"; 2267 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2268 iommu-map-mask = <0x0>; 2269 dma-coherent; 2270 }; 2271 2272 pcie@14120000 { 2273 compatible = "nvidia,tegra194-pcie"; 2274 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2275 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2276 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2277 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2278 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2279 reg-names = "appl", "config", "atu_dma", "dbi"; 2280 2281 status = "disabled"; 2282 2283 #address-cells = <3>; 2284 #size-cells = <2>; 2285 device_type = "pci"; 2286 num-lanes = <1>; 2287 linux,pci-domain = <2>; 2288 2289 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2290 clock-names = "core"; 2291 2292 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2293 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2294 reset-names = "apb", "core"; 2295 2296 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2297 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2298 interrupt-names = "intr", "msi"; 2299 2300 #interrupt-cells = <1>; 2301 interrupt-map-mask = <0 0 0 0>; 2302 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2303 2304 nvidia,bpmp = <&bpmp 2>; 2305 2306 nvidia,aspm-cmrt-us = <60>; 2307 nvidia,aspm-pwr-on-t-us = <20>; 2308 nvidia,aspm-l0s-entrance-latency-us = <3>; 2309 2310 bus-range = <0x0 0xff>; 2311 2312 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2313 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2314 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2315 2316 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2317 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2318 interconnect-names = "dma-mem", "write"; 2319 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2320 iommu-map-mask = <0x0>; 2321 dma-coherent; 2322 }; 2323 2324 pcie@14140000 { 2325 compatible = "nvidia,tegra194-pcie"; 2326 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2327 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2328 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2329 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2330 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2331 reg-names = "appl", "config", "atu_dma", "dbi"; 2332 2333 status = "disabled"; 2334 2335 #address-cells = <3>; 2336 #size-cells = <2>; 2337 device_type = "pci"; 2338 num-lanes = <1>; 2339 linux,pci-domain = <3>; 2340 2341 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2342 clock-names = "core"; 2343 2344 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2345 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2346 reset-names = "apb", "core"; 2347 2348 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2349 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2350 interrupt-names = "intr", "msi"; 2351 2352 #interrupt-cells = <1>; 2353 interrupt-map-mask = <0 0 0 0>; 2354 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2355 2356 nvidia,bpmp = <&bpmp 3>; 2357 2358 nvidia,aspm-cmrt-us = <60>; 2359 nvidia,aspm-pwr-on-t-us = <20>; 2360 nvidia,aspm-l0s-entrance-latency-us = <3>; 2361 2362 bus-range = <0x0 0xff>; 2363 2364 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2365 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2366 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2367 2368 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2369 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2370 interconnect-names = "dma-mem", "write"; 2371 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2372 iommu-map-mask = <0x0>; 2373 dma-coherent; 2374 }; 2375 2376 pcie@14160000 { 2377 compatible = "nvidia,tegra194-pcie"; 2378 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2379 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2380 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2381 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2382 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2383 reg-names = "appl", "config", "atu_dma", "dbi"; 2384 2385 status = "disabled"; 2386 2387 #address-cells = <3>; 2388 #size-cells = <2>; 2389 device_type = "pci"; 2390 num-lanes = <4>; 2391 linux,pci-domain = <4>; 2392 2393 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2394 clock-names = "core"; 2395 2396 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2397 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2398 reset-names = "apb", "core"; 2399 2400 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2401 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2402 interrupt-names = "intr", "msi"; 2403 2404 #interrupt-cells = <1>; 2405 interrupt-map-mask = <0 0 0 0>; 2406 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2407 2408 nvidia,bpmp = <&bpmp 4>; 2409 2410 nvidia,aspm-cmrt-us = <60>; 2411 nvidia,aspm-pwr-on-t-us = <20>; 2412 nvidia,aspm-l0s-entrance-latency-us = <3>; 2413 2414 bus-range = <0x0 0xff>; 2415 2416 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2417 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2418 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2419 2420 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2421 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2422 interconnect-names = "dma-mem", "write"; 2423 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2424 iommu-map-mask = <0x0>; 2425 dma-coherent; 2426 }; 2427 2428 pcie@14180000 { 2429 compatible = "nvidia,tegra194-pcie"; 2430 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2431 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2432 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2433 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2434 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2435 reg-names = "appl", "config", "atu_dma", "dbi"; 2436 2437 status = "disabled"; 2438 2439 #address-cells = <3>; 2440 #size-cells = <2>; 2441 device_type = "pci"; 2442 num-lanes = <8>; 2443 linux,pci-domain = <0>; 2444 2445 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2446 clock-names = "core"; 2447 2448 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2449 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2450 reset-names = "apb", "core"; 2451 2452 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2453 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2454 interrupt-names = "intr", "msi"; 2455 2456 #interrupt-cells = <1>; 2457 interrupt-map-mask = <0 0 0 0>; 2458 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2459 2460 nvidia,bpmp = <&bpmp 0>; 2461 2462 nvidia,aspm-cmrt-us = <60>; 2463 nvidia,aspm-pwr-on-t-us = <20>; 2464 nvidia,aspm-l0s-entrance-latency-us = <3>; 2465 2466 bus-range = <0x0 0xff>; 2467 2468 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2469 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2470 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2471 2472 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2473 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2474 interconnect-names = "dma-mem", "write"; 2475 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2476 iommu-map-mask = <0x0>; 2477 dma-coherent; 2478 }; 2479 2480 pcie@141a0000 { 2481 compatible = "nvidia,tegra194-pcie"; 2482 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2483 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2484 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2485 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2486 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2487 reg-names = "appl", "config", "atu_dma", "dbi"; 2488 2489 status = "disabled"; 2490 2491 #address-cells = <3>; 2492 #size-cells = <2>; 2493 device_type = "pci"; 2494 num-lanes = <8>; 2495 linux,pci-domain = <5>; 2496 2497 pinctrl-names = "default"; 2498 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2499 2500 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2501 clock-names = "core"; 2502 2503 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2504 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2505 reset-names = "apb", "core"; 2506 2507 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2508 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2509 interrupt-names = "intr", "msi"; 2510 2511 nvidia,bpmp = <&bpmp 5>; 2512 2513 #interrupt-cells = <1>; 2514 interrupt-map-mask = <0 0 0 0>; 2515 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2516 2517 nvidia,aspm-cmrt-us = <60>; 2518 nvidia,aspm-pwr-on-t-us = <20>; 2519 nvidia,aspm-l0s-entrance-latency-us = <3>; 2520 2521 bus-range = <0x0 0xff>; 2522 2523 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2524 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2525 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2526 2527 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2528 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2529 interconnect-names = "dma-mem", "write"; 2530 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2531 iommu-map-mask = <0x0>; 2532 dma-coherent; 2533 }; 2534 2535 pcie-ep@14160000 { 2536 compatible = "nvidia,tegra194-pcie-ep"; 2537 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2538 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2539 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2540 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2541 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2542 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2543 2544 status = "disabled"; 2545 2546 num-lanes = <4>; 2547 num-ib-windows = <2>; 2548 num-ob-windows = <8>; 2549 2550 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2551 clock-names = "core"; 2552 2553 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2554 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2555 reset-names = "apb", "core"; 2556 2557 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2558 interrupt-names = "intr"; 2559 2560 nvidia,bpmp = <&bpmp 4>; 2561 2562 nvidia,aspm-cmrt-us = <60>; 2563 nvidia,aspm-pwr-on-t-us = <20>; 2564 nvidia,aspm-l0s-entrance-latency-us = <3>; 2565 2566 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2567 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2568 interconnect-names = "dma-mem", "write"; 2569 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2570 iommu-map-mask = <0x0>; 2571 dma-coherent; 2572 }; 2573 2574 pcie-ep@14180000 { 2575 compatible = "nvidia,tegra194-pcie-ep"; 2576 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2577 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2578 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2579 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2580 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2581 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2582 2583 status = "disabled"; 2584 2585 num-lanes = <8>; 2586 num-ib-windows = <2>; 2587 num-ob-windows = <8>; 2588 2589 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2590 clock-names = "core"; 2591 2592 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2593 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2594 reset-names = "apb", "core"; 2595 2596 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2597 interrupt-names = "intr"; 2598 2599 nvidia,bpmp = <&bpmp 0>; 2600 2601 nvidia,aspm-cmrt-us = <60>; 2602 nvidia,aspm-pwr-on-t-us = <20>; 2603 nvidia,aspm-l0s-entrance-latency-us = <3>; 2604 2605 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2606 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2607 interconnect-names = "dma-mem", "write"; 2608 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2609 iommu-map-mask = <0x0>; 2610 dma-coherent; 2611 }; 2612 2613 pcie-ep@141a0000 { 2614 compatible = "nvidia,tegra194-pcie-ep"; 2615 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2616 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2617 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2618 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2619 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2620 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2621 2622 status = "disabled"; 2623 2624 num-lanes = <8>; 2625 num-ib-windows = <2>; 2626 num-ob-windows = <8>; 2627 2628 pinctrl-names = "default"; 2629 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2630 2631 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2632 clock-names = "core"; 2633 2634 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2635 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2636 reset-names = "apb", "core"; 2637 2638 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2639 interrupt-names = "intr"; 2640 2641 nvidia,bpmp = <&bpmp 5>; 2642 2643 nvidia,aspm-cmrt-us = <60>; 2644 nvidia,aspm-pwr-on-t-us = <20>; 2645 nvidia,aspm-l0s-entrance-latency-us = <3>; 2646 2647 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2648 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2649 interconnect-names = "dma-mem", "write"; 2650 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2651 iommu-map-mask = <0x0>; 2652 dma-coherent; 2653 }; 2654 2655 sram@40000000 { 2656 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2657 reg = <0x0 0x40000000 0x0 0x50000>; 2658 #address-cells = <1>; 2659 #size-cells = <1>; 2660 ranges = <0x0 0x0 0x40000000 0x50000>; 2661 2662 cpu_bpmp_tx: sram@4e000 { 2663 reg = <0x4e000 0x1000>; 2664 label = "cpu-bpmp-tx"; 2665 pool; 2666 }; 2667 2668 cpu_bpmp_rx: sram@4f000 { 2669 reg = <0x4f000 0x1000>; 2670 label = "cpu-bpmp-rx"; 2671 pool; 2672 }; 2673 }; 2674 2675 bpmp: bpmp { 2676 compatible = "nvidia,tegra186-bpmp"; 2677 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2678 TEGRA_HSP_DB_MASTER_BPMP>; 2679 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2680 #clock-cells = <1>; 2681 #reset-cells = <1>; 2682 #power-domain-cells = <1>; 2683 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2684 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2685 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2686 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2687 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2688 iommus = <&smmu TEGRA194_SID_BPMP>; 2689 2690 bpmp_i2c: i2c { 2691 compatible = "nvidia,tegra186-bpmp-i2c"; 2692 nvidia,bpmp-bus-id = <5>; 2693 #address-cells = <1>; 2694 #size-cells = <0>; 2695 }; 2696 2697 bpmp_thermal: thermal { 2698 compatible = "nvidia,tegra186-bpmp-thermal"; 2699 #thermal-sensor-cells = <1>; 2700 }; 2701 }; 2702 2703 cpus { 2704 compatible = "nvidia,tegra194-ccplex"; 2705 nvidia,bpmp = <&bpmp>; 2706 #address-cells = <1>; 2707 #size-cells = <0>; 2708 2709 cpu0_0: cpu@0 { 2710 compatible = "nvidia,tegra194-carmel"; 2711 device_type = "cpu"; 2712 reg = <0x000>; 2713 enable-method = "psci"; 2714 i-cache-size = <131072>; 2715 i-cache-line-size = <64>; 2716 i-cache-sets = <512>; 2717 d-cache-size = <65536>; 2718 d-cache-line-size = <64>; 2719 d-cache-sets = <256>; 2720 next-level-cache = <&l2c_0>; 2721 }; 2722 2723 cpu0_1: cpu@1 { 2724 compatible = "nvidia,tegra194-carmel"; 2725 device_type = "cpu"; 2726 reg = <0x001>; 2727 enable-method = "psci"; 2728 i-cache-size = <131072>; 2729 i-cache-line-size = <64>; 2730 i-cache-sets = <512>; 2731 d-cache-size = <65536>; 2732 d-cache-line-size = <64>; 2733 d-cache-sets = <256>; 2734 next-level-cache = <&l2c_0>; 2735 }; 2736 2737 cpu1_0: cpu@100 { 2738 compatible = "nvidia,tegra194-carmel"; 2739 device_type = "cpu"; 2740 reg = <0x100>; 2741 enable-method = "psci"; 2742 i-cache-size = <131072>; 2743 i-cache-line-size = <64>; 2744 i-cache-sets = <512>; 2745 d-cache-size = <65536>; 2746 d-cache-line-size = <64>; 2747 d-cache-sets = <256>; 2748 next-level-cache = <&l2c_1>; 2749 }; 2750 2751 cpu1_1: cpu@101 { 2752 compatible = "nvidia,tegra194-carmel"; 2753 device_type = "cpu"; 2754 reg = <0x101>; 2755 enable-method = "psci"; 2756 i-cache-size = <131072>; 2757 i-cache-line-size = <64>; 2758 i-cache-sets = <512>; 2759 d-cache-size = <65536>; 2760 d-cache-line-size = <64>; 2761 d-cache-sets = <256>; 2762 next-level-cache = <&l2c_1>; 2763 }; 2764 2765 cpu2_0: cpu@200 { 2766 compatible = "nvidia,tegra194-carmel"; 2767 device_type = "cpu"; 2768 reg = <0x200>; 2769 enable-method = "psci"; 2770 i-cache-size = <131072>; 2771 i-cache-line-size = <64>; 2772 i-cache-sets = <512>; 2773 d-cache-size = <65536>; 2774 d-cache-line-size = <64>; 2775 d-cache-sets = <256>; 2776 next-level-cache = <&l2c_2>; 2777 }; 2778 2779 cpu2_1: cpu@201 { 2780 compatible = "nvidia,tegra194-carmel"; 2781 device_type = "cpu"; 2782 reg = <0x201>; 2783 enable-method = "psci"; 2784 i-cache-size = <131072>; 2785 i-cache-line-size = <64>; 2786 i-cache-sets = <512>; 2787 d-cache-size = <65536>; 2788 d-cache-line-size = <64>; 2789 d-cache-sets = <256>; 2790 next-level-cache = <&l2c_2>; 2791 }; 2792 2793 cpu3_0: cpu@300 { 2794 compatible = "nvidia,tegra194-carmel"; 2795 device_type = "cpu"; 2796 reg = <0x300>; 2797 enable-method = "psci"; 2798 i-cache-size = <131072>; 2799 i-cache-line-size = <64>; 2800 i-cache-sets = <512>; 2801 d-cache-size = <65536>; 2802 d-cache-line-size = <64>; 2803 d-cache-sets = <256>; 2804 next-level-cache = <&l2c_3>; 2805 }; 2806 2807 cpu3_1: cpu@301 { 2808 compatible = "nvidia,tegra194-carmel"; 2809 device_type = "cpu"; 2810 reg = <0x301>; 2811 enable-method = "psci"; 2812 i-cache-size = <131072>; 2813 i-cache-line-size = <64>; 2814 i-cache-sets = <512>; 2815 d-cache-size = <65536>; 2816 d-cache-line-size = <64>; 2817 d-cache-sets = <256>; 2818 next-level-cache = <&l2c_3>; 2819 }; 2820 2821 cpu-map { 2822 cluster0 { 2823 core0 { 2824 cpu = <&cpu0_0>; 2825 }; 2826 2827 core1 { 2828 cpu = <&cpu0_1>; 2829 }; 2830 }; 2831 2832 cluster1 { 2833 core0 { 2834 cpu = <&cpu1_0>; 2835 }; 2836 2837 core1 { 2838 cpu = <&cpu1_1>; 2839 }; 2840 }; 2841 2842 cluster2 { 2843 core0 { 2844 cpu = <&cpu2_0>; 2845 }; 2846 2847 core1 { 2848 cpu = <&cpu2_1>; 2849 }; 2850 }; 2851 2852 cluster3 { 2853 core0 { 2854 cpu = <&cpu3_0>; 2855 }; 2856 2857 core1 { 2858 cpu = <&cpu3_1>; 2859 }; 2860 }; 2861 }; 2862 2863 l2c_0: l2-cache0 { 2864 cache-size = <2097152>; 2865 cache-line-size = <64>; 2866 cache-sets = <2048>; 2867 next-level-cache = <&l3c>; 2868 }; 2869 2870 l2c_1: l2-cache1 { 2871 cache-size = <2097152>; 2872 cache-line-size = <64>; 2873 cache-sets = <2048>; 2874 next-level-cache = <&l3c>; 2875 }; 2876 2877 l2c_2: l2-cache2 { 2878 cache-size = <2097152>; 2879 cache-line-size = <64>; 2880 cache-sets = <2048>; 2881 next-level-cache = <&l3c>; 2882 }; 2883 2884 l2c_3: l2-cache3 { 2885 cache-size = <2097152>; 2886 cache-line-size = <64>; 2887 cache-sets = <2048>; 2888 next-level-cache = <&l3c>; 2889 }; 2890 2891 l3c: l3-cache { 2892 cache-size = <4194304>; 2893 cache-line-size = <64>; 2894 cache-sets = <4096>; 2895 }; 2896 }; 2897 2898 pmu { 2899 compatible = "nvidia,carmel-pmu"; 2900 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2901 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2902 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2903 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 2904 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 2905 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 2906 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 2907 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 2908 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 2909 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 2910 }; 2911 2912 psci { 2913 compatible = "arm,psci-1.0"; 2914 status = "okay"; 2915 method = "smc"; 2916 }; 2917 2918 sound { 2919 status = "disabled"; 2920 2921 clocks = <&bpmp TEGRA194_CLK_PLLA>, 2922 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2923 clock-names = "pll_a", "plla_out0"; 2924 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 2925 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 2926 <&bpmp TEGRA194_CLK_AUD_MCLK>; 2927 assigned-clock-parents = <0>, 2928 <&bpmp TEGRA194_CLK_PLLA>, 2929 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2930 /* 2931 * PLLA supports dynamic ramp. Below initial rate is chosen 2932 * for this to work and oscillate between base rates required 2933 * for 8x and 11.025x sample rate streams. 2934 */ 2935 assigned-clock-rates = <258000000>; 2936 }; 2937 2938 tcu: serial { 2939 compatible = "nvidia,tegra194-tcu"; 2940 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2941 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2942 mbox-names = "rx", "tx"; 2943 }; 2944 2945 thermal-zones { 2946 cpu-thermal { 2947 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2948 status = "disabled"; 2949 }; 2950 2951 gpu-thermal { 2952 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2953 status = "disabled"; 2954 }; 2955 2956 aux-thermal { 2957 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2958 status = "disabled"; 2959 }; 2960 2961 pllx-thermal { 2962 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2963 status = "disabled"; 2964 }; 2965 2966 ao-thermal { 2967 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 2968 status = "disabled"; 2969 }; 2970 2971 tj-thermal { 2972 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2973 status = "disabled"; 2974 }; 2975 }; 2976 2977 timer { 2978 compatible = "arm,armv8-timer"; 2979 interrupts = <GIC_PPI 13 2980 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2981 <GIC_PPI 14 2982 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2983 <GIC_PPI 11 2984 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2985 <GIC_PPI 10 2986 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2987 interrupt-parent = <&gic>; 2988 always-on; 2989 }; 2990}; 2991