1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/reset/tegra194-reset.h> 9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10#include <dt-bindings/memory/tegra194-mc.h> 11 12/ { 13 compatible = "nvidia,tegra194"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* control backbone */ 19 bus@0 { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra194-misc"; 27 reg = <0x00100000 0xf000>, 28 <0x0010f000 0x1000>; 29 }; 30 31 gpio: gpio@2200000 { 32 compatible = "nvidia,tegra194-gpio"; 33 reg-names = "security", "gpio"; 34 reg = <0x2200000 0x10000>, 35 <0x2210000 0x10000>; 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 84 #interrupt-cells = <2>; 85 interrupt-controller; 86 #gpio-cells = <2>; 87 gpio-controller; 88 }; 89 90 ethernet@2490000 { 91 compatible = "nvidia,tegra194-eqos", 92 "nvidia,tegra186-eqos", 93 "snps,dwc-qos-ethernet-4.10"; 94 reg = <0x02490000 0x10000>; 95 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 96 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 97 <&bpmp TEGRA194_CLK_EQOS_AXI>, 98 <&bpmp TEGRA194_CLK_EQOS_RX>, 99 <&bpmp TEGRA194_CLK_EQOS_TX>, 100 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 101 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 102 resets = <&bpmp TEGRA194_RESET_EQOS>; 103 reset-names = "eqos"; 104 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 105 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 106 interconnect-names = "dma-mem", "write"; 107 iommus = <&smmu TEGRA194_SID_EQOS>; 108 status = "disabled"; 109 110 snps,write-requests = <1>; 111 snps,read-requests = <3>; 112 snps,burst-map = <0x7>; 113 snps,txpbl = <16>; 114 snps,rxpbl = <8>; 115 }; 116 117 aconnect@2900000 { 118 compatible = "nvidia,tegra194-aconnect", 119 "nvidia,tegra210-aconnect"; 120 clocks = <&bpmp TEGRA194_CLK_APE>, 121 <&bpmp TEGRA194_CLK_APB2APE>; 122 clock-names = "ape", "apb2ape"; 123 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 ranges = <0x02900000 0x02900000 0x200000>; 127 status = "disabled"; 128 129 adma: dma-controller@2930000 { 130 compatible = "nvidia,tegra194-adma", 131 "nvidia,tegra186-adma"; 132 reg = <0x02930000 0x20000>; 133 interrupt-parent = <&agic>; 134 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 166 #dma-cells = <1>; 167 clocks = <&bpmp TEGRA194_CLK_AHUB>; 168 clock-names = "d_audio"; 169 status = "disabled"; 170 }; 171 172 agic: interrupt-controller@2a40000 { 173 compatible = "nvidia,tegra194-agic", 174 "nvidia,tegra210-agic"; 175 #interrupt-cells = <3>; 176 interrupt-controller; 177 reg = <0x02a41000 0x1000>, 178 <0x02a42000 0x2000>; 179 interrupts = <GIC_SPI 145 180 (GIC_CPU_MASK_SIMPLE(4) | 181 IRQ_TYPE_LEVEL_HIGH)>; 182 clocks = <&bpmp TEGRA194_CLK_APE>; 183 clock-names = "clk"; 184 status = "disabled"; 185 }; 186 187 tegra_ahub: ahub@2900800 { 188 compatible = "nvidia,tegra194-ahub", 189 "nvidia,tegra186-ahub"; 190 reg = <0x02900800 0x800>; 191 clocks = <&bpmp TEGRA194_CLK_AHUB>; 192 clock-names = "ahub"; 193 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 194 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 ranges = <0x02900800 0x02900800 0x11800>; 198 status = "disabled"; 199 200 tegra_admaif: admaif@290f000 { 201 compatible = "nvidia,tegra194-admaif", 202 "nvidia,tegra186-admaif"; 203 reg = <0x0290f000 0x1000>; 204 dmas = <&adma 1>, <&adma 1>, 205 <&adma 2>, <&adma 2>, 206 <&adma 3>, <&adma 3>, 207 <&adma 4>, <&adma 4>, 208 <&adma 5>, <&adma 5>, 209 <&adma 6>, <&adma 6>, 210 <&adma 7>, <&adma 7>, 211 <&adma 8>, <&adma 8>, 212 <&adma 9>, <&adma 9>, 213 <&adma 10>, <&adma 10>, 214 <&adma 11>, <&adma 11>, 215 <&adma 12>, <&adma 12>, 216 <&adma 13>, <&adma 13>, 217 <&adma 14>, <&adma 14>, 218 <&adma 15>, <&adma 15>, 219 <&adma 16>, <&adma 16>, 220 <&adma 17>, <&adma 17>, 221 <&adma 18>, <&adma 18>, 222 <&adma 19>, <&adma 19>, 223 <&adma 20>, <&adma 20>; 224 dma-names = "rx1", "tx1", 225 "rx2", "tx2", 226 "rx3", "tx3", 227 "rx4", "tx4", 228 "rx5", "tx5", 229 "rx6", "tx6", 230 "rx7", "tx7", 231 "rx8", "tx8", 232 "rx9", "tx9", 233 "rx10", "tx10", 234 "rx11", "tx11", 235 "rx12", "tx12", 236 "rx13", "tx13", 237 "rx14", "tx14", 238 "rx15", "tx15", 239 "rx16", "tx16", 240 "rx17", "tx17", 241 "rx18", "tx18", 242 "rx19", "tx19", 243 "rx20", "tx20"; 244 status = "disabled"; 245 }; 246 247 tegra_i2s1: i2s@2901000 { 248 compatible = "nvidia,tegra194-i2s", 249 "nvidia,tegra210-i2s"; 250 reg = <0x2901000 0x100>; 251 clocks = <&bpmp TEGRA194_CLK_I2S1>, 252 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 253 clock-names = "i2s", "sync_input"; 254 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 255 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 256 assigned-clock-rates = <1536000>; 257 sound-name-prefix = "I2S1"; 258 status = "disabled"; 259 }; 260 261 tegra_i2s2: i2s@2901100 { 262 compatible = "nvidia,tegra194-i2s", 263 "nvidia,tegra210-i2s"; 264 reg = <0x2901100 0x100>; 265 clocks = <&bpmp TEGRA194_CLK_I2S2>, 266 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 267 clock-names = "i2s", "sync_input"; 268 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 269 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 270 assigned-clock-rates = <1536000>; 271 sound-name-prefix = "I2S2"; 272 status = "disabled"; 273 }; 274 275 tegra_i2s3: i2s@2901200 { 276 compatible = "nvidia,tegra194-i2s", 277 "nvidia,tegra210-i2s"; 278 reg = <0x2901200 0x100>; 279 clocks = <&bpmp TEGRA194_CLK_I2S3>, 280 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 281 clock-names = "i2s", "sync_input"; 282 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 283 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 284 assigned-clock-rates = <1536000>; 285 sound-name-prefix = "I2S3"; 286 status = "disabled"; 287 }; 288 289 tegra_i2s4: i2s@2901300 { 290 compatible = "nvidia,tegra194-i2s", 291 "nvidia,tegra210-i2s"; 292 reg = <0x2901300 0x100>; 293 clocks = <&bpmp TEGRA194_CLK_I2S4>, 294 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 295 clock-names = "i2s", "sync_input"; 296 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 297 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 298 assigned-clock-rates = <1536000>; 299 sound-name-prefix = "I2S4"; 300 status = "disabled"; 301 }; 302 303 tegra_i2s5: i2s@2901400 { 304 compatible = "nvidia,tegra194-i2s", 305 "nvidia,tegra210-i2s"; 306 reg = <0x2901400 0x100>; 307 clocks = <&bpmp TEGRA194_CLK_I2S5>, 308 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 309 clock-names = "i2s", "sync_input"; 310 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 311 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 312 assigned-clock-rates = <1536000>; 313 sound-name-prefix = "I2S5"; 314 status = "disabled"; 315 }; 316 317 tegra_i2s6: i2s@2901500 { 318 compatible = "nvidia,tegra194-i2s", 319 "nvidia,tegra210-i2s"; 320 reg = <0x2901500 0x100>; 321 clocks = <&bpmp TEGRA194_CLK_I2S6>, 322 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 323 clock-names = "i2s", "sync_input"; 324 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 325 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 326 assigned-clock-rates = <1536000>; 327 sound-name-prefix = "I2S6"; 328 status = "disabled"; 329 }; 330 331 tegra_dmic1: dmic@2904000 { 332 compatible = "nvidia,tegra194-dmic", 333 "nvidia,tegra210-dmic"; 334 reg = <0x2904000 0x100>; 335 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 336 clock-names = "dmic"; 337 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 338 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 339 assigned-clock-rates = <3072000>; 340 sound-name-prefix = "DMIC1"; 341 status = "disabled"; 342 }; 343 344 tegra_dmic2: dmic@2904100 { 345 compatible = "nvidia,tegra194-dmic", 346 "nvidia,tegra210-dmic"; 347 reg = <0x2904100 0x100>; 348 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 349 clock-names = "dmic"; 350 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 351 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 352 assigned-clock-rates = <3072000>; 353 sound-name-prefix = "DMIC2"; 354 status = "disabled"; 355 }; 356 357 tegra_dmic3: dmic@2904200 { 358 compatible = "nvidia,tegra194-dmic", 359 "nvidia,tegra210-dmic"; 360 reg = <0x2904200 0x100>; 361 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 362 clock-names = "dmic"; 363 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 364 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 365 assigned-clock-rates = <3072000>; 366 sound-name-prefix = "DMIC3"; 367 status = "disabled"; 368 }; 369 370 tegra_dmic4: dmic@2904300 { 371 compatible = "nvidia,tegra194-dmic", 372 "nvidia,tegra210-dmic"; 373 reg = <0x2904300 0x100>; 374 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 375 clock-names = "dmic"; 376 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 377 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 378 assigned-clock-rates = <3072000>; 379 sound-name-prefix = "DMIC4"; 380 status = "disabled"; 381 }; 382 383 tegra_dspk1: dspk@2905000 { 384 compatible = "nvidia,tegra194-dspk", 385 "nvidia,tegra186-dspk"; 386 reg = <0x2905000 0x100>; 387 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 388 clock-names = "dspk"; 389 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 390 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 391 assigned-clock-rates = <12288000>; 392 sound-name-prefix = "DSPK1"; 393 status = "disabled"; 394 }; 395 396 tegra_dspk2: dspk@2905100 { 397 compatible = "nvidia,tegra194-dspk", 398 "nvidia,tegra186-dspk"; 399 reg = <0x2905100 0x100>; 400 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 401 clock-names = "dspk"; 402 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 403 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 404 assigned-clock-rates = <12288000>; 405 sound-name-prefix = "DSPK2"; 406 status = "disabled"; 407 }; 408 }; 409 }; 410 411 pinmux: pinmux@2430000 { 412 compatible = "nvidia,tegra194-pinmux"; 413 reg = <0x2430000 0x17000>, 414 <0xc300000 0x4000>; 415 416 status = "okay"; 417 418 pex_rst_c5_out_state: pex_rst_c5_out { 419 pex_rst { 420 nvidia,pins = "pex_l5_rst_n_pgg1"; 421 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 422 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 423 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 424 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 425 nvidia,tristate = <TEGRA_PIN_DISABLE>; 426 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 427 }; 428 }; 429 430 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 431 clkreq { 432 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 433 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 434 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 435 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 436 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 437 nvidia,tristate = <TEGRA_PIN_DISABLE>; 438 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 439 }; 440 }; 441 }; 442 443 mc: memory-controller@2c00000 { 444 compatible = "nvidia,tegra194-mc"; 445 reg = <0x02c00000 0x100000>, 446 <0x02b80000 0x040000>, 447 <0x01700000 0x100000>; 448 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 449 #interconnect-cells = <1>; 450 status = "disabled"; 451 452 #address-cells = <2>; 453 #size-cells = <2>; 454 455 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 456 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 457 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 458 459 /* 460 * Bit 39 of addresses passing through the memory 461 * controller selects the XBAR format used when memory 462 * is accessed. This is used to transparently access 463 * memory in the XBAR format used by the discrete GPU 464 * (bit 39 set) or Tegra (bit 39 clear). 465 * 466 * As a consequence, the operating system must ensure 467 * that bit 39 is never used implicitly, for example 468 * via an I/O virtual address mapping of an IOMMU. If 469 * devices require access to the XBAR switch, their 470 * drivers must set this bit explicitly. 471 * 472 * Limit the DMA range for memory clients to [38:0]. 473 */ 474 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 475 476 emc: external-memory-controller@2c60000 { 477 compatible = "nvidia,tegra194-emc"; 478 reg = <0x0 0x02c60000 0x0 0x90000>, 479 <0x0 0x01780000 0x0 0x80000>; 480 clocks = <&bpmp TEGRA194_CLK_EMC>; 481 clock-names = "emc"; 482 483 #interconnect-cells = <0>; 484 485 nvidia,bpmp = <&bpmp>; 486 }; 487 }; 488 489 uarta: serial@3100000 { 490 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 491 reg = <0x03100000 0x40>; 492 reg-shift = <2>; 493 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&bpmp TEGRA194_CLK_UARTA>; 495 clock-names = "serial"; 496 resets = <&bpmp TEGRA194_RESET_UARTA>; 497 reset-names = "serial"; 498 status = "disabled"; 499 }; 500 501 uartb: serial@3110000 { 502 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 503 reg = <0x03110000 0x40>; 504 reg-shift = <2>; 505 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&bpmp TEGRA194_CLK_UARTB>; 507 clock-names = "serial"; 508 resets = <&bpmp TEGRA194_RESET_UARTB>; 509 reset-names = "serial"; 510 status = "disabled"; 511 }; 512 513 uartd: serial@3130000 { 514 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 515 reg = <0x03130000 0x40>; 516 reg-shift = <2>; 517 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&bpmp TEGRA194_CLK_UARTD>; 519 clock-names = "serial"; 520 resets = <&bpmp TEGRA194_RESET_UARTD>; 521 reset-names = "serial"; 522 status = "disabled"; 523 }; 524 525 uarte: serial@3140000 { 526 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 527 reg = <0x03140000 0x40>; 528 reg-shift = <2>; 529 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&bpmp TEGRA194_CLK_UARTE>; 531 clock-names = "serial"; 532 resets = <&bpmp TEGRA194_RESET_UARTE>; 533 reset-names = "serial"; 534 status = "disabled"; 535 }; 536 537 uartf: serial@3150000 { 538 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 539 reg = <0x03150000 0x40>; 540 reg-shift = <2>; 541 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&bpmp TEGRA194_CLK_UARTF>; 543 clock-names = "serial"; 544 resets = <&bpmp TEGRA194_RESET_UARTF>; 545 reset-names = "serial"; 546 status = "disabled"; 547 }; 548 549 gen1_i2c: i2c@3160000 { 550 compatible = "nvidia,tegra194-i2c"; 551 reg = <0x03160000 0x10000>; 552 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 clocks = <&bpmp TEGRA194_CLK_I2C1>; 556 clock-names = "div-clk"; 557 resets = <&bpmp TEGRA194_RESET_I2C1>; 558 reset-names = "i2c"; 559 status = "disabled"; 560 }; 561 562 uarth: serial@3170000 { 563 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 564 reg = <0x03170000 0x40>; 565 reg-shift = <2>; 566 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&bpmp TEGRA194_CLK_UARTH>; 568 clock-names = "serial"; 569 resets = <&bpmp TEGRA194_RESET_UARTH>; 570 reset-names = "serial"; 571 status = "disabled"; 572 }; 573 574 cam_i2c: i2c@3180000 { 575 compatible = "nvidia,tegra194-i2c"; 576 reg = <0x03180000 0x10000>; 577 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 clocks = <&bpmp TEGRA194_CLK_I2C3>; 581 clock-names = "div-clk"; 582 resets = <&bpmp TEGRA194_RESET_I2C3>; 583 reset-names = "i2c"; 584 status = "disabled"; 585 }; 586 587 /* shares pads with dpaux1 */ 588 dp_aux_ch1_i2c: i2c@3190000 { 589 compatible = "nvidia,tegra194-i2c"; 590 reg = <0x03190000 0x10000>; 591 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 clocks = <&bpmp TEGRA194_CLK_I2C4>; 595 clock-names = "div-clk"; 596 resets = <&bpmp TEGRA194_RESET_I2C4>; 597 reset-names = "i2c"; 598 pinctrl-0 = <&state_dpaux1_i2c>; 599 pinctrl-1 = <&state_dpaux1_off>; 600 pinctrl-names = "default", "idle"; 601 status = "disabled"; 602 }; 603 604 /* shares pads with dpaux0 */ 605 dp_aux_ch0_i2c: i2c@31b0000 { 606 compatible = "nvidia,tegra194-i2c"; 607 reg = <0x031b0000 0x10000>; 608 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 clocks = <&bpmp TEGRA194_CLK_I2C6>; 612 clock-names = "div-clk"; 613 resets = <&bpmp TEGRA194_RESET_I2C6>; 614 reset-names = "i2c"; 615 pinctrl-0 = <&state_dpaux0_i2c>; 616 pinctrl-1 = <&state_dpaux0_off>; 617 pinctrl-names = "default", "idle"; 618 status = "disabled"; 619 }; 620 621 /* shares pads with dpaux2 */ 622 dp_aux_ch2_i2c: i2c@31c0000 { 623 compatible = "nvidia,tegra194-i2c"; 624 reg = <0x031c0000 0x10000>; 625 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 clocks = <&bpmp TEGRA194_CLK_I2C7>; 629 clock-names = "div-clk"; 630 resets = <&bpmp TEGRA194_RESET_I2C7>; 631 reset-names = "i2c"; 632 pinctrl-0 = <&state_dpaux2_i2c>; 633 pinctrl-1 = <&state_dpaux2_off>; 634 pinctrl-names = "default", "idle"; 635 status = "disabled"; 636 }; 637 638 /* shares pads with dpaux3 */ 639 dp_aux_ch3_i2c: i2c@31e0000 { 640 compatible = "nvidia,tegra194-i2c"; 641 reg = <0x031e0000 0x10000>; 642 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 clocks = <&bpmp TEGRA194_CLK_I2C9>; 646 clock-names = "div-clk"; 647 resets = <&bpmp TEGRA194_RESET_I2C9>; 648 reset-names = "i2c"; 649 pinctrl-0 = <&state_dpaux3_i2c>; 650 pinctrl-1 = <&state_dpaux3_off>; 651 pinctrl-names = "default", "idle"; 652 status = "disabled"; 653 }; 654 655 spi@3270000 { 656 compatible = "nvidia,tegra194-qspi"; 657 reg = <0x3270000 0x1000>; 658 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 662 <&bpmp TEGRA194_CLK_QSPI0_PM>; 663 clock-names = "qspi", "qspi_out"; 664 resets = <&bpmp TEGRA194_RESET_QSPI0>; 665 reset-names = "qspi"; 666 status = "disabled"; 667 }; 668 669 spi@3300000 { 670 compatible = "nvidia,tegra194-qspi"; 671 reg = <0x3300000 0x1000>; 672 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 676 <&bpmp TEGRA194_CLK_QSPI1_PM>; 677 clock-names = "qspi", "qspi_out"; 678 resets = <&bpmp TEGRA194_RESET_QSPI1>; 679 reset-names = "qspi"; 680 status = "disabled"; 681 }; 682 683 pwm1: pwm@3280000 { 684 compatible = "nvidia,tegra194-pwm", 685 "nvidia,tegra186-pwm"; 686 reg = <0x3280000 0x10000>; 687 clocks = <&bpmp TEGRA194_CLK_PWM1>; 688 clock-names = "pwm"; 689 resets = <&bpmp TEGRA194_RESET_PWM1>; 690 reset-names = "pwm"; 691 status = "disabled"; 692 #pwm-cells = <2>; 693 }; 694 695 pwm2: pwm@3290000 { 696 compatible = "nvidia,tegra194-pwm", 697 "nvidia,tegra186-pwm"; 698 reg = <0x3290000 0x10000>; 699 clocks = <&bpmp TEGRA194_CLK_PWM2>; 700 clock-names = "pwm"; 701 resets = <&bpmp TEGRA194_RESET_PWM2>; 702 reset-names = "pwm"; 703 status = "disabled"; 704 #pwm-cells = <2>; 705 }; 706 707 pwm3: pwm@32a0000 { 708 compatible = "nvidia,tegra194-pwm", 709 "nvidia,tegra186-pwm"; 710 reg = <0x32a0000 0x10000>; 711 clocks = <&bpmp TEGRA194_CLK_PWM3>; 712 clock-names = "pwm"; 713 resets = <&bpmp TEGRA194_RESET_PWM3>; 714 reset-names = "pwm"; 715 status = "disabled"; 716 #pwm-cells = <2>; 717 }; 718 719 pwm5: pwm@32c0000 { 720 compatible = "nvidia,tegra194-pwm", 721 "nvidia,tegra186-pwm"; 722 reg = <0x32c0000 0x10000>; 723 clocks = <&bpmp TEGRA194_CLK_PWM5>; 724 clock-names = "pwm"; 725 resets = <&bpmp TEGRA194_RESET_PWM5>; 726 reset-names = "pwm"; 727 status = "disabled"; 728 #pwm-cells = <2>; 729 }; 730 731 pwm6: pwm@32d0000 { 732 compatible = "nvidia,tegra194-pwm", 733 "nvidia,tegra186-pwm"; 734 reg = <0x32d0000 0x10000>; 735 clocks = <&bpmp TEGRA194_CLK_PWM6>; 736 clock-names = "pwm"; 737 resets = <&bpmp TEGRA194_RESET_PWM6>; 738 reset-names = "pwm"; 739 status = "disabled"; 740 #pwm-cells = <2>; 741 }; 742 743 pwm7: pwm@32e0000 { 744 compatible = "nvidia,tegra194-pwm", 745 "nvidia,tegra186-pwm"; 746 reg = <0x32e0000 0x10000>; 747 clocks = <&bpmp TEGRA194_CLK_PWM7>; 748 clock-names = "pwm"; 749 resets = <&bpmp TEGRA194_RESET_PWM7>; 750 reset-names = "pwm"; 751 status = "disabled"; 752 #pwm-cells = <2>; 753 }; 754 755 pwm8: pwm@32f0000 { 756 compatible = "nvidia,tegra194-pwm", 757 "nvidia,tegra186-pwm"; 758 reg = <0x32f0000 0x10000>; 759 clocks = <&bpmp TEGRA194_CLK_PWM8>; 760 clock-names = "pwm"; 761 resets = <&bpmp TEGRA194_RESET_PWM8>; 762 reset-names = "pwm"; 763 status = "disabled"; 764 #pwm-cells = <2>; 765 }; 766 767 sdmmc1: mmc@3400000 { 768 compatible = "nvidia,tegra194-sdhci"; 769 reg = <0x03400000 0x10000>; 770 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 772 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 773 clock-names = "sdhci", "tmclk"; 774 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 775 reset-names = "sdhci"; 776 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 777 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 778 interconnect-names = "dma-mem", "write"; 779 iommus = <&smmu TEGRA194_SID_SDMMC1>; 780 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 781 <0x07>; 782 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 783 <0x07>; 784 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 785 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 786 <0x07>; 787 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 788 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 789 nvidia,default-tap = <0x9>; 790 nvidia,default-trim = <0x5>; 791 status = "disabled"; 792 }; 793 794 sdmmc3: mmc@3440000 { 795 compatible = "nvidia,tegra194-sdhci"; 796 reg = <0x03440000 0x10000>; 797 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 799 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 800 clock-names = "sdhci", "tmclk"; 801 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 802 reset-names = "sdhci"; 803 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 804 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 805 interconnect-names = "dma-mem", "write"; 806 iommus = <&smmu TEGRA194_SID_SDMMC3>; 807 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 808 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 809 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 810 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 811 <0x07>; 812 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 813 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 814 <0x07>; 815 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 816 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 817 nvidia,default-tap = <0x9>; 818 nvidia,default-trim = <0x5>; 819 status = "disabled"; 820 }; 821 822 sdmmc4: mmc@3460000 { 823 compatible = "nvidia,tegra194-sdhci"; 824 reg = <0x03460000 0x10000>; 825 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 827 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 828 clock-names = "sdhci", "tmclk"; 829 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 830 <&bpmp TEGRA194_CLK_PLLC4>; 831 assigned-clock-parents = 832 <&bpmp TEGRA194_CLK_PLLC4>; 833 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 834 reset-names = "sdhci"; 835 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 836 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 837 interconnect-names = "dma-mem", "write"; 838 iommus = <&smmu TEGRA194_SID_SDMMC4>; 839 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 840 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 841 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 842 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 843 <0x0a>; 844 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 845 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 846 <0x0a>; 847 nvidia,default-tap = <0x8>; 848 nvidia,default-trim = <0x14>; 849 nvidia,dqs-trim = <40>; 850 supports-cqe; 851 status = "disabled"; 852 }; 853 854 hda@3510000 { 855 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 856 reg = <0x3510000 0x10000>; 857 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&bpmp TEGRA194_CLK_HDA>, 859 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 860 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 861 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 862 resets = <&bpmp TEGRA194_RESET_HDA>, 863 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>, 864 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>; 865 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 866 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 867 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 868 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 869 interconnect-names = "dma-mem", "write"; 870 iommus = <&smmu TEGRA194_SID_HDA>; 871 status = "disabled"; 872 }; 873 874 xusb_padctl: padctl@3520000 { 875 compatible = "nvidia,tegra194-xusb-padctl"; 876 reg = <0x03520000 0x1000>, 877 <0x03540000 0x1000>; 878 reg-names = "padctl", "ao"; 879 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 880 881 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 882 reset-names = "padctl"; 883 884 status = "disabled"; 885 886 pads { 887 usb2 { 888 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 889 clock-names = "trk"; 890 891 lanes { 892 usb2-0 { 893 nvidia,function = "xusb"; 894 status = "disabled"; 895 #phy-cells = <0>; 896 }; 897 898 usb2-1 { 899 nvidia,function = "xusb"; 900 status = "disabled"; 901 #phy-cells = <0>; 902 }; 903 904 usb2-2 { 905 nvidia,function = "xusb"; 906 status = "disabled"; 907 #phy-cells = <0>; 908 }; 909 910 usb2-3 { 911 nvidia,function = "xusb"; 912 status = "disabled"; 913 #phy-cells = <0>; 914 }; 915 }; 916 }; 917 918 usb3 { 919 lanes { 920 usb3-0 { 921 nvidia,function = "xusb"; 922 status = "disabled"; 923 #phy-cells = <0>; 924 }; 925 926 usb3-1 { 927 nvidia,function = "xusb"; 928 status = "disabled"; 929 #phy-cells = <0>; 930 }; 931 932 usb3-2 { 933 nvidia,function = "xusb"; 934 status = "disabled"; 935 #phy-cells = <0>; 936 }; 937 938 usb3-3 { 939 nvidia,function = "xusb"; 940 status = "disabled"; 941 #phy-cells = <0>; 942 }; 943 }; 944 }; 945 }; 946 947 ports { 948 usb2-0 { 949 status = "disabled"; 950 }; 951 952 usb2-1 { 953 status = "disabled"; 954 }; 955 956 usb2-2 { 957 status = "disabled"; 958 }; 959 960 usb2-3 { 961 status = "disabled"; 962 }; 963 964 usb3-0 { 965 status = "disabled"; 966 }; 967 968 usb3-1 { 969 status = "disabled"; 970 }; 971 972 usb3-2 { 973 status = "disabled"; 974 }; 975 976 usb3-3 { 977 status = "disabled"; 978 }; 979 }; 980 }; 981 982 usb@3550000 { 983 compatible = "nvidia,tegra194-xudc"; 984 reg = <0x03550000 0x8000>, 985 <0x03558000 0x1000>; 986 reg-names = "base", "fpci"; 987 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 989 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 990 <&bpmp TEGRA194_CLK_XUSB_SS>, 991 <&bpmp TEGRA194_CLK_XUSB_FS>; 992 clock-names = "dev", "ss", "ss_src", "fs_src"; 993 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 994 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 995 interconnect-names = "dma-mem", "write"; 996 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 997 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 998 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 999 power-domain-names = "dev", "ss"; 1000 nvidia,xusb-padctl = <&xusb_padctl>; 1001 status = "disabled"; 1002 }; 1003 1004 usb@3610000 { 1005 compatible = "nvidia,tegra194-xusb"; 1006 reg = <0x03610000 0x40000>, 1007 <0x03600000 0x10000>; 1008 reg-names = "hcd", "fpci"; 1009 1010 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1012 1013 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1014 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1015 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1016 <&bpmp TEGRA194_CLK_XUSB_SS>, 1017 <&bpmp TEGRA194_CLK_CLK_M>, 1018 <&bpmp TEGRA194_CLK_XUSB_FS>, 1019 <&bpmp TEGRA194_CLK_UTMIPLL>, 1020 <&bpmp TEGRA194_CLK_CLK_M>, 1021 <&bpmp TEGRA194_CLK_PLLE>; 1022 clock-names = "xusb_host", "xusb_falcon_src", 1023 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1024 "xusb_fs_src", "pll_u_480m", "clk_m", 1025 "pll_e"; 1026 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1027 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1028 interconnect-names = "dma-mem", "write"; 1029 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1030 1031 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1032 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1033 power-domain-names = "xusb_host", "xusb_ss"; 1034 1035 nvidia,xusb-padctl = <&xusb_padctl>; 1036 status = "disabled"; 1037 }; 1038 1039 fuse@3820000 { 1040 compatible = "nvidia,tegra194-efuse"; 1041 reg = <0x03820000 0x10000>; 1042 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1043 clock-names = "fuse"; 1044 }; 1045 1046 gic: interrupt-controller@3881000 { 1047 compatible = "arm,gic-400"; 1048 #interrupt-cells = <3>; 1049 interrupt-controller; 1050 reg = <0x03881000 0x1000>, 1051 <0x03882000 0x2000>, 1052 <0x03884000 0x2000>, 1053 <0x03886000 0x2000>; 1054 interrupts = <GIC_PPI 9 1055 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1056 interrupt-parent = <&gic>; 1057 }; 1058 1059 cec@3960000 { 1060 compatible = "nvidia,tegra194-cec"; 1061 reg = <0x03960000 0x10000>; 1062 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&bpmp TEGRA194_CLK_CEC>; 1064 clock-names = "cec"; 1065 status = "disabled"; 1066 }; 1067 1068 hsp_top0: hsp@3c00000 { 1069 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1070 reg = <0x03c00000 0xa0000>; 1071 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1080 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1081 "shared3", "shared4", "shared5", "shared6", 1082 "shared7"; 1083 #mbox-cells = <2>; 1084 }; 1085 1086 p2u_hsio_0: phy@3e10000 { 1087 compatible = "nvidia,tegra194-p2u"; 1088 reg = <0x03e10000 0x10000>; 1089 reg-names = "ctl"; 1090 1091 #phy-cells = <0>; 1092 }; 1093 1094 p2u_hsio_1: phy@3e20000 { 1095 compatible = "nvidia,tegra194-p2u"; 1096 reg = <0x03e20000 0x10000>; 1097 reg-names = "ctl"; 1098 1099 #phy-cells = <0>; 1100 }; 1101 1102 p2u_hsio_2: phy@3e30000 { 1103 compatible = "nvidia,tegra194-p2u"; 1104 reg = <0x03e30000 0x10000>; 1105 reg-names = "ctl"; 1106 1107 #phy-cells = <0>; 1108 }; 1109 1110 p2u_hsio_3: phy@3e40000 { 1111 compatible = "nvidia,tegra194-p2u"; 1112 reg = <0x03e40000 0x10000>; 1113 reg-names = "ctl"; 1114 1115 #phy-cells = <0>; 1116 }; 1117 1118 p2u_hsio_4: phy@3e50000 { 1119 compatible = "nvidia,tegra194-p2u"; 1120 reg = <0x03e50000 0x10000>; 1121 reg-names = "ctl"; 1122 1123 #phy-cells = <0>; 1124 }; 1125 1126 p2u_hsio_5: phy@3e60000 { 1127 compatible = "nvidia,tegra194-p2u"; 1128 reg = <0x03e60000 0x10000>; 1129 reg-names = "ctl"; 1130 1131 #phy-cells = <0>; 1132 }; 1133 1134 p2u_hsio_6: phy@3e70000 { 1135 compatible = "nvidia,tegra194-p2u"; 1136 reg = <0x03e70000 0x10000>; 1137 reg-names = "ctl"; 1138 1139 #phy-cells = <0>; 1140 }; 1141 1142 p2u_hsio_7: phy@3e80000 { 1143 compatible = "nvidia,tegra194-p2u"; 1144 reg = <0x03e80000 0x10000>; 1145 reg-names = "ctl"; 1146 1147 #phy-cells = <0>; 1148 }; 1149 1150 p2u_hsio_8: phy@3e90000 { 1151 compatible = "nvidia,tegra194-p2u"; 1152 reg = <0x03e90000 0x10000>; 1153 reg-names = "ctl"; 1154 1155 #phy-cells = <0>; 1156 }; 1157 1158 p2u_hsio_9: phy@3ea0000 { 1159 compatible = "nvidia,tegra194-p2u"; 1160 reg = <0x03ea0000 0x10000>; 1161 reg-names = "ctl"; 1162 1163 #phy-cells = <0>; 1164 }; 1165 1166 p2u_nvhs_0: phy@3eb0000 { 1167 compatible = "nvidia,tegra194-p2u"; 1168 reg = <0x03eb0000 0x10000>; 1169 reg-names = "ctl"; 1170 1171 #phy-cells = <0>; 1172 }; 1173 1174 p2u_nvhs_1: phy@3ec0000 { 1175 compatible = "nvidia,tegra194-p2u"; 1176 reg = <0x03ec0000 0x10000>; 1177 reg-names = "ctl"; 1178 1179 #phy-cells = <0>; 1180 }; 1181 1182 p2u_nvhs_2: phy@3ed0000 { 1183 compatible = "nvidia,tegra194-p2u"; 1184 reg = <0x03ed0000 0x10000>; 1185 reg-names = "ctl"; 1186 1187 #phy-cells = <0>; 1188 }; 1189 1190 p2u_nvhs_3: phy@3ee0000 { 1191 compatible = "nvidia,tegra194-p2u"; 1192 reg = <0x03ee0000 0x10000>; 1193 reg-names = "ctl"; 1194 1195 #phy-cells = <0>; 1196 }; 1197 1198 p2u_nvhs_4: phy@3ef0000 { 1199 compatible = "nvidia,tegra194-p2u"; 1200 reg = <0x03ef0000 0x10000>; 1201 reg-names = "ctl"; 1202 1203 #phy-cells = <0>; 1204 }; 1205 1206 p2u_nvhs_5: phy@3f00000 { 1207 compatible = "nvidia,tegra194-p2u"; 1208 reg = <0x03f00000 0x10000>; 1209 reg-names = "ctl"; 1210 1211 #phy-cells = <0>; 1212 }; 1213 1214 p2u_nvhs_6: phy@3f10000 { 1215 compatible = "nvidia,tegra194-p2u"; 1216 reg = <0x03f10000 0x10000>; 1217 reg-names = "ctl"; 1218 1219 #phy-cells = <0>; 1220 }; 1221 1222 p2u_nvhs_7: phy@3f20000 { 1223 compatible = "nvidia,tegra194-p2u"; 1224 reg = <0x03f20000 0x10000>; 1225 reg-names = "ctl"; 1226 1227 #phy-cells = <0>; 1228 }; 1229 1230 p2u_hsio_10: phy@3f30000 { 1231 compatible = "nvidia,tegra194-p2u"; 1232 reg = <0x03f30000 0x10000>; 1233 reg-names = "ctl"; 1234 1235 #phy-cells = <0>; 1236 }; 1237 1238 p2u_hsio_11: phy@3f40000 { 1239 compatible = "nvidia,tegra194-p2u"; 1240 reg = <0x03f40000 0x10000>; 1241 reg-names = "ctl"; 1242 1243 #phy-cells = <0>; 1244 }; 1245 1246 hsp_aon: hsp@c150000 { 1247 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1248 reg = <0x0c150000 0x90000>; 1249 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1253 /* 1254 * Shared interrupt 0 is routed only to AON/SPE, so 1255 * we only have 4 shared interrupts for the CCPLEX. 1256 */ 1257 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1258 #mbox-cells = <2>; 1259 }; 1260 1261 gen2_i2c: i2c@c240000 { 1262 compatible = "nvidia,tegra194-i2c"; 1263 reg = <0x0c240000 0x10000>; 1264 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1268 clock-names = "div-clk"; 1269 resets = <&bpmp TEGRA194_RESET_I2C2>; 1270 reset-names = "i2c"; 1271 status = "disabled"; 1272 }; 1273 1274 gen8_i2c: i2c@c250000 { 1275 compatible = "nvidia,tegra194-i2c"; 1276 reg = <0x0c250000 0x10000>; 1277 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1281 clock-names = "div-clk"; 1282 resets = <&bpmp TEGRA194_RESET_I2C8>; 1283 reset-names = "i2c"; 1284 status = "disabled"; 1285 }; 1286 1287 uartc: serial@c280000 { 1288 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1289 reg = <0x0c280000 0x40>; 1290 reg-shift = <2>; 1291 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1292 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1293 clock-names = "serial"; 1294 resets = <&bpmp TEGRA194_RESET_UARTC>; 1295 reset-names = "serial"; 1296 status = "disabled"; 1297 }; 1298 1299 uartg: serial@c290000 { 1300 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1301 reg = <0x0c290000 0x40>; 1302 reg-shift = <2>; 1303 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1304 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1305 clock-names = "serial"; 1306 resets = <&bpmp TEGRA194_RESET_UARTG>; 1307 reset-names = "serial"; 1308 status = "disabled"; 1309 }; 1310 1311 rtc: rtc@c2a0000 { 1312 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1313 reg = <0x0c2a0000 0x10000>; 1314 interrupt-parent = <&pmc>; 1315 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1316 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1317 clock-names = "rtc"; 1318 status = "disabled"; 1319 }; 1320 1321 gpio_aon: gpio@c2f0000 { 1322 compatible = "nvidia,tegra194-gpio-aon"; 1323 reg-names = "security", "gpio"; 1324 reg = <0xc2f0000 0x1000>, 1325 <0xc2f1000 0x1000>; 1326 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1327 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1330 gpio-controller; 1331 #gpio-cells = <2>; 1332 interrupt-controller; 1333 #interrupt-cells = <2>; 1334 }; 1335 1336 pwm4: pwm@c340000 { 1337 compatible = "nvidia,tegra194-pwm", 1338 "nvidia,tegra186-pwm"; 1339 reg = <0xc340000 0x10000>; 1340 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1341 clock-names = "pwm"; 1342 resets = <&bpmp TEGRA194_RESET_PWM4>; 1343 reset-names = "pwm"; 1344 status = "disabled"; 1345 #pwm-cells = <2>; 1346 }; 1347 1348 pmc: pmc@c360000 { 1349 compatible = "nvidia,tegra194-pmc"; 1350 reg = <0x0c360000 0x10000>, 1351 <0x0c370000 0x10000>, 1352 <0x0c380000 0x10000>, 1353 <0x0c390000 0x10000>, 1354 <0x0c3a0000 0x10000>; 1355 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1356 1357 #interrupt-cells = <2>; 1358 interrupt-controller; 1359 }; 1360 1361 smmu: iommu@12000000 { 1362 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1363 reg = <0x12000000 0x800000>, 1364 <0x11000000 0x800000>; 1365 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1415 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1416 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1431 stream-match-mask = <0x7f80>; 1432 #global-interrupts = <2>; 1433 #iommu-cells = <1>; 1434 1435 nvidia,memory-controller = <&mc>; 1436 status = "okay"; 1437 }; 1438 1439 host1x@13e00000 { 1440 compatible = "nvidia,tegra194-host1x"; 1441 reg = <0x13e00000 0x10000>, 1442 <0x13e10000 0x10000>; 1443 reg-names = "hypervisor", "vm"; 1444 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1446 interrupt-names = "syncpt", "host1x"; 1447 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1448 clock-names = "host1x"; 1449 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1450 reset-names = "host1x"; 1451 1452 #address-cells = <1>; 1453 #size-cells = <1>; 1454 1455 ranges = <0x15000000 0x15000000 0x01000000>; 1456 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1457 interconnect-names = "dma-mem"; 1458 iommus = <&smmu TEGRA194_SID_HOST1X>; 1459 1460 nvdec@15140000 { 1461 compatible = "nvidia,tegra194-nvdec"; 1462 reg = <0x15140000 0x00040000>; 1463 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1464 clock-names = "nvdec"; 1465 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1466 reset-names = "nvdec"; 1467 1468 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1469 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1470 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1471 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1472 interconnect-names = "dma-mem", "read-1", "write"; 1473 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1474 dma-coherent; 1475 1476 nvidia,host1x-class = <0xf5>; 1477 }; 1478 1479 display-hub@15200000 { 1480 compatible = "nvidia,tegra194-display"; 1481 reg = <0x15200000 0x00040000>; 1482 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1483 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1484 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1485 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1486 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1487 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1488 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1489 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1490 "wgrp3", "wgrp4", "wgrp5"; 1491 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1492 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1493 clock-names = "disp", "hub"; 1494 status = "disabled"; 1495 1496 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1497 1498 #address-cells = <1>; 1499 #size-cells = <1>; 1500 1501 ranges = <0x15200000 0x15200000 0x40000>; 1502 1503 display@15200000 { 1504 compatible = "nvidia,tegra194-dc"; 1505 reg = <0x15200000 0x10000>; 1506 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1507 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1508 clock-names = "dc"; 1509 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1510 reset-names = "dc"; 1511 1512 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1513 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1514 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1515 interconnect-names = "dma-mem", "read-1"; 1516 1517 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1518 nvidia,head = <0>; 1519 }; 1520 1521 display@15210000 { 1522 compatible = "nvidia,tegra194-dc"; 1523 reg = <0x15210000 0x10000>; 1524 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1525 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1526 clock-names = "dc"; 1527 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1528 reset-names = "dc"; 1529 1530 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1531 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1532 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1533 interconnect-names = "dma-mem", "read-1"; 1534 1535 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1536 nvidia,head = <1>; 1537 }; 1538 1539 display@15220000 { 1540 compatible = "nvidia,tegra194-dc"; 1541 reg = <0x15220000 0x10000>; 1542 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1543 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1544 clock-names = "dc"; 1545 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1546 reset-names = "dc"; 1547 1548 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1549 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1550 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1551 interconnect-names = "dma-mem", "read-1"; 1552 1553 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1554 nvidia,head = <2>; 1555 }; 1556 1557 display@15230000 { 1558 compatible = "nvidia,tegra194-dc"; 1559 reg = <0x15230000 0x10000>; 1560 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1561 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1562 clock-names = "dc"; 1563 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1564 reset-names = "dc"; 1565 1566 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1567 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1568 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1569 interconnect-names = "dma-mem", "read-1"; 1570 1571 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1572 nvidia,head = <3>; 1573 }; 1574 }; 1575 1576 vic@15340000 { 1577 compatible = "nvidia,tegra194-vic"; 1578 reg = <0x15340000 0x00040000>; 1579 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1580 clocks = <&bpmp TEGRA194_CLK_VIC>; 1581 clock-names = "vic"; 1582 resets = <&bpmp TEGRA194_RESET_VIC>; 1583 reset-names = "vic"; 1584 1585 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1586 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1587 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1588 interconnect-names = "dma-mem", "write"; 1589 iommus = <&smmu TEGRA194_SID_VIC>; 1590 }; 1591 1592 nvdec@15480000 { 1593 compatible = "nvidia,tegra194-nvdec"; 1594 reg = <0x15480000 0x00040000>; 1595 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 1596 clock-names = "nvdec"; 1597 resets = <&bpmp TEGRA194_RESET_NVDEC>; 1598 reset-names = "nvdec"; 1599 1600 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 1601 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 1602 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 1603 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 1604 interconnect-names = "dma-mem", "read-1", "write"; 1605 iommus = <&smmu TEGRA194_SID_NVDEC>; 1606 dma-coherent; 1607 1608 nvidia,host1x-class = <0xf0>; 1609 }; 1610 1611 dpaux0: dpaux@155c0000 { 1612 compatible = "nvidia,tegra194-dpaux"; 1613 reg = <0x155c0000 0x10000>; 1614 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1615 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1616 <&bpmp TEGRA194_CLK_PLLDP>; 1617 clock-names = "dpaux", "parent"; 1618 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1619 reset-names = "dpaux"; 1620 status = "disabled"; 1621 1622 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1623 1624 state_dpaux0_aux: pinmux-aux { 1625 groups = "dpaux-io"; 1626 function = "aux"; 1627 }; 1628 1629 state_dpaux0_i2c: pinmux-i2c { 1630 groups = "dpaux-io"; 1631 function = "i2c"; 1632 }; 1633 1634 state_dpaux0_off: pinmux-off { 1635 groups = "dpaux-io"; 1636 function = "off"; 1637 }; 1638 1639 i2c-bus { 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 }; 1643 }; 1644 1645 dpaux1: dpaux@155d0000 { 1646 compatible = "nvidia,tegra194-dpaux"; 1647 reg = <0x155d0000 0x10000>; 1648 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1649 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1650 <&bpmp TEGRA194_CLK_PLLDP>; 1651 clock-names = "dpaux", "parent"; 1652 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1653 reset-names = "dpaux"; 1654 status = "disabled"; 1655 1656 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1657 1658 state_dpaux1_aux: pinmux-aux { 1659 groups = "dpaux-io"; 1660 function = "aux"; 1661 }; 1662 1663 state_dpaux1_i2c: pinmux-i2c { 1664 groups = "dpaux-io"; 1665 function = "i2c"; 1666 }; 1667 1668 state_dpaux1_off: pinmux-off { 1669 groups = "dpaux-io"; 1670 function = "off"; 1671 }; 1672 1673 i2c-bus { 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 }; 1677 }; 1678 1679 dpaux2: dpaux@155e0000 { 1680 compatible = "nvidia,tegra194-dpaux"; 1681 reg = <0x155e0000 0x10000>; 1682 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1683 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1684 <&bpmp TEGRA194_CLK_PLLDP>; 1685 clock-names = "dpaux", "parent"; 1686 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1687 reset-names = "dpaux"; 1688 status = "disabled"; 1689 1690 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1691 1692 state_dpaux2_aux: pinmux-aux { 1693 groups = "dpaux-io"; 1694 function = "aux"; 1695 }; 1696 1697 state_dpaux2_i2c: pinmux-i2c { 1698 groups = "dpaux-io"; 1699 function = "i2c"; 1700 }; 1701 1702 state_dpaux2_off: pinmux-off { 1703 groups = "dpaux-io"; 1704 function = "off"; 1705 }; 1706 1707 i2c-bus { 1708 #address-cells = <1>; 1709 #size-cells = <0>; 1710 }; 1711 }; 1712 1713 dpaux3: dpaux@155f0000 { 1714 compatible = "nvidia,tegra194-dpaux"; 1715 reg = <0x155f0000 0x10000>; 1716 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1717 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1718 <&bpmp TEGRA194_CLK_PLLDP>; 1719 clock-names = "dpaux", "parent"; 1720 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1721 reset-names = "dpaux"; 1722 status = "disabled"; 1723 1724 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1725 1726 state_dpaux3_aux: pinmux-aux { 1727 groups = "dpaux-io"; 1728 function = "aux"; 1729 }; 1730 1731 state_dpaux3_i2c: pinmux-i2c { 1732 groups = "dpaux-io"; 1733 function = "i2c"; 1734 }; 1735 1736 state_dpaux3_off: pinmux-off { 1737 groups = "dpaux-io"; 1738 function = "off"; 1739 }; 1740 1741 i2c-bus { 1742 #address-cells = <1>; 1743 #size-cells = <0>; 1744 }; 1745 }; 1746 1747 sor0: sor@15b00000 { 1748 compatible = "nvidia,tegra194-sor"; 1749 reg = <0x15b00000 0x40000>; 1750 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1751 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1752 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1753 <&bpmp TEGRA194_CLK_PLLD>, 1754 <&bpmp TEGRA194_CLK_PLLDP>, 1755 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1756 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1757 clock-names = "sor", "out", "parent", "dp", "safe", 1758 "pad"; 1759 resets = <&bpmp TEGRA194_RESET_SOR0>; 1760 reset-names = "sor"; 1761 pinctrl-0 = <&state_dpaux0_aux>; 1762 pinctrl-1 = <&state_dpaux0_i2c>; 1763 pinctrl-2 = <&state_dpaux0_off>; 1764 pinctrl-names = "aux", "i2c", "off"; 1765 status = "disabled"; 1766 1767 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1768 nvidia,interface = <0>; 1769 }; 1770 1771 sor1: sor@15b40000 { 1772 compatible = "nvidia,tegra194-sor"; 1773 reg = <0x15b40000 0x40000>; 1774 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1775 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1776 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1777 <&bpmp TEGRA194_CLK_PLLD2>, 1778 <&bpmp TEGRA194_CLK_PLLDP>, 1779 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1780 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1781 clock-names = "sor", "out", "parent", "dp", "safe", 1782 "pad"; 1783 resets = <&bpmp TEGRA194_RESET_SOR1>; 1784 reset-names = "sor"; 1785 pinctrl-0 = <&state_dpaux1_aux>; 1786 pinctrl-1 = <&state_dpaux1_i2c>; 1787 pinctrl-2 = <&state_dpaux1_off>; 1788 pinctrl-names = "aux", "i2c", "off"; 1789 status = "disabled"; 1790 1791 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1792 nvidia,interface = <1>; 1793 }; 1794 1795 sor2: sor@15b80000 { 1796 compatible = "nvidia,tegra194-sor"; 1797 reg = <0x15b80000 0x40000>; 1798 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1799 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1800 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1801 <&bpmp TEGRA194_CLK_PLLD3>, 1802 <&bpmp TEGRA194_CLK_PLLDP>, 1803 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1804 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1805 clock-names = "sor", "out", "parent", "dp", "safe", 1806 "pad"; 1807 resets = <&bpmp TEGRA194_RESET_SOR2>; 1808 reset-names = "sor"; 1809 pinctrl-0 = <&state_dpaux2_aux>; 1810 pinctrl-1 = <&state_dpaux2_i2c>; 1811 pinctrl-2 = <&state_dpaux2_off>; 1812 pinctrl-names = "aux", "i2c", "off"; 1813 status = "disabled"; 1814 1815 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1816 nvidia,interface = <2>; 1817 }; 1818 1819 sor3: sor@15bc0000 { 1820 compatible = "nvidia,tegra194-sor"; 1821 reg = <0x15bc0000 0x40000>; 1822 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1823 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1824 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1825 <&bpmp TEGRA194_CLK_PLLD4>, 1826 <&bpmp TEGRA194_CLK_PLLDP>, 1827 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1828 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1829 clock-names = "sor", "out", "parent", "dp", "safe", 1830 "pad"; 1831 resets = <&bpmp TEGRA194_RESET_SOR3>; 1832 reset-names = "sor"; 1833 pinctrl-0 = <&state_dpaux3_aux>; 1834 pinctrl-1 = <&state_dpaux3_i2c>; 1835 pinctrl-2 = <&state_dpaux3_off>; 1836 pinctrl-names = "aux", "i2c", "off"; 1837 status = "disabled"; 1838 1839 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1840 nvidia,interface = <3>; 1841 }; 1842 }; 1843 1844 gpu@17000000 { 1845 compatible = "nvidia,gv11b"; 1846 reg = <0x17000000 0x1000000>, 1847 <0x18000000 0x1000000>; 1848 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1850 interrupt-names = "stall", "nonstall"; 1851 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 1852 <&bpmp TEGRA194_CLK_GPU_PWR>, 1853 <&bpmp TEGRA194_CLK_FUSE>; 1854 clock-names = "gpu", "pwr", "fuse"; 1855 resets = <&bpmp TEGRA194_RESET_GPU>; 1856 reset-names = "gpu"; 1857 dma-coherent; 1858 1859 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 1860 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 1861 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 1862 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 1863 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 1864 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 1865 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 1866 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 1867 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 1868 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 1869 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 1870 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 1871 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 1872 interconnect-names = "dma-mem", "read-0-hp", "write-0", 1873 "read-1", "read-1-hp", "write-1", 1874 "read-2", "read-2-hp", "write-2", 1875 "read-3", "read-3-hp", "write-3"; 1876 }; 1877 }; 1878 1879 pcie@14100000 { 1880 compatible = "nvidia,tegra194-pcie"; 1881 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1882 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1883 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1884 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1885 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1886 reg-names = "appl", "config", "atu_dma", "dbi"; 1887 1888 status = "disabled"; 1889 1890 #address-cells = <3>; 1891 #size-cells = <2>; 1892 device_type = "pci"; 1893 num-lanes = <1>; 1894 num-viewport = <8>; 1895 linux,pci-domain = <1>; 1896 1897 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 1898 clock-names = "core"; 1899 1900 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 1901 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 1902 reset-names = "apb", "core"; 1903 1904 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1905 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1906 interrupt-names = "intr", "msi"; 1907 1908 #interrupt-cells = <1>; 1909 interrupt-map-mask = <0 0 0 0>; 1910 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1911 1912 nvidia,bpmp = <&bpmp 1>; 1913 1914 nvidia,aspm-cmrt-us = <60>; 1915 nvidia,aspm-pwr-on-t-us = <20>; 1916 nvidia,aspm-l0s-entrance-latency-us = <3>; 1917 1918 bus-range = <0x0 0xff>; 1919 1920 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1921 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 1922 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1923 1924 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1925 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1926 interconnect-names = "dma-mem", "write"; 1927 iommus = <&smmu TEGRA194_SID_PCIE1>; 1928 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 1929 iommu-map-mask = <0x0>; 1930 dma-coherent; 1931 }; 1932 1933 pcie@14120000 { 1934 compatible = "nvidia,tegra194-pcie"; 1935 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1936 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1937 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1938 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1939 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1940 reg-names = "appl", "config", "atu_dma", "dbi"; 1941 1942 status = "disabled"; 1943 1944 #address-cells = <3>; 1945 #size-cells = <2>; 1946 device_type = "pci"; 1947 num-lanes = <1>; 1948 num-viewport = <8>; 1949 linux,pci-domain = <2>; 1950 1951 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 1952 clock-names = "core"; 1953 1954 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 1955 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 1956 reset-names = "apb", "core"; 1957 1958 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1959 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1960 interrupt-names = "intr", "msi"; 1961 1962 #interrupt-cells = <1>; 1963 interrupt-map-mask = <0 0 0 0>; 1964 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1965 1966 nvidia,bpmp = <&bpmp 2>; 1967 1968 nvidia,aspm-cmrt-us = <60>; 1969 nvidia,aspm-pwr-on-t-us = <20>; 1970 nvidia,aspm-l0s-entrance-latency-us = <3>; 1971 1972 bus-range = <0x0 0xff>; 1973 1974 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1975 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 1976 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1977 1978 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1979 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1980 interconnect-names = "dma-mem", "write"; 1981 iommus = <&smmu TEGRA194_SID_PCIE2>; 1982 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 1983 iommu-map-mask = <0x0>; 1984 dma-coherent; 1985 }; 1986 1987 pcie@14140000 { 1988 compatible = "nvidia,tegra194-pcie"; 1989 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1990 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1991 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1992 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1993 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1994 reg-names = "appl", "config", "atu_dma", "dbi"; 1995 1996 status = "disabled"; 1997 1998 #address-cells = <3>; 1999 #size-cells = <2>; 2000 device_type = "pci"; 2001 num-lanes = <1>; 2002 num-viewport = <8>; 2003 linux,pci-domain = <3>; 2004 2005 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2006 clock-names = "core"; 2007 2008 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2009 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2010 reset-names = "apb", "core"; 2011 2012 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2013 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2014 interrupt-names = "intr", "msi"; 2015 2016 #interrupt-cells = <1>; 2017 interrupt-map-mask = <0 0 0 0>; 2018 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2019 2020 nvidia,bpmp = <&bpmp 3>; 2021 2022 nvidia,aspm-cmrt-us = <60>; 2023 nvidia,aspm-pwr-on-t-us = <20>; 2024 nvidia,aspm-l0s-entrance-latency-us = <3>; 2025 2026 bus-range = <0x0 0xff>; 2027 2028 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2029 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2030 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2031 2032 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2033 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2034 interconnect-names = "dma-mem", "write"; 2035 iommus = <&smmu TEGRA194_SID_PCIE3>; 2036 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2037 iommu-map-mask = <0x0>; 2038 dma-coherent; 2039 }; 2040 2041 pcie@14160000 { 2042 compatible = "nvidia,tegra194-pcie"; 2043 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2044 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2045 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2046 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2047 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2048 reg-names = "appl", "config", "atu_dma", "dbi"; 2049 2050 status = "disabled"; 2051 2052 #address-cells = <3>; 2053 #size-cells = <2>; 2054 device_type = "pci"; 2055 num-lanes = <4>; 2056 num-viewport = <8>; 2057 linux,pci-domain = <4>; 2058 2059 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2060 clock-names = "core"; 2061 2062 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2063 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2064 reset-names = "apb", "core"; 2065 2066 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2067 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2068 interrupt-names = "intr", "msi"; 2069 2070 #interrupt-cells = <1>; 2071 interrupt-map-mask = <0 0 0 0>; 2072 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2073 2074 nvidia,bpmp = <&bpmp 4>; 2075 2076 nvidia,aspm-cmrt-us = <60>; 2077 nvidia,aspm-pwr-on-t-us = <20>; 2078 nvidia,aspm-l0s-entrance-latency-us = <3>; 2079 2080 bus-range = <0x0 0xff>; 2081 2082 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2083 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2084 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2085 2086 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2087 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2088 interconnect-names = "dma-mem", "write"; 2089 iommus = <&smmu TEGRA194_SID_PCIE4>; 2090 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2091 iommu-map-mask = <0x0>; 2092 dma-coherent; 2093 }; 2094 2095 pcie@14180000 { 2096 compatible = "nvidia,tegra194-pcie"; 2097 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2098 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2099 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2100 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2101 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2102 reg-names = "appl", "config", "atu_dma", "dbi"; 2103 2104 status = "disabled"; 2105 2106 #address-cells = <3>; 2107 #size-cells = <2>; 2108 device_type = "pci"; 2109 num-lanes = <8>; 2110 num-viewport = <8>; 2111 linux,pci-domain = <0>; 2112 2113 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2114 clock-names = "core"; 2115 2116 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2117 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2118 reset-names = "apb", "core"; 2119 2120 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2121 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2122 interrupt-names = "intr", "msi"; 2123 2124 #interrupt-cells = <1>; 2125 interrupt-map-mask = <0 0 0 0>; 2126 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2127 2128 nvidia,bpmp = <&bpmp 0>; 2129 2130 nvidia,aspm-cmrt-us = <60>; 2131 nvidia,aspm-pwr-on-t-us = <20>; 2132 nvidia,aspm-l0s-entrance-latency-us = <3>; 2133 2134 bus-range = <0x0 0xff>; 2135 2136 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2137 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2138 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2139 2140 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2141 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2142 interconnect-names = "dma-mem", "write"; 2143 iommus = <&smmu TEGRA194_SID_PCIE0>; 2144 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2145 iommu-map-mask = <0x0>; 2146 dma-coherent; 2147 }; 2148 2149 pcie@141a0000 { 2150 compatible = "nvidia,tegra194-pcie"; 2151 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2152 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2153 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2154 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2155 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2156 reg-names = "appl", "config", "atu_dma", "dbi"; 2157 2158 status = "disabled"; 2159 2160 #address-cells = <3>; 2161 #size-cells = <2>; 2162 device_type = "pci"; 2163 num-lanes = <8>; 2164 num-viewport = <8>; 2165 linux,pci-domain = <5>; 2166 2167 pinctrl-names = "default"; 2168 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2169 2170 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 2171 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 2172 clock-names = "core", "core_m"; 2173 2174 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2175 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2176 reset-names = "apb", "core"; 2177 2178 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2179 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2180 interrupt-names = "intr", "msi"; 2181 2182 nvidia,bpmp = <&bpmp 5>; 2183 2184 #interrupt-cells = <1>; 2185 interrupt-map-mask = <0 0 0 0>; 2186 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2187 2188 nvidia,aspm-cmrt-us = <60>; 2189 nvidia,aspm-pwr-on-t-us = <20>; 2190 nvidia,aspm-l0s-entrance-latency-us = <3>; 2191 2192 bus-range = <0x0 0xff>; 2193 2194 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2195 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2196 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2197 2198 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2199 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2200 interconnect-names = "dma-mem", "write"; 2201 iommus = <&smmu TEGRA194_SID_PCIE5>; 2202 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2203 iommu-map-mask = <0x0>; 2204 dma-coherent; 2205 }; 2206 2207 pcie_ep@14160000 { 2208 compatible = "nvidia,tegra194-pcie-ep"; 2209 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2210 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2211 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2212 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2213 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2214 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2215 2216 status = "disabled"; 2217 2218 num-lanes = <4>; 2219 num-ib-windows = <2>; 2220 num-ob-windows = <8>; 2221 2222 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2223 clock-names = "core"; 2224 2225 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2226 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2227 reset-names = "apb", "core"; 2228 2229 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2230 interrupt-names = "intr"; 2231 2232 nvidia,bpmp = <&bpmp 4>; 2233 2234 nvidia,aspm-cmrt-us = <60>; 2235 nvidia,aspm-pwr-on-t-us = <20>; 2236 nvidia,aspm-l0s-entrance-latency-us = <3>; 2237 2238 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2239 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2240 interconnect-names = "dma-mem", "write"; 2241 iommus = <&smmu TEGRA194_SID_PCIE4>; 2242 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2243 iommu-map-mask = <0x0>; 2244 dma-coherent; 2245 }; 2246 2247 pcie_ep@14180000 { 2248 compatible = "nvidia,tegra194-pcie-ep"; 2249 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2250 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2251 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2252 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2253 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2254 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2255 2256 status = "disabled"; 2257 2258 num-lanes = <8>; 2259 num-ib-windows = <2>; 2260 num-ob-windows = <8>; 2261 2262 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2263 clock-names = "core"; 2264 2265 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2266 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2267 reset-names = "apb", "core"; 2268 2269 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2270 interrupt-names = "intr"; 2271 2272 nvidia,bpmp = <&bpmp 0>; 2273 2274 nvidia,aspm-cmrt-us = <60>; 2275 nvidia,aspm-pwr-on-t-us = <20>; 2276 nvidia,aspm-l0s-entrance-latency-us = <3>; 2277 2278 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2279 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2280 interconnect-names = "dma-mem", "write"; 2281 iommus = <&smmu TEGRA194_SID_PCIE0>; 2282 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2283 iommu-map-mask = <0x0>; 2284 dma-coherent; 2285 }; 2286 2287 pcie_ep@141a0000 { 2288 compatible = "nvidia,tegra194-pcie-ep"; 2289 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2290 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2291 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2292 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2293 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2294 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2295 2296 status = "disabled"; 2297 2298 num-lanes = <8>; 2299 num-ib-windows = <2>; 2300 num-ob-windows = <8>; 2301 2302 pinctrl-names = "default"; 2303 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2304 2305 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2306 clock-names = "core"; 2307 2308 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2309 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2310 reset-names = "apb", "core"; 2311 2312 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2313 interrupt-names = "intr"; 2314 2315 nvidia,bpmp = <&bpmp 5>; 2316 2317 nvidia,aspm-cmrt-us = <60>; 2318 nvidia,aspm-pwr-on-t-us = <20>; 2319 nvidia,aspm-l0s-entrance-latency-us = <3>; 2320 2321 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2322 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2323 interconnect-names = "dma-mem", "write"; 2324 iommus = <&smmu TEGRA194_SID_PCIE5>; 2325 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2326 iommu-map-mask = <0x0>; 2327 dma-coherent; 2328 }; 2329 2330 sram@40000000 { 2331 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2332 reg = <0x0 0x40000000 0x0 0x50000>; 2333 #address-cells = <1>; 2334 #size-cells = <1>; 2335 ranges = <0x0 0x0 0x40000000 0x50000>; 2336 2337 cpu_bpmp_tx: sram@4e000 { 2338 reg = <0x4e000 0x1000>; 2339 label = "cpu-bpmp-tx"; 2340 pool; 2341 }; 2342 2343 cpu_bpmp_rx: sram@4f000 { 2344 reg = <0x4f000 0x1000>; 2345 label = "cpu-bpmp-rx"; 2346 pool; 2347 }; 2348 }; 2349 2350 bpmp: bpmp { 2351 compatible = "nvidia,tegra186-bpmp"; 2352 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2353 TEGRA_HSP_DB_MASTER_BPMP>; 2354 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 2355 #clock-cells = <1>; 2356 #reset-cells = <1>; 2357 #power-domain-cells = <1>; 2358 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2359 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2360 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2361 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2362 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2363 iommus = <&smmu TEGRA194_SID_BPMP>; 2364 2365 bpmp_i2c: i2c { 2366 compatible = "nvidia,tegra186-bpmp-i2c"; 2367 nvidia,bpmp-bus-id = <5>; 2368 #address-cells = <1>; 2369 #size-cells = <0>; 2370 }; 2371 2372 bpmp_thermal: thermal { 2373 compatible = "nvidia,tegra186-bpmp-thermal"; 2374 #thermal-sensor-cells = <1>; 2375 }; 2376 }; 2377 2378 cpus { 2379 compatible = "nvidia,tegra194-ccplex"; 2380 nvidia,bpmp = <&bpmp>; 2381 #address-cells = <1>; 2382 #size-cells = <0>; 2383 2384 cpu0_0: cpu@0 { 2385 compatible = "nvidia,tegra194-carmel"; 2386 device_type = "cpu"; 2387 reg = <0x000>; 2388 enable-method = "psci"; 2389 i-cache-size = <131072>; 2390 i-cache-line-size = <64>; 2391 i-cache-sets = <512>; 2392 d-cache-size = <65536>; 2393 d-cache-line-size = <64>; 2394 d-cache-sets = <256>; 2395 next-level-cache = <&l2c_0>; 2396 }; 2397 2398 cpu0_1: cpu@1 { 2399 compatible = "nvidia,tegra194-carmel"; 2400 device_type = "cpu"; 2401 reg = <0x001>; 2402 enable-method = "psci"; 2403 i-cache-size = <131072>; 2404 i-cache-line-size = <64>; 2405 i-cache-sets = <512>; 2406 d-cache-size = <65536>; 2407 d-cache-line-size = <64>; 2408 d-cache-sets = <256>; 2409 next-level-cache = <&l2c_0>; 2410 }; 2411 2412 cpu1_0: cpu@100 { 2413 compatible = "nvidia,tegra194-carmel"; 2414 device_type = "cpu"; 2415 reg = <0x100>; 2416 enable-method = "psci"; 2417 i-cache-size = <131072>; 2418 i-cache-line-size = <64>; 2419 i-cache-sets = <512>; 2420 d-cache-size = <65536>; 2421 d-cache-line-size = <64>; 2422 d-cache-sets = <256>; 2423 next-level-cache = <&l2c_1>; 2424 }; 2425 2426 cpu1_1: cpu@101 { 2427 compatible = "nvidia,tegra194-carmel"; 2428 device_type = "cpu"; 2429 reg = <0x101>; 2430 enable-method = "psci"; 2431 i-cache-size = <131072>; 2432 i-cache-line-size = <64>; 2433 i-cache-sets = <512>; 2434 d-cache-size = <65536>; 2435 d-cache-line-size = <64>; 2436 d-cache-sets = <256>; 2437 next-level-cache = <&l2c_1>; 2438 }; 2439 2440 cpu2_0: cpu@200 { 2441 compatible = "nvidia,tegra194-carmel"; 2442 device_type = "cpu"; 2443 reg = <0x200>; 2444 enable-method = "psci"; 2445 i-cache-size = <131072>; 2446 i-cache-line-size = <64>; 2447 i-cache-sets = <512>; 2448 d-cache-size = <65536>; 2449 d-cache-line-size = <64>; 2450 d-cache-sets = <256>; 2451 next-level-cache = <&l2c_2>; 2452 }; 2453 2454 cpu2_1: cpu@201 { 2455 compatible = "nvidia,tegra194-carmel"; 2456 device_type = "cpu"; 2457 reg = <0x201>; 2458 enable-method = "psci"; 2459 i-cache-size = <131072>; 2460 i-cache-line-size = <64>; 2461 i-cache-sets = <512>; 2462 d-cache-size = <65536>; 2463 d-cache-line-size = <64>; 2464 d-cache-sets = <256>; 2465 next-level-cache = <&l2c_2>; 2466 }; 2467 2468 cpu3_0: cpu@300 { 2469 compatible = "nvidia,tegra194-carmel"; 2470 device_type = "cpu"; 2471 reg = <0x300>; 2472 enable-method = "psci"; 2473 i-cache-size = <131072>; 2474 i-cache-line-size = <64>; 2475 i-cache-sets = <512>; 2476 d-cache-size = <65536>; 2477 d-cache-line-size = <64>; 2478 d-cache-sets = <256>; 2479 next-level-cache = <&l2c_3>; 2480 }; 2481 2482 cpu3_1: cpu@301 { 2483 compatible = "nvidia,tegra194-carmel"; 2484 device_type = "cpu"; 2485 reg = <0x301>; 2486 enable-method = "psci"; 2487 i-cache-size = <131072>; 2488 i-cache-line-size = <64>; 2489 i-cache-sets = <512>; 2490 d-cache-size = <65536>; 2491 d-cache-line-size = <64>; 2492 d-cache-sets = <256>; 2493 next-level-cache = <&l2c_3>; 2494 }; 2495 2496 cpu-map { 2497 cluster0 { 2498 core0 { 2499 cpu = <&cpu0_0>; 2500 }; 2501 2502 core1 { 2503 cpu = <&cpu0_1>; 2504 }; 2505 }; 2506 2507 cluster1 { 2508 core0 { 2509 cpu = <&cpu1_0>; 2510 }; 2511 2512 core1 { 2513 cpu = <&cpu1_1>; 2514 }; 2515 }; 2516 2517 cluster2 { 2518 core0 { 2519 cpu = <&cpu2_0>; 2520 }; 2521 2522 core1 { 2523 cpu = <&cpu2_1>; 2524 }; 2525 }; 2526 2527 cluster3 { 2528 core0 { 2529 cpu = <&cpu3_0>; 2530 }; 2531 2532 core1 { 2533 cpu = <&cpu3_1>; 2534 }; 2535 }; 2536 }; 2537 2538 l2c_0: l2-cache0 { 2539 cache-size = <2097152>; 2540 cache-line-size = <64>; 2541 cache-sets = <2048>; 2542 next-level-cache = <&l3c>; 2543 }; 2544 2545 l2c_1: l2-cache1 { 2546 cache-size = <2097152>; 2547 cache-line-size = <64>; 2548 cache-sets = <2048>; 2549 next-level-cache = <&l3c>; 2550 }; 2551 2552 l2c_2: l2-cache2 { 2553 cache-size = <2097152>; 2554 cache-line-size = <64>; 2555 cache-sets = <2048>; 2556 next-level-cache = <&l3c>; 2557 }; 2558 2559 l2c_3: l2-cache3 { 2560 cache-size = <2097152>; 2561 cache-line-size = <64>; 2562 cache-sets = <2048>; 2563 next-level-cache = <&l3c>; 2564 }; 2565 2566 l3c: l3-cache { 2567 cache-size = <4194304>; 2568 cache-line-size = <64>; 2569 cache-sets = <4096>; 2570 }; 2571 }; 2572 2573 pmu { 2574 compatible = "arm,armv8-pmuv3"; 2575 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2576 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2577 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2578 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 2579 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 2580 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 2581 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 2582 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 2583 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 2584 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 2585 }; 2586 2587 psci { 2588 compatible = "arm,psci-1.0"; 2589 status = "okay"; 2590 method = "smc"; 2591 }; 2592 2593 sound { 2594 status = "disabled"; 2595 2596 clocks = <&bpmp TEGRA194_CLK_PLLA>, 2597 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2598 clock-names = "pll_a", "plla_out0"; 2599 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 2600 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 2601 <&bpmp TEGRA194_CLK_AUD_MCLK>; 2602 assigned-clock-parents = <0>, 2603 <&bpmp TEGRA194_CLK_PLLA>, 2604 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2605 /* 2606 * PLLA supports dynamic ramp. Below initial rate is chosen 2607 * for this to work and oscillate between base rates required 2608 * for 8x and 11.025x sample rate streams. 2609 */ 2610 assigned-clock-rates = <258000000>; 2611 2612 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 2613 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 2614 interconnect-names = "dma-mem", "write"; 2615 iommus = <&smmu TEGRA194_SID_APE>; 2616 }; 2617 2618 tcu: tcu { 2619 compatible = "nvidia,tegra194-tcu"; 2620 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2621 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2622 mbox-names = "rx", "tx"; 2623 }; 2624 2625 thermal-zones { 2626 cpu { 2627 thermal-sensors = <&{/bpmp/thermal} 2628 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2629 status = "disabled"; 2630 }; 2631 2632 gpu { 2633 thermal-sensors = <&{/bpmp/thermal} 2634 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2635 status = "disabled"; 2636 }; 2637 2638 aux { 2639 thermal-sensors = <&{/bpmp/thermal} 2640 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2641 status = "disabled"; 2642 }; 2643 2644 pllx { 2645 thermal-sensors = <&{/bpmp/thermal} 2646 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2647 status = "disabled"; 2648 }; 2649 2650 ao { 2651 thermal-sensors = <&{/bpmp/thermal} 2652 TEGRA194_BPMP_THERMAL_ZONE_AO>; 2653 status = "disabled"; 2654 }; 2655 2656 tj { 2657 thermal-sensors = <&{/bpmp/thermal} 2658 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2659 status = "disabled"; 2660 }; 2661 }; 2662 2663 timer { 2664 compatible = "arm,armv8-timer"; 2665 interrupts = <GIC_PPI 13 2666 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2667 <GIC_PPI 14 2668 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2669 <GIC_PPI 11 2670 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2671 <GIC_PPI 10 2672 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2673 interrupt-parent = <&gic>; 2674 always-on; 2675 }; 2676}; 2677