1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/reset/tegra194-reset.h> 9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10#include <dt-bindings/memory/tegra194-mc.h> 11 12/ { 13 compatible = "nvidia,tegra194"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* control backbone */ 19 bus@0 { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra194-misc"; 27 reg = <0x00100000 0xf000>, 28 <0x0010f000 0x1000>; 29 }; 30 31 gpio: gpio@2200000 { 32 compatible = "nvidia,tegra194-gpio"; 33 reg-names = "security", "gpio"; 34 reg = <0x2200000 0x10000>, 35 <0x2210000 0x10000>; 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42 #interrupt-cells = <2>; 43 interrupt-controller; 44 #gpio-cells = <2>; 45 gpio-controller; 46 }; 47 48 ethernet@2490000 { 49 compatible = "nvidia,tegra194-eqos", 50 "nvidia,tegra186-eqos", 51 "snps,dwc-qos-ethernet-4.10"; 52 reg = <0x02490000 0x10000>; 53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55 <&bpmp TEGRA194_CLK_EQOS_AXI>, 56 <&bpmp TEGRA194_CLK_EQOS_RX>, 57 <&bpmp TEGRA194_CLK_EQOS_TX>, 58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60 resets = <&bpmp TEGRA194_RESET_EQOS>; 61 reset-names = "eqos"; 62 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 63 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 64 interconnect-names = "dma-mem", "write"; 65 status = "disabled"; 66 67 snps,write-requests = <1>; 68 snps,read-requests = <3>; 69 snps,burst-map = <0x7>; 70 snps,txpbl = <16>; 71 snps,rxpbl = <8>; 72 }; 73 74 aconnect@2900000 { 75 compatible = "nvidia,tegra194-aconnect", 76 "nvidia,tegra210-aconnect"; 77 clocks = <&bpmp TEGRA194_CLK_APE>, 78 <&bpmp TEGRA194_CLK_APB2APE>; 79 clock-names = "ape", "apb2ape"; 80 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges = <0x02900000 0x02900000 0x200000>; 84 status = "disabled"; 85 86 adma: dma-controller@2930000 { 87 compatible = "nvidia,tegra194-adma", 88 "nvidia,tegra186-adma"; 89 reg = <0x02930000 0x20000>; 90 interrupt-parent = <&agic>; 91 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 123 #dma-cells = <1>; 124 clocks = <&bpmp TEGRA194_CLK_AHUB>; 125 clock-names = "d_audio"; 126 status = "disabled"; 127 }; 128 129 agic: interrupt-controller@2a40000 { 130 compatible = "nvidia,tegra194-agic", 131 "nvidia,tegra210-agic"; 132 #interrupt-cells = <3>; 133 interrupt-controller; 134 reg = <0x02a41000 0x1000>, 135 <0x02a42000 0x2000>; 136 interrupts = <GIC_SPI 145 137 (GIC_CPU_MASK_SIMPLE(4) | 138 IRQ_TYPE_LEVEL_HIGH)>; 139 clocks = <&bpmp TEGRA194_CLK_APE>; 140 clock-names = "clk"; 141 status = "disabled"; 142 }; 143 144 tegra_ahub: ahub@2900800 { 145 compatible = "nvidia,tegra194-ahub", 146 "nvidia,tegra186-ahub"; 147 reg = <0x02900800 0x800>; 148 clocks = <&bpmp TEGRA194_CLK_AHUB>; 149 clock-names = "ahub"; 150 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 151 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 152 #address-cells = <1>; 153 #size-cells = <1>; 154 ranges = <0x02900800 0x02900800 0x11800>; 155 status = "disabled"; 156 157 tegra_admaif: admaif@290f000 { 158 compatible = "nvidia,tegra194-admaif", 159 "nvidia,tegra186-admaif"; 160 reg = <0x0290f000 0x1000>; 161 dmas = <&adma 1>, <&adma 1>, 162 <&adma 2>, <&adma 2>, 163 <&adma 3>, <&adma 3>, 164 <&adma 4>, <&adma 4>, 165 <&adma 5>, <&adma 5>, 166 <&adma 6>, <&adma 6>, 167 <&adma 7>, <&adma 7>, 168 <&adma 8>, <&adma 8>, 169 <&adma 9>, <&adma 9>, 170 <&adma 10>, <&adma 10>, 171 <&adma 11>, <&adma 11>, 172 <&adma 12>, <&adma 12>, 173 <&adma 13>, <&adma 13>, 174 <&adma 14>, <&adma 14>, 175 <&adma 15>, <&adma 15>, 176 <&adma 16>, <&adma 16>, 177 <&adma 17>, <&adma 17>, 178 <&adma 18>, <&adma 18>, 179 <&adma 19>, <&adma 19>, 180 <&adma 20>, <&adma 20>; 181 dma-names = "rx1", "tx1", 182 "rx2", "tx2", 183 "rx3", "tx3", 184 "rx4", "tx4", 185 "rx5", "tx5", 186 "rx6", "tx6", 187 "rx7", "tx7", 188 "rx8", "tx8", 189 "rx9", "tx9", 190 "rx10", "tx10", 191 "rx11", "tx11", 192 "rx12", "tx12", 193 "rx13", "tx13", 194 "rx14", "tx14", 195 "rx15", "tx15", 196 "rx16", "tx16", 197 "rx17", "tx17", 198 "rx18", "tx18", 199 "rx19", "tx19", 200 "rx20", "tx20"; 201 status = "disabled"; 202 }; 203 204 tegra_i2s1: i2s@2901000 { 205 compatible = "nvidia,tegra194-i2s", 206 "nvidia,tegra210-i2s"; 207 reg = <0x2901000 0x100>; 208 clocks = <&bpmp TEGRA194_CLK_I2S1>, 209 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 210 clock-names = "i2s", "sync_input"; 211 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 212 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 213 assigned-clock-rates = <1536000>; 214 sound-name-prefix = "I2S1"; 215 status = "disabled"; 216 }; 217 218 tegra_i2s2: i2s@2901100 { 219 compatible = "nvidia,tegra194-i2s", 220 "nvidia,tegra210-i2s"; 221 reg = <0x2901100 0x100>; 222 clocks = <&bpmp TEGRA194_CLK_I2S2>, 223 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 224 clock-names = "i2s", "sync_input"; 225 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 226 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 227 assigned-clock-rates = <1536000>; 228 sound-name-prefix = "I2S2"; 229 status = "disabled"; 230 }; 231 232 tegra_i2s3: i2s@2901200 { 233 compatible = "nvidia,tegra194-i2s", 234 "nvidia,tegra210-i2s"; 235 reg = <0x2901200 0x100>; 236 clocks = <&bpmp TEGRA194_CLK_I2S3>, 237 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 238 clock-names = "i2s", "sync_input"; 239 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 240 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 241 assigned-clock-rates = <1536000>; 242 sound-name-prefix = "I2S3"; 243 status = "disabled"; 244 }; 245 246 tegra_i2s4: i2s@2901300 { 247 compatible = "nvidia,tegra194-i2s", 248 "nvidia,tegra210-i2s"; 249 reg = <0x2901300 0x100>; 250 clocks = <&bpmp TEGRA194_CLK_I2S4>, 251 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 252 clock-names = "i2s", "sync_input"; 253 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 254 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 255 assigned-clock-rates = <1536000>; 256 sound-name-prefix = "I2S4"; 257 status = "disabled"; 258 }; 259 260 tegra_i2s5: i2s@2901400 { 261 compatible = "nvidia,tegra194-i2s", 262 "nvidia,tegra210-i2s"; 263 reg = <0x2901400 0x100>; 264 clocks = <&bpmp TEGRA194_CLK_I2S5>, 265 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 266 clock-names = "i2s", "sync_input"; 267 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 268 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 269 assigned-clock-rates = <1536000>; 270 sound-name-prefix = "I2S5"; 271 status = "disabled"; 272 }; 273 274 tegra_i2s6: i2s@2901500 { 275 compatible = "nvidia,tegra194-i2s", 276 "nvidia,tegra210-i2s"; 277 reg = <0x2901500 0x100>; 278 clocks = <&bpmp TEGRA194_CLK_I2S6>, 279 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 280 clock-names = "i2s", "sync_input"; 281 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 282 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 283 assigned-clock-rates = <1536000>; 284 sound-name-prefix = "I2S6"; 285 status = "disabled"; 286 }; 287 288 tegra_dmic1: dmic@2904000 { 289 compatible = "nvidia,tegra194-dmic", 290 "nvidia,tegra210-dmic"; 291 reg = <0x2904000 0x100>; 292 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 293 clock-names = "dmic"; 294 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 295 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 296 assigned-clock-rates = <3072000>; 297 sound-name-prefix = "DMIC1"; 298 status = "disabled"; 299 }; 300 301 tegra_dmic2: dmic@2904100 { 302 compatible = "nvidia,tegra194-dmic", 303 "nvidia,tegra210-dmic"; 304 reg = <0x2904100 0x100>; 305 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 306 clock-names = "dmic"; 307 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 308 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 309 assigned-clock-rates = <3072000>; 310 sound-name-prefix = "DMIC2"; 311 status = "disabled"; 312 }; 313 314 tegra_dmic3: dmic@2904200 { 315 compatible = "nvidia,tegra194-dmic", 316 "nvidia,tegra210-dmic"; 317 reg = <0x2904200 0x100>; 318 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 319 clock-names = "dmic"; 320 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 321 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 322 assigned-clock-rates = <3072000>; 323 sound-name-prefix = "DMIC3"; 324 status = "disabled"; 325 }; 326 327 tegra_dmic4: dmic@2904300 { 328 compatible = "nvidia,tegra194-dmic", 329 "nvidia,tegra210-dmic"; 330 reg = <0x2904300 0x100>; 331 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 332 clock-names = "dmic"; 333 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 334 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 335 assigned-clock-rates = <3072000>; 336 sound-name-prefix = "DMIC4"; 337 status = "disabled"; 338 }; 339 340 tegra_dspk1: dspk@2905000 { 341 compatible = "nvidia,tegra194-dspk", 342 "nvidia,tegra186-dspk"; 343 reg = <0x2905000 0x100>; 344 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 345 clock-names = "dspk"; 346 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 347 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 348 assigned-clock-rates = <12288000>; 349 sound-name-prefix = "DSPK1"; 350 status = "disabled"; 351 }; 352 353 tegra_dspk2: dspk@2905100 { 354 compatible = "nvidia,tegra194-dspk", 355 "nvidia,tegra186-dspk"; 356 reg = <0x2905100 0x100>; 357 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 358 clock-names = "dspk"; 359 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 360 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 361 assigned-clock-rates = <12288000>; 362 sound-name-prefix = "DSPK2"; 363 status = "disabled"; 364 }; 365 }; 366 }; 367 368 pinmux: pinmux@2430000 { 369 compatible = "nvidia,tegra194-pinmux"; 370 reg = <0x2430000 0x17000>, 371 <0xc300000 0x4000>; 372 373 status = "okay"; 374 375 pex_rst_c5_out_state: pex_rst_c5_out { 376 pex_rst { 377 nvidia,pins = "pex_l5_rst_n_pgg1"; 378 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 379 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 380 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 381 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 382 nvidia,tristate = <TEGRA_PIN_DISABLE>; 383 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 384 }; 385 }; 386 387 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 388 clkreq { 389 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 390 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 391 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 392 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 393 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 394 nvidia,tristate = <TEGRA_PIN_DISABLE>; 395 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 396 }; 397 }; 398 }; 399 400 mc: memory-controller@2c00000 { 401 compatible = "nvidia,tegra194-mc"; 402 reg = <0x02c00000 0x100000>, 403 <0x02b80000 0x040000>, 404 <0x01700000 0x100000>; 405 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 406 #interconnect-cells = <1>; 407 status = "disabled"; 408 409 #address-cells = <2>; 410 #size-cells = <2>; 411 412 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 413 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 414 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 415 416 /* 417 * Bit 39 of addresses passing through the memory 418 * controller selects the XBAR format used when memory 419 * is accessed. This is used to transparently access 420 * memory in the XBAR format used by the discrete GPU 421 * (bit 39 set) or Tegra (bit 39 clear). 422 * 423 * As a consequence, the operating system must ensure 424 * that bit 39 is never used implicitly, for example 425 * via an I/O virtual address mapping of an IOMMU. If 426 * devices require access to the XBAR switch, their 427 * drivers must set this bit explicitly. 428 * 429 * Limit the DMA range for memory clients to [38:0]. 430 */ 431 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 432 433 emc: external-memory-controller@2c60000 { 434 compatible = "nvidia,tegra194-emc"; 435 reg = <0x0 0x02c60000 0x0 0x90000>, 436 <0x0 0x01780000 0x0 0x80000>; 437 clocks = <&bpmp TEGRA194_CLK_EMC>; 438 clock-names = "emc"; 439 440 #interconnect-cells = <0>; 441 442 nvidia,bpmp = <&bpmp>; 443 }; 444 }; 445 446 uarta: serial@3100000 { 447 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 448 reg = <0x03100000 0x40>; 449 reg-shift = <2>; 450 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&bpmp TEGRA194_CLK_UARTA>; 452 clock-names = "serial"; 453 resets = <&bpmp TEGRA194_RESET_UARTA>; 454 reset-names = "serial"; 455 status = "disabled"; 456 }; 457 458 uartb: serial@3110000 { 459 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 460 reg = <0x03110000 0x40>; 461 reg-shift = <2>; 462 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&bpmp TEGRA194_CLK_UARTB>; 464 clock-names = "serial"; 465 resets = <&bpmp TEGRA194_RESET_UARTB>; 466 reset-names = "serial"; 467 status = "disabled"; 468 }; 469 470 uartd: serial@3130000 { 471 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 472 reg = <0x03130000 0x40>; 473 reg-shift = <2>; 474 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&bpmp TEGRA194_CLK_UARTD>; 476 clock-names = "serial"; 477 resets = <&bpmp TEGRA194_RESET_UARTD>; 478 reset-names = "serial"; 479 status = "disabled"; 480 }; 481 482 uarte: serial@3140000 { 483 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 484 reg = <0x03140000 0x40>; 485 reg-shift = <2>; 486 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&bpmp TEGRA194_CLK_UARTE>; 488 clock-names = "serial"; 489 resets = <&bpmp TEGRA194_RESET_UARTE>; 490 reset-names = "serial"; 491 status = "disabled"; 492 }; 493 494 uartf: serial@3150000 { 495 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 496 reg = <0x03150000 0x40>; 497 reg-shift = <2>; 498 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&bpmp TEGRA194_CLK_UARTF>; 500 clock-names = "serial"; 501 resets = <&bpmp TEGRA194_RESET_UARTF>; 502 reset-names = "serial"; 503 status = "disabled"; 504 }; 505 506 gen1_i2c: i2c@3160000 { 507 compatible = "nvidia,tegra194-i2c"; 508 reg = <0x03160000 0x10000>; 509 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 clocks = <&bpmp TEGRA194_CLK_I2C1>; 513 clock-names = "div-clk"; 514 resets = <&bpmp TEGRA194_RESET_I2C1>; 515 reset-names = "i2c"; 516 status = "disabled"; 517 }; 518 519 uarth: serial@3170000 { 520 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 521 reg = <0x03170000 0x40>; 522 reg-shift = <2>; 523 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&bpmp TEGRA194_CLK_UARTH>; 525 clock-names = "serial"; 526 resets = <&bpmp TEGRA194_RESET_UARTH>; 527 reset-names = "serial"; 528 status = "disabled"; 529 }; 530 531 cam_i2c: i2c@3180000 { 532 compatible = "nvidia,tegra194-i2c"; 533 reg = <0x03180000 0x10000>; 534 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 clocks = <&bpmp TEGRA194_CLK_I2C3>; 538 clock-names = "div-clk"; 539 resets = <&bpmp TEGRA194_RESET_I2C3>; 540 reset-names = "i2c"; 541 status = "disabled"; 542 }; 543 544 /* shares pads with dpaux1 */ 545 dp_aux_ch1_i2c: i2c@3190000 { 546 compatible = "nvidia,tegra194-i2c"; 547 reg = <0x03190000 0x10000>; 548 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 clocks = <&bpmp TEGRA194_CLK_I2C4>; 552 clock-names = "div-clk"; 553 resets = <&bpmp TEGRA194_RESET_I2C4>; 554 reset-names = "i2c"; 555 pinctrl-0 = <&state_dpaux1_i2c>; 556 pinctrl-1 = <&state_dpaux1_off>; 557 pinctrl-names = "default", "idle"; 558 status = "disabled"; 559 }; 560 561 /* shares pads with dpaux0 */ 562 dp_aux_ch0_i2c: i2c@31b0000 { 563 compatible = "nvidia,tegra194-i2c"; 564 reg = <0x031b0000 0x10000>; 565 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 clocks = <&bpmp TEGRA194_CLK_I2C6>; 569 clock-names = "div-clk"; 570 resets = <&bpmp TEGRA194_RESET_I2C6>; 571 reset-names = "i2c"; 572 pinctrl-0 = <&state_dpaux0_i2c>; 573 pinctrl-1 = <&state_dpaux0_off>; 574 pinctrl-names = "default", "idle"; 575 status = "disabled"; 576 }; 577 578 /* shares pads with dpaux2 */ 579 dp_aux_ch2_i2c: i2c@31c0000 { 580 compatible = "nvidia,tegra194-i2c"; 581 reg = <0x031c0000 0x10000>; 582 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 clocks = <&bpmp TEGRA194_CLK_I2C7>; 586 clock-names = "div-clk"; 587 resets = <&bpmp TEGRA194_RESET_I2C7>; 588 reset-names = "i2c"; 589 pinctrl-0 = <&state_dpaux2_i2c>; 590 pinctrl-1 = <&state_dpaux2_off>; 591 pinctrl-names = "default", "idle"; 592 status = "disabled"; 593 }; 594 595 /* shares pads with dpaux3 */ 596 dp_aux_ch3_i2c: i2c@31e0000 { 597 compatible = "nvidia,tegra194-i2c"; 598 reg = <0x031e0000 0x10000>; 599 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 clocks = <&bpmp TEGRA194_CLK_I2C9>; 603 clock-names = "div-clk"; 604 resets = <&bpmp TEGRA194_RESET_I2C9>; 605 reset-names = "i2c"; 606 pinctrl-0 = <&state_dpaux3_i2c>; 607 pinctrl-1 = <&state_dpaux3_off>; 608 pinctrl-names = "default", "idle"; 609 status = "disabled"; 610 }; 611 612 pwm1: pwm@3280000 { 613 compatible = "nvidia,tegra194-pwm", 614 "nvidia,tegra186-pwm"; 615 reg = <0x3280000 0x10000>; 616 clocks = <&bpmp TEGRA194_CLK_PWM1>; 617 clock-names = "pwm"; 618 resets = <&bpmp TEGRA194_RESET_PWM1>; 619 reset-names = "pwm"; 620 status = "disabled"; 621 #pwm-cells = <2>; 622 }; 623 624 pwm2: pwm@3290000 { 625 compatible = "nvidia,tegra194-pwm", 626 "nvidia,tegra186-pwm"; 627 reg = <0x3290000 0x10000>; 628 clocks = <&bpmp TEGRA194_CLK_PWM2>; 629 clock-names = "pwm"; 630 resets = <&bpmp TEGRA194_RESET_PWM2>; 631 reset-names = "pwm"; 632 status = "disabled"; 633 #pwm-cells = <2>; 634 }; 635 636 pwm3: pwm@32a0000 { 637 compatible = "nvidia,tegra194-pwm", 638 "nvidia,tegra186-pwm"; 639 reg = <0x32a0000 0x10000>; 640 clocks = <&bpmp TEGRA194_CLK_PWM3>; 641 clock-names = "pwm"; 642 resets = <&bpmp TEGRA194_RESET_PWM3>; 643 reset-names = "pwm"; 644 status = "disabled"; 645 #pwm-cells = <2>; 646 }; 647 648 pwm5: pwm@32c0000 { 649 compatible = "nvidia,tegra194-pwm", 650 "nvidia,tegra186-pwm"; 651 reg = <0x32c0000 0x10000>; 652 clocks = <&bpmp TEGRA194_CLK_PWM5>; 653 clock-names = "pwm"; 654 resets = <&bpmp TEGRA194_RESET_PWM5>; 655 reset-names = "pwm"; 656 status = "disabled"; 657 #pwm-cells = <2>; 658 }; 659 660 pwm6: pwm@32d0000 { 661 compatible = "nvidia,tegra194-pwm", 662 "nvidia,tegra186-pwm"; 663 reg = <0x32d0000 0x10000>; 664 clocks = <&bpmp TEGRA194_CLK_PWM6>; 665 clock-names = "pwm"; 666 resets = <&bpmp TEGRA194_RESET_PWM6>; 667 reset-names = "pwm"; 668 status = "disabled"; 669 #pwm-cells = <2>; 670 }; 671 672 pwm7: pwm@32e0000 { 673 compatible = "nvidia,tegra194-pwm", 674 "nvidia,tegra186-pwm"; 675 reg = <0x32e0000 0x10000>; 676 clocks = <&bpmp TEGRA194_CLK_PWM7>; 677 clock-names = "pwm"; 678 resets = <&bpmp TEGRA194_RESET_PWM7>; 679 reset-names = "pwm"; 680 status = "disabled"; 681 #pwm-cells = <2>; 682 }; 683 684 pwm8: pwm@32f0000 { 685 compatible = "nvidia,tegra194-pwm", 686 "nvidia,tegra186-pwm"; 687 reg = <0x32f0000 0x10000>; 688 clocks = <&bpmp TEGRA194_CLK_PWM8>; 689 clock-names = "pwm"; 690 resets = <&bpmp TEGRA194_RESET_PWM8>; 691 reset-names = "pwm"; 692 status = "disabled"; 693 #pwm-cells = <2>; 694 }; 695 696 sdmmc1: mmc@3400000 { 697 compatible = "nvidia,tegra194-sdhci"; 698 reg = <0x03400000 0x10000>; 699 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 701 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 702 clock-names = "sdhci", "tmclk"; 703 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 704 reset-names = "sdhci"; 705 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 706 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 707 interconnect-names = "dma-mem", "write"; 708 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 709 <0x07>; 710 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 711 <0x07>; 712 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 713 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 714 <0x07>; 715 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 716 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 717 nvidia,default-tap = <0x9>; 718 nvidia,default-trim = <0x5>; 719 status = "disabled"; 720 }; 721 722 sdmmc3: mmc@3440000 { 723 compatible = "nvidia,tegra194-sdhci"; 724 reg = <0x03440000 0x10000>; 725 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 727 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 728 clock-names = "sdhci", "tmclk"; 729 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 730 reset-names = "sdhci"; 731 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 732 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 733 interconnect-names = "dma-mem", "write"; 734 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 735 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 736 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 737 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 738 <0x07>; 739 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 740 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 741 <0x07>; 742 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 743 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 744 nvidia,default-tap = <0x9>; 745 nvidia,default-trim = <0x5>; 746 status = "disabled"; 747 }; 748 749 sdmmc4: mmc@3460000 { 750 compatible = "nvidia,tegra194-sdhci"; 751 reg = <0x03460000 0x10000>; 752 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 754 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 755 clock-names = "sdhci", "tmclk"; 756 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 757 <&bpmp TEGRA194_CLK_PLLC4>; 758 assigned-clock-parents = 759 <&bpmp TEGRA194_CLK_PLLC4>; 760 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 761 reset-names = "sdhci"; 762 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 763 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 764 interconnect-names = "dma-mem", "write"; 765 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 766 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 767 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 768 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 769 <0x0a>; 770 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 771 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 772 <0x0a>; 773 nvidia,default-tap = <0x8>; 774 nvidia,default-trim = <0x14>; 775 nvidia,dqs-trim = <40>; 776 supports-cqe; 777 status = "disabled"; 778 }; 779 780 hda@3510000 { 781 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 782 reg = <0x3510000 0x10000>; 783 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 784 clocks = <&bpmp TEGRA194_CLK_HDA>, 785 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 786 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 787 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 788 resets = <&bpmp TEGRA194_RESET_HDA>, 789 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 790 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 791 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 792 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 793 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 794 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 795 interconnect-names = "dma-mem", "write"; 796 status = "disabled"; 797 }; 798 799 xusb_padctl: padctl@3520000 { 800 compatible = "nvidia,tegra194-xusb-padctl"; 801 reg = <0x03520000 0x1000>, 802 <0x03540000 0x1000>; 803 reg-names = "padctl", "ao"; 804 805 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 806 reset-names = "padctl"; 807 808 status = "disabled"; 809 810 pads { 811 usb2 { 812 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 813 clock-names = "trk"; 814 815 lanes { 816 usb2-0 { 817 nvidia,function = "xusb"; 818 status = "disabled"; 819 #phy-cells = <0>; 820 }; 821 822 usb2-1 { 823 nvidia,function = "xusb"; 824 status = "disabled"; 825 #phy-cells = <0>; 826 }; 827 828 usb2-2 { 829 nvidia,function = "xusb"; 830 status = "disabled"; 831 #phy-cells = <0>; 832 }; 833 834 usb2-3 { 835 nvidia,function = "xusb"; 836 status = "disabled"; 837 #phy-cells = <0>; 838 }; 839 }; 840 }; 841 842 usb3 { 843 lanes { 844 usb3-0 { 845 nvidia,function = "xusb"; 846 status = "disabled"; 847 #phy-cells = <0>; 848 }; 849 850 usb3-1 { 851 nvidia,function = "xusb"; 852 status = "disabled"; 853 #phy-cells = <0>; 854 }; 855 856 usb3-2 { 857 nvidia,function = "xusb"; 858 status = "disabled"; 859 #phy-cells = <0>; 860 }; 861 862 usb3-3 { 863 nvidia,function = "xusb"; 864 status = "disabled"; 865 #phy-cells = <0>; 866 }; 867 }; 868 }; 869 }; 870 871 ports { 872 usb2-0 { 873 status = "disabled"; 874 }; 875 876 usb2-1 { 877 status = "disabled"; 878 }; 879 880 usb2-2 { 881 status = "disabled"; 882 }; 883 884 usb2-3 { 885 status = "disabled"; 886 }; 887 888 usb3-0 { 889 status = "disabled"; 890 }; 891 892 usb3-1 { 893 status = "disabled"; 894 }; 895 896 usb3-2 { 897 status = "disabled"; 898 }; 899 900 usb3-3 { 901 status = "disabled"; 902 }; 903 }; 904 }; 905 906 usb@3550000 { 907 compatible = "nvidia,tegra194-xudc"; 908 reg = <0x03550000 0x8000>, 909 <0x03558000 0x1000>; 910 reg-names = "base", "fpci"; 911 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 913 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 914 <&bpmp TEGRA194_CLK_XUSB_SS>, 915 <&bpmp TEGRA194_CLK_XUSB_FS>; 916 clock-names = "dev", "ss", "ss_src", "fs_src"; 917 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 918 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 919 power-domain-names = "dev", "ss"; 920 nvidia,xusb-padctl = <&xusb_padctl>; 921 status = "disabled"; 922 }; 923 924 usb@3610000 { 925 compatible = "nvidia,tegra194-xusb"; 926 reg = <0x03610000 0x40000>, 927 <0x03600000 0x10000>; 928 reg-names = "hcd", "fpci"; 929 930 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 932 933 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 934 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 935 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 936 <&bpmp TEGRA194_CLK_XUSB_SS>, 937 <&bpmp TEGRA194_CLK_CLK_M>, 938 <&bpmp TEGRA194_CLK_XUSB_FS>, 939 <&bpmp TEGRA194_CLK_UTMIPLL>, 940 <&bpmp TEGRA194_CLK_CLK_M>, 941 <&bpmp TEGRA194_CLK_PLLE>; 942 clock-names = "xusb_host", "xusb_falcon_src", 943 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 944 "xusb_fs_src", "pll_u_480m", "clk_m", 945 "pll_e"; 946 947 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 948 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 949 power-domain-names = "xusb_host", "xusb_ss"; 950 951 nvidia,xusb-padctl = <&xusb_padctl>; 952 status = "disabled"; 953 }; 954 955 fuse@3820000 { 956 compatible = "nvidia,tegra194-efuse"; 957 reg = <0x03820000 0x10000>; 958 clocks = <&bpmp TEGRA194_CLK_FUSE>; 959 clock-names = "fuse"; 960 }; 961 962 gic: interrupt-controller@3881000 { 963 compatible = "arm,gic-400"; 964 #interrupt-cells = <3>; 965 interrupt-controller; 966 reg = <0x03881000 0x1000>, 967 <0x03882000 0x2000>, 968 <0x03884000 0x2000>, 969 <0x03886000 0x2000>; 970 interrupts = <GIC_PPI 9 971 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 972 interrupt-parent = <&gic>; 973 }; 974 975 cec@3960000 { 976 compatible = "nvidia,tegra194-cec"; 977 reg = <0x03960000 0x10000>; 978 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&bpmp TEGRA194_CLK_CEC>; 980 clock-names = "cec"; 981 status = "disabled"; 982 }; 983 984 hsp_top0: hsp@3c00000 { 985 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 986 reg = <0x03c00000 0xa0000>; 987 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 996 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 997 "shared3", "shared4", "shared5", "shared6", 998 "shared7"; 999 #mbox-cells = <2>; 1000 }; 1001 1002 p2u_hsio_0: phy@3e10000 { 1003 compatible = "nvidia,tegra194-p2u"; 1004 reg = <0x03e10000 0x10000>; 1005 reg-names = "ctl"; 1006 1007 #phy-cells = <0>; 1008 }; 1009 1010 p2u_hsio_1: phy@3e20000 { 1011 compatible = "nvidia,tegra194-p2u"; 1012 reg = <0x03e20000 0x10000>; 1013 reg-names = "ctl"; 1014 1015 #phy-cells = <0>; 1016 }; 1017 1018 p2u_hsio_2: phy@3e30000 { 1019 compatible = "nvidia,tegra194-p2u"; 1020 reg = <0x03e30000 0x10000>; 1021 reg-names = "ctl"; 1022 1023 #phy-cells = <0>; 1024 }; 1025 1026 p2u_hsio_3: phy@3e40000 { 1027 compatible = "nvidia,tegra194-p2u"; 1028 reg = <0x03e40000 0x10000>; 1029 reg-names = "ctl"; 1030 1031 #phy-cells = <0>; 1032 }; 1033 1034 p2u_hsio_4: phy@3e50000 { 1035 compatible = "nvidia,tegra194-p2u"; 1036 reg = <0x03e50000 0x10000>; 1037 reg-names = "ctl"; 1038 1039 #phy-cells = <0>; 1040 }; 1041 1042 p2u_hsio_5: phy@3e60000 { 1043 compatible = "nvidia,tegra194-p2u"; 1044 reg = <0x03e60000 0x10000>; 1045 reg-names = "ctl"; 1046 1047 #phy-cells = <0>; 1048 }; 1049 1050 p2u_hsio_6: phy@3e70000 { 1051 compatible = "nvidia,tegra194-p2u"; 1052 reg = <0x03e70000 0x10000>; 1053 reg-names = "ctl"; 1054 1055 #phy-cells = <0>; 1056 }; 1057 1058 p2u_hsio_7: phy@3e80000 { 1059 compatible = "nvidia,tegra194-p2u"; 1060 reg = <0x03e80000 0x10000>; 1061 reg-names = "ctl"; 1062 1063 #phy-cells = <0>; 1064 }; 1065 1066 p2u_hsio_8: phy@3e90000 { 1067 compatible = "nvidia,tegra194-p2u"; 1068 reg = <0x03e90000 0x10000>; 1069 reg-names = "ctl"; 1070 1071 #phy-cells = <0>; 1072 }; 1073 1074 p2u_hsio_9: phy@3ea0000 { 1075 compatible = "nvidia,tegra194-p2u"; 1076 reg = <0x03ea0000 0x10000>; 1077 reg-names = "ctl"; 1078 1079 #phy-cells = <0>; 1080 }; 1081 1082 p2u_nvhs_0: phy@3eb0000 { 1083 compatible = "nvidia,tegra194-p2u"; 1084 reg = <0x03eb0000 0x10000>; 1085 reg-names = "ctl"; 1086 1087 #phy-cells = <0>; 1088 }; 1089 1090 p2u_nvhs_1: phy@3ec0000 { 1091 compatible = "nvidia,tegra194-p2u"; 1092 reg = <0x03ec0000 0x10000>; 1093 reg-names = "ctl"; 1094 1095 #phy-cells = <0>; 1096 }; 1097 1098 p2u_nvhs_2: phy@3ed0000 { 1099 compatible = "nvidia,tegra194-p2u"; 1100 reg = <0x03ed0000 0x10000>; 1101 reg-names = "ctl"; 1102 1103 #phy-cells = <0>; 1104 }; 1105 1106 p2u_nvhs_3: phy@3ee0000 { 1107 compatible = "nvidia,tegra194-p2u"; 1108 reg = <0x03ee0000 0x10000>; 1109 reg-names = "ctl"; 1110 1111 #phy-cells = <0>; 1112 }; 1113 1114 p2u_nvhs_4: phy@3ef0000 { 1115 compatible = "nvidia,tegra194-p2u"; 1116 reg = <0x03ef0000 0x10000>; 1117 reg-names = "ctl"; 1118 1119 #phy-cells = <0>; 1120 }; 1121 1122 p2u_nvhs_5: phy@3f00000 { 1123 compatible = "nvidia,tegra194-p2u"; 1124 reg = <0x03f00000 0x10000>; 1125 reg-names = "ctl"; 1126 1127 #phy-cells = <0>; 1128 }; 1129 1130 p2u_nvhs_6: phy@3f10000 { 1131 compatible = "nvidia,tegra194-p2u"; 1132 reg = <0x03f10000 0x10000>; 1133 reg-names = "ctl"; 1134 1135 #phy-cells = <0>; 1136 }; 1137 1138 p2u_nvhs_7: phy@3f20000 { 1139 compatible = "nvidia,tegra194-p2u"; 1140 reg = <0x03f20000 0x10000>; 1141 reg-names = "ctl"; 1142 1143 #phy-cells = <0>; 1144 }; 1145 1146 p2u_hsio_10: phy@3f30000 { 1147 compatible = "nvidia,tegra194-p2u"; 1148 reg = <0x03f30000 0x10000>; 1149 reg-names = "ctl"; 1150 1151 #phy-cells = <0>; 1152 }; 1153 1154 p2u_hsio_11: phy@3f40000 { 1155 compatible = "nvidia,tegra194-p2u"; 1156 reg = <0x03f40000 0x10000>; 1157 reg-names = "ctl"; 1158 1159 #phy-cells = <0>; 1160 }; 1161 1162 hsp_aon: hsp@c150000 { 1163 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1164 reg = <0x0c150000 0x90000>; 1165 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1169 /* 1170 * Shared interrupt 0 is routed only to AON/SPE, so 1171 * we only have 4 shared interrupts for the CCPLEX. 1172 */ 1173 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1174 #mbox-cells = <2>; 1175 }; 1176 1177 gen2_i2c: i2c@c240000 { 1178 compatible = "nvidia,tegra194-i2c"; 1179 reg = <0x0c240000 0x10000>; 1180 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1184 clock-names = "div-clk"; 1185 resets = <&bpmp TEGRA194_RESET_I2C2>; 1186 reset-names = "i2c"; 1187 status = "disabled"; 1188 }; 1189 1190 gen8_i2c: i2c@c250000 { 1191 compatible = "nvidia,tegra194-i2c"; 1192 reg = <0x0c250000 0x10000>; 1193 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1197 clock-names = "div-clk"; 1198 resets = <&bpmp TEGRA194_RESET_I2C8>; 1199 reset-names = "i2c"; 1200 status = "disabled"; 1201 }; 1202 1203 uartc: serial@c280000 { 1204 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1205 reg = <0x0c280000 0x40>; 1206 reg-shift = <2>; 1207 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1208 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1209 clock-names = "serial"; 1210 resets = <&bpmp TEGRA194_RESET_UARTC>; 1211 reset-names = "serial"; 1212 status = "disabled"; 1213 }; 1214 1215 uartg: serial@c290000 { 1216 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1217 reg = <0x0c290000 0x40>; 1218 reg-shift = <2>; 1219 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1220 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1221 clock-names = "serial"; 1222 resets = <&bpmp TEGRA194_RESET_UARTG>; 1223 reset-names = "serial"; 1224 status = "disabled"; 1225 }; 1226 1227 rtc: rtc@c2a0000 { 1228 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1229 reg = <0x0c2a0000 0x10000>; 1230 interrupt-parent = <&pmc>; 1231 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1233 clock-names = "rtc"; 1234 status = "disabled"; 1235 }; 1236 1237 gpio_aon: gpio@c2f0000 { 1238 compatible = "nvidia,tegra194-gpio-aon"; 1239 reg-names = "security", "gpio"; 1240 reg = <0xc2f0000 0x1000>, 1241 <0xc2f1000 0x1000>; 1242 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1243 gpio-controller; 1244 #gpio-cells = <2>; 1245 interrupt-controller; 1246 #interrupt-cells = <2>; 1247 }; 1248 1249 pwm4: pwm@c340000 { 1250 compatible = "nvidia,tegra194-pwm", 1251 "nvidia,tegra186-pwm"; 1252 reg = <0xc340000 0x10000>; 1253 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1254 clock-names = "pwm"; 1255 resets = <&bpmp TEGRA194_RESET_PWM4>; 1256 reset-names = "pwm"; 1257 status = "disabled"; 1258 #pwm-cells = <2>; 1259 }; 1260 1261 pmc: pmc@c360000 { 1262 compatible = "nvidia,tegra194-pmc"; 1263 reg = <0x0c360000 0x10000>, 1264 <0x0c370000 0x10000>, 1265 <0x0c380000 0x10000>, 1266 <0x0c390000 0x10000>, 1267 <0x0c3a0000 0x10000>; 1268 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1269 1270 #interrupt-cells = <2>; 1271 interrupt-controller; 1272 }; 1273 1274 host1x@13e00000 { 1275 compatible = "nvidia,tegra194-host1x"; 1276 reg = <0x13e00000 0x10000>, 1277 <0x13e10000 0x10000>; 1278 reg-names = "hypervisor", "vm"; 1279 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1281 interrupt-names = "syncpt", "host1x"; 1282 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1283 clock-names = "host1x"; 1284 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1285 reset-names = "host1x"; 1286 1287 #address-cells = <1>; 1288 #size-cells = <1>; 1289 1290 ranges = <0x15000000 0x15000000 0x01000000>; 1291 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1292 interconnect-names = "dma-mem"; 1293 1294 display-hub@15200000 { 1295 compatible = "nvidia,tegra194-display"; 1296 reg = <0x15200000 0x00040000>; 1297 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1298 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1299 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1300 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1301 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1302 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1303 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1304 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1305 "wgrp3", "wgrp4", "wgrp5"; 1306 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1307 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1308 clock-names = "disp", "hub"; 1309 status = "disabled"; 1310 1311 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1312 1313 #address-cells = <1>; 1314 #size-cells = <1>; 1315 1316 ranges = <0x15200000 0x15200000 0x40000>; 1317 1318 display@15200000 { 1319 compatible = "nvidia,tegra194-dc"; 1320 reg = <0x15200000 0x10000>; 1321 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1322 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1323 clock-names = "dc"; 1324 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1325 reset-names = "dc"; 1326 1327 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1328 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1329 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1330 interconnect-names = "dma-mem", "read-1"; 1331 1332 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1333 nvidia,head = <0>; 1334 }; 1335 1336 display@15210000 { 1337 compatible = "nvidia,tegra194-dc"; 1338 reg = <0x15210000 0x10000>; 1339 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1340 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1341 clock-names = "dc"; 1342 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1343 reset-names = "dc"; 1344 1345 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1346 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1347 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1348 interconnect-names = "dma-mem", "read-1"; 1349 1350 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1351 nvidia,head = <1>; 1352 }; 1353 1354 display@15220000 { 1355 compatible = "nvidia,tegra194-dc"; 1356 reg = <0x15220000 0x10000>; 1357 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1358 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1359 clock-names = "dc"; 1360 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1361 reset-names = "dc"; 1362 1363 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1364 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1365 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1366 interconnect-names = "dma-mem", "read-1"; 1367 1368 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1369 nvidia,head = <2>; 1370 }; 1371 1372 display@15230000 { 1373 compatible = "nvidia,tegra194-dc"; 1374 reg = <0x15230000 0x10000>; 1375 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1376 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1377 clock-names = "dc"; 1378 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1379 reset-names = "dc"; 1380 1381 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1382 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1383 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1384 interconnect-names = "dma-mem", "read-1"; 1385 1386 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1387 nvidia,head = <3>; 1388 }; 1389 }; 1390 1391 vic@15340000 { 1392 compatible = "nvidia,tegra194-vic"; 1393 reg = <0x15340000 0x00040000>; 1394 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1395 clocks = <&bpmp TEGRA194_CLK_VIC>; 1396 clock-names = "vic"; 1397 resets = <&bpmp TEGRA194_RESET_VIC>; 1398 reset-names = "vic"; 1399 1400 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1401 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1402 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1403 interconnect-names = "dma-mem", "write"; 1404 }; 1405 1406 dpaux0: dpaux@155c0000 { 1407 compatible = "nvidia,tegra194-dpaux"; 1408 reg = <0x155c0000 0x10000>; 1409 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1410 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1411 <&bpmp TEGRA194_CLK_PLLDP>; 1412 clock-names = "dpaux", "parent"; 1413 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1414 reset-names = "dpaux"; 1415 status = "disabled"; 1416 1417 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1418 1419 state_dpaux0_aux: pinmux-aux { 1420 groups = "dpaux-io"; 1421 function = "aux"; 1422 }; 1423 1424 state_dpaux0_i2c: pinmux-i2c { 1425 groups = "dpaux-io"; 1426 function = "i2c"; 1427 }; 1428 1429 state_dpaux0_off: pinmux-off { 1430 groups = "dpaux-io"; 1431 function = "off"; 1432 }; 1433 1434 i2c-bus { 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 }; 1438 }; 1439 1440 dpaux1: dpaux@155d0000 { 1441 compatible = "nvidia,tegra194-dpaux"; 1442 reg = <0x155d0000 0x10000>; 1443 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1444 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1445 <&bpmp TEGRA194_CLK_PLLDP>; 1446 clock-names = "dpaux", "parent"; 1447 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1448 reset-names = "dpaux"; 1449 status = "disabled"; 1450 1451 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1452 1453 state_dpaux1_aux: pinmux-aux { 1454 groups = "dpaux-io"; 1455 function = "aux"; 1456 }; 1457 1458 state_dpaux1_i2c: pinmux-i2c { 1459 groups = "dpaux-io"; 1460 function = "i2c"; 1461 }; 1462 1463 state_dpaux1_off: pinmux-off { 1464 groups = "dpaux-io"; 1465 function = "off"; 1466 }; 1467 1468 i2c-bus { 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 }; 1472 }; 1473 1474 dpaux2: dpaux@155e0000 { 1475 compatible = "nvidia,tegra194-dpaux"; 1476 reg = <0x155e0000 0x10000>; 1477 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1478 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1479 <&bpmp TEGRA194_CLK_PLLDP>; 1480 clock-names = "dpaux", "parent"; 1481 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1482 reset-names = "dpaux"; 1483 status = "disabled"; 1484 1485 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1486 1487 state_dpaux2_aux: pinmux-aux { 1488 groups = "dpaux-io"; 1489 function = "aux"; 1490 }; 1491 1492 state_dpaux2_i2c: pinmux-i2c { 1493 groups = "dpaux-io"; 1494 function = "i2c"; 1495 }; 1496 1497 state_dpaux2_off: pinmux-off { 1498 groups = "dpaux-io"; 1499 function = "off"; 1500 }; 1501 1502 i2c-bus { 1503 #address-cells = <1>; 1504 #size-cells = <0>; 1505 }; 1506 }; 1507 1508 dpaux3: dpaux@155f0000 { 1509 compatible = "nvidia,tegra194-dpaux"; 1510 reg = <0x155f0000 0x10000>; 1511 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1512 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1513 <&bpmp TEGRA194_CLK_PLLDP>; 1514 clock-names = "dpaux", "parent"; 1515 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1516 reset-names = "dpaux"; 1517 status = "disabled"; 1518 1519 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1520 1521 state_dpaux3_aux: pinmux-aux { 1522 groups = "dpaux-io"; 1523 function = "aux"; 1524 }; 1525 1526 state_dpaux3_i2c: pinmux-i2c { 1527 groups = "dpaux-io"; 1528 function = "i2c"; 1529 }; 1530 1531 state_dpaux3_off: pinmux-off { 1532 groups = "dpaux-io"; 1533 function = "off"; 1534 }; 1535 1536 i2c-bus { 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 }; 1540 }; 1541 1542 sor0: sor@15b00000 { 1543 compatible = "nvidia,tegra194-sor"; 1544 reg = <0x15b00000 0x40000>; 1545 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1546 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1547 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1548 <&bpmp TEGRA194_CLK_PLLD>, 1549 <&bpmp TEGRA194_CLK_PLLDP>, 1550 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1551 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1552 clock-names = "sor", "out", "parent", "dp", "safe", 1553 "pad"; 1554 resets = <&bpmp TEGRA194_RESET_SOR0>; 1555 reset-names = "sor"; 1556 pinctrl-0 = <&state_dpaux0_aux>; 1557 pinctrl-1 = <&state_dpaux0_i2c>; 1558 pinctrl-2 = <&state_dpaux0_off>; 1559 pinctrl-names = "aux", "i2c", "off"; 1560 status = "disabled"; 1561 1562 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1563 nvidia,interface = <0>; 1564 }; 1565 1566 sor1: sor@15b40000 { 1567 compatible = "nvidia,tegra194-sor"; 1568 reg = <0x15b40000 0x40000>; 1569 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1570 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1571 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1572 <&bpmp TEGRA194_CLK_PLLD2>, 1573 <&bpmp TEGRA194_CLK_PLLDP>, 1574 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1575 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1576 clock-names = "sor", "out", "parent", "dp", "safe", 1577 "pad"; 1578 resets = <&bpmp TEGRA194_RESET_SOR1>; 1579 reset-names = "sor"; 1580 pinctrl-0 = <&state_dpaux1_aux>; 1581 pinctrl-1 = <&state_dpaux1_i2c>; 1582 pinctrl-2 = <&state_dpaux1_off>; 1583 pinctrl-names = "aux", "i2c", "off"; 1584 status = "disabled"; 1585 1586 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1587 nvidia,interface = <1>; 1588 }; 1589 1590 sor2: sor@15b80000 { 1591 compatible = "nvidia,tegra194-sor"; 1592 reg = <0x15b80000 0x40000>; 1593 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1594 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1595 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1596 <&bpmp TEGRA194_CLK_PLLD3>, 1597 <&bpmp TEGRA194_CLK_PLLDP>, 1598 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1599 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1600 clock-names = "sor", "out", "parent", "dp", "safe", 1601 "pad"; 1602 resets = <&bpmp TEGRA194_RESET_SOR2>; 1603 reset-names = "sor"; 1604 pinctrl-0 = <&state_dpaux2_aux>; 1605 pinctrl-1 = <&state_dpaux2_i2c>; 1606 pinctrl-2 = <&state_dpaux2_off>; 1607 pinctrl-names = "aux", "i2c", "off"; 1608 status = "disabled"; 1609 1610 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1611 nvidia,interface = <2>; 1612 }; 1613 1614 sor3: sor@15bc0000 { 1615 compatible = "nvidia,tegra194-sor"; 1616 reg = <0x15bc0000 0x40000>; 1617 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1618 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1619 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1620 <&bpmp TEGRA194_CLK_PLLD4>, 1621 <&bpmp TEGRA194_CLK_PLLDP>, 1622 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1623 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1624 clock-names = "sor", "out", "parent", "dp", "safe", 1625 "pad"; 1626 resets = <&bpmp TEGRA194_RESET_SOR3>; 1627 reset-names = "sor"; 1628 pinctrl-0 = <&state_dpaux3_aux>; 1629 pinctrl-1 = <&state_dpaux3_i2c>; 1630 pinctrl-2 = <&state_dpaux3_off>; 1631 pinctrl-names = "aux", "i2c", "off"; 1632 status = "disabled"; 1633 1634 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1635 nvidia,interface = <3>; 1636 }; 1637 }; 1638 1639 gpu@17000000 { 1640 compatible = "nvidia,gv11b"; 1641 reg = <0x17000000 0x1000000>, 1642 <0x18000000 0x1000000>; 1643 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1645 interrupt-names = "stall", "nonstall"; 1646 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 1647 <&bpmp TEGRA194_CLK_GPU_PWR>, 1648 <&bpmp TEGRA194_CLK_FUSE>; 1649 clock-names = "gpu", "pwr", "fuse"; 1650 resets = <&bpmp TEGRA194_RESET_GPU>; 1651 reset-names = "gpu"; 1652 dma-coherent; 1653 1654 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 1655 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 1656 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 1657 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 1658 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 1659 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 1660 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 1661 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 1662 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 1663 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 1664 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 1665 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 1666 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 1667 interconnect-names = "dma-mem", "read-0-hp", "write-0", 1668 "read-1", "read-1-hp", "write-1", 1669 "read-2", "read-2-hp", "write-2", 1670 "read-3", "read-3-hp", "write-3"; 1671 }; 1672 }; 1673 1674 pcie@14100000 { 1675 compatible = "nvidia,tegra194-pcie"; 1676 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1677 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1678 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1679 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1680 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1681 reg-names = "appl", "config", "atu_dma", "dbi"; 1682 1683 status = "disabled"; 1684 1685 #address-cells = <3>; 1686 #size-cells = <2>; 1687 device_type = "pci"; 1688 num-lanes = <1>; 1689 num-viewport = <8>; 1690 linux,pci-domain = <1>; 1691 1692 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 1693 clock-names = "core"; 1694 1695 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 1696 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 1697 reset-names = "apb", "core"; 1698 1699 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1700 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1701 interrupt-names = "intr", "msi"; 1702 1703 #interrupt-cells = <1>; 1704 interrupt-map-mask = <0 0 0 0>; 1705 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1706 1707 nvidia,bpmp = <&bpmp 1>; 1708 1709 nvidia,aspm-cmrt-us = <60>; 1710 nvidia,aspm-pwr-on-t-us = <20>; 1711 nvidia,aspm-l0s-entrance-latency-us = <3>; 1712 1713 bus-range = <0x0 0xff>; 1714 1715 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1716 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 1717 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1718 1719 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1720 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1721 interconnect-names = "read", "write"; 1722 }; 1723 1724 pcie@14120000 { 1725 compatible = "nvidia,tegra194-pcie"; 1726 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1727 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1728 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1729 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1730 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1731 reg-names = "appl", "config", "atu_dma", "dbi"; 1732 1733 status = "disabled"; 1734 1735 #address-cells = <3>; 1736 #size-cells = <2>; 1737 device_type = "pci"; 1738 num-lanes = <1>; 1739 num-viewport = <8>; 1740 linux,pci-domain = <2>; 1741 1742 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 1743 clock-names = "core"; 1744 1745 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 1746 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 1747 reset-names = "apb", "core"; 1748 1749 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1750 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1751 interrupt-names = "intr", "msi"; 1752 1753 #interrupt-cells = <1>; 1754 interrupt-map-mask = <0 0 0 0>; 1755 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1756 1757 nvidia,bpmp = <&bpmp 2>; 1758 1759 nvidia,aspm-cmrt-us = <60>; 1760 nvidia,aspm-pwr-on-t-us = <20>; 1761 nvidia,aspm-l0s-entrance-latency-us = <3>; 1762 1763 bus-range = <0x0 0xff>; 1764 1765 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1766 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 1767 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1768 1769 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1770 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1771 interconnect-names = "read", "write"; 1772 }; 1773 1774 pcie@14140000 { 1775 compatible = "nvidia,tegra194-pcie"; 1776 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1777 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1778 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1779 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1780 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1781 reg-names = "appl", "config", "atu_dma", "dbi"; 1782 1783 status = "disabled"; 1784 1785 #address-cells = <3>; 1786 #size-cells = <2>; 1787 device_type = "pci"; 1788 num-lanes = <1>; 1789 num-viewport = <8>; 1790 linux,pci-domain = <3>; 1791 1792 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 1793 clock-names = "core"; 1794 1795 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 1796 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 1797 reset-names = "apb", "core"; 1798 1799 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1800 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1801 interrupt-names = "intr", "msi"; 1802 1803 #interrupt-cells = <1>; 1804 interrupt-map-mask = <0 0 0 0>; 1805 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1806 1807 nvidia,bpmp = <&bpmp 3>; 1808 1809 nvidia,aspm-cmrt-us = <60>; 1810 nvidia,aspm-pwr-on-t-us = <20>; 1811 nvidia,aspm-l0s-entrance-latency-us = <3>; 1812 1813 bus-range = <0x0 0xff>; 1814 1815 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1816 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 1817 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1818 1819 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 1820 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 1821 interconnect-names = "read", "write"; 1822 }; 1823 1824 pcie@14160000 { 1825 compatible = "nvidia,tegra194-pcie"; 1826 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1827 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1828 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 1829 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1830 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1831 reg-names = "appl", "config", "atu_dma", "dbi"; 1832 1833 status = "disabled"; 1834 1835 #address-cells = <3>; 1836 #size-cells = <2>; 1837 device_type = "pci"; 1838 num-lanes = <4>; 1839 num-viewport = <8>; 1840 linux,pci-domain = <4>; 1841 1842 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1843 clock-names = "core"; 1844 1845 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1846 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1847 reset-names = "apb", "core"; 1848 1849 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1850 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1851 interrupt-names = "intr", "msi"; 1852 1853 #interrupt-cells = <1>; 1854 interrupt-map-mask = <0 0 0 0>; 1855 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1856 1857 nvidia,bpmp = <&bpmp 4>; 1858 1859 nvidia,aspm-cmrt-us = <60>; 1860 nvidia,aspm-pwr-on-t-us = <20>; 1861 nvidia,aspm-l0s-entrance-latency-us = <3>; 1862 1863 bus-range = <0x0 0xff>; 1864 1865 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1866 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1867 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1868 1869 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 1870 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 1871 interconnect-names = "read", "write"; 1872 }; 1873 1874 pcie@14180000 { 1875 compatible = "nvidia,tegra194-pcie"; 1876 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1877 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1878 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 1879 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1880 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1881 reg-names = "appl", "config", "atu_dma", "dbi"; 1882 1883 status = "disabled"; 1884 1885 #address-cells = <3>; 1886 #size-cells = <2>; 1887 device_type = "pci"; 1888 num-lanes = <8>; 1889 num-viewport = <8>; 1890 linux,pci-domain = <0>; 1891 1892 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1893 clock-names = "core"; 1894 1895 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1896 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1897 reset-names = "apb", "core"; 1898 1899 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1900 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1901 interrupt-names = "intr", "msi"; 1902 1903 #interrupt-cells = <1>; 1904 interrupt-map-mask = <0 0 0 0>; 1905 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1906 1907 nvidia,bpmp = <&bpmp 0>; 1908 1909 nvidia,aspm-cmrt-us = <60>; 1910 nvidia,aspm-pwr-on-t-us = <20>; 1911 nvidia,aspm-l0s-entrance-latency-us = <3>; 1912 1913 bus-range = <0x0 0xff>; 1914 1915 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1916 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1917 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1918 1919 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 1920 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 1921 interconnect-names = "read", "write"; 1922 }; 1923 1924 pcie@141a0000 { 1925 compatible = "nvidia,tegra194-pcie"; 1926 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1927 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1928 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 1929 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1930 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1931 reg-names = "appl", "config", "atu_dma", "dbi"; 1932 1933 status = "disabled"; 1934 1935 #address-cells = <3>; 1936 #size-cells = <2>; 1937 device_type = "pci"; 1938 num-lanes = <8>; 1939 num-viewport = <8>; 1940 linux,pci-domain = <5>; 1941 1942 pinctrl-names = "default"; 1943 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1944 1945 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 1946 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 1947 clock-names = "core", "core_m"; 1948 1949 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1950 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1951 reset-names = "apb", "core"; 1952 1953 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1954 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1955 interrupt-names = "intr", "msi"; 1956 1957 nvidia,bpmp = <&bpmp 5>; 1958 1959 #interrupt-cells = <1>; 1960 interrupt-map-mask = <0 0 0 0>; 1961 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1962 1963 nvidia,aspm-cmrt-us = <60>; 1964 nvidia,aspm-pwr-on-t-us = <20>; 1965 nvidia,aspm-l0s-entrance-latency-us = <3>; 1966 1967 bus-range = <0x0 0xff>; 1968 1969 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1970 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1971 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1972 1973 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 1974 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 1975 interconnect-names = "read", "write"; 1976 }; 1977 1978 pcie_ep@14160000 { 1979 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1980 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1981 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1982 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1983 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1984 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1985 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1986 1987 status = "disabled"; 1988 1989 num-lanes = <4>; 1990 num-ib-windows = <2>; 1991 num-ob-windows = <8>; 1992 1993 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1994 clock-names = "core"; 1995 1996 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1997 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1998 reset-names = "apb", "core"; 1999 2000 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2001 interrupt-names = "intr"; 2002 2003 nvidia,bpmp = <&bpmp 4>; 2004 2005 nvidia,aspm-cmrt-us = <60>; 2006 nvidia,aspm-pwr-on-t-us = <20>; 2007 nvidia,aspm-l0s-entrance-latency-us = <3>; 2008 }; 2009 2010 pcie_ep@14180000 { 2011 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 2012 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2013 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2014 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2015 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2016 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2017 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2018 2019 status = "disabled"; 2020 2021 num-lanes = <8>; 2022 num-ib-windows = <2>; 2023 num-ob-windows = <8>; 2024 2025 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2026 clock-names = "core"; 2027 2028 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2029 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2030 reset-names = "apb", "core"; 2031 2032 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2033 interrupt-names = "intr"; 2034 2035 nvidia,bpmp = <&bpmp 0>; 2036 2037 nvidia,aspm-cmrt-us = <60>; 2038 nvidia,aspm-pwr-on-t-us = <20>; 2039 nvidia,aspm-l0s-entrance-latency-us = <3>; 2040 }; 2041 2042 pcie_ep@141a0000 { 2043 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 2044 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2045 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2046 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2047 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2048 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2049 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2050 2051 status = "disabled"; 2052 2053 num-lanes = <8>; 2054 num-ib-windows = <2>; 2055 num-ob-windows = <8>; 2056 2057 pinctrl-names = "default"; 2058 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2059 2060 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2061 clock-names = "core"; 2062 2063 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2064 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2065 reset-names = "apb", "core"; 2066 2067 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2068 interrupt-names = "intr"; 2069 2070 nvidia,bpmp = <&bpmp 5>; 2071 2072 nvidia,aspm-cmrt-us = <60>; 2073 nvidia,aspm-pwr-on-t-us = <20>; 2074 nvidia,aspm-l0s-entrance-latency-us = <3>; 2075 }; 2076 2077 sram@40000000 { 2078 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2079 reg = <0x0 0x40000000 0x0 0x50000>; 2080 #address-cells = <1>; 2081 #size-cells = <1>; 2082 ranges = <0x0 0x0 0x40000000 0x50000>; 2083 2084 cpu_bpmp_tx: sram@4e000 { 2085 reg = <0x4e000 0x1000>; 2086 label = "cpu-bpmp-tx"; 2087 pool; 2088 }; 2089 2090 cpu_bpmp_rx: sram@4f000 { 2091 reg = <0x4f000 0x1000>; 2092 label = "cpu-bpmp-rx"; 2093 pool; 2094 }; 2095 }; 2096 2097 bpmp: bpmp { 2098 compatible = "nvidia,tegra186-bpmp"; 2099 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2100 TEGRA_HSP_DB_MASTER_BPMP>; 2101 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 2102 #clock-cells = <1>; 2103 #reset-cells = <1>; 2104 #power-domain-cells = <1>; 2105 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2106 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2107 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2108 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2109 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2110 2111 bpmp_i2c: i2c { 2112 compatible = "nvidia,tegra186-bpmp-i2c"; 2113 nvidia,bpmp-bus-id = <5>; 2114 #address-cells = <1>; 2115 #size-cells = <0>; 2116 }; 2117 2118 bpmp_thermal: thermal { 2119 compatible = "nvidia,tegra186-bpmp-thermal"; 2120 #thermal-sensor-cells = <1>; 2121 }; 2122 }; 2123 2124 cpus { 2125 compatible = "nvidia,tegra194-ccplex"; 2126 nvidia,bpmp = <&bpmp>; 2127 #address-cells = <1>; 2128 #size-cells = <0>; 2129 2130 cpu0_0: cpu@0 { 2131 compatible = "nvidia,tegra194-carmel"; 2132 device_type = "cpu"; 2133 reg = <0x000>; 2134 enable-method = "psci"; 2135 i-cache-size = <131072>; 2136 i-cache-line-size = <64>; 2137 i-cache-sets = <512>; 2138 d-cache-size = <65536>; 2139 d-cache-line-size = <64>; 2140 d-cache-sets = <256>; 2141 next-level-cache = <&l2c_0>; 2142 }; 2143 2144 cpu0_1: cpu@1 { 2145 compatible = "nvidia,tegra194-carmel"; 2146 device_type = "cpu"; 2147 reg = <0x001>; 2148 enable-method = "psci"; 2149 i-cache-size = <131072>; 2150 i-cache-line-size = <64>; 2151 i-cache-sets = <512>; 2152 d-cache-size = <65536>; 2153 d-cache-line-size = <64>; 2154 d-cache-sets = <256>; 2155 next-level-cache = <&l2c_0>; 2156 }; 2157 2158 cpu1_0: cpu@100 { 2159 compatible = "nvidia,tegra194-carmel"; 2160 device_type = "cpu"; 2161 reg = <0x100>; 2162 enable-method = "psci"; 2163 i-cache-size = <131072>; 2164 i-cache-line-size = <64>; 2165 i-cache-sets = <512>; 2166 d-cache-size = <65536>; 2167 d-cache-line-size = <64>; 2168 d-cache-sets = <256>; 2169 next-level-cache = <&l2c_1>; 2170 }; 2171 2172 cpu1_1: cpu@101 { 2173 compatible = "nvidia,tegra194-carmel"; 2174 device_type = "cpu"; 2175 reg = <0x101>; 2176 enable-method = "psci"; 2177 i-cache-size = <131072>; 2178 i-cache-line-size = <64>; 2179 i-cache-sets = <512>; 2180 d-cache-size = <65536>; 2181 d-cache-line-size = <64>; 2182 d-cache-sets = <256>; 2183 next-level-cache = <&l2c_1>; 2184 }; 2185 2186 cpu2_0: cpu@200 { 2187 compatible = "nvidia,tegra194-carmel"; 2188 device_type = "cpu"; 2189 reg = <0x200>; 2190 enable-method = "psci"; 2191 i-cache-size = <131072>; 2192 i-cache-line-size = <64>; 2193 i-cache-sets = <512>; 2194 d-cache-size = <65536>; 2195 d-cache-line-size = <64>; 2196 d-cache-sets = <256>; 2197 next-level-cache = <&l2c_2>; 2198 }; 2199 2200 cpu2_1: cpu@201 { 2201 compatible = "nvidia,tegra194-carmel"; 2202 device_type = "cpu"; 2203 reg = <0x201>; 2204 enable-method = "psci"; 2205 i-cache-size = <131072>; 2206 i-cache-line-size = <64>; 2207 i-cache-sets = <512>; 2208 d-cache-size = <65536>; 2209 d-cache-line-size = <64>; 2210 d-cache-sets = <256>; 2211 next-level-cache = <&l2c_2>; 2212 }; 2213 2214 cpu3_0: cpu@300 { 2215 compatible = "nvidia,tegra194-carmel"; 2216 device_type = "cpu"; 2217 reg = <0x300>; 2218 enable-method = "psci"; 2219 i-cache-size = <131072>; 2220 i-cache-line-size = <64>; 2221 i-cache-sets = <512>; 2222 d-cache-size = <65536>; 2223 d-cache-line-size = <64>; 2224 d-cache-sets = <256>; 2225 next-level-cache = <&l2c_3>; 2226 }; 2227 2228 cpu3_1: cpu@301 { 2229 compatible = "nvidia,tegra194-carmel"; 2230 device_type = "cpu"; 2231 reg = <0x301>; 2232 enable-method = "psci"; 2233 i-cache-size = <131072>; 2234 i-cache-line-size = <64>; 2235 i-cache-sets = <512>; 2236 d-cache-size = <65536>; 2237 d-cache-line-size = <64>; 2238 d-cache-sets = <256>; 2239 next-level-cache = <&l2c_3>; 2240 }; 2241 2242 cpu-map { 2243 cluster0 { 2244 core0 { 2245 cpu = <&cpu0_0>; 2246 }; 2247 2248 core1 { 2249 cpu = <&cpu0_1>; 2250 }; 2251 }; 2252 2253 cluster1 { 2254 core0 { 2255 cpu = <&cpu1_0>; 2256 }; 2257 2258 core1 { 2259 cpu = <&cpu1_1>; 2260 }; 2261 }; 2262 2263 cluster2 { 2264 core0 { 2265 cpu = <&cpu2_0>; 2266 }; 2267 2268 core1 { 2269 cpu = <&cpu2_1>; 2270 }; 2271 }; 2272 2273 cluster3 { 2274 core0 { 2275 cpu = <&cpu3_0>; 2276 }; 2277 2278 core1 { 2279 cpu = <&cpu3_1>; 2280 }; 2281 }; 2282 }; 2283 2284 l2c_0: l2-cache0 { 2285 cache-size = <2097152>; 2286 cache-line-size = <64>; 2287 cache-sets = <2048>; 2288 next-level-cache = <&l3c>; 2289 }; 2290 2291 l2c_1: l2-cache1 { 2292 cache-size = <2097152>; 2293 cache-line-size = <64>; 2294 cache-sets = <2048>; 2295 next-level-cache = <&l3c>; 2296 }; 2297 2298 l2c_2: l2-cache2 { 2299 cache-size = <2097152>; 2300 cache-line-size = <64>; 2301 cache-sets = <2048>; 2302 next-level-cache = <&l3c>; 2303 }; 2304 2305 l2c_3: l2-cache3 { 2306 cache-size = <2097152>; 2307 cache-line-size = <64>; 2308 cache-sets = <2048>; 2309 next-level-cache = <&l3c>; 2310 }; 2311 2312 l3c: l3-cache { 2313 cache-size = <4194304>; 2314 cache-line-size = <64>; 2315 cache-sets = <4096>; 2316 }; 2317 }; 2318 2319 psci { 2320 compatible = "arm,psci-1.0"; 2321 status = "okay"; 2322 method = "smc"; 2323 }; 2324 2325 tcu: tcu { 2326 compatible = "nvidia,tegra194-tcu"; 2327 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2328 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2329 mbox-names = "rx", "tx"; 2330 }; 2331 2332 thermal-zones { 2333 cpu { 2334 thermal-sensors = <&{/bpmp/thermal} 2335 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2336 status = "disabled"; 2337 }; 2338 2339 gpu { 2340 thermal-sensors = <&{/bpmp/thermal} 2341 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2342 status = "disabled"; 2343 }; 2344 2345 aux { 2346 thermal-sensors = <&{/bpmp/thermal} 2347 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2348 status = "disabled"; 2349 }; 2350 2351 pllx { 2352 thermal-sensors = <&{/bpmp/thermal} 2353 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2354 status = "disabled"; 2355 }; 2356 2357 ao { 2358 thermal-sensors = <&{/bpmp/thermal} 2359 TEGRA194_BPMP_THERMAL_ZONE_AO>; 2360 status = "disabled"; 2361 }; 2362 2363 tj { 2364 thermal-sensors = <&{/bpmp/thermal} 2365 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2366 status = "disabled"; 2367 }; 2368 }; 2369 2370 timer { 2371 compatible = "arm,armv8-timer"; 2372 interrupts = <GIC_PPI 13 2373 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2374 <GIC_PPI 14 2375 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2376 <GIC_PPI 11 2377 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2378 <GIC_PPI 10 2379 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2380 interrupt-parent = <&gic>; 2381 always-on; 2382 }; 2383}; 2384