1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 }; 90 91 ethernet@2490000 { 92 compatible = "nvidia,tegra194-eqos", 93 "nvidia,tegra186-eqos", 94 "snps,dwc-qos-ethernet-4.10"; 95 reg = <0x02490000 0x10000>; 96 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 98 <&bpmp TEGRA194_CLK_EQOS_AXI>, 99 <&bpmp TEGRA194_CLK_EQOS_RX>, 100 <&bpmp TEGRA194_CLK_EQOS_TX>, 101 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 102 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 103 resets = <&bpmp TEGRA194_RESET_EQOS>; 104 reset-names = "eqos"; 105 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 106 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 107 interconnect-names = "dma-mem", "write"; 108 iommus = <&smmu TEGRA194_SID_EQOS>; 109 status = "disabled"; 110 111 snps,write-requests = <1>; 112 snps,read-requests = <3>; 113 snps,burst-map = <0x7>; 114 snps,txpbl = <16>; 115 snps,rxpbl = <8>; 116 }; 117 118 gpcdma: dma-controller@2600000 { 119 compatible = "nvidia,tegra194-gpcdma", 120 "nvidia,tegra186-gpcdma"; 121 reg = <0x2600000 0x210000>; 122 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 123 reset-names = "gpcdma"; 124 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 155 #dma-cells = <1>; 156 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 157 dma-coherent; 158 status = "okay"; 159 }; 160 161 aconnect@2900000 { 162 compatible = "nvidia,tegra194-aconnect", 163 "nvidia,tegra210-aconnect"; 164 clocks = <&bpmp TEGRA194_CLK_APE>, 165 <&bpmp TEGRA194_CLK_APB2APE>; 166 clock-names = "ape", "apb2ape"; 167 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 168 #address-cells = <1>; 169 #size-cells = <1>; 170 ranges = <0x02900000 0x02900000 0x200000>; 171 status = "disabled"; 172 173 adma: dma-controller@2930000 { 174 compatible = "nvidia,tegra194-adma", 175 "nvidia,tegra186-adma"; 176 reg = <0x02930000 0x20000>; 177 interrupt-parent = <&agic>; 178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #dma-cells = <1>; 211 clocks = <&bpmp TEGRA194_CLK_AHUB>; 212 clock-names = "d_audio"; 213 status = "disabled"; 214 }; 215 216 agic: interrupt-controller@2a40000 { 217 compatible = "nvidia,tegra194-agic", 218 "nvidia,tegra210-agic"; 219 #interrupt-cells = <3>; 220 interrupt-controller; 221 reg = <0x02a41000 0x1000>, 222 <0x02a42000 0x2000>; 223 interrupts = <GIC_SPI 145 224 (GIC_CPU_MASK_SIMPLE(4) | 225 IRQ_TYPE_LEVEL_HIGH)>; 226 clocks = <&bpmp TEGRA194_CLK_APE>; 227 clock-names = "clk"; 228 status = "disabled"; 229 }; 230 231 tegra_ahub: ahub@2900800 { 232 compatible = "nvidia,tegra194-ahub", 233 "nvidia,tegra186-ahub"; 234 reg = <0x02900800 0x800>; 235 clocks = <&bpmp TEGRA194_CLK_AHUB>; 236 clock-names = "ahub"; 237 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 238 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 239 #address-cells = <1>; 240 #size-cells = <1>; 241 ranges = <0x02900800 0x02900800 0x11800>; 242 status = "disabled"; 243 244 tegra_admaif: admaif@290f000 { 245 compatible = "nvidia,tegra194-admaif", 246 "nvidia,tegra186-admaif"; 247 reg = <0x0290f000 0x1000>; 248 dmas = <&adma 1>, <&adma 1>, 249 <&adma 2>, <&adma 2>, 250 <&adma 3>, <&adma 3>, 251 <&adma 4>, <&adma 4>, 252 <&adma 5>, <&adma 5>, 253 <&adma 6>, <&adma 6>, 254 <&adma 7>, <&adma 7>, 255 <&adma 8>, <&adma 8>, 256 <&adma 9>, <&adma 9>, 257 <&adma 10>, <&adma 10>, 258 <&adma 11>, <&adma 11>, 259 <&adma 12>, <&adma 12>, 260 <&adma 13>, <&adma 13>, 261 <&adma 14>, <&adma 14>, 262 <&adma 15>, <&adma 15>, 263 <&adma 16>, <&adma 16>, 264 <&adma 17>, <&adma 17>, 265 <&adma 18>, <&adma 18>, 266 <&adma 19>, <&adma 19>, 267 <&adma 20>, <&adma 20>; 268 dma-names = "rx1", "tx1", 269 "rx2", "tx2", 270 "rx3", "tx3", 271 "rx4", "tx4", 272 "rx5", "tx5", 273 "rx6", "tx6", 274 "rx7", "tx7", 275 "rx8", "tx8", 276 "rx9", "tx9", 277 "rx10", "tx10", 278 "rx11", "tx11", 279 "rx12", "tx12", 280 "rx13", "tx13", 281 "rx14", "tx14", 282 "rx15", "tx15", 283 "rx16", "tx16", 284 "rx17", "tx17", 285 "rx18", "tx18", 286 "rx19", "tx19", 287 "rx20", "tx20"; 288 status = "disabled"; 289 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 290 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 291 interconnect-names = "dma-mem", "write"; 292 iommus = <&smmu TEGRA194_SID_APE>; 293 }; 294 295 tegra_i2s1: i2s@2901000 { 296 compatible = "nvidia,tegra194-i2s", 297 "nvidia,tegra210-i2s"; 298 reg = <0x2901000 0x100>; 299 clocks = <&bpmp TEGRA194_CLK_I2S1>, 300 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 301 clock-names = "i2s", "sync_input"; 302 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 303 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 304 assigned-clock-rates = <1536000>; 305 sound-name-prefix = "I2S1"; 306 status = "disabled"; 307 }; 308 309 tegra_i2s2: i2s@2901100 { 310 compatible = "nvidia,tegra194-i2s", 311 "nvidia,tegra210-i2s"; 312 reg = <0x2901100 0x100>; 313 clocks = <&bpmp TEGRA194_CLK_I2S2>, 314 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 315 clock-names = "i2s", "sync_input"; 316 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 317 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 318 assigned-clock-rates = <1536000>; 319 sound-name-prefix = "I2S2"; 320 status = "disabled"; 321 }; 322 323 tegra_i2s3: i2s@2901200 { 324 compatible = "nvidia,tegra194-i2s", 325 "nvidia,tegra210-i2s"; 326 reg = <0x2901200 0x100>; 327 clocks = <&bpmp TEGRA194_CLK_I2S3>, 328 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 329 clock-names = "i2s", "sync_input"; 330 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 331 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 332 assigned-clock-rates = <1536000>; 333 sound-name-prefix = "I2S3"; 334 status = "disabled"; 335 }; 336 337 tegra_i2s4: i2s@2901300 { 338 compatible = "nvidia,tegra194-i2s", 339 "nvidia,tegra210-i2s"; 340 reg = <0x2901300 0x100>; 341 clocks = <&bpmp TEGRA194_CLK_I2S4>, 342 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 343 clock-names = "i2s", "sync_input"; 344 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 345 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 346 assigned-clock-rates = <1536000>; 347 sound-name-prefix = "I2S4"; 348 status = "disabled"; 349 }; 350 351 tegra_i2s5: i2s@2901400 { 352 compatible = "nvidia,tegra194-i2s", 353 "nvidia,tegra210-i2s"; 354 reg = <0x2901400 0x100>; 355 clocks = <&bpmp TEGRA194_CLK_I2S5>, 356 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 357 clock-names = "i2s", "sync_input"; 358 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 359 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 360 assigned-clock-rates = <1536000>; 361 sound-name-prefix = "I2S5"; 362 status = "disabled"; 363 }; 364 365 tegra_i2s6: i2s@2901500 { 366 compatible = "nvidia,tegra194-i2s", 367 "nvidia,tegra210-i2s"; 368 reg = <0x2901500 0x100>; 369 clocks = <&bpmp TEGRA194_CLK_I2S6>, 370 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 371 clock-names = "i2s", "sync_input"; 372 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 373 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 374 assigned-clock-rates = <1536000>; 375 sound-name-prefix = "I2S6"; 376 status = "disabled"; 377 }; 378 379 tegra_dmic1: dmic@2904000 { 380 compatible = "nvidia,tegra194-dmic", 381 "nvidia,tegra210-dmic"; 382 reg = <0x2904000 0x100>; 383 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 384 clock-names = "dmic"; 385 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 386 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 387 assigned-clock-rates = <3072000>; 388 sound-name-prefix = "DMIC1"; 389 status = "disabled"; 390 }; 391 392 tegra_dmic2: dmic@2904100 { 393 compatible = "nvidia,tegra194-dmic", 394 "nvidia,tegra210-dmic"; 395 reg = <0x2904100 0x100>; 396 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 397 clock-names = "dmic"; 398 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 399 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 400 assigned-clock-rates = <3072000>; 401 sound-name-prefix = "DMIC2"; 402 status = "disabled"; 403 }; 404 405 tegra_dmic3: dmic@2904200 { 406 compatible = "nvidia,tegra194-dmic", 407 "nvidia,tegra210-dmic"; 408 reg = <0x2904200 0x100>; 409 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 410 clock-names = "dmic"; 411 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 412 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 413 assigned-clock-rates = <3072000>; 414 sound-name-prefix = "DMIC3"; 415 status = "disabled"; 416 }; 417 418 tegra_dmic4: dmic@2904300 { 419 compatible = "nvidia,tegra194-dmic", 420 "nvidia,tegra210-dmic"; 421 reg = <0x2904300 0x100>; 422 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 423 clock-names = "dmic"; 424 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 425 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 426 assigned-clock-rates = <3072000>; 427 sound-name-prefix = "DMIC4"; 428 status = "disabled"; 429 }; 430 431 tegra_dspk1: dspk@2905000 { 432 compatible = "nvidia,tegra194-dspk", 433 "nvidia,tegra186-dspk"; 434 reg = <0x2905000 0x100>; 435 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 436 clock-names = "dspk"; 437 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 438 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 439 assigned-clock-rates = <12288000>; 440 sound-name-prefix = "DSPK1"; 441 status = "disabled"; 442 }; 443 444 tegra_dspk2: dspk@2905100 { 445 compatible = "nvidia,tegra194-dspk", 446 "nvidia,tegra186-dspk"; 447 reg = <0x2905100 0x100>; 448 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 449 clock-names = "dspk"; 450 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 451 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 452 assigned-clock-rates = <12288000>; 453 sound-name-prefix = "DSPK2"; 454 status = "disabled"; 455 }; 456 457 tegra_sfc1: sfc@2902000 { 458 compatible = "nvidia,tegra194-sfc", 459 "nvidia,tegra210-sfc"; 460 reg = <0x2902000 0x200>; 461 sound-name-prefix = "SFC1"; 462 status = "disabled"; 463 }; 464 465 tegra_sfc2: sfc@2902200 { 466 compatible = "nvidia,tegra194-sfc", 467 "nvidia,tegra210-sfc"; 468 reg = <0x2902200 0x200>; 469 sound-name-prefix = "SFC2"; 470 status = "disabled"; 471 }; 472 473 tegra_sfc3: sfc@2902400 { 474 compatible = "nvidia,tegra194-sfc", 475 "nvidia,tegra210-sfc"; 476 reg = <0x2902400 0x200>; 477 sound-name-prefix = "SFC3"; 478 status = "disabled"; 479 }; 480 481 tegra_sfc4: sfc@2902600 { 482 compatible = "nvidia,tegra194-sfc", 483 "nvidia,tegra210-sfc"; 484 reg = <0x2902600 0x200>; 485 sound-name-prefix = "SFC4"; 486 status = "disabled"; 487 }; 488 489 tegra_mvc1: mvc@290a000 { 490 compatible = "nvidia,tegra194-mvc", 491 "nvidia,tegra210-mvc"; 492 reg = <0x290a000 0x200>; 493 sound-name-prefix = "MVC1"; 494 status = "disabled"; 495 }; 496 497 tegra_mvc2: mvc@290a200 { 498 compatible = "nvidia,tegra194-mvc", 499 "nvidia,tegra210-mvc"; 500 reg = <0x290a200 0x200>; 501 sound-name-prefix = "MVC2"; 502 status = "disabled"; 503 }; 504 505 tegra_amx1: amx@2903000 { 506 compatible = "nvidia,tegra194-amx"; 507 reg = <0x2903000 0x100>; 508 sound-name-prefix = "AMX1"; 509 status = "disabled"; 510 }; 511 512 tegra_amx2: amx@2903100 { 513 compatible = "nvidia,tegra194-amx"; 514 reg = <0x2903100 0x100>; 515 sound-name-prefix = "AMX2"; 516 status = "disabled"; 517 }; 518 519 tegra_amx3: amx@2903200 { 520 compatible = "nvidia,tegra194-amx"; 521 reg = <0x2903200 0x100>; 522 sound-name-prefix = "AMX3"; 523 status = "disabled"; 524 }; 525 526 tegra_amx4: amx@2903300 { 527 compatible = "nvidia,tegra194-amx"; 528 reg = <0x2903300 0x100>; 529 sound-name-prefix = "AMX4"; 530 status = "disabled"; 531 }; 532 533 tegra_adx1: adx@2903800 { 534 compatible = "nvidia,tegra194-adx", 535 "nvidia,tegra210-adx"; 536 reg = <0x2903800 0x100>; 537 sound-name-prefix = "ADX1"; 538 status = "disabled"; 539 }; 540 541 tegra_adx2: adx@2903900 { 542 compatible = "nvidia,tegra194-adx", 543 "nvidia,tegra210-adx"; 544 reg = <0x2903900 0x100>; 545 sound-name-prefix = "ADX2"; 546 status = "disabled"; 547 }; 548 549 tegra_adx3: adx@2903a00 { 550 compatible = "nvidia,tegra194-adx", 551 "nvidia,tegra210-adx"; 552 reg = <0x2903a00 0x100>; 553 sound-name-prefix = "ADX3"; 554 status = "disabled"; 555 }; 556 557 tegra_adx4: adx@2903b00 { 558 compatible = "nvidia,tegra194-adx", 559 "nvidia,tegra210-adx"; 560 reg = <0x2903b00 0x100>; 561 sound-name-prefix = "ADX4"; 562 status = "disabled"; 563 }; 564 565 tegra_amixer: amixer@290bb00 { 566 compatible = "nvidia,tegra194-amixer", 567 "nvidia,tegra210-amixer"; 568 reg = <0x290bb00 0x800>; 569 sound-name-prefix = "MIXER1"; 570 status = "disabled"; 571 }; 572 573 tegra_asrc: asrc@2910000 { 574 compatible = "nvidia,tegra194-asrc", 575 "nvidia,tegra186-asrc"; 576 reg = <0x2910000 0x2000>; 577 sound-name-prefix = "ASRC1"; 578 status = "disabled"; 579 }; 580 }; 581 }; 582 583 pinmux: pinmux@2430000 { 584 compatible = "nvidia,tegra194-pinmux"; 585 reg = <0x2430000 0x17000>, 586 <0xc300000 0x4000>; 587 588 status = "okay"; 589 590 pex_rst_c5_out_state: pex_rst_c5_out { 591 pex_rst { 592 nvidia,pins = "pex_l5_rst_n_pgg1"; 593 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 594 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 595 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 596 nvidia,tristate = <TEGRA_PIN_DISABLE>; 597 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 598 }; 599 }; 600 601 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 602 clkreq { 603 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 604 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 605 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 606 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 607 nvidia,tristate = <TEGRA_PIN_DISABLE>; 608 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 609 }; 610 }; 611 }; 612 613 mc: memory-controller@2c00000 { 614 compatible = "nvidia,tegra194-mc"; 615 reg = <0x02c00000 0x100000>, 616 <0x02b80000 0x040000>, 617 <0x01700000 0x100000>; 618 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 619 #interconnect-cells = <1>; 620 status = "disabled"; 621 622 #address-cells = <2>; 623 #size-cells = <2>; 624 625 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 626 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 627 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 628 629 /* 630 * Bit 39 of addresses passing through the memory 631 * controller selects the XBAR format used when memory 632 * is accessed. This is used to transparently access 633 * memory in the XBAR format used by the discrete GPU 634 * (bit 39 set) or Tegra (bit 39 clear). 635 * 636 * As a consequence, the operating system must ensure 637 * that bit 39 is never used implicitly, for example 638 * via an I/O virtual address mapping of an IOMMU. If 639 * devices require access to the XBAR switch, their 640 * drivers must set this bit explicitly. 641 * 642 * Limit the DMA range for memory clients to [38:0]. 643 */ 644 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 645 646 emc: external-memory-controller@2c60000 { 647 compatible = "nvidia,tegra194-emc"; 648 reg = <0x0 0x02c60000 0x0 0x90000>, 649 <0x0 0x01780000 0x0 0x80000>; 650 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&bpmp TEGRA194_CLK_EMC>; 652 clock-names = "emc"; 653 654 #interconnect-cells = <0>; 655 656 nvidia,bpmp = <&bpmp>; 657 }; 658 }; 659 660 uarta: serial@3100000 { 661 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 662 reg = <0x03100000 0x40>; 663 reg-shift = <2>; 664 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&bpmp TEGRA194_CLK_UARTA>; 666 clock-names = "serial"; 667 resets = <&bpmp TEGRA194_RESET_UARTA>; 668 reset-names = "serial"; 669 status = "disabled"; 670 }; 671 672 uartb: serial@3110000 { 673 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 674 reg = <0x03110000 0x40>; 675 reg-shift = <2>; 676 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&bpmp TEGRA194_CLK_UARTB>; 678 clock-names = "serial"; 679 resets = <&bpmp TEGRA194_RESET_UARTB>; 680 reset-names = "serial"; 681 status = "disabled"; 682 }; 683 684 uartd: serial@3130000 { 685 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 686 reg = <0x03130000 0x40>; 687 reg-shift = <2>; 688 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&bpmp TEGRA194_CLK_UARTD>; 690 clock-names = "serial"; 691 resets = <&bpmp TEGRA194_RESET_UARTD>; 692 reset-names = "serial"; 693 status = "disabled"; 694 }; 695 696 uarte: serial@3140000 { 697 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 698 reg = <0x03140000 0x40>; 699 reg-shift = <2>; 700 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&bpmp TEGRA194_CLK_UARTE>; 702 clock-names = "serial"; 703 resets = <&bpmp TEGRA194_RESET_UARTE>; 704 reset-names = "serial"; 705 status = "disabled"; 706 }; 707 708 uartf: serial@3150000 { 709 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 710 reg = <0x03150000 0x40>; 711 reg-shift = <2>; 712 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&bpmp TEGRA194_CLK_UARTF>; 714 clock-names = "serial"; 715 resets = <&bpmp TEGRA194_RESET_UARTF>; 716 reset-names = "serial"; 717 status = "disabled"; 718 }; 719 720 gen1_i2c: i2c@3160000 { 721 compatible = "nvidia,tegra194-i2c"; 722 reg = <0x03160000 0x10000>; 723 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 clocks = <&bpmp TEGRA194_CLK_I2C1>; 727 clock-names = "div-clk"; 728 resets = <&bpmp TEGRA194_RESET_I2C1>; 729 reset-names = "i2c"; 730 status = "disabled"; 731 }; 732 733 uarth: serial@3170000 { 734 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 735 reg = <0x03170000 0x40>; 736 reg-shift = <2>; 737 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&bpmp TEGRA194_CLK_UARTH>; 739 clock-names = "serial"; 740 resets = <&bpmp TEGRA194_RESET_UARTH>; 741 reset-names = "serial"; 742 status = "disabled"; 743 }; 744 745 cam_i2c: i2c@3180000 { 746 compatible = "nvidia,tegra194-i2c"; 747 reg = <0x03180000 0x10000>; 748 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 clocks = <&bpmp TEGRA194_CLK_I2C3>; 752 clock-names = "div-clk"; 753 resets = <&bpmp TEGRA194_RESET_I2C3>; 754 reset-names = "i2c"; 755 status = "disabled"; 756 }; 757 758 /* shares pads with dpaux1 */ 759 dp_aux_ch1_i2c: i2c@3190000 { 760 compatible = "nvidia,tegra194-i2c"; 761 reg = <0x03190000 0x10000>; 762 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 clocks = <&bpmp TEGRA194_CLK_I2C4>; 766 clock-names = "div-clk"; 767 resets = <&bpmp TEGRA194_RESET_I2C4>; 768 reset-names = "i2c"; 769 pinctrl-0 = <&state_dpaux1_i2c>; 770 pinctrl-1 = <&state_dpaux1_off>; 771 pinctrl-names = "default", "idle"; 772 status = "disabled"; 773 }; 774 775 /* shares pads with dpaux0 */ 776 dp_aux_ch0_i2c: i2c@31b0000 { 777 compatible = "nvidia,tegra194-i2c"; 778 reg = <0x031b0000 0x10000>; 779 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 clocks = <&bpmp TEGRA194_CLK_I2C6>; 783 clock-names = "div-clk"; 784 resets = <&bpmp TEGRA194_RESET_I2C6>; 785 reset-names = "i2c"; 786 pinctrl-0 = <&state_dpaux0_i2c>; 787 pinctrl-1 = <&state_dpaux0_off>; 788 pinctrl-names = "default", "idle"; 789 status = "disabled"; 790 }; 791 792 /* shares pads with dpaux2 */ 793 dp_aux_ch2_i2c: i2c@31c0000 { 794 compatible = "nvidia,tegra194-i2c"; 795 reg = <0x031c0000 0x10000>; 796 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 797 #address-cells = <1>; 798 #size-cells = <0>; 799 clocks = <&bpmp TEGRA194_CLK_I2C7>; 800 clock-names = "div-clk"; 801 resets = <&bpmp TEGRA194_RESET_I2C7>; 802 reset-names = "i2c"; 803 pinctrl-0 = <&state_dpaux2_i2c>; 804 pinctrl-1 = <&state_dpaux2_off>; 805 pinctrl-names = "default", "idle"; 806 status = "disabled"; 807 }; 808 809 /* shares pads with dpaux3 */ 810 dp_aux_ch3_i2c: i2c@31e0000 { 811 compatible = "nvidia,tegra194-i2c"; 812 reg = <0x031e0000 0x10000>; 813 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 clocks = <&bpmp TEGRA194_CLK_I2C9>; 817 clock-names = "div-clk"; 818 resets = <&bpmp TEGRA194_RESET_I2C9>; 819 reset-names = "i2c"; 820 pinctrl-0 = <&state_dpaux3_i2c>; 821 pinctrl-1 = <&state_dpaux3_off>; 822 pinctrl-names = "default", "idle"; 823 status = "disabled"; 824 }; 825 826 spi@3270000 { 827 compatible = "nvidia,tegra194-qspi"; 828 reg = <0x3270000 0x1000>; 829 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 833 <&bpmp TEGRA194_CLK_QSPI0_PM>; 834 clock-names = "qspi", "qspi_out"; 835 resets = <&bpmp TEGRA194_RESET_QSPI0>; 836 reset-names = "qspi"; 837 status = "disabled"; 838 }; 839 840 spi@3300000 { 841 compatible = "nvidia,tegra194-qspi"; 842 reg = <0x3300000 0x1000>; 843 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 847 <&bpmp TEGRA194_CLK_QSPI1_PM>; 848 clock-names = "qspi", "qspi_out"; 849 resets = <&bpmp TEGRA194_RESET_QSPI1>; 850 reset-names = "qspi"; 851 status = "disabled"; 852 }; 853 854 pwm1: pwm@3280000 { 855 compatible = "nvidia,tegra194-pwm", 856 "nvidia,tegra186-pwm"; 857 reg = <0x3280000 0x10000>; 858 clocks = <&bpmp TEGRA194_CLK_PWM1>; 859 clock-names = "pwm"; 860 resets = <&bpmp TEGRA194_RESET_PWM1>; 861 reset-names = "pwm"; 862 status = "disabled"; 863 #pwm-cells = <2>; 864 }; 865 866 pwm2: pwm@3290000 { 867 compatible = "nvidia,tegra194-pwm", 868 "nvidia,tegra186-pwm"; 869 reg = <0x3290000 0x10000>; 870 clocks = <&bpmp TEGRA194_CLK_PWM2>; 871 clock-names = "pwm"; 872 resets = <&bpmp TEGRA194_RESET_PWM2>; 873 reset-names = "pwm"; 874 status = "disabled"; 875 #pwm-cells = <2>; 876 }; 877 878 pwm3: pwm@32a0000 { 879 compatible = "nvidia,tegra194-pwm", 880 "nvidia,tegra186-pwm"; 881 reg = <0x32a0000 0x10000>; 882 clocks = <&bpmp TEGRA194_CLK_PWM3>; 883 clock-names = "pwm"; 884 resets = <&bpmp TEGRA194_RESET_PWM3>; 885 reset-names = "pwm"; 886 status = "disabled"; 887 #pwm-cells = <2>; 888 }; 889 890 pwm5: pwm@32c0000 { 891 compatible = "nvidia,tegra194-pwm", 892 "nvidia,tegra186-pwm"; 893 reg = <0x32c0000 0x10000>; 894 clocks = <&bpmp TEGRA194_CLK_PWM5>; 895 clock-names = "pwm"; 896 resets = <&bpmp TEGRA194_RESET_PWM5>; 897 reset-names = "pwm"; 898 status = "disabled"; 899 #pwm-cells = <2>; 900 }; 901 902 pwm6: pwm@32d0000 { 903 compatible = "nvidia,tegra194-pwm", 904 "nvidia,tegra186-pwm"; 905 reg = <0x32d0000 0x10000>; 906 clocks = <&bpmp TEGRA194_CLK_PWM6>; 907 clock-names = "pwm"; 908 resets = <&bpmp TEGRA194_RESET_PWM6>; 909 reset-names = "pwm"; 910 status = "disabled"; 911 #pwm-cells = <2>; 912 }; 913 914 pwm7: pwm@32e0000 { 915 compatible = "nvidia,tegra194-pwm", 916 "nvidia,tegra186-pwm"; 917 reg = <0x32e0000 0x10000>; 918 clocks = <&bpmp TEGRA194_CLK_PWM7>; 919 clock-names = "pwm"; 920 resets = <&bpmp TEGRA194_RESET_PWM7>; 921 reset-names = "pwm"; 922 status = "disabled"; 923 #pwm-cells = <2>; 924 }; 925 926 pwm8: pwm@32f0000 { 927 compatible = "nvidia,tegra194-pwm", 928 "nvidia,tegra186-pwm"; 929 reg = <0x32f0000 0x10000>; 930 clocks = <&bpmp TEGRA194_CLK_PWM8>; 931 clock-names = "pwm"; 932 resets = <&bpmp TEGRA194_RESET_PWM8>; 933 reset-names = "pwm"; 934 status = "disabled"; 935 #pwm-cells = <2>; 936 }; 937 938 sdmmc1: mmc@3400000 { 939 compatible = "nvidia,tegra194-sdhci"; 940 reg = <0x03400000 0x10000>; 941 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 942 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 943 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 944 clock-names = "sdhci", "tmclk"; 945 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 946 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 947 assigned-clock-parents = 948 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 949 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 950 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 951 reset-names = "sdhci"; 952 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 953 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 954 interconnect-names = "dma-mem", "write"; 955 iommus = <&smmu TEGRA194_SID_SDMMC1>; 956 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 957 pinctrl-0 = <&sdmmc1_3v3>; 958 pinctrl-1 = <&sdmmc1_1v8>; 959 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 960 <0x07>; 961 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 962 <0x07>; 963 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 964 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 965 <0x07>; 966 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 967 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 968 nvidia,default-tap = <0x9>; 969 nvidia,default-trim = <0x5>; 970 sd-uhs-sdr25; 971 sd-uhs-sdr50; 972 sd-uhs-ddr50; 973 sd-uhs-sdr104; 974 status = "disabled"; 975 }; 976 977 sdmmc3: mmc@3440000 { 978 compatible = "nvidia,tegra194-sdhci"; 979 reg = <0x03440000 0x10000>; 980 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 982 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 983 clock-names = "sdhci", "tmclk"; 984 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 985 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 986 assigned-clock-parents = 987 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 988 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 989 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 990 reset-names = "sdhci"; 991 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 992 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 993 interconnect-names = "dma-mem", "write"; 994 iommus = <&smmu TEGRA194_SID_SDMMC3>; 995 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 996 pinctrl-0 = <&sdmmc3_3v3>; 997 pinctrl-1 = <&sdmmc3_1v8>; 998 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 999 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1000 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1001 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1002 <0x07>; 1003 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1004 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1005 <0x07>; 1006 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1007 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1008 nvidia,default-tap = <0x9>; 1009 nvidia,default-trim = <0x5>; 1010 sd-uhs-sdr25; 1011 sd-uhs-sdr50; 1012 sd-uhs-ddr50; 1013 sd-uhs-sdr104; 1014 status = "disabled"; 1015 }; 1016 1017 sdmmc4: mmc@3460000 { 1018 compatible = "nvidia,tegra194-sdhci"; 1019 reg = <0x03460000 0x10000>; 1020 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1022 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1023 clock-names = "sdhci", "tmclk"; 1024 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1025 <&bpmp TEGRA194_CLK_PLLC4>; 1026 assigned-clock-parents = 1027 <&bpmp TEGRA194_CLK_PLLC4>; 1028 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1029 reset-names = "sdhci"; 1030 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1031 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1032 interconnect-names = "dma-mem", "write"; 1033 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1034 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1035 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1036 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1037 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1038 <0x0a>; 1039 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1040 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1041 <0x0a>; 1042 nvidia,default-tap = <0x8>; 1043 nvidia,default-trim = <0x14>; 1044 nvidia,dqs-trim = <40>; 1045 cap-mmc-highspeed; 1046 mmc-ddr-1_8v; 1047 mmc-hs200-1_8v; 1048 mmc-hs400-1_8v; 1049 mmc-hs400-enhanced-strobe; 1050 supports-cqe; 1051 status = "disabled"; 1052 }; 1053 1054 hda@3510000 { 1055 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 1056 reg = <0x3510000 0x10000>; 1057 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1058 clocks = <&bpmp TEGRA194_CLK_HDA>, 1059 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1060 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1061 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1062 resets = <&bpmp TEGRA194_RESET_HDA>, 1063 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1064 reset-names = "hda", "hda2hdmi"; 1065 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1066 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1067 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1068 interconnect-names = "dma-mem", "write"; 1069 iommus = <&smmu TEGRA194_SID_HDA>; 1070 status = "disabled"; 1071 }; 1072 1073 xusb_padctl: padctl@3520000 { 1074 compatible = "nvidia,tegra194-xusb-padctl"; 1075 reg = <0x03520000 0x1000>, 1076 <0x03540000 0x1000>; 1077 reg-names = "padctl", "ao"; 1078 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1079 1080 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1081 reset-names = "padctl"; 1082 1083 status = "disabled"; 1084 1085 pads { 1086 usb2 { 1087 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1088 clock-names = "trk"; 1089 1090 lanes { 1091 usb2-0 { 1092 nvidia,function = "xusb"; 1093 status = "disabled"; 1094 #phy-cells = <0>; 1095 }; 1096 1097 usb2-1 { 1098 nvidia,function = "xusb"; 1099 status = "disabled"; 1100 #phy-cells = <0>; 1101 }; 1102 1103 usb2-2 { 1104 nvidia,function = "xusb"; 1105 status = "disabled"; 1106 #phy-cells = <0>; 1107 }; 1108 1109 usb2-3 { 1110 nvidia,function = "xusb"; 1111 status = "disabled"; 1112 #phy-cells = <0>; 1113 }; 1114 }; 1115 }; 1116 1117 usb3 { 1118 lanes { 1119 usb3-0 { 1120 nvidia,function = "xusb"; 1121 status = "disabled"; 1122 #phy-cells = <0>; 1123 }; 1124 1125 usb3-1 { 1126 nvidia,function = "xusb"; 1127 status = "disabled"; 1128 #phy-cells = <0>; 1129 }; 1130 1131 usb3-2 { 1132 nvidia,function = "xusb"; 1133 status = "disabled"; 1134 #phy-cells = <0>; 1135 }; 1136 1137 usb3-3 { 1138 nvidia,function = "xusb"; 1139 status = "disabled"; 1140 #phy-cells = <0>; 1141 }; 1142 }; 1143 }; 1144 }; 1145 1146 ports { 1147 usb2-0 { 1148 status = "disabled"; 1149 }; 1150 1151 usb2-1 { 1152 status = "disabled"; 1153 }; 1154 1155 usb2-2 { 1156 status = "disabled"; 1157 }; 1158 1159 usb2-3 { 1160 status = "disabled"; 1161 }; 1162 1163 usb3-0 { 1164 status = "disabled"; 1165 }; 1166 1167 usb3-1 { 1168 status = "disabled"; 1169 }; 1170 1171 usb3-2 { 1172 status = "disabled"; 1173 }; 1174 1175 usb3-3 { 1176 status = "disabled"; 1177 }; 1178 }; 1179 }; 1180 1181 usb@3550000 { 1182 compatible = "nvidia,tegra194-xudc"; 1183 reg = <0x03550000 0x8000>, 1184 <0x03558000 0x1000>; 1185 reg-names = "base", "fpci"; 1186 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1187 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1188 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1189 <&bpmp TEGRA194_CLK_XUSB_SS>, 1190 <&bpmp TEGRA194_CLK_XUSB_FS>; 1191 clock-names = "dev", "ss", "ss_src", "fs_src"; 1192 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1193 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1194 interconnect-names = "dma-mem", "write"; 1195 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1196 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1197 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1198 power-domain-names = "dev", "ss"; 1199 nvidia,xusb-padctl = <&xusb_padctl>; 1200 status = "disabled"; 1201 }; 1202 1203 usb@3610000 { 1204 compatible = "nvidia,tegra194-xusb"; 1205 reg = <0x03610000 0x40000>, 1206 <0x03600000 0x10000>; 1207 reg-names = "hcd", "fpci"; 1208 1209 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1211 1212 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1213 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1214 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1215 <&bpmp TEGRA194_CLK_XUSB_SS>, 1216 <&bpmp TEGRA194_CLK_CLK_M>, 1217 <&bpmp TEGRA194_CLK_XUSB_FS>, 1218 <&bpmp TEGRA194_CLK_UTMIPLL>, 1219 <&bpmp TEGRA194_CLK_CLK_M>, 1220 <&bpmp TEGRA194_CLK_PLLE>; 1221 clock-names = "xusb_host", "xusb_falcon_src", 1222 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1223 "xusb_fs_src", "pll_u_480m", "clk_m", 1224 "pll_e"; 1225 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1226 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1227 interconnect-names = "dma-mem", "write"; 1228 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1229 1230 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1231 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1232 power-domain-names = "xusb_host", "xusb_ss"; 1233 1234 nvidia,xusb-padctl = <&xusb_padctl>; 1235 status = "disabled"; 1236 }; 1237 1238 fuse@3820000 { 1239 compatible = "nvidia,tegra194-efuse"; 1240 reg = <0x03820000 0x10000>; 1241 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1242 clock-names = "fuse"; 1243 }; 1244 1245 gic: interrupt-controller@3881000 { 1246 compatible = "arm,gic-400"; 1247 #interrupt-cells = <3>; 1248 interrupt-controller; 1249 reg = <0x03881000 0x1000>, 1250 <0x03882000 0x2000>, 1251 <0x03884000 0x2000>, 1252 <0x03886000 0x2000>; 1253 interrupts = <GIC_PPI 9 1254 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1255 interrupt-parent = <&gic>; 1256 }; 1257 1258 cec@3960000 { 1259 compatible = "nvidia,tegra194-cec"; 1260 reg = <0x03960000 0x10000>; 1261 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1262 clocks = <&bpmp TEGRA194_CLK_CEC>; 1263 clock-names = "cec"; 1264 status = "disabled"; 1265 }; 1266 1267 hsp_top0: hsp@3c00000 { 1268 compatible = "nvidia,tegra194-hsp"; 1269 reg = <0x03c00000 0xa0000>; 1270 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1279 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1280 "shared3", "shared4", "shared5", "shared6", 1281 "shared7"; 1282 #mbox-cells = <2>; 1283 }; 1284 1285 p2u_hsio_0: phy@3e10000 { 1286 compatible = "nvidia,tegra194-p2u"; 1287 reg = <0x03e10000 0x10000>; 1288 reg-names = "ctl"; 1289 1290 #phy-cells = <0>; 1291 }; 1292 1293 p2u_hsio_1: phy@3e20000 { 1294 compatible = "nvidia,tegra194-p2u"; 1295 reg = <0x03e20000 0x10000>; 1296 reg-names = "ctl"; 1297 1298 #phy-cells = <0>; 1299 }; 1300 1301 p2u_hsio_2: phy@3e30000 { 1302 compatible = "nvidia,tegra194-p2u"; 1303 reg = <0x03e30000 0x10000>; 1304 reg-names = "ctl"; 1305 1306 #phy-cells = <0>; 1307 }; 1308 1309 p2u_hsio_3: phy@3e40000 { 1310 compatible = "nvidia,tegra194-p2u"; 1311 reg = <0x03e40000 0x10000>; 1312 reg-names = "ctl"; 1313 1314 #phy-cells = <0>; 1315 }; 1316 1317 p2u_hsio_4: phy@3e50000 { 1318 compatible = "nvidia,tegra194-p2u"; 1319 reg = <0x03e50000 0x10000>; 1320 reg-names = "ctl"; 1321 1322 #phy-cells = <0>; 1323 }; 1324 1325 p2u_hsio_5: phy@3e60000 { 1326 compatible = "nvidia,tegra194-p2u"; 1327 reg = <0x03e60000 0x10000>; 1328 reg-names = "ctl"; 1329 1330 #phy-cells = <0>; 1331 }; 1332 1333 p2u_hsio_6: phy@3e70000 { 1334 compatible = "nvidia,tegra194-p2u"; 1335 reg = <0x03e70000 0x10000>; 1336 reg-names = "ctl"; 1337 1338 #phy-cells = <0>; 1339 }; 1340 1341 p2u_hsio_7: phy@3e80000 { 1342 compatible = "nvidia,tegra194-p2u"; 1343 reg = <0x03e80000 0x10000>; 1344 reg-names = "ctl"; 1345 1346 #phy-cells = <0>; 1347 }; 1348 1349 p2u_hsio_8: phy@3e90000 { 1350 compatible = "nvidia,tegra194-p2u"; 1351 reg = <0x03e90000 0x10000>; 1352 reg-names = "ctl"; 1353 1354 #phy-cells = <0>; 1355 }; 1356 1357 p2u_hsio_9: phy@3ea0000 { 1358 compatible = "nvidia,tegra194-p2u"; 1359 reg = <0x03ea0000 0x10000>; 1360 reg-names = "ctl"; 1361 1362 #phy-cells = <0>; 1363 }; 1364 1365 p2u_nvhs_0: phy@3eb0000 { 1366 compatible = "nvidia,tegra194-p2u"; 1367 reg = <0x03eb0000 0x10000>; 1368 reg-names = "ctl"; 1369 1370 #phy-cells = <0>; 1371 }; 1372 1373 p2u_nvhs_1: phy@3ec0000 { 1374 compatible = "nvidia,tegra194-p2u"; 1375 reg = <0x03ec0000 0x10000>; 1376 reg-names = "ctl"; 1377 1378 #phy-cells = <0>; 1379 }; 1380 1381 p2u_nvhs_2: phy@3ed0000 { 1382 compatible = "nvidia,tegra194-p2u"; 1383 reg = <0x03ed0000 0x10000>; 1384 reg-names = "ctl"; 1385 1386 #phy-cells = <0>; 1387 }; 1388 1389 p2u_nvhs_3: phy@3ee0000 { 1390 compatible = "nvidia,tegra194-p2u"; 1391 reg = <0x03ee0000 0x10000>; 1392 reg-names = "ctl"; 1393 1394 #phy-cells = <0>; 1395 }; 1396 1397 p2u_nvhs_4: phy@3ef0000 { 1398 compatible = "nvidia,tegra194-p2u"; 1399 reg = <0x03ef0000 0x10000>; 1400 reg-names = "ctl"; 1401 1402 #phy-cells = <0>; 1403 }; 1404 1405 p2u_nvhs_5: phy@3f00000 { 1406 compatible = "nvidia,tegra194-p2u"; 1407 reg = <0x03f00000 0x10000>; 1408 reg-names = "ctl"; 1409 1410 #phy-cells = <0>; 1411 }; 1412 1413 p2u_nvhs_6: phy@3f10000 { 1414 compatible = "nvidia,tegra194-p2u"; 1415 reg = <0x03f10000 0x10000>; 1416 reg-names = "ctl"; 1417 1418 #phy-cells = <0>; 1419 }; 1420 1421 p2u_nvhs_7: phy@3f20000 { 1422 compatible = "nvidia,tegra194-p2u"; 1423 reg = <0x03f20000 0x10000>; 1424 reg-names = "ctl"; 1425 1426 #phy-cells = <0>; 1427 }; 1428 1429 p2u_hsio_10: phy@3f30000 { 1430 compatible = "nvidia,tegra194-p2u"; 1431 reg = <0x03f30000 0x10000>; 1432 reg-names = "ctl"; 1433 1434 #phy-cells = <0>; 1435 }; 1436 1437 p2u_hsio_11: phy@3f40000 { 1438 compatible = "nvidia,tegra194-p2u"; 1439 reg = <0x03f40000 0x10000>; 1440 reg-names = "ctl"; 1441 1442 #phy-cells = <0>; 1443 }; 1444 1445 hsp_aon: hsp@c150000 { 1446 compatible = "nvidia,tegra194-hsp"; 1447 reg = <0x0c150000 0x90000>; 1448 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1452 /* 1453 * Shared interrupt 0 is routed only to AON/SPE, so 1454 * we only have 4 shared interrupts for the CCPLEX. 1455 */ 1456 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1457 #mbox-cells = <2>; 1458 }; 1459 1460 gen2_i2c: i2c@c240000 { 1461 compatible = "nvidia,tegra194-i2c"; 1462 reg = <0x0c240000 0x10000>; 1463 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1467 clock-names = "div-clk"; 1468 resets = <&bpmp TEGRA194_RESET_I2C2>; 1469 reset-names = "i2c"; 1470 status = "disabled"; 1471 }; 1472 1473 gen8_i2c: i2c@c250000 { 1474 compatible = "nvidia,tegra194-i2c"; 1475 reg = <0x0c250000 0x10000>; 1476 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1477 #address-cells = <1>; 1478 #size-cells = <0>; 1479 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1480 clock-names = "div-clk"; 1481 resets = <&bpmp TEGRA194_RESET_I2C8>; 1482 reset-names = "i2c"; 1483 status = "disabled"; 1484 }; 1485 1486 uartc: serial@c280000 { 1487 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1488 reg = <0x0c280000 0x40>; 1489 reg-shift = <2>; 1490 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1491 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1492 clock-names = "serial"; 1493 resets = <&bpmp TEGRA194_RESET_UARTC>; 1494 reset-names = "serial"; 1495 status = "disabled"; 1496 }; 1497 1498 uartg: serial@c290000 { 1499 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1500 reg = <0x0c290000 0x40>; 1501 reg-shift = <2>; 1502 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1503 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1504 clock-names = "serial"; 1505 resets = <&bpmp TEGRA194_RESET_UARTG>; 1506 reset-names = "serial"; 1507 status = "disabled"; 1508 }; 1509 1510 rtc: rtc@c2a0000 { 1511 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1512 reg = <0x0c2a0000 0x10000>; 1513 interrupt-parent = <&pmc>; 1514 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1515 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1516 clock-names = "rtc"; 1517 status = "disabled"; 1518 }; 1519 1520 gpio_aon: gpio@c2f0000 { 1521 compatible = "nvidia,tegra194-gpio-aon"; 1522 reg-names = "security", "gpio"; 1523 reg = <0xc2f0000 0x1000>, 1524 <0xc2f1000 0x1000>; 1525 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1529 gpio-controller; 1530 #gpio-cells = <2>; 1531 interrupt-controller; 1532 #interrupt-cells = <2>; 1533 }; 1534 1535 pwm4: pwm@c340000 { 1536 compatible = "nvidia,tegra194-pwm", 1537 "nvidia,tegra186-pwm"; 1538 reg = <0xc340000 0x10000>; 1539 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1540 clock-names = "pwm"; 1541 resets = <&bpmp TEGRA194_RESET_PWM4>; 1542 reset-names = "pwm"; 1543 status = "disabled"; 1544 #pwm-cells = <2>; 1545 }; 1546 1547 pmc: pmc@c360000 { 1548 compatible = "nvidia,tegra194-pmc"; 1549 reg = <0x0c360000 0x10000>, 1550 <0x0c370000 0x10000>, 1551 <0x0c380000 0x10000>, 1552 <0x0c390000 0x10000>, 1553 <0x0c3a0000 0x10000>; 1554 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1555 1556 #interrupt-cells = <2>; 1557 interrupt-controller; 1558 sdmmc1_3v3: sdmmc1-3v3 { 1559 pins = "sdmmc1-hv"; 1560 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1561 }; 1562 1563 sdmmc1_1v8: sdmmc1-1v8 { 1564 pins = "sdmmc1-hv"; 1565 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1566 }; 1567 sdmmc3_3v3: sdmmc3-3v3 { 1568 pins = "sdmmc3-hv"; 1569 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1570 }; 1571 1572 sdmmc3_1v8: sdmmc3-1v8 { 1573 pins = "sdmmc3-hv"; 1574 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1575 }; 1576 1577 }; 1578 1579 iommu@10000000 { 1580 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1581 reg = <0x10000000 0x800000>; 1582 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1647 stream-match-mask = <0x7f80>; 1648 #global-interrupts = <1>; 1649 #iommu-cells = <1>; 1650 1651 nvidia,memory-controller = <&mc>; 1652 status = "disabled"; 1653 }; 1654 1655 smmu: iommu@12000000 { 1656 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1657 reg = <0x12000000 0x800000>, 1658 <0x11000000 0x800000>; 1659 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1718 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1719 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1725 stream-match-mask = <0x7f80>; 1726 #global-interrupts = <2>; 1727 #iommu-cells = <1>; 1728 1729 nvidia,memory-controller = <&mc>; 1730 status = "okay"; 1731 }; 1732 1733 host1x@13e00000 { 1734 compatible = "nvidia,tegra194-host1x"; 1735 reg = <0x13e00000 0x10000>, 1736 <0x13e10000 0x10000>; 1737 reg-names = "hypervisor", "vm"; 1738 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1740 interrupt-names = "syncpt", "host1x"; 1741 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1742 clock-names = "host1x"; 1743 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1744 reset-names = "host1x"; 1745 1746 #address-cells = <1>; 1747 #size-cells = <1>; 1748 1749 ranges = <0x15000000 0x15000000 0x01000000>; 1750 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1751 interconnect-names = "dma-mem"; 1752 iommus = <&smmu TEGRA194_SID_HOST1X>; 1753 1754 nvdec@15140000 { 1755 compatible = "nvidia,tegra194-nvdec"; 1756 reg = <0x15140000 0x00040000>; 1757 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1758 clock-names = "nvdec"; 1759 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1760 reset-names = "nvdec"; 1761 1762 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1763 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1764 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1765 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1766 interconnect-names = "dma-mem", "read-1", "write"; 1767 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1768 dma-coherent; 1769 1770 nvidia,host1x-class = <0xf5>; 1771 }; 1772 1773 display-hub@15200000 { 1774 compatible = "nvidia,tegra194-display"; 1775 reg = <0x15200000 0x00040000>; 1776 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1777 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1778 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1779 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1780 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1781 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1782 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1783 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1784 "wgrp3", "wgrp4", "wgrp5"; 1785 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1786 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1787 clock-names = "disp", "hub"; 1788 status = "disabled"; 1789 1790 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1791 1792 #address-cells = <1>; 1793 #size-cells = <1>; 1794 1795 ranges = <0x15200000 0x15200000 0x40000>; 1796 1797 display@15200000 { 1798 compatible = "nvidia,tegra194-dc"; 1799 reg = <0x15200000 0x10000>; 1800 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1801 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1802 clock-names = "dc"; 1803 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1804 reset-names = "dc"; 1805 1806 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1807 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1808 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1809 interconnect-names = "dma-mem", "read-1"; 1810 1811 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1812 nvidia,head = <0>; 1813 }; 1814 1815 display@15210000 { 1816 compatible = "nvidia,tegra194-dc"; 1817 reg = <0x15210000 0x10000>; 1818 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1819 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1820 clock-names = "dc"; 1821 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1822 reset-names = "dc"; 1823 1824 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1825 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1826 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1827 interconnect-names = "dma-mem", "read-1"; 1828 1829 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1830 nvidia,head = <1>; 1831 }; 1832 1833 display@15220000 { 1834 compatible = "nvidia,tegra194-dc"; 1835 reg = <0x15220000 0x10000>; 1836 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1837 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1838 clock-names = "dc"; 1839 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1840 reset-names = "dc"; 1841 1842 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1843 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1844 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1845 interconnect-names = "dma-mem", "read-1"; 1846 1847 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1848 nvidia,head = <2>; 1849 }; 1850 1851 display@15230000 { 1852 compatible = "nvidia,tegra194-dc"; 1853 reg = <0x15230000 0x10000>; 1854 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1855 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1856 clock-names = "dc"; 1857 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1858 reset-names = "dc"; 1859 1860 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1861 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1862 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1863 interconnect-names = "dma-mem", "read-1"; 1864 1865 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1866 nvidia,head = <3>; 1867 }; 1868 }; 1869 1870 vic@15340000 { 1871 compatible = "nvidia,tegra194-vic"; 1872 reg = <0x15340000 0x00040000>; 1873 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1874 clocks = <&bpmp TEGRA194_CLK_VIC>; 1875 clock-names = "vic"; 1876 resets = <&bpmp TEGRA194_RESET_VIC>; 1877 reset-names = "vic"; 1878 1879 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1880 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1881 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1882 interconnect-names = "dma-mem", "write"; 1883 iommus = <&smmu TEGRA194_SID_VIC>; 1884 dma-coherent; 1885 }; 1886 1887 nvjpg@15380000 { 1888 compatible = "nvidia,tegra194-nvjpg"; 1889 reg = <0x15380000 0x40000>; 1890 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1891 clock-names = "nvjpg"; 1892 resets = <&bpmp TEGRA194_RESET_NVJPG>; 1893 reset-names = "nvjpg"; 1894 1895 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1896 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1897 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1898 interconnect-names = "dma-mem", "write"; 1899 iommus = <&smmu TEGRA194_SID_NVJPG>; 1900 dma-coherent; 1901 }; 1902 1903 nvdec@15480000 { 1904 compatible = "nvidia,tegra194-nvdec"; 1905 reg = <0x15480000 0x00040000>; 1906 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 1907 clock-names = "nvdec"; 1908 resets = <&bpmp TEGRA194_RESET_NVDEC>; 1909 reset-names = "nvdec"; 1910 1911 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 1912 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 1913 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 1914 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 1915 interconnect-names = "dma-mem", "read-1", "write"; 1916 iommus = <&smmu TEGRA194_SID_NVDEC>; 1917 dma-coherent; 1918 1919 nvidia,host1x-class = <0xf0>; 1920 }; 1921 1922 nvenc@154c0000 { 1923 compatible = "nvidia,tegra194-nvenc"; 1924 reg = <0x154c0000 0x40000>; 1925 clocks = <&bpmp TEGRA194_CLK_NVENC>; 1926 clock-names = "nvenc"; 1927 resets = <&bpmp TEGRA194_RESET_NVENC>; 1928 reset-names = "nvenc"; 1929 1930 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 1931 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 1932 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 1933 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 1934 interconnect-names = "dma-mem", "read-1", "write"; 1935 iommus = <&smmu TEGRA194_SID_NVENC>; 1936 dma-coherent; 1937 1938 nvidia,host1x-class = <0x21>; 1939 }; 1940 1941 dpaux0: dpaux@155c0000 { 1942 compatible = "nvidia,tegra194-dpaux"; 1943 reg = <0x155c0000 0x10000>; 1944 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1945 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1946 <&bpmp TEGRA194_CLK_PLLDP>; 1947 clock-names = "dpaux", "parent"; 1948 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1949 reset-names = "dpaux"; 1950 status = "disabled"; 1951 1952 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1953 1954 state_dpaux0_aux: pinmux-aux { 1955 groups = "dpaux-io"; 1956 function = "aux"; 1957 }; 1958 1959 state_dpaux0_i2c: pinmux-i2c { 1960 groups = "dpaux-io"; 1961 function = "i2c"; 1962 }; 1963 1964 state_dpaux0_off: pinmux-off { 1965 groups = "dpaux-io"; 1966 function = "off"; 1967 }; 1968 1969 i2c-bus { 1970 #address-cells = <1>; 1971 #size-cells = <0>; 1972 }; 1973 }; 1974 1975 dpaux1: dpaux@155d0000 { 1976 compatible = "nvidia,tegra194-dpaux"; 1977 reg = <0x155d0000 0x10000>; 1978 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1979 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1980 <&bpmp TEGRA194_CLK_PLLDP>; 1981 clock-names = "dpaux", "parent"; 1982 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1983 reset-names = "dpaux"; 1984 status = "disabled"; 1985 1986 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1987 1988 state_dpaux1_aux: pinmux-aux { 1989 groups = "dpaux-io"; 1990 function = "aux"; 1991 }; 1992 1993 state_dpaux1_i2c: pinmux-i2c { 1994 groups = "dpaux-io"; 1995 function = "i2c"; 1996 }; 1997 1998 state_dpaux1_off: pinmux-off { 1999 groups = "dpaux-io"; 2000 function = "off"; 2001 }; 2002 2003 i2c-bus { 2004 #address-cells = <1>; 2005 #size-cells = <0>; 2006 }; 2007 }; 2008 2009 dpaux2: dpaux@155e0000 { 2010 compatible = "nvidia,tegra194-dpaux"; 2011 reg = <0x155e0000 0x10000>; 2012 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2013 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2014 <&bpmp TEGRA194_CLK_PLLDP>; 2015 clock-names = "dpaux", "parent"; 2016 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2017 reset-names = "dpaux"; 2018 status = "disabled"; 2019 2020 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2021 2022 state_dpaux2_aux: pinmux-aux { 2023 groups = "dpaux-io"; 2024 function = "aux"; 2025 }; 2026 2027 state_dpaux2_i2c: pinmux-i2c { 2028 groups = "dpaux-io"; 2029 function = "i2c"; 2030 }; 2031 2032 state_dpaux2_off: pinmux-off { 2033 groups = "dpaux-io"; 2034 function = "off"; 2035 }; 2036 2037 i2c-bus { 2038 #address-cells = <1>; 2039 #size-cells = <0>; 2040 }; 2041 }; 2042 2043 dpaux3: dpaux@155f0000 { 2044 compatible = "nvidia,tegra194-dpaux"; 2045 reg = <0x155f0000 0x10000>; 2046 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2047 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2048 <&bpmp TEGRA194_CLK_PLLDP>; 2049 clock-names = "dpaux", "parent"; 2050 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2051 reset-names = "dpaux"; 2052 status = "disabled"; 2053 2054 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2055 2056 state_dpaux3_aux: pinmux-aux { 2057 groups = "dpaux-io"; 2058 function = "aux"; 2059 }; 2060 2061 state_dpaux3_i2c: pinmux-i2c { 2062 groups = "dpaux-io"; 2063 function = "i2c"; 2064 }; 2065 2066 state_dpaux3_off: pinmux-off { 2067 groups = "dpaux-io"; 2068 function = "off"; 2069 }; 2070 2071 i2c-bus { 2072 #address-cells = <1>; 2073 #size-cells = <0>; 2074 }; 2075 }; 2076 2077 nvenc@15a80000 { 2078 compatible = "nvidia,tegra194-nvenc"; 2079 reg = <0x15a80000 0x00040000>; 2080 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2081 clock-names = "nvenc"; 2082 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2083 reset-names = "nvenc"; 2084 2085 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2086 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2087 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2088 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2089 interconnect-names = "dma-mem", "read-1", "write"; 2090 iommus = <&smmu TEGRA194_SID_NVENC1>; 2091 dma-coherent; 2092 2093 nvidia,host1x-class = <0x22>; 2094 }; 2095 2096 sor0: sor@15b00000 { 2097 compatible = "nvidia,tegra194-sor"; 2098 reg = <0x15b00000 0x40000>; 2099 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2100 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2101 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2102 <&bpmp TEGRA194_CLK_PLLD>, 2103 <&bpmp TEGRA194_CLK_PLLDP>, 2104 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2105 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2106 clock-names = "sor", "out", "parent", "dp", "safe", 2107 "pad"; 2108 resets = <&bpmp TEGRA194_RESET_SOR0>; 2109 reset-names = "sor"; 2110 pinctrl-0 = <&state_dpaux0_aux>; 2111 pinctrl-1 = <&state_dpaux0_i2c>; 2112 pinctrl-2 = <&state_dpaux0_off>; 2113 pinctrl-names = "aux", "i2c", "off"; 2114 status = "disabled"; 2115 2116 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2117 nvidia,interface = <0>; 2118 }; 2119 2120 sor1: sor@15b40000 { 2121 compatible = "nvidia,tegra194-sor"; 2122 reg = <0x15b40000 0x40000>; 2123 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2124 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2125 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2126 <&bpmp TEGRA194_CLK_PLLD2>, 2127 <&bpmp TEGRA194_CLK_PLLDP>, 2128 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2129 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2130 clock-names = "sor", "out", "parent", "dp", "safe", 2131 "pad"; 2132 resets = <&bpmp TEGRA194_RESET_SOR1>; 2133 reset-names = "sor"; 2134 pinctrl-0 = <&state_dpaux1_aux>; 2135 pinctrl-1 = <&state_dpaux1_i2c>; 2136 pinctrl-2 = <&state_dpaux1_off>; 2137 pinctrl-names = "aux", "i2c", "off"; 2138 status = "disabled"; 2139 2140 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2141 nvidia,interface = <1>; 2142 }; 2143 2144 sor2: sor@15b80000 { 2145 compatible = "nvidia,tegra194-sor"; 2146 reg = <0x15b80000 0x40000>; 2147 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2148 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2149 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2150 <&bpmp TEGRA194_CLK_PLLD3>, 2151 <&bpmp TEGRA194_CLK_PLLDP>, 2152 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2153 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2154 clock-names = "sor", "out", "parent", "dp", "safe", 2155 "pad"; 2156 resets = <&bpmp TEGRA194_RESET_SOR2>; 2157 reset-names = "sor"; 2158 pinctrl-0 = <&state_dpaux2_aux>; 2159 pinctrl-1 = <&state_dpaux2_i2c>; 2160 pinctrl-2 = <&state_dpaux2_off>; 2161 pinctrl-names = "aux", "i2c", "off"; 2162 status = "disabled"; 2163 2164 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2165 nvidia,interface = <2>; 2166 }; 2167 2168 sor3: sor@15bc0000 { 2169 compatible = "nvidia,tegra194-sor"; 2170 reg = <0x15bc0000 0x40000>; 2171 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2172 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2173 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2174 <&bpmp TEGRA194_CLK_PLLD4>, 2175 <&bpmp TEGRA194_CLK_PLLDP>, 2176 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2177 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2178 clock-names = "sor", "out", "parent", "dp", "safe", 2179 "pad"; 2180 resets = <&bpmp TEGRA194_RESET_SOR3>; 2181 reset-names = "sor"; 2182 pinctrl-0 = <&state_dpaux3_aux>; 2183 pinctrl-1 = <&state_dpaux3_i2c>; 2184 pinctrl-2 = <&state_dpaux3_off>; 2185 pinctrl-names = "aux", "i2c", "off"; 2186 status = "disabled"; 2187 2188 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2189 nvidia,interface = <3>; 2190 }; 2191 }; 2192 2193 gpu@17000000 { 2194 compatible = "nvidia,gv11b"; 2195 reg = <0x17000000 0x1000000>, 2196 <0x18000000 0x1000000>; 2197 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2198 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2199 interrupt-names = "stall", "nonstall"; 2200 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2201 <&bpmp TEGRA194_CLK_GPU_PWR>, 2202 <&bpmp TEGRA194_CLK_FUSE>; 2203 clock-names = "gpu", "pwr", "fuse"; 2204 resets = <&bpmp TEGRA194_RESET_GPU>; 2205 reset-names = "gpu"; 2206 dma-coherent; 2207 2208 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2209 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2210 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2211 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2212 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2213 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2214 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2215 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2216 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2217 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2218 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2219 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2220 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2221 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2222 "read-1", "read-1-hp", "write-1", 2223 "read-2", "read-2-hp", "write-2", 2224 "read-3", "read-3-hp", "write-3"; 2225 }; 2226 }; 2227 2228 pcie@14100000 { 2229 compatible = "nvidia,tegra194-pcie"; 2230 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2231 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2232 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2233 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2234 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2235 reg-names = "appl", "config", "atu_dma", "dbi"; 2236 2237 status = "disabled"; 2238 2239 #address-cells = <3>; 2240 #size-cells = <2>; 2241 device_type = "pci"; 2242 num-lanes = <1>; 2243 linux,pci-domain = <1>; 2244 2245 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2246 clock-names = "core"; 2247 2248 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2249 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2250 reset-names = "apb", "core"; 2251 2252 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2253 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2254 interrupt-names = "intr", "msi"; 2255 2256 #interrupt-cells = <1>; 2257 interrupt-map-mask = <0 0 0 0>; 2258 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2259 2260 nvidia,bpmp = <&bpmp 1>; 2261 2262 nvidia,aspm-cmrt-us = <60>; 2263 nvidia,aspm-pwr-on-t-us = <20>; 2264 nvidia,aspm-l0s-entrance-latency-us = <3>; 2265 2266 bus-range = <0x0 0xff>; 2267 2268 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2269 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2270 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2271 2272 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2273 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2274 interconnect-names = "dma-mem", "write"; 2275 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2276 iommu-map-mask = <0x0>; 2277 dma-coherent; 2278 }; 2279 2280 pcie@14120000 { 2281 compatible = "nvidia,tegra194-pcie"; 2282 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2283 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2284 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2285 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2286 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2287 reg-names = "appl", "config", "atu_dma", "dbi"; 2288 2289 status = "disabled"; 2290 2291 #address-cells = <3>; 2292 #size-cells = <2>; 2293 device_type = "pci"; 2294 num-lanes = <1>; 2295 linux,pci-domain = <2>; 2296 2297 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2298 clock-names = "core"; 2299 2300 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2301 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2302 reset-names = "apb", "core"; 2303 2304 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2305 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2306 interrupt-names = "intr", "msi"; 2307 2308 #interrupt-cells = <1>; 2309 interrupt-map-mask = <0 0 0 0>; 2310 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2311 2312 nvidia,bpmp = <&bpmp 2>; 2313 2314 nvidia,aspm-cmrt-us = <60>; 2315 nvidia,aspm-pwr-on-t-us = <20>; 2316 nvidia,aspm-l0s-entrance-latency-us = <3>; 2317 2318 bus-range = <0x0 0xff>; 2319 2320 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2321 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2322 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2323 2324 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2325 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2326 interconnect-names = "dma-mem", "write"; 2327 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2328 iommu-map-mask = <0x0>; 2329 dma-coherent; 2330 }; 2331 2332 pcie@14140000 { 2333 compatible = "nvidia,tegra194-pcie"; 2334 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2335 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2336 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2337 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2338 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2339 reg-names = "appl", "config", "atu_dma", "dbi"; 2340 2341 status = "disabled"; 2342 2343 #address-cells = <3>; 2344 #size-cells = <2>; 2345 device_type = "pci"; 2346 num-lanes = <1>; 2347 linux,pci-domain = <3>; 2348 2349 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2350 clock-names = "core"; 2351 2352 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2353 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2354 reset-names = "apb", "core"; 2355 2356 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2357 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2358 interrupt-names = "intr", "msi"; 2359 2360 #interrupt-cells = <1>; 2361 interrupt-map-mask = <0 0 0 0>; 2362 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2363 2364 nvidia,bpmp = <&bpmp 3>; 2365 2366 nvidia,aspm-cmrt-us = <60>; 2367 nvidia,aspm-pwr-on-t-us = <20>; 2368 nvidia,aspm-l0s-entrance-latency-us = <3>; 2369 2370 bus-range = <0x0 0xff>; 2371 2372 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2373 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2374 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2375 2376 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2377 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2378 interconnect-names = "dma-mem", "write"; 2379 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2380 iommu-map-mask = <0x0>; 2381 dma-coherent; 2382 }; 2383 2384 pcie@14160000 { 2385 compatible = "nvidia,tegra194-pcie"; 2386 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2387 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2388 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2389 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2390 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2391 reg-names = "appl", "config", "atu_dma", "dbi"; 2392 2393 status = "disabled"; 2394 2395 #address-cells = <3>; 2396 #size-cells = <2>; 2397 device_type = "pci"; 2398 num-lanes = <4>; 2399 linux,pci-domain = <4>; 2400 2401 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2402 clock-names = "core"; 2403 2404 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2405 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2406 reset-names = "apb", "core"; 2407 2408 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2409 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2410 interrupt-names = "intr", "msi"; 2411 2412 #interrupt-cells = <1>; 2413 interrupt-map-mask = <0 0 0 0>; 2414 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2415 2416 nvidia,bpmp = <&bpmp 4>; 2417 2418 nvidia,aspm-cmrt-us = <60>; 2419 nvidia,aspm-pwr-on-t-us = <20>; 2420 nvidia,aspm-l0s-entrance-latency-us = <3>; 2421 2422 bus-range = <0x0 0xff>; 2423 2424 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2425 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2426 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2427 2428 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2429 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2430 interconnect-names = "dma-mem", "write"; 2431 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2432 iommu-map-mask = <0x0>; 2433 dma-coherent; 2434 }; 2435 2436 pcie@14180000 { 2437 compatible = "nvidia,tegra194-pcie"; 2438 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2439 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2440 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2441 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2442 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2443 reg-names = "appl", "config", "atu_dma", "dbi"; 2444 2445 status = "disabled"; 2446 2447 #address-cells = <3>; 2448 #size-cells = <2>; 2449 device_type = "pci"; 2450 num-lanes = <8>; 2451 linux,pci-domain = <0>; 2452 2453 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2454 clock-names = "core"; 2455 2456 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2457 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2458 reset-names = "apb", "core"; 2459 2460 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2461 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2462 interrupt-names = "intr", "msi"; 2463 2464 #interrupt-cells = <1>; 2465 interrupt-map-mask = <0 0 0 0>; 2466 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2467 2468 nvidia,bpmp = <&bpmp 0>; 2469 2470 nvidia,aspm-cmrt-us = <60>; 2471 nvidia,aspm-pwr-on-t-us = <20>; 2472 nvidia,aspm-l0s-entrance-latency-us = <3>; 2473 2474 bus-range = <0x0 0xff>; 2475 2476 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2477 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2478 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2479 2480 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2481 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2482 interconnect-names = "dma-mem", "write"; 2483 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2484 iommu-map-mask = <0x0>; 2485 dma-coherent; 2486 }; 2487 2488 pcie@141a0000 { 2489 compatible = "nvidia,tegra194-pcie"; 2490 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2491 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2492 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2493 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2494 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2495 reg-names = "appl", "config", "atu_dma", "dbi"; 2496 2497 status = "disabled"; 2498 2499 #address-cells = <3>; 2500 #size-cells = <2>; 2501 device_type = "pci"; 2502 num-lanes = <8>; 2503 linux,pci-domain = <5>; 2504 2505 pinctrl-names = "default"; 2506 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2507 2508 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2509 clock-names = "core"; 2510 2511 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2512 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2513 reset-names = "apb", "core"; 2514 2515 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2516 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2517 interrupt-names = "intr", "msi"; 2518 2519 nvidia,bpmp = <&bpmp 5>; 2520 2521 #interrupt-cells = <1>; 2522 interrupt-map-mask = <0 0 0 0>; 2523 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2524 2525 nvidia,aspm-cmrt-us = <60>; 2526 nvidia,aspm-pwr-on-t-us = <20>; 2527 nvidia,aspm-l0s-entrance-latency-us = <3>; 2528 2529 bus-range = <0x0 0xff>; 2530 2531 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2532 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2533 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2534 2535 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2536 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2537 interconnect-names = "dma-mem", "write"; 2538 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2539 iommu-map-mask = <0x0>; 2540 dma-coherent; 2541 }; 2542 2543 pcie-ep@14160000 { 2544 compatible = "nvidia,tegra194-pcie-ep"; 2545 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2546 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2547 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2548 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2549 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2550 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2551 2552 status = "disabled"; 2553 2554 num-lanes = <4>; 2555 num-ib-windows = <2>; 2556 num-ob-windows = <8>; 2557 2558 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2559 clock-names = "core"; 2560 2561 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2562 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2563 reset-names = "apb", "core"; 2564 2565 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2566 interrupt-names = "intr"; 2567 2568 nvidia,bpmp = <&bpmp 4>; 2569 2570 nvidia,aspm-cmrt-us = <60>; 2571 nvidia,aspm-pwr-on-t-us = <20>; 2572 nvidia,aspm-l0s-entrance-latency-us = <3>; 2573 2574 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2575 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2576 interconnect-names = "dma-mem", "write"; 2577 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2578 iommu-map-mask = <0x0>; 2579 dma-coherent; 2580 }; 2581 2582 pcie-ep@14180000 { 2583 compatible = "nvidia,tegra194-pcie-ep"; 2584 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2585 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2586 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2587 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2588 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2589 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2590 2591 status = "disabled"; 2592 2593 num-lanes = <8>; 2594 num-ib-windows = <2>; 2595 num-ob-windows = <8>; 2596 2597 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2598 clock-names = "core"; 2599 2600 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2601 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2602 reset-names = "apb", "core"; 2603 2604 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2605 interrupt-names = "intr"; 2606 2607 nvidia,bpmp = <&bpmp 0>; 2608 2609 nvidia,aspm-cmrt-us = <60>; 2610 nvidia,aspm-pwr-on-t-us = <20>; 2611 nvidia,aspm-l0s-entrance-latency-us = <3>; 2612 2613 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2614 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2615 interconnect-names = "dma-mem", "write"; 2616 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2617 iommu-map-mask = <0x0>; 2618 dma-coherent; 2619 }; 2620 2621 pcie-ep@141a0000 { 2622 compatible = "nvidia,tegra194-pcie-ep"; 2623 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2624 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2625 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2626 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2627 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2628 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2629 2630 status = "disabled"; 2631 2632 num-lanes = <8>; 2633 num-ib-windows = <2>; 2634 num-ob-windows = <8>; 2635 2636 pinctrl-names = "default"; 2637 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2638 2639 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2640 clock-names = "core"; 2641 2642 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2643 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2644 reset-names = "apb", "core"; 2645 2646 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2647 interrupt-names = "intr"; 2648 2649 nvidia,bpmp = <&bpmp 5>; 2650 2651 nvidia,aspm-cmrt-us = <60>; 2652 nvidia,aspm-pwr-on-t-us = <20>; 2653 nvidia,aspm-l0s-entrance-latency-us = <3>; 2654 2655 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2656 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2657 interconnect-names = "dma-mem", "write"; 2658 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2659 iommu-map-mask = <0x0>; 2660 dma-coherent; 2661 }; 2662 2663 sram@40000000 { 2664 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2665 reg = <0x0 0x40000000 0x0 0x50000>; 2666 #address-cells = <1>; 2667 #size-cells = <1>; 2668 ranges = <0x0 0x0 0x40000000 0x50000>; 2669 2670 cpu_bpmp_tx: sram@4e000 { 2671 reg = <0x4e000 0x1000>; 2672 label = "cpu-bpmp-tx"; 2673 pool; 2674 }; 2675 2676 cpu_bpmp_rx: sram@4f000 { 2677 reg = <0x4f000 0x1000>; 2678 label = "cpu-bpmp-rx"; 2679 pool; 2680 }; 2681 }; 2682 2683 bpmp: bpmp { 2684 compatible = "nvidia,tegra186-bpmp"; 2685 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2686 TEGRA_HSP_DB_MASTER_BPMP>; 2687 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2688 #clock-cells = <1>; 2689 #reset-cells = <1>; 2690 #power-domain-cells = <1>; 2691 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2692 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2693 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2694 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2695 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2696 iommus = <&smmu TEGRA194_SID_BPMP>; 2697 2698 bpmp_i2c: i2c { 2699 compatible = "nvidia,tegra186-bpmp-i2c"; 2700 nvidia,bpmp-bus-id = <5>; 2701 #address-cells = <1>; 2702 #size-cells = <0>; 2703 }; 2704 2705 bpmp_thermal: thermal { 2706 compatible = "nvidia,tegra186-bpmp-thermal"; 2707 #thermal-sensor-cells = <1>; 2708 }; 2709 }; 2710 2711 cpus { 2712 compatible = "nvidia,tegra194-ccplex"; 2713 nvidia,bpmp = <&bpmp>; 2714 #address-cells = <1>; 2715 #size-cells = <0>; 2716 2717 cpu0_0: cpu@0 { 2718 compatible = "nvidia,tegra194-carmel"; 2719 device_type = "cpu"; 2720 reg = <0x000>; 2721 enable-method = "psci"; 2722 i-cache-size = <131072>; 2723 i-cache-line-size = <64>; 2724 i-cache-sets = <512>; 2725 d-cache-size = <65536>; 2726 d-cache-line-size = <64>; 2727 d-cache-sets = <256>; 2728 next-level-cache = <&l2c_0>; 2729 }; 2730 2731 cpu0_1: cpu@1 { 2732 compatible = "nvidia,tegra194-carmel"; 2733 device_type = "cpu"; 2734 reg = <0x001>; 2735 enable-method = "psci"; 2736 i-cache-size = <131072>; 2737 i-cache-line-size = <64>; 2738 i-cache-sets = <512>; 2739 d-cache-size = <65536>; 2740 d-cache-line-size = <64>; 2741 d-cache-sets = <256>; 2742 next-level-cache = <&l2c_0>; 2743 }; 2744 2745 cpu1_0: cpu@100 { 2746 compatible = "nvidia,tegra194-carmel"; 2747 device_type = "cpu"; 2748 reg = <0x100>; 2749 enable-method = "psci"; 2750 i-cache-size = <131072>; 2751 i-cache-line-size = <64>; 2752 i-cache-sets = <512>; 2753 d-cache-size = <65536>; 2754 d-cache-line-size = <64>; 2755 d-cache-sets = <256>; 2756 next-level-cache = <&l2c_1>; 2757 }; 2758 2759 cpu1_1: cpu@101 { 2760 compatible = "nvidia,tegra194-carmel"; 2761 device_type = "cpu"; 2762 reg = <0x101>; 2763 enable-method = "psci"; 2764 i-cache-size = <131072>; 2765 i-cache-line-size = <64>; 2766 i-cache-sets = <512>; 2767 d-cache-size = <65536>; 2768 d-cache-line-size = <64>; 2769 d-cache-sets = <256>; 2770 next-level-cache = <&l2c_1>; 2771 }; 2772 2773 cpu2_0: cpu@200 { 2774 compatible = "nvidia,tegra194-carmel"; 2775 device_type = "cpu"; 2776 reg = <0x200>; 2777 enable-method = "psci"; 2778 i-cache-size = <131072>; 2779 i-cache-line-size = <64>; 2780 i-cache-sets = <512>; 2781 d-cache-size = <65536>; 2782 d-cache-line-size = <64>; 2783 d-cache-sets = <256>; 2784 next-level-cache = <&l2c_2>; 2785 }; 2786 2787 cpu2_1: cpu@201 { 2788 compatible = "nvidia,tegra194-carmel"; 2789 device_type = "cpu"; 2790 reg = <0x201>; 2791 enable-method = "psci"; 2792 i-cache-size = <131072>; 2793 i-cache-line-size = <64>; 2794 i-cache-sets = <512>; 2795 d-cache-size = <65536>; 2796 d-cache-line-size = <64>; 2797 d-cache-sets = <256>; 2798 next-level-cache = <&l2c_2>; 2799 }; 2800 2801 cpu3_0: cpu@300 { 2802 compatible = "nvidia,tegra194-carmel"; 2803 device_type = "cpu"; 2804 reg = <0x300>; 2805 enable-method = "psci"; 2806 i-cache-size = <131072>; 2807 i-cache-line-size = <64>; 2808 i-cache-sets = <512>; 2809 d-cache-size = <65536>; 2810 d-cache-line-size = <64>; 2811 d-cache-sets = <256>; 2812 next-level-cache = <&l2c_3>; 2813 }; 2814 2815 cpu3_1: cpu@301 { 2816 compatible = "nvidia,tegra194-carmel"; 2817 device_type = "cpu"; 2818 reg = <0x301>; 2819 enable-method = "psci"; 2820 i-cache-size = <131072>; 2821 i-cache-line-size = <64>; 2822 i-cache-sets = <512>; 2823 d-cache-size = <65536>; 2824 d-cache-line-size = <64>; 2825 d-cache-sets = <256>; 2826 next-level-cache = <&l2c_3>; 2827 }; 2828 2829 cpu-map { 2830 cluster0 { 2831 core0 { 2832 cpu = <&cpu0_0>; 2833 }; 2834 2835 core1 { 2836 cpu = <&cpu0_1>; 2837 }; 2838 }; 2839 2840 cluster1 { 2841 core0 { 2842 cpu = <&cpu1_0>; 2843 }; 2844 2845 core1 { 2846 cpu = <&cpu1_1>; 2847 }; 2848 }; 2849 2850 cluster2 { 2851 core0 { 2852 cpu = <&cpu2_0>; 2853 }; 2854 2855 core1 { 2856 cpu = <&cpu2_1>; 2857 }; 2858 }; 2859 2860 cluster3 { 2861 core0 { 2862 cpu = <&cpu3_0>; 2863 }; 2864 2865 core1 { 2866 cpu = <&cpu3_1>; 2867 }; 2868 }; 2869 }; 2870 2871 l2c_0: l2-cache0 { 2872 cache-size = <2097152>; 2873 cache-line-size = <64>; 2874 cache-sets = <2048>; 2875 next-level-cache = <&l3c>; 2876 }; 2877 2878 l2c_1: l2-cache1 { 2879 cache-size = <2097152>; 2880 cache-line-size = <64>; 2881 cache-sets = <2048>; 2882 next-level-cache = <&l3c>; 2883 }; 2884 2885 l2c_2: l2-cache2 { 2886 cache-size = <2097152>; 2887 cache-line-size = <64>; 2888 cache-sets = <2048>; 2889 next-level-cache = <&l3c>; 2890 }; 2891 2892 l2c_3: l2-cache3 { 2893 cache-size = <2097152>; 2894 cache-line-size = <64>; 2895 cache-sets = <2048>; 2896 next-level-cache = <&l3c>; 2897 }; 2898 2899 l3c: l3-cache { 2900 cache-size = <4194304>; 2901 cache-line-size = <64>; 2902 cache-sets = <4096>; 2903 }; 2904 }; 2905 2906 pmu { 2907 compatible = "nvidia,carmel-pmu"; 2908 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2909 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2910 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2911 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 2912 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 2913 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 2914 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 2915 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 2916 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 2917 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 2918 }; 2919 2920 psci { 2921 compatible = "arm,psci-1.0"; 2922 status = "okay"; 2923 method = "smc"; 2924 }; 2925 2926 sound { 2927 status = "disabled"; 2928 2929 clocks = <&bpmp TEGRA194_CLK_PLLA>, 2930 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2931 clock-names = "pll_a", "plla_out0"; 2932 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 2933 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 2934 <&bpmp TEGRA194_CLK_AUD_MCLK>; 2935 assigned-clock-parents = <0>, 2936 <&bpmp TEGRA194_CLK_PLLA>, 2937 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2938 /* 2939 * PLLA supports dynamic ramp. Below initial rate is chosen 2940 * for this to work and oscillate between base rates required 2941 * for 8x and 11.025x sample rate streams. 2942 */ 2943 assigned-clock-rates = <258000000>; 2944 }; 2945 2946 tcu: serial { 2947 compatible = "nvidia,tegra194-tcu"; 2948 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2949 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2950 mbox-names = "rx", "tx"; 2951 }; 2952 2953 thermal-zones { 2954 cpu-thermal { 2955 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2956 status = "disabled"; 2957 }; 2958 2959 gpu-thermal { 2960 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2961 status = "disabled"; 2962 }; 2963 2964 aux-thermal { 2965 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2966 status = "disabled"; 2967 }; 2968 2969 pllx-thermal { 2970 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2971 status = "disabled"; 2972 }; 2973 2974 ao-thermal { 2975 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 2976 status = "disabled"; 2977 }; 2978 2979 tj-thermal { 2980 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2981 status = "disabled"; 2982 }; 2983 }; 2984 2985 timer { 2986 compatible = "arm,armv8-timer"; 2987 interrupts = <GIC_PPI 13 2988 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2989 <GIC_PPI 14 2990 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2991 <GIC_PPI 11 2992 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2993 <GIC_PPI 10 2994 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2995 interrupt-parent = <&gic>; 2996 always-on; 2997 }; 2998}; 2999