1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/reset/tegra194-reset.h> 9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10#include <dt-bindings/memory/tegra194-mc.h> 11 12/ { 13 compatible = "nvidia,tegra194"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* control backbone */ 19 bus@0 { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra194-misc"; 27 reg = <0x00100000 0xf000>, 28 <0x0010f000 0x1000>; 29 }; 30 31 gpio: gpio@2200000 { 32 compatible = "nvidia,tegra194-gpio"; 33 reg-names = "security", "gpio"; 34 reg = <0x2200000 0x10000>, 35 <0x2210000 0x10000>; 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 84 #interrupt-cells = <2>; 85 interrupt-controller; 86 #gpio-cells = <2>; 87 gpio-controller; 88 }; 89 90 ethernet@2490000 { 91 compatible = "nvidia,tegra194-eqos", 92 "nvidia,tegra186-eqos", 93 "snps,dwc-qos-ethernet-4.10"; 94 reg = <0x02490000 0x10000>; 95 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 96 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 97 <&bpmp TEGRA194_CLK_EQOS_AXI>, 98 <&bpmp TEGRA194_CLK_EQOS_RX>, 99 <&bpmp TEGRA194_CLK_EQOS_TX>, 100 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 101 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 102 resets = <&bpmp TEGRA194_RESET_EQOS>; 103 reset-names = "eqos"; 104 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 105 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 106 interconnect-names = "dma-mem", "write"; 107 iommus = <&smmu TEGRA194_SID_EQOS>; 108 status = "disabled"; 109 110 snps,write-requests = <1>; 111 snps,read-requests = <3>; 112 snps,burst-map = <0x7>; 113 snps,txpbl = <16>; 114 snps,rxpbl = <8>; 115 }; 116 117 aconnect@2900000 { 118 compatible = "nvidia,tegra194-aconnect", 119 "nvidia,tegra210-aconnect"; 120 clocks = <&bpmp TEGRA194_CLK_APE>, 121 <&bpmp TEGRA194_CLK_APB2APE>; 122 clock-names = "ape", "apb2ape"; 123 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 ranges = <0x02900000 0x02900000 0x200000>; 127 status = "disabled"; 128 129 adma: dma-controller@2930000 { 130 compatible = "nvidia,tegra194-adma", 131 "nvidia,tegra186-adma"; 132 reg = <0x02930000 0x20000>; 133 interrupt-parent = <&agic>; 134 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 166 #dma-cells = <1>; 167 clocks = <&bpmp TEGRA194_CLK_AHUB>; 168 clock-names = "d_audio"; 169 status = "disabled"; 170 }; 171 172 agic: interrupt-controller@2a40000 { 173 compatible = "nvidia,tegra194-agic", 174 "nvidia,tegra210-agic"; 175 #interrupt-cells = <3>; 176 interrupt-controller; 177 reg = <0x02a41000 0x1000>, 178 <0x02a42000 0x2000>; 179 interrupts = <GIC_SPI 145 180 (GIC_CPU_MASK_SIMPLE(4) | 181 IRQ_TYPE_LEVEL_HIGH)>; 182 clocks = <&bpmp TEGRA194_CLK_APE>; 183 clock-names = "clk"; 184 status = "disabled"; 185 }; 186 187 tegra_ahub: ahub@2900800 { 188 compatible = "nvidia,tegra194-ahub", 189 "nvidia,tegra186-ahub"; 190 reg = <0x02900800 0x800>; 191 clocks = <&bpmp TEGRA194_CLK_AHUB>; 192 clock-names = "ahub"; 193 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 194 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 ranges = <0x02900800 0x02900800 0x11800>; 198 status = "disabled"; 199 200 tegra_admaif: admaif@290f000 { 201 compatible = "nvidia,tegra194-admaif", 202 "nvidia,tegra186-admaif"; 203 reg = <0x0290f000 0x1000>; 204 dmas = <&adma 1>, <&adma 1>, 205 <&adma 2>, <&adma 2>, 206 <&adma 3>, <&adma 3>, 207 <&adma 4>, <&adma 4>, 208 <&adma 5>, <&adma 5>, 209 <&adma 6>, <&adma 6>, 210 <&adma 7>, <&adma 7>, 211 <&adma 8>, <&adma 8>, 212 <&adma 9>, <&adma 9>, 213 <&adma 10>, <&adma 10>, 214 <&adma 11>, <&adma 11>, 215 <&adma 12>, <&adma 12>, 216 <&adma 13>, <&adma 13>, 217 <&adma 14>, <&adma 14>, 218 <&adma 15>, <&adma 15>, 219 <&adma 16>, <&adma 16>, 220 <&adma 17>, <&adma 17>, 221 <&adma 18>, <&adma 18>, 222 <&adma 19>, <&adma 19>, 223 <&adma 20>, <&adma 20>; 224 dma-names = "rx1", "tx1", 225 "rx2", "tx2", 226 "rx3", "tx3", 227 "rx4", "tx4", 228 "rx5", "tx5", 229 "rx6", "tx6", 230 "rx7", "tx7", 231 "rx8", "tx8", 232 "rx9", "tx9", 233 "rx10", "tx10", 234 "rx11", "tx11", 235 "rx12", "tx12", 236 "rx13", "tx13", 237 "rx14", "tx14", 238 "rx15", "tx15", 239 "rx16", "tx16", 240 "rx17", "tx17", 241 "rx18", "tx18", 242 "rx19", "tx19", 243 "rx20", "tx20"; 244 status = "disabled"; 245 }; 246 247 tegra_i2s1: i2s@2901000 { 248 compatible = "nvidia,tegra194-i2s", 249 "nvidia,tegra210-i2s"; 250 reg = <0x2901000 0x100>; 251 clocks = <&bpmp TEGRA194_CLK_I2S1>, 252 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 253 clock-names = "i2s", "sync_input"; 254 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 255 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 256 assigned-clock-rates = <1536000>; 257 sound-name-prefix = "I2S1"; 258 status = "disabled"; 259 }; 260 261 tegra_i2s2: i2s@2901100 { 262 compatible = "nvidia,tegra194-i2s", 263 "nvidia,tegra210-i2s"; 264 reg = <0x2901100 0x100>; 265 clocks = <&bpmp TEGRA194_CLK_I2S2>, 266 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 267 clock-names = "i2s", "sync_input"; 268 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 269 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 270 assigned-clock-rates = <1536000>; 271 sound-name-prefix = "I2S2"; 272 status = "disabled"; 273 }; 274 275 tegra_i2s3: i2s@2901200 { 276 compatible = "nvidia,tegra194-i2s", 277 "nvidia,tegra210-i2s"; 278 reg = <0x2901200 0x100>; 279 clocks = <&bpmp TEGRA194_CLK_I2S3>, 280 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 281 clock-names = "i2s", "sync_input"; 282 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 283 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 284 assigned-clock-rates = <1536000>; 285 sound-name-prefix = "I2S3"; 286 status = "disabled"; 287 }; 288 289 tegra_i2s4: i2s@2901300 { 290 compatible = "nvidia,tegra194-i2s", 291 "nvidia,tegra210-i2s"; 292 reg = <0x2901300 0x100>; 293 clocks = <&bpmp TEGRA194_CLK_I2S4>, 294 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 295 clock-names = "i2s", "sync_input"; 296 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 297 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 298 assigned-clock-rates = <1536000>; 299 sound-name-prefix = "I2S4"; 300 status = "disabled"; 301 }; 302 303 tegra_i2s5: i2s@2901400 { 304 compatible = "nvidia,tegra194-i2s", 305 "nvidia,tegra210-i2s"; 306 reg = <0x2901400 0x100>; 307 clocks = <&bpmp TEGRA194_CLK_I2S5>, 308 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 309 clock-names = "i2s", "sync_input"; 310 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 311 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 312 assigned-clock-rates = <1536000>; 313 sound-name-prefix = "I2S5"; 314 status = "disabled"; 315 }; 316 317 tegra_i2s6: i2s@2901500 { 318 compatible = "nvidia,tegra194-i2s", 319 "nvidia,tegra210-i2s"; 320 reg = <0x2901500 0x100>; 321 clocks = <&bpmp TEGRA194_CLK_I2S6>, 322 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 323 clock-names = "i2s", "sync_input"; 324 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 325 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 326 assigned-clock-rates = <1536000>; 327 sound-name-prefix = "I2S6"; 328 status = "disabled"; 329 }; 330 331 tegra_dmic1: dmic@2904000 { 332 compatible = "nvidia,tegra194-dmic", 333 "nvidia,tegra210-dmic"; 334 reg = <0x2904000 0x100>; 335 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 336 clock-names = "dmic"; 337 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 338 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 339 assigned-clock-rates = <3072000>; 340 sound-name-prefix = "DMIC1"; 341 status = "disabled"; 342 }; 343 344 tegra_dmic2: dmic@2904100 { 345 compatible = "nvidia,tegra194-dmic", 346 "nvidia,tegra210-dmic"; 347 reg = <0x2904100 0x100>; 348 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 349 clock-names = "dmic"; 350 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 351 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 352 assigned-clock-rates = <3072000>; 353 sound-name-prefix = "DMIC2"; 354 status = "disabled"; 355 }; 356 357 tegra_dmic3: dmic@2904200 { 358 compatible = "nvidia,tegra194-dmic", 359 "nvidia,tegra210-dmic"; 360 reg = <0x2904200 0x100>; 361 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 362 clock-names = "dmic"; 363 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 364 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 365 assigned-clock-rates = <3072000>; 366 sound-name-prefix = "DMIC3"; 367 status = "disabled"; 368 }; 369 370 tegra_dmic4: dmic@2904300 { 371 compatible = "nvidia,tegra194-dmic", 372 "nvidia,tegra210-dmic"; 373 reg = <0x2904300 0x100>; 374 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 375 clock-names = "dmic"; 376 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 377 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 378 assigned-clock-rates = <3072000>; 379 sound-name-prefix = "DMIC4"; 380 status = "disabled"; 381 }; 382 383 tegra_dspk1: dspk@2905000 { 384 compatible = "nvidia,tegra194-dspk", 385 "nvidia,tegra186-dspk"; 386 reg = <0x2905000 0x100>; 387 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 388 clock-names = "dspk"; 389 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 390 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 391 assigned-clock-rates = <12288000>; 392 sound-name-prefix = "DSPK1"; 393 status = "disabled"; 394 }; 395 396 tegra_dspk2: dspk@2905100 { 397 compatible = "nvidia,tegra194-dspk", 398 "nvidia,tegra186-dspk"; 399 reg = <0x2905100 0x100>; 400 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 401 clock-names = "dspk"; 402 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 403 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 404 assigned-clock-rates = <12288000>; 405 sound-name-prefix = "DSPK2"; 406 status = "disabled"; 407 }; 408 409 tegra_sfc1: sfc@2902000 { 410 compatible = "nvidia,tegra194-sfc", 411 "nvidia,tegra210-sfc"; 412 reg = <0x2902000 0x200>; 413 sound-name-prefix = "SFC1"; 414 status = "disabled"; 415 }; 416 417 tegra_sfc2: sfc@2902200 { 418 compatible = "nvidia,tegra194-sfc", 419 "nvidia,tegra210-sfc"; 420 reg = <0x2902200 0x200>; 421 sound-name-prefix = "SFC2"; 422 status = "disabled"; 423 }; 424 425 tegra_sfc3: sfc@2902400 { 426 compatible = "nvidia,tegra194-sfc", 427 "nvidia,tegra210-sfc"; 428 reg = <0x2902400 0x200>; 429 sound-name-prefix = "SFC3"; 430 status = "disabled"; 431 }; 432 433 tegra_sfc4: sfc@2902600 { 434 compatible = "nvidia,tegra194-sfc", 435 "nvidia,tegra210-sfc"; 436 reg = <0x2902600 0x200>; 437 sound-name-prefix = "SFC4"; 438 status = "disabled"; 439 }; 440 441 tegra_mvc1: mvc@290a000 { 442 compatible = "nvidia,tegra194-mvc", 443 "nvidia,tegra210-mvc"; 444 reg = <0x290a000 0x200>; 445 sound-name-prefix = "MVC1"; 446 status = "disabled"; 447 }; 448 449 tegra_mvc2: mvc@290a200 { 450 compatible = "nvidia,tegra194-mvc", 451 "nvidia,tegra210-mvc"; 452 reg = <0x290a200 0x200>; 453 sound-name-prefix = "MVC2"; 454 status = "disabled"; 455 }; 456 457 tegra_amx1: amx@2903000 { 458 compatible = "nvidia,tegra194-amx"; 459 reg = <0x2903000 0x100>; 460 sound-name-prefix = "AMX1"; 461 status = "disabled"; 462 }; 463 464 tegra_amx2: amx@2903100 { 465 compatible = "nvidia,tegra194-amx"; 466 reg = <0x2903100 0x100>; 467 sound-name-prefix = "AMX2"; 468 status = "disabled"; 469 }; 470 471 tegra_amx3: amx@2903200 { 472 compatible = "nvidia,tegra194-amx"; 473 reg = <0x2903200 0x100>; 474 sound-name-prefix = "AMX3"; 475 status = "disabled"; 476 }; 477 478 tegra_amx4: amx@2903300 { 479 compatible = "nvidia,tegra194-amx"; 480 reg = <0x2903300 0x100>; 481 sound-name-prefix = "AMX4"; 482 status = "disabled"; 483 }; 484 485 tegra_adx1: adx@2903800 { 486 compatible = "nvidia,tegra194-adx", 487 "nvidia,tegra210-adx"; 488 reg = <0x2903800 0x100>; 489 sound-name-prefix = "ADX1"; 490 status = "disabled"; 491 }; 492 493 tegra_adx2: adx@2903900 { 494 compatible = "nvidia,tegra194-adx", 495 "nvidia,tegra210-adx"; 496 reg = <0x2903900 0x100>; 497 sound-name-prefix = "ADX2"; 498 status = "disabled"; 499 }; 500 501 tegra_adx3: adx@2903a00 { 502 compatible = "nvidia,tegra194-adx", 503 "nvidia,tegra210-adx"; 504 reg = <0x2903a00 0x100>; 505 sound-name-prefix = "ADX3"; 506 status = "disabled"; 507 }; 508 509 tegra_adx4: adx@2903b00 { 510 compatible = "nvidia,tegra194-adx", 511 "nvidia,tegra210-adx"; 512 reg = <0x2903b00 0x100>; 513 sound-name-prefix = "ADX4"; 514 status = "disabled"; 515 }; 516 517 tegra_amixer: amixer@290bb00 { 518 compatible = "nvidia,tegra194-amixer", 519 "nvidia,tegra210-amixer"; 520 reg = <0x290bb00 0x800>; 521 sound-name-prefix = "MIXER1"; 522 status = "disabled"; 523 }; 524 }; 525 }; 526 527 pinmux: pinmux@2430000 { 528 compatible = "nvidia,tegra194-pinmux"; 529 reg = <0x2430000 0x17000>, 530 <0xc300000 0x4000>; 531 532 status = "okay"; 533 534 pex_rst_c5_out_state: pex_rst_c5_out { 535 pex_rst { 536 nvidia,pins = "pex_l5_rst_n_pgg1"; 537 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 538 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 539 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 540 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 541 nvidia,tristate = <TEGRA_PIN_DISABLE>; 542 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 543 }; 544 }; 545 546 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 547 clkreq { 548 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 549 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 550 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 551 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 552 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 553 nvidia,tristate = <TEGRA_PIN_DISABLE>; 554 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 555 }; 556 }; 557 }; 558 559 mc: memory-controller@2c00000 { 560 compatible = "nvidia,tegra194-mc"; 561 reg = <0x02c00000 0x100000>, 562 <0x02b80000 0x040000>, 563 <0x01700000 0x100000>; 564 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 565 #interconnect-cells = <1>; 566 status = "disabled"; 567 568 #address-cells = <2>; 569 #size-cells = <2>; 570 571 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 572 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 573 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 574 575 /* 576 * Bit 39 of addresses passing through the memory 577 * controller selects the XBAR format used when memory 578 * is accessed. This is used to transparently access 579 * memory in the XBAR format used by the discrete GPU 580 * (bit 39 set) or Tegra (bit 39 clear). 581 * 582 * As a consequence, the operating system must ensure 583 * that bit 39 is never used implicitly, for example 584 * via an I/O virtual address mapping of an IOMMU. If 585 * devices require access to the XBAR switch, their 586 * drivers must set this bit explicitly. 587 * 588 * Limit the DMA range for memory clients to [38:0]. 589 */ 590 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 591 592 emc: external-memory-controller@2c60000 { 593 compatible = "nvidia,tegra194-emc"; 594 reg = <0x0 0x02c60000 0x0 0x90000>, 595 <0x0 0x01780000 0x0 0x80000>; 596 clocks = <&bpmp TEGRA194_CLK_EMC>; 597 clock-names = "emc"; 598 599 #interconnect-cells = <0>; 600 601 nvidia,bpmp = <&bpmp>; 602 }; 603 }; 604 605 uarta: serial@3100000 { 606 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 607 reg = <0x03100000 0x40>; 608 reg-shift = <2>; 609 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&bpmp TEGRA194_CLK_UARTA>; 611 clock-names = "serial"; 612 resets = <&bpmp TEGRA194_RESET_UARTA>; 613 reset-names = "serial"; 614 status = "disabled"; 615 }; 616 617 uartb: serial@3110000 { 618 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 619 reg = <0x03110000 0x40>; 620 reg-shift = <2>; 621 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&bpmp TEGRA194_CLK_UARTB>; 623 clock-names = "serial"; 624 resets = <&bpmp TEGRA194_RESET_UARTB>; 625 reset-names = "serial"; 626 status = "disabled"; 627 }; 628 629 uartd: serial@3130000 { 630 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 631 reg = <0x03130000 0x40>; 632 reg-shift = <2>; 633 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&bpmp TEGRA194_CLK_UARTD>; 635 clock-names = "serial"; 636 resets = <&bpmp TEGRA194_RESET_UARTD>; 637 reset-names = "serial"; 638 status = "disabled"; 639 }; 640 641 uarte: serial@3140000 { 642 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 643 reg = <0x03140000 0x40>; 644 reg-shift = <2>; 645 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&bpmp TEGRA194_CLK_UARTE>; 647 clock-names = "serial"; 648 resets = <&bpmp TEGRA194_RESET_UARTE>; 649 reset-names = "serial"; 650 status = "disabled"; 651 }; 652 653 uartf: serial@3150000 { 654 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 655 reg = <0x03150000 0x40>; 656 reg-shift = <2>; 657 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&bpmp TEGRA194_CLK_UARTF>; 659 clock-names = "serial"; 660 resets = <&bpmp TEGRA194_RESET_UARTF>; 661 reset-names = "serial"; 662 status = "disabled"; 663 }; 664 665 gen1_i2c: i2c@3160000 { 666 compatible = "nvidia,tegra194-i2c"; 667 reg = <0x03160000 0x10000>; 668 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 clocks = <&bpmp TEGRA194_CLK_I2C1>; 672 clock-names = "div-clk"; 673 resets = <&bpmp TEGRA194_RESET_I2C1>; 674 reset-names = "i2c"; 675 status = "disabled"; 676 }; 677 678 uarth: serial@3170000 { 679 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 680 reg = <0x03170000 0x40>; 681 reg-shift = <2>; 682 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&bpmp TEGRA194_CLK_UARTH>; 684 clock-names = "serial"; 685 resets = <&bpmp TEGRA194_RESET_UARTH>; 686 reset-names = "serial"; 687 status = "disabled"; 688 }; 689 690 cam_i2c: i2c@3180000 { 691 compatible = "nvidia,tegra194-i2c"; 692 reg = <0x03180000 0x10000>; 693 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 clocks = <&bpmp TEGRA194_CLK_I2C3>; 697 clock-names = "div-clk"; 698 resets = <&bpmp TEGRA194_RESET_I2C3>; 699 reset-names = "i2c"; 700 status = "disabled"; 701 }; 702 703 /* shares pads with dpaux1 */ 704 dp_aux_ch1_i2c: i2c@3190000 { 705 compatible = "nvidia,tegra194-i2c"; 706 reg = <0x03190000 0x10000>; 707 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 clocks = <&bpmp TEGRA194_CLK_I2C4>; 711 clock-names = "div-clk"; 712 resets = <&bpmp TEGRA194_RESET_I2C4>; 713 reset-names = "i2c"; 714 pinctrl-0 = <&state_dpaux1_i2c>; 715 pinctrl-1 = <&state_dpaux1_off>; 716 pinctrl-names = "default", "idle"; 717 status = "disabled"; 718 }; 719 720 /* shares pads with dpaux0 */ 721 dp_aux_ch0_i2c: i2c@31b0000 { 722 compatible = "nvidia,tegra194-i2c"; 723 reg = <0x031b0000 0x10000>; 724 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 clocks = <&bpmp TEGRA194_CLK_I2C6>; 728 clock-names = "div-clk"; 729 resets = <&bpmp TEGRA194_RESET_I2C6>; 730 reset-names = "i2c"; 731 pinctrl-0 = <&state_dpaux0_i2c>; 732 pinctrl-1 = <&state_dpaux0_off>; 733 pinctrl-names = "default", "idle"; 734 status = "disabled"; 735 }; 736 737 /* shares pads with dpaux2 */ 738 dp_aux_ch2_i2c: i2c@31c0000 { 739 compatible = "nvidia,tegra194-i2c"; 740 reg = <0x031c0000 0x10000>; 741 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 clocks = <&bpmp TEGRA194_CLK_I2C7>; 745 clock-names = "div-clk"; 746 resets = <&bpmp TEGRA194_RESET_I2C7>; 747 reset-names = "i2c"; 748 pinctrl-0 = <&state_dpaux2_i2c>; 749 pinctrl-1 = <&state_dpaux2_off>; 750 pinctrl-names = "default", "idle"; 751 status = "disabled"; 752 }; 753 754 /* shares pads with dpaux3 */ 755 dp_aux_ch3_i2c: i2c@31e0000 { 756 compatible = "nvidia,tegra194-i2c"; 757 reg = <0x031e0000 0x10000>; 758 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 clocks = <&bpmp TEGRA194_CLK_I2C9>; 762 clock-names = "div-clk"; 763 resets = <&bpmp TEGRA194_RESET_I2C9>; 764 reset-names = "i2c"; 765 pinctrl-0 = <&state_dpaux3_i2c>; 766 pinctrl-1 = <&state_dpaux3_off>; 767 pinctrl-names = "default", "idle"; 768 status = "disabled"; 769 }; 770 771 spi@3270000 { 772 compatible = "nvidia,tegra194-qspi"; 773 reg = <0x3270000 0x1000>; 774 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 775 #address-cells = <1>; 776 #size-cells = <0>; 777 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 778 <&bpmp TEGRA194_CLK_QSPI0_PM>; 779 clock-names = "qspi", "qspi_out"; 780 resets = <&bpmp TEGRA194_RESET_QSPI0>; 781 reset-names = "qspi"; 782 status = "disabled"; 783 }; 784 785 spi@3300000 { 786 compatible = "nvidia,tegra194-qspi"; 787 reg = <0x3300000 0x1000>; 788 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 792 <&bpmp TEGRA194_CLK_QSPI1_PM>; 793 clock-names = "qspi", "qspi_out"; 794 resets = <&bpmp TEGRA194_RESET_QSPI1>; 795 reset-names = "qspi"; 796 status = "disabled"; 797 }; 798 799 pwm1: pwm@3280000 { 800 compatible = "nvidia,tegra194-pwm", 801 "nvidia,tegra186-pwm"; 802 reg = <0x3280000 0x10000>; 803 clocks = <&bpmp TEGRA194_CLK_PWM1>; 804 clock-names = "pwm"; 805 resets = <&bpmp TEGRA194_RESET_PWM1>; 806 reset-names = "pwm"; 807 status = "disabled"; 808 #pwm-cells = <2>; 809 }; 810 811 pwm2: pwm@3290000 { 812 compatible = "nvidia,tegra194-pwm", 813 "nvidia,tegra186-pwm"; 814 reg = <0x3290000 0x10000>; 815 clocks = <&bpmp TEGRA194_CLK_PWM2>; 816 clock-names = "pwm"; 817 resets = <&bpmp TEGRA194_RESET_PWM2>; 818 reset-names = "pwm"; 819 status = "disabled"; 820 #pwm-cells = <2>; 821 }; 822 823 pwm3: pwm@32a0000 { 824 compatible = "nvidia,tegra194-pwm", 825 "nvidia,tegra186-pwm"; 826 reg = <0x32a0000 0x10000>; 827 clocks = <&bpmp TEGRA194_CLK_PWM3>; 828 clock-names = "pwm"; 829 resets = <&bpmp TEGRA194_RESET_PWM3>; 830 reset-names = "pwm"; 831 status = "disabled"; 832 #pwm-cells = <2>; 833 }; 834 835 pwm5: pwm@32c0000 { 836 compatible = "nvidia,tegra194-pwm", 837 "nvidia,tegra186-pwm"; 838 reg = <0x32c0000 0x10000>; 839 clocks = <&bpmp TEGRA194_CLK_PWM5>; 840 clock-names = "pwm"; 841 resets = <&bpmp TEGRA194_RESET_PWM5>; 842 reset-names = "pwm"; 843 status = "disabled"; 844 #pwm-cells = <2>; 845 }; 846 847 pwm6: pwm@32d0000 { 848 compatible = "nvidia,tegra194-pwm", 849 "nvidia,tegra186-pwm"; 850 reg = <0x32d0000 0x10000>; 851 clocks = <&bpmp TEGRA194_CLK_PWM6>; 852 clock-names = "pwm"; 853 resets = <&bpmp TEGRA194_RESET_PWM6>; 854 reset-names = "pwm"; 855 status = "disabled"; 856 #pwm-cells = <2>; 857 }; 858 859 pwm7: pwm@32e0000 { 860 compatible = "nvidia,tegra194-pwm", 861 "nvidia,tegra186-pwm"; 862 reg = <0x32e0000 0x10000>; 863 clocks = <&bpmp TEGRA194_CLK_PWM7>; 864 clock-names = "pwm"; 865 resets = <&bpmp TEGRA194_RESET_PWM7>; 866 reset-names = "pwm"; 867 status = "disabled"; 868 #pwm-cells = <2>; 869 }; 870 871 pwm8: pwm@32f0000 { 872 compatible = "nvidia,tegra194-pwm", 873 "nvidia,tegra186-pwm"; 874 reg = <0x32f0000 0x10000>; 875 clocks = <&bpmp TEGRA194_CLK_PWM8>; 876 clock-names = "pwm"; 877 resets = <&bpmp TEGRA194_RESET_PWM8>; 878 reset-names = "pwm"; 879 status = "disabled"; 880 #pwm-cells = <2>; 881 }; 882 883 sdmmc1: mmc@3400000 { 884 compatible = "nvidia,tegra194-sdhci"; 885 reg = <0x03400000 0x10000>; 886 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 888 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 889 clock-names = "sdhci", "tmclk"; 890 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 891 reset-names = "sdhci"; 892 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 893 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 894 interconnect-names = "dma-mem", "write"; 895 iommus = <&smmu TEGRA194_SID_SDMMC1>; 896 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 897 <0x07>; 898 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 899 <0x07>; 900 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 901 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 902 <0x07>; 903 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 904 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 905 nvidia,default-tap = <0x9>; 906 nvidia,default-trim = <0x5>; 907 status = "disabled"; 908 }; 909 910 sdmmc3: mmc@3440000 { 911 compatible = "nvidia,tegra194-sdhci"; 912 reg = <0x03440000 0x10000>; 913 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 915 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 916 clock-names = "sdhci", "tmclk"; 917 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 918 reset-names = "sdhci"; 919 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 920 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 921 interconnect-names = "dma-mem", "write"; 922 iommus = <&smmu TEGRA194_SID_SDMMC3>; 923 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 924 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 925 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 926 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 927 <0x07>; 928 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 929 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 930 <0x07>; 931 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 932 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 933 nvidia,default-tap = <0x9>; 934 nvidia,default-trim = <0x5>; 935 status = "disabled"; 936 }; 937 938 sdmmc4: mmc@3460000 { 939 compatible = "nvidia,tegra194-sdhci"; 940 reg = <0x03460000 0x10000>; 941 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 942 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 943 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 944 clock-names = "sdhci", "tmclk"; 945 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 946 <&bpmp TEGRA194_CLK_PLLC4>; 947 assigned-clock-parents = 948 <&bpmp TEGRA194_CLK_PLLC4>; 949 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 950 reset-names = "sdhci"; 951 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 952 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 953 interconnect-names = "dma-mem", "write"; 954 iommus = <&smmu TEGRA194_SID_SDMMC4>; 955 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 956 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 957 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 958 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 959 <0x0a>; 960 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 961 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 962 <0x0a>; 963 nvidia,default-tap = <0x8>; 964 nvidia,default-trim = <0x14>; 965 nvidia,dqs-trim = <40>; 966 supports-cqe; 967 status = "disabled"; 968 }; 969 970 hda@3510000 { 971 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 972 reg = <0x3510000 0x10000>; 973 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&bpmp TEGRA194_CLK_HDA>, 975 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 976 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 977 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 978 resets = <&bpmp TEGRA194_RESET_HDA>, 979 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 980 reset-names = "hda", "hda2hdmi"; 981 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 982 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 983 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 984 interconnect-names = "dma-mem", "write"; 985 iommus = <&smmu TEGRA194_SID_HDA>; 986 status = "disabled"; 987 }; 988 989 xusb_padctl: padctl@3520000 { 990 compatible = "nvidia,tegra194-xusb-padctl"; 991 reg = <0x03520000 0x1000>, 992 <0x03540000 0x1000>; 993 reg-names = "padctl", "ao"; 994 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 995 996 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 997 reset-names = "padctl"; 998 999 status = "disabled"; 1000 1001 pads { 1002 usb2 { 1003 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1004 clock-names = "trk"; 1005 1006 lanes { 1007 usb2-0 { 1008 nvidia,function = "xusb"; 1009 status = "disabled"; 1010 #phy-cells = <0>; 1011 }; 1012 1013 usb2-1 { 1014 nvidia,function = "xusb"; 1015 status = "disabled"; 1016 #phy-cells = <0>; 1017 }; 1018 1019 usb2-2 { 1020 nvidia,function = "xusb"; 1021 status = "disabled"; 1022 #phy-cells = <0>; 1023 }; 1024 1025 usb2-3 { 1026 nvidia,function = "xusb"; 1027 status = "disabled"; 1028 #phy-cells = <0>; 1029 }; 1030 }; 1031 }; 1032 1033 usb3 { 1034 lanes { 1035 usb3-0 { 1036 nvidia,function = "xusb"; 1037 status = "disabled"; 1038 #phy-cells = <0>; 1039 }; 1040 1041 usb3-1 { 1042 nvidia,function = "xusb"; 1043 status = "disabled"; 1044 #phy-cells = <0>; 1045 }; 1046 1047 usb3-2 { 1048 nvidia,function = "xusb"; 1049 status = "disabled"; 1050 #phy-cells = <0>; 1051 }; 1052 1053 usb3-3 { 1054 nvidia,function = "xusb"; 1055 status = "disabled"; 1056 #phy-cells = <0>; 1057 }; 1058 }; 1059 }; 1060 }; 1061 1062 ports { 1063 usb2-0 { 1064 status = "disabled"; 1065 }; 1066 1067 usb2-1 { 1068 status = "disabled"; 1069 }; 1070 1071 usb2-2 { 1072 status = "disabled"; 1073 }; 1074 1075 usb2-3 { 1076 status = "disabled"; 1077 }; 1078 1079 usb3-0 { 1080 status = "disabled"; 1081 }; 1082 1083 usb3-1 { 1084 status = "disabled"; 1085 }; 1086 1087 usb3-2 { 1088 status = "disabled"; 1089 }; 1090 1091 usb3-3 { 1092 status = "disabled"; 1093 }; 1094 }; 1095 }; 1096 1097 usb@3550000 { 1098 compatible = "nvidia,tegra194-xudc"; 1099 reg = <0x03550000 0x8000>, 1100 <0x03558000 0x1000>; 1101 reg-names = "base", "fpci"; 1102 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1104 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1105 <&bpmp TEGRA194_CLK_XUSB_SS>, 1106 <&bpmp TEGRA194_CLK_XUSB_FS>; 1107 clock-names = "dev", "ss", "ss_src", "fs_src"; 1108 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1109 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1110 interconnect-names = "dma-mem", "write"; 1111 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1112 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1113 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1114 power-domain-names = "dev", "ss"; 1115 nvidia,xusb-padctl = <&xusb_padctl>; 1116 status = "disabled"; 1117 }; 1118 1119 usb@3610000 { 1120 compatible = "nvidia,tegra194-xusb"; 1121 reg = <0x03610000 0x40000>, 1122 <0x03600000 0x10000>; 1123 reg-names = "hcd", "fpci"; 1124 1125 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1127 1128 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1129 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1130 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1131 <&bpmp TEGRA194_CLK_XUSB_SS>, 1132 <&bpmp TEGRA194_CLK_CLK_M>, 1133 <&bpmp TEGRA194_CLK_XUSB_FS>, 1134 <&bpmp TEGRA194_CLK_UTMIPLL>, 1135 <&bpmp TEGRA194_CLK_CLK_M>, 1136 <&bpmp TEGRA194_CLK_PLLE>; 1137 clock-names = "xusb_host", "xusb_falcon_src", 1138 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1139 "xusb_fs_src", "pll_u_480m", "clk_m", 1140 "pll_e"; 1141 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1142 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1143 interconnect-names = "dma-mem", "write"; 1144 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1145 1146 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1147 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1148 power-domain-names = "xusb_host", "xusb_ss"; 1149 1150 nvidia,xusb-padctl = <&xusb_padctl>; 1151 status = "disabled"; 1152 }; 1153 1154 fuse@3820000 { 1155 compatible = "nvidia,tegra194-efuse"; 1156 reg = <0x03820000 0x10000>; 1157 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1158 clock-names = "fuse"; 1159 }; 1160 1161 gic: interrupt-controller@3881000 { 1162 compatible = "arm,gic-400"; 1163 #interrupt-cells = <3>; 1164 interrupt-controller; 1165 reg = <0x03881000 0x1000>, 1166 <0x03882000 0x2000>, 1167 <0x03884000 0x2000>, 1168 <0x03886000 0x2000>; 1169 interrupts = <GIC_PPI 9 1170 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1171 interrupt-parent = <&gic>; 1172 }; 1173 1174 cec@3960000 { 1175 compatible = "nvidia,tegra194-cec"; 1176 reg = <0x03960000 0x10000>; 1177 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1178 clocks = <&bpmp TEGRA194_CLK_CEC>; 1179 clock-names = "cec"; 1180 status = "disabled"; 1181 }; 1182 1183 hsp_top0: hsp@3c00000 { 1184 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1185 reg = <0x03c00000 0xa0000>; 1186 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1195 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1196 "shared3", "shared4", "shared5", "shared6", 1197 "shared7"; 1198 #mbox-cells = <2>; 1199 }; 1200 1201 p2u_hsio_0: phy@3e10000 { 1202 compatible = "nvidia,tegra194-p2u"; 1203 reg = <0x03e10000 0x10000>; 1204 reg-names = "ctl"; 1205 1206 #phy-cells = <0>; 1207 }; 1208 1209 p2u_hsio_1: phy@3e20000 { 1210 compatible = "nvidia,tegra194-p2u"; 1211 reg = <0x03e20000 0x10000>; 1212 reg-names = "ctl"; 1213 1214 #phy-cells = <0>; 1215 }; 1216 1217 p2u_hsio_2: phy@3e30000 { 1218 compatible = "nvidia,tegra194-p2u"; 1219 reg = <0x03e30000 0x10000>; 1220 reg-names = "ctl"; 1221 1222 #phy-cells = <0>; 1223 }; 1224 1225 p2u_hsio_3: phy@3e40000 { 1226 compatible = "nvidia,tegra194-p2u"; 1227 reg = <0x03e40000 0x10000>; 1228 reg-names = "ctl"; 1229 1230 #phy-cells = <0>; 1231 }; 1232 1233 p2u_hsio_4: phy@3e50000 { 1234 compatible = "nvidia,tegra194-p2u"; 1235 reg = <0x03e50000 0x10000>; 1236 reg-names = "ctl"; 1237 1238 #phy-cells = <0>; 1239 }; 1240 1241 p2u_hsio_5: phy@3e60000 { 1242 compatible = "nvidia,tegra194-p2u"; 1243 reg = <0x03e60000 0x10000>; 1244 reg-names = "ctl"; 1245 1246 #phy-cells = <0>; 1247 }; 1248 1249 p2u_hsio_6: phy@3e70000 { 1250 compatible = "nvidia,tegra194-p2u"; 1251 reg = <0x03e70000 0x10000>; 1252 reg-names = "ctl"; 1253 1254 #phy-cells = <0>; 1255 }; 1256 1257 p2u_hsio_7: phy@3e80000 { 1258 compatible = "nvidia,tegra194-p2u"; 1259 reg = <0x03e80000 0x10000>; 1260 reg-names = "ctl"; 1261 1262 #phy-cells = <0>; 1263 }; 1264 1265 p2u_hsio_8: phy@3e90000 { 1266 compatible = "nvidia,tegra194-p2u"; 1267 reg = <0x03e90000 0x10000>; 1268 reg-names = "ctl"; 1269 1270 #phy-cells = <0>; 1271 }; 1272 1273 p2u_hsio_9: phy@3ea0000 { 1274 compatible = "nvidia,tegra194-p2u"; 1275 reg = <0x03ea0000 0x10000>; 1276 reg-names = "ctl"; 1277 1278 #phy-cells = <0>; 1279 }; 1280 1281 p2u_nvhs_0: phy@3eb0000 { 1282 compatible = "nvidia,tegra194-p2u"; 1283 reg = <0x03eb0000 0x10000>; 1284 reg-names = "ctl"; 1285 1286 #phy-cells = <0>; 1287 }; 1288 1289 p2u_nvhs_1: phy@3ec0000 { 1290 compatible = "nvidia,tegra194-p2u"; 1291 reg = <0x03ec0000 0x10000>; 1292 reg-names = "ctl"; 1293 1294 #phy-cells = <0>; 1295 }; 1296 1297 p2u_nvhs_2: phy@3ed0000 { 1298 compatible = "nvidia,tegra194-p2u"; 1299 reg = <0x03ed0000 0x10000>; 1300 reg-names = "ctl"; 1301 1302 #phy-cells = <0>; 1303 }; 1304 1305 p2u_nvhs_3: phy@3ee0000 { 1306 compatible = "nvidia,tegra194-p2u"; 1307 reg = <0x03ee0000 0x10000>; 1308 reg-names = "ctl"; 1309 1310 #phy-cells = <0>; 1311 }; 1312 1313 p2u_nvhs_4: phy@3ef0000 { 1314 compatible = "nvidia,tegra194-p2u"; 1315 reg = <0x03ef0000 0x10000>; 1316 reg-names = "ctl"; 1317 1318 #phy-cells = <0>; 1319 }; 1320 1321 p2u_nvhs_5: phy@3f00000 { 1322 compatible = "nvidia,tegra194-p2u"; 1323 reg = <0x03f00000 0x10000>; 1324 reg-names = "ctl"; 1325 1326 #phy-cells = <0>; 1327 }; 1328 1329 p2u_nvhs_6: phy@3f10000 { 1330 compatible = "nvidia,tegra194-p2u"; 1331 reg = <0x03f10000 0x10000>; 1332 reg-names = "ctl"; 1333 1334 #phy-cells = <0>; 1335 }; 1336 1337 p2u_nvhs_7: phy@3f20000 { 1338 compatible = "nvidia,tegra194-p2u"; 1339 reg = <0x03f20000 0x10000>; 1340 reg-names = "ctl"; 1341 1342 #phy-cells = <0>; 1343 }; 1344 1345 p2u_hsio_10: phy@3f30000 { 1346 compatible = "nvidia,tegra194-p2u"; 1347 reg = <0x03f30000 0x10000>; 1348 reg-names = "ctl"; 1349 1350 #phy-cells = <0>; 1351 }; 1352 1353 p2u_hsio_11: phy@3f40000 { 1354 compatible = "nvidia,tegra194-p2u"; 1355 reg = <0x03f40000 0x10000>; 1356 reg-names = "ctl"; 1357 1358 #phy-cells = <0>; 1359 }; 1360 1361 hsp_aon: hsp@c150000 { 1362 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1363 reg = <0x0c150000 0x90000>; 1364 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1368 /* 1369 * Shared interrupt 0 is routed only to AON/SPE, so 1370 * we only have 4 shared interrupts for the CCPLEX. 1371 */ 1372 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1373 #mbox-cells = <2>; 1374 }; 1375 1376 gen2_i2c: i2c@c240000 { 1377 compatible = "nvidia,tegra194-i2c"; 1378 reg = <0x0c240000 0x10000>; 1379 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1383 clock-names = "div-clk"; 1384 resets = <&bpmp TEGRA194_RESET_I2C2>; 1385 reset-names = "i2c"; 1386 status = "disabled"; 1387 }; 1388 1389 gen8_i2c: i2c@c250000 { 1390 compatible = "nvidia,tegra194-i2c"; 1391 reg = <0x0c250000 0x10000>; 1392 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1396 clock-names = "div-clk"; 1397 resets = <&bpmp TEGRA194_RESET_I2C8>; 1398 reset-names = "i2c"; 1399 status = "disabled"; 1400 }; 1401 1402 uartc: serial@c280000 { 1403 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1404 reg = <0x0c280000 0x40>; 1405 reg-shift = <2>; 1406 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1407 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1408 clock-names = "serial"; 1409 resets = <&bpmp TEGRA194_RESET_UARTC>; 1410 reset-names = "serial"; 1411 status = "disabled"; 1412 }; 1413 1414 uartg: serial@c290000 { 1415 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1416 reg = <0x0c290000 0x40>; 1417 reg-shift = <2>; 1418 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1419 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1420 clock-names = "serial"; 1421 resets = <&bpmp TEGRA194_RESET_UARTG>; 1422 reset-names = "serial"; 1423 status = "disabled"; 1424 }; 1425 1426 rtc: rtc@c2a0000 { 1427 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1428 reg = <0x0c2a0000 0x10000>; 1429 interrupt-parent = <&pmc>; 1430 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1431 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1432 clock-names = "rtc"; 1433 status = "disabled"; 1434 }; 1435 1436 gpio_aon: gpio@c2f0000 { 1437 compatible = "nvidia,tegra194-gpio-aon"; 1438 reg-names = "security", "gpio"; 1439 reg = <0xc2f0000 0x1000>, 1440 <0xc2f1000 0x1000>; 1441 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1445 gpio-controller; 1446 #gpio-cells = <2>; 1447 interrupt-controller; 1448 #interrupt-cells = <2>; 1449 }; 1450 1451 pwm4: pwm@c340000 { 1452 compatible = "nvidia,tegra194-pwm", 1453 "nvidia,tegra186-pwm"; 1454 reg = <0xc340000 0x10000>; 1455 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1456 clock-names = "pwm"; 1457 resets = <&bpmp TEGRA194_RESET_PWM4>; 1458 reset-names = "pwm"; 1459 status = "disabled"; 1460 #pwm-cells = <2>; 1461 }; 1462 1463 pmc: pmc@c360000 { 1464 compatible = "nvidia,tegra194-pmc"; 1465 reg = <0x0c360000 0x10000>, 1466 <0x0c370000 0x10000>, 1467 <0x0c380000 0x10000>, 1468 <0x0c390000 0x10000>, 1469 <0x0c3a0000 0x10000>; 1470 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1471 1472 #interrupt-cells = <2>; 1473 interrupt-controller; 1474 }; 1475 1476 smmu: iommu@12000000 { 1477 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1478 reg = <0x12000000 0x800000>, 1479 <0x11000000 0x800000>; 1480 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1546 stream-match-mask = <0x7f80>; 1547 #global-interrupts = <2>; 1548 #iommu-cells = <1>; 1549 1550 nvidia,memory-controller = <&mc>; 1551 status = "okay"; 1552 }; 1553 1554 host1x@13e00000 { 1555 compatible = "nvidia,tegra194-host1x"; 1556 reg = <0x13e00000 0x10000>, 1557 <0x13e10000 0x10000>; 1558 reg-names = "hypervisor", "vm"; 1559 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1561 interrupt-names = "syncpt", "host1x"; 1562 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1563 clock-names = "host1x"; 1564 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1565 reset-names = "host1x"; 1566 1567 #address-cells = <1>; 1568 #size-cells = <1>; 1569 1570 ranges = <0x15000000 0x15000000 0x01000000>; 1571 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1572 interconnect-names = "dma-mem"; 1573 iommus = <&smmu TEGRA194_SID_HOST1X>; 1574 1575 nvdec@15140000 { 1576 compatible = "nvidia,tegra194-nvdec"; 1577 reg = <0x15140000 0x00040000>; 1578 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1579 clock-names = "nvdec"; 1580 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1581 reset-names = "nvdec"; 1582 1583 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1584 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1585 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1586 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1587 interconnect-names = "dma-mem", "read-1", "write"; 1588 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1589 dma-coherent; 1590 1591 nvidia,host1x-class = <0xf5>; 1592 }; 1593 1594 display-hub@15200000 { 1595 compatible = "nvidia,tegra194-display"; 1596 reg = <0x15200000 0x00040000>; 1597 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1598 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1599 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1600 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1601 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1602 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1603 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1604 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1605 "wgrp3", "wgrp4", "wgrp5"; 1606 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1607 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1608 clock-names = "disp", "hub"; 1609 status = "disabled"; 1610 1611 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1612 1613 #address-cells = <1>; 1614 #size-cells = <1>; 1615 1616 ranges = <0x15200000 0x15200000 0x40000>; 1617 1618 display@15200000 { 1619 compatible = "nvidia,tegra194-dc"; 1620 reg = <0x15200000 0x10000>; 1621 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1622 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1623 clock-names = "dc"; 1624 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1625 reset-names = "dc"; 1626 1627 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1628 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1629 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1630 interconnect-names = "dma-mem", "read-1"; 1631 1632 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1633 nvidia,head = <0>; 1634 }; 1635 1636 display@15210000 { 1637 compatible = "nvidia,tegra194-dc"; 1638 reg = <0x15210000 0x10000>; 1639 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1640 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1641 clock-names = "dc"; 1642 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1643 reset-names = "dc"; 1644 1645 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1646 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1647 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1648 interconnect-names = "dma-mem", "read-1"; 1649 1650 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1651 nvidia,head = <1>; 1652 }; 1653 1654 display@15220000 { 1655 compatible = "nvidia,tegra194-dc"; 1656 reg = <0x15220000 0x10000>; 1657 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1658 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1659 clock-names = "dc"; 1660 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1661 reset-names = "dc"; 1662 1663 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1664 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1665 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1666 interconnect-names = "dma-mem", "read-1"; 1667 1668 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1669 nvidia,head = <2>; 1670 }; 1671 1672 display@15230000 { 1673 compatible = "nvidia,tegra194-dc"; 1674 reg = <0x15230000 0x10000>; 1675 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1676 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1677 clock-names = "dc"; 1678 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1679 reset-names = "dc"; 1680 1681 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1682 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1683 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1684 interconnect-names = "dma-mem", "read-1"; 1685 1686 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1687 nvidia,head = <3>; 1688 }; 1689 }; 1690 1691 vic@15340000 { 1692 compatible = "nvidia,tegra194-vic"; 1693 reg = <0x15340000 0x00040000>; 1694 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1695 clocks = <&bpmp TEGRA194_CLK_VIC>; 1696 clock-names = "vic"; 1697 resets = <&bpmp TEGRA194_RESET_VIC>; 1698 reset-names = "vic"; 1699 1700 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1701 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1702 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1703 interconnect-names = "dma-mem", "write"; 1704 iommus = <&smmu TEGRA194_SID_VIC>; 1705 }; 1706 1707 nvdec@15480000 { 1708 compatible = "nvidia,tegra194-nvdec"; 1709 reg = <0x15480000 0x00040000>; 1710 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 1711 clock-names = "nvdec"; 1712 resets = <&bpmp TEGRA194_RESET_NVDEC>; 1713 reset-names = "nvdec"; 1714 1715 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 1716 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 1717 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 1718 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 1719 interconnect-names = "dma-mem", "read-1", "write"; 1720 iommus = <&smmu TEGRA194_SID_NVDEC>; 1721 dma-coherent; 1722 1723 nvidia,host1x-class = <0xf0>; 1724 }; 1725 1726 dpaux0: dpaux@155c0000 { 1727 compatible = "nvidia,tegra194-dpaux"; 1728 reg = <0x155c0000 0x10000>; 1729 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1730 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1731 <&bpmp TEGRA194_CLK_PLLDP>; 1732 clock-names = "dpaux", "parent"; 1733 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1734 reset-names = "dpaux"; 1735 status = "disabled"; 1736 1737 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1738 1739 state_dpaux0_aux: pinmux-aux { 1740 groups = "dpaux-io"; 1741 function = "aux"; 1742 }; 1743 1744 state_dpaux0_i2c: pinmux-i2c { 1745 groups = "dpaux-io"; 1746 function = "i2c"; 1747 }; 1748 1749 state_dpaux0_off: pinmux-off { 1750 groups = "dpaux-io"; 1751 function = "off"; 1752 }; 1753 1754 i2c-bus { 1755 #address-cells = <1>; 1756 #size-cells = <0>; 1757 }; 1758 }; 1759 1760 dpaux1: dpaux@155d0000 { 1761 compatible = "nvidia,tegra194-dpaux"; 1762 reg = <0x155d0000 0x10000>; 1763 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1764 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1765 <&bpmp TEGRA194_CLK_PLLDP>; 1766 clock-names = "dpaux", "parent"; 1767 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1768 reset-names = "dpaux"; 1769 status = "disabled"; 1770 1771 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1772 1773 state_dpaux1_aux: pinmux-aux { 1774 groups = "dpaux-io"; 1775 function = "aux"; 1776 }; 1777 1778 state_dpaux1_i2c: pinmux-i2c { 1779 groups = "dpaux-io"; 1780 function = "i2c"; 1781 }; 1782 1783 state_dpaux1_off: pinmux-off { 1784 groups = "dpaux-io"; 1785 function = "off"; 1786 }; 1787 1788 i2c-bus { 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 }; 1792 }; 1793 1794 dpaux2: dpaux@155e0000 { 1795 compatible = "nvidia,tegra194-dpaux"; 1796 reg = <0x155e0000 0x10000>; 1797 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1798 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1799 <&bpmp TEGRA194_CLK_PLLDP>; 1800 clock-names = "dpaux", "parent"; 1801 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1802 reset-names = "dpaux"; 1803 status = "disabled"; 1804 1805 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1806 1807 state_dpaux2_aux: pinmux-aux { 1808 groups = "dpaux-io"; 1809 function = "aux"; 1810 }; 1811 1812 state_dpaux2_i2c: pinmux-i2c { 1813 groups = "dpaux-io"; 1814 function = "i2c"; 1815 }; 1816 1817 state_dpaux2_off: pinmux-off { 1818 groups = "dpaux-io"; 1819 function = "off"; 1820 }; 1821 1822 i2c-bus { 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 }; 1826 }; 1827 1828 dpaux3: dpaux@155f0000 { 1829 compatible = "nvidia,tegra194-dpaux"; 1830 reg = <0x155f0000 0x10000>; 1831 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1832 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1833 <&bpmp TEGRA194_CLK_PLLDP>; 1834 clock-names = "dpaux", "parent"; 1835 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1836 reset-names = "dpaux"; 1837 status = "disabled"; 1838 1839 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1840 1841 state_dpaux3_aux: pinmux-aux { 1842 groups = "dpaux-io"; 1843 function = "aux"; 1844 }; 1845 1846 state_dpaux3_i2c: pinmux-i2c { 1847 groups = "dpaux-io"; 1848 function = "i2c"; 1849 }; 1850 1851 state_dpaux3_off: pinmux-off { 1852 groups = "dpaux-io"; 1853 function = "off"; 1854 }; 1855 1856 i2c-bus { 1857 #address-cells = <1>; 1858 #size-cells = <0>; 1859 }; 1860 }; 1861 1862 sor0: sor@15b00000 { 1863 compatible = "nvidia,tegra194-sor"; 1864 reg = <0x15b00000 0x40000>; 1865 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1866 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1867 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1868 <&bpmp TEGRA194_CLK_PLLD>, 1869 <&bpmp TEGRA194_CLK_PLLDP>, 1870 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1871 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1872 clock-names = "sor", "out", "parent", "dp", "safe", 1873 "pad"; 1874 resets = <&bpmp TEGRA194_RESET_SOR0>; 1875 reset-names = "sor"; 1876 pinctrl-0 = <&state_dpaux0_aux>; 1877 pinctrl-1 = <&state_dpaux0_i2c>; 1878 pinctrl-2 = <&state_dpaux0_off>; 1879 pinctrl-names = "aux", "i2c", "off"; 1880 status = "disabled"; 1881 1882 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1883 nvidia,interface = <0>; 1884 }; 1885 1886 sor1: sor@15b40000 { 1887 compatible = "nvidia,tegra194-sor"; 1888 reg = <0x15b40000 0x40000>; 1889 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1890 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1891 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1892 <&bpmp TEGRA194_CLK_PLLD2>, 1893 <&bpmp TEGRA194_CLK_PLLDP>, 1894 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1895 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1896 clock-names = "sor", "out", "parent", "dp", "safe", 1897 "pad"; 1898 resets = <&bpmp TEGRA194_RESET_SOR1>; 1899 reset-names = "sor"; 1900 pinctrl-0 = <&state_dpaux1_aux>; 1901 pinctrl-1 = <&state_dpaux1_i2c>; 1902 pinctrl-2 = <&state_dpaux1_off>; 1903 pinctrl-names = "aux", "i2c", "off"; 1904 status = "disabled"; 1905 1906 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1907 nvidia,interface = <1>; 1908 }; 1909 1910 sor2: sor@15b80000 { 1911 compatible = "nvidia,tegra194-sor"; 1912 reg = <0x15b80000 0x40000>; 1913 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1914 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1915 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1916 <&bpmp TEGRA194_CLK_PLLD3>, 1917 <&bpmp TEGRA194_CLK_PLLDP>, 1918 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1919 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1920 clock-names = "sor", "out", "parent", "dp", "safe", 1921 "pad"; 1922 resets = <&bpmp TEGRA194_RESET_SOR2>; 1923 reset-names = "sor"; 1924 pinctrl-0 = <&state_dpaux2_aux>; 1925 pinctrl-1 = <&state_dpaux2_i2c>; 1926 pinctrl-2 = <&state_dpaux2_off>; 1927 pinctrl-names = "aux", "i2c", "off"; 1928 status = "disabled"; 1929 1930 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1931 nvidia,interface = <2>; 1932 }; 1933 1934 sor3: sor@15bc0000 { 1935 compatible = "nvidia,tegra194-sor"; 1936 reg = <0x15bc0000 0x40000>; 1937 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1938 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1939 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1940 <&bpmp TEGRA194_CLK_PLLD4>, 1941 <&bpmp TEGRA194_CLK_PLLDP>, 1942 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1943 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1944 clock-names = "sor", "out", "parent", "dp", "safe", 1945 "pad"; 1946 resets = <&bpmp TEGRA194_RESET_SOR3>; 1947 reset-names = "sor"; 1948 pinctrl-0 = <&state_dpaux3_aux>; 1949 pinctrl-1 = <&state_dpaux3_i2c>; 1950 pinctrl-2 = <&state_dpaux3_off>; 1951 pinctrl-names = "aux", "i2c", "off"; 1952 status = "disabled"; 1953 1954 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1955 nvidia,interface = <3>; 1956 }; 1957 }; 1958 1959 gpu@17000000 { 1960 compatible = "nvidia,gv11b"; 1961 reg = <0x17000000 0x1000000>, 1962 <0x18000000 0x1000000>; 1963 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1965 interrupt-names = "stall", "nonstall"; 1966 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 1967 <&bpmp TEGRA194_CLK_GPU_PWR>, 1968 <&bpmp TEGRA194_CLK_FUSE>; 1969 clock-names = "gpu", "pwr", "fuse"; 1970 resets = <&bpmp TEGRA194_RESET_GPU>; 1971 reset-names = "gpu"; 1972 dma-coherent; 1973 1974 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 1975 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 1976 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 1977 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 1978 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 1979 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 1980 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 1981 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 1982 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 1983 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 1984 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 1985 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 1986 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 1987 interconnect-names = "dma-mem", "read-0-hp", "write-0", 1988 "read-1", "read-1-hp", "write-1", 1989 "read-2", "read-2-hp", "write-2", 1990 "read-3", "read-3-hp", "write-3"; 1991 }; 1992 }; 1993 1994 pcie@14100000 { 1995 compatible = "nvidia,tegra194-pcie"; 1996 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1997 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1998 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1999 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2000 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2001 reg-names = "appl", "config", "atu_dma", "dbi"; 2002 2003 status = "disabled"; 2004 2005 #address-cells = <3>; 2006 #size-cells = <2>; 2007 device_type = "pci"; 2008 num-lanes = <1>; 2009 num-viewport = <8>; 2010 linux,pci-domain = <1>; 2011 2012 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2013 clock-names = "core"; 2014 2015 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2016 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2017 reset-names = "apb", "core"; 2018 2019 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2020 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2021 interrupt-names = "intr", "msi"; 2022 2023 #interrupt-cells = <1>; 2024 interrupt-map-mask = <0 0 0 0>; 2025 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2026 2027 nvidia,bpmp = <&bpmp 1>; 2028 2029 nvidia,aspm-cmrt-us = <60>; 2030 nvidia,aspm-pwr-on-t-us = <20>; 2031 nvidia,aspm-l0s-entrance-latency-us = <3>; 2032 2033 bus-range = <0x0 0xff>; 2034 2035 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2036 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2037 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2038 2039 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2040 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2041 interconnect-names = "dma-mem", "write"; 2042 iommus = <&smmu TEGRA194_SID_PCIE1>; 2043 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2044 iommu-map-mask = <0x0>; 2045 dma-coherent; 2046 }; 2047 2048 pcie@14120000 { 2049 compatible = "nvidia,tegra194-pcie"; 2050 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2051 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2052 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2053 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2054 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2055 reg-names = "appl", "config", "atu_dma", "dbi"; 2056 2057 status = "disabled"; 2058 2059 #address-cells = <3>; 2060 #size-cells = <2>; 2061 device_type = "pci"; 2062 num-lanes = <1>; 2063 num-viewport = <8>; 2064 linux,pci-domain = <2>; 2065 2066 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2067 clock-names = "core"; 2068 2069 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2070 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2071 reset-names = "apb", "core"; 2072 2073 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2074 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2075 interrupt-names = "intr", "msi"; 2076 2077 #interrupt-cells = <1>; 2078 interrupt-map-mask = <0 0 0 0>; 2079 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2080 2081 nvidia,bpmp = <&bpmp 2>; 2082 2083 nvidia,aspm-cmrt-us = <60>; 2084 nvidia,aspm-pwr-on-t-us = <20>; 2085 nvidia,aspm-l0s-entrance-latency-us = <3>; 2086 2087 bus-range = <0x0 0xff>; 2088 2089 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2090 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2091 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2092 2093 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2094 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2095 interconnect-names = "dma-mem", "write"; 2096 iommus = <&smmu TEGRA194_SID_PCIE2>; 2097 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2098 iommu-map-mask = <0x0>; 2099 dma-coherent; 2100 }; 2101 2102 pcie@14140000 { 2103 compatible = "nvidia,tegra194-pcie"; 2104 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2105 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2106 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2107 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2108 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2109 reg-names = "appl", "config", "atu_dma", "dbi"; 2110 2111 status = "disabled"; 2112 2113 #address-cells = <3>; 2114 #size-cells = <2>; 2115 device_type = "pci"; 2116 num-lanes = <1>; 2117 num-viewport = <8>; 2118 linux,pci-domain = <3>; 2119 2120 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2121 clock-names = "core"; 2122 2123 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2124 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2125 reset-names = "apb", "core"; 2126 2127 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2128 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2129 interrupt-names = "intr", "msi"; 2130 2131 #interrupt-cells = <1>; 2132 interrupt-map-mask = <0 0 0 0>; 2133 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2134 2135 nvidia,bpmp = <&bpmp 3>; 2136 2137 nvidia,aspm-cmrt-us = <60>; 2138 nvidia,aspm-pwr-on-t-us = <20>; 2139 nvidia,aspm-l0s-entrance-latency-us = <3>; 2140 2141 bus-range = <0x0 0xff>; 2142 2143 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2144 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2145 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2146 2147 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2148 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2149 interconnect-names = "dma-mem", "write"; 2150 iommus = <&smmu TEGRA194_SID_PCIE3>; 2151 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2152 iommu-map-mask = <0x0>; 2153 dma-coherent; 2154 }; 2155 2156 pcie@14160000 { 2157 compatible = "nvidia,tegra194-pcie"; 2158 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2159 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2160 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2161 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2162 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2163 reg-names = "appl", "config", "atu_dma", "dbi"; 2164 2165 status = "disabled"; 2166 2167 #address-cells = <3>; 2168 #size-cells = <2>; 2169 device_type = "pci"; 2170 num-lanes = <4>; 2171 num-viewport = <8>; 2172 linux,pci-domain = <4>; 2173 2174 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2175 clock-names = "core"; 2176 2177 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2178 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2179 reset-names = "apb", "core"; 2180 2181 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2182 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2183 interrupt-names = "intr", "msi"; 2184 2185 #interrupt-cells = <1>; 2186 interrupt-map-mask = <0 0 0 0>; 2187 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2188 2189 nvidia,bpmp = <&bpmp 4>; 2190 2191 nvidia,aspm-cmrt-us = <60>; 2192 nvidia,aspm-pwr-on-t-us = <20>; 2193 nvidia,aspm-l0s-entrance-latency-us = <3>; 2194 2195 bus-range = <0x0 0xff>; 2196 2197 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2198 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2199 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2200 2201 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2202 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2203 interconnect-names = "dma-mem", "write"; 2204 iommus = <&smmu TEGRA194_SID_PCIE4>; 2205 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2206 iommu-map-mask = <0x0>; 2207 dma-coherent; 2208 }; 2209 2210 pcie@14180000 { 2211 compatible = "nvidia,tegra194-pcie"; 2212 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2213 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2214 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2215 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2216 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2217 reg-names = "appl", "config", "atu_dma", "dbi"; 2218 2219 status = "disabled"; 2220 2221 #address-cells = <3>; 2222 #size-cells = <2>; 2223 device_type = "pci"; 2224 num-lanes = <8>; 2225 num-viewport = <8>; 2226 linux,pci-domain = <0>; 2227 2228 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2229 clock-names = "core"; 2230 2231 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2232 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2233 reset-names = "apb", "core"; 2234 2235 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2236 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2237 interrupt-names = "intr", "msi"; 2238 2239 #interrupt-cells = <1>; 2240 interrupt-map-mask = <0 0 0 0>; 2241 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2242 2243 nvidia,bpmp = <&bpmp 0>; 2244 2245 nvidia,aspm-cmrt-us = <60>; 2246 nvidia,aspm-pwr-on-t-us = <20>; 2247 nvidia,aspm-l0s-entrance-latency-us = <3>; 2248 2249 bus-range = <0x0 0xff>; 2250 2251 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2252 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2253 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2254 2255 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2256 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2257 interconnect-names = "dma-mem", "write"; 2258 iommus = <&smmu TEGRA194_SID_PCIE0>; 2259 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2260 iommu-map-mask = <0x0>; 2261 dma-coherent; 2262 }; 2263 2264 pcie@141a0000 { 2265 compatible = "nvidia,tegra194-pcie"; 2266 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2267 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2268 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2269 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2270 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2271 reg-names = "appl", "config", "atu_dma", "dbi"; 2272 2273 status = "disabled"; 2274 2275 #address-cells = <3>; 2276 #size-cells = <2>; 2277 device_type = "pci"; 2278 num-lanes = <8>; 2279 num-viewport = <8>; 2280 linux,pci-domain = <5>; 2281 2282 pinctrl-names = "default"; 2283 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2284 2285 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 2286 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 2287 clock-names = "core", "core_m"; 2288 2289 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2290 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2291 reset-names = "apb", "core"; 2292 2293 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2294 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2295 interrupt-names = "intr", "msi"; 2296 2297 nvidia,bpmp = <&bpmp 5>; 2298 2299 #interrupt-cells = <1>; 2300 interrupt-map-mask = <0 0 0 0>; 2301 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2302 2303 nvidia,aspm-cmrt-us = <60>; 2304 nvidia,aspm-pwr-on-t-us = <20>; 2305 nvidia,aspm-l0s-entrance-latency-us = <3>; 2306 2307 bus-range = <0x0 0xff>; 2308 2309 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2310 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2311 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2312 2313 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2314 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2315 interconnect-names = "dma-mem", "write"; 2316 iommus = <&smmu TEGRA194_SID_PCIE5>; 2317 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2318 iommu-map-mask = <0x0>; 2319 dma-coherent; 2320 }; 2321 2322 pcie-ep@14160000 { 2323 compatible = "nvidia,tegra194-pcie-ep"; 2324 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2325 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2326 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2327 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2328 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2329 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2330 2331 status = "disabled"; 2332 2333 num-lanes = <4>; 2334 num-ib-windows = <2>; 2335 num-ob-windows = <8>; 2336 2337 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2338 clock-names = "core"; 2339 2340 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2341 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2342 reset-names = "apb", "core"; 2343 2344 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2345 interrupt-names = "intr"; 2346 2347 nvidia,bpmp = <&bpmp 4>; 2348 2349 nvidia,aspm-cmrt-us = <60>; 2350 nvidia,aspm-pwr-on-t-us = <20>; 2351 nvidia,aspm-l0s-entrance-latency-us = <3>; 2352 2353 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2354 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2355 interconnect-names = "dma-mem", "write"; 2356 iommus = <&smmu TEGRA194_SID_PCIE4>; 2357 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2358 iommu-map-mask = <0x0>; 2359 dma-coherent; 2360 }; 2361 2362 pcie-ep@14180000 { 2363 compatible = "nvidia,tegra194-pcie-ep"; 2364 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2365 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2366 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2367 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2368 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2369 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2370 2371 status = "disabled"; 2372 2373 num-lanes = <8>; 2374 num-ib-windows = <2>; 2375 num-ob-windows = <8>; 2376 2377 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2378 clock-names = "core"; 2379 2380 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2381 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2382 reset-names = "apb", "core"; 2383 2384 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2385 interrupt-names = "intr"; 2386 2387 nvidia,bpmp = <&bpmp 0>; 2388 2389 nvidia,aspm-cmrt-us = <60>; 2390 nvidia,aspm-pwr-on-t-us = <20>; 2391 nvidia,aspm-l0s-entrance-latency-us = <3>; 2392 2393 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2394 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2395 interconnect-names = "dma-mem", "write"; 2396 iommus = <&smmu TEGRA194_SID_PCIE0>; 2397 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2398 iommu-map-mask = <0x0>; 2399 dma-coherent; 2400 }; 2401 2402 pcie-ep@141a0000 { 2403 compatible = "nvidia,tegra194-pcie-ep"; 2404 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2405 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2406 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2407 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2408 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2409 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2410 2411 status = "disabled"; 2412 2413 num-lanes = <8>; 2414 num-ib-windows = <2>; 2415 num-ob-windows = <8>; 2416 2417 pinctrl-names = "default"; 2418 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2419 2420 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2421 clock-names = "core"; 2422 2423 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2424 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2425 reset-names = "apb", "core"; 2426 2427 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2428 interrupt-names = "intr"; 2429 2430 nvidia,bpmp = <&bpmp 5>; 2431 2432 nvidia,aspm-cmrt-us = <60>; 2433 nvidia,aspm-pwr-on-t-us = <20>; 2434 nvidia,aspm-l0s-entrance-latency-us = <3>; 2435 2436 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2437 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2438 interconnect-names = "dma-mem", "write"; 2439 iommus = <&smmu TEGRA194_SID_PCIE5>; 2440 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2441 iommu-map-mask = <0x0>; 2442 dma-coherent; 2443 }; 2444 2445 sram@40000000 { 2446 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2447 reg = <0x0 0x40000000 0x0 0x50000>; 2448 #address-cells = <1>; 2449 #size-cells = <1>; 2450 ranges = <0x0 0x0 0x40000000 0x50000>; 2451 2452 cpu_bpmp_tx: sram@4e000 { 2453 reg = <0x4e000 0x1000>; 2454 label = "cpu-bpmp-tx"; 2455 pool; 2456 }; 2457 2458 cpu_bpmp_rx: sram@4f000 { 2459 reg = <0x4f000 0x1000>; 2460 label = "cpu-bpmp-rx"; 2461 pool; 2462 }; 2463 }; 2464 2465 bpmp: bpmp { 2466 compatible = "nvidia,tegra186-bpmp"; 2467 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2468 TEGRA_HSP_DB_MASTER_BPMP>; 2469 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 2470 #clock-cells = <1>; 2471 #reset-cells = <1>; 2472 #power-domain-cells = <1>; 2473 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2474 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2475 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2476 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2477 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2478 iommus = <&smmu TEGRA194_SID_BPMP>; 2479 2480 bpmp_i2c: i2c { 2481 compatible = "nvidia,tegra186-bpmp-i2c"; 2482 nvidia,bpmp-bus-id = <5>; 2483 #address-cells = <1>; 2484 #size-cells = <0>; 2485 }; 2486 2487 bpmp_thermal: thermal { 2488 compatible = "nvidia,tegra186-bpmp-thermal"; 2489 #thermal-sensor-cells = <1>; 2490 }; 2491 }; 2492 2493 cpus { 2494 compatible = "nvidia,tegra194-ccplex"; 2495 nvidia,bpmp = <&bpmp>; 2496 #address-cells = <1>; 2497 #size-cells = <0>; 2498 2499 cpu0_0: cpu@0 { 2500 compatible = "nvidia,tegra194-carmel"; 2501 device_type = "cpu"; 2502 reg = <0x000>; 2503 enable-method = "psci"; 2504 i-cache-size = <131072>; 2505 i-cache-line-size = <64>; 2506 i-cache-sets = <512>; 2507 d-cache-size = <65536>; 2508 d-cache-line-size = <64>; 2509 d-cache-sets = <256>; 2510 next-level-cache = <&l2c_0>; 2511 }; 2512 2513 cpu0_1: cpu@1 { 2514 compatible = "nvidia,tegra194-carmel"; 2515 device_type = "cpu"; 2516 reg = <0x001>; 2517 enable-method = "psci"; 2518 i-cache-size = <131072>; 2519 i-cache-line-size = <64>; 2520 i-cache-sets = <512>; 2521 d-cache-size = <65536>; 2522 d-cache-line-size = <64>; 2523 d-cache-sets = <256>; 2524 next-level-cache = <&l2c_0>; 2525 }; 2526 2527 cpu1_0: cpu@100 { 2528 compatible = "nvidia,tegra194-carmel"; 2529 device_type = "cpu"; 2530 reg = <0x100>; 2531 enable-method = "psci"; 2532 i-cache-size = <131072>; 2533 i-cache-line-size = <64>; 2534 i-cache-sets = <512>; 2535 d-cache-size = <65536>; 2536 d-cache-line-size = <64>; 2537 d-cache-sets = <256>; 2538 next-level-cache = <&l2c_1>; 2539 }; 2540 2541 cpu1_1: cpu@101 { 2542 compatible = "nvidia,tegra194-carmel"; 2543 device_type = "cpu"; 2544 reg = <0x101>; 2545 enable-method = "psci"; 2546 i-cache-size = <131072>; 2547 i-cache-line-size = <64>; 2548 i-cache-sets = <512>; 2549 d-cache-size = <65536>; 2550 d-cache-line-size = <64>; 2551 d-cache-sets = <256>; 2552 next-level-cache = <&l2c_1>; 2553 }; 2554 2555 cpu2_0: cpu@200 { 2556 compatible = "nvidia,tegra194-carmel"; 2557 device_type = "cpu"; 2558 reg = <0x200>; 2559 enable-method = "psci"; 2560 i-cache-size = <131072>; 2561 i-cache-line-size = <64>; 2562 i-cache-sets = <512>; 2563 d-cache-size = <65536>; 2564 d-cache-line-size = <64>; 2565 d-cache-sets = <256>; 2566 next-level-cache = <&l2c_2>; 2567 }; 2568 2569 cpu2_1: cpu@201 { 2570 compatible = "nvidia,tegra194-carmel"; 2571 device_type = "cpu"; 2572 reg = <0x201>; 2573 enable-method = "psci"; 2574 i-cache-size = <131072>; 2575 i-cache-line-size = <64>; 2576 i-cache-sets = <512>; 2577 d-cache-size = <65536>; 2578 d-cache-line-size = <64>; 2579 d-cache-sets = <256>; 2580 next-level-cache = <&l2c_2>; 2581 }; 2582 2583 cpu3_0: cpu@300 { 2584 compatible = "nvidia,tegra194-carmel"; 2585 device_type = "cpu"; 2586 reg = <0x300>; 2587 enable-method = "psci"; 2588 i-cache-size = <131072>; 2589 i-cache-line-size = <64>; 2590 i-cache-sets = <512>; 2591 d-cache-size = <65536>; 2592 d-cache-line-size = <64>; 2593 d-cache-sets = <256>; 2594 next-level-cache = <&l2c_3>; 2595 }; 2596 2597 cpu3_1: cpu@301 { 2598 compatible = "nvidia,tegra194-carmel"; 2599 device_type = "cpu"; 2600 reg = <0x301>; 2601 enable-method = "psci"; 2602 i-cache-size = <131072>; 2603 i-cache-line-size = <64>; 2604 i-cache-sets = <512>; 2605 d-cache-size = <65536>; 2606 d-cache-line-size = <64>; 2607 d-cache-sets = <256>; 2608 next-level-cache = <&l2c_3>; 2609 }; 2610 2611 cpu-map { 2612 cluster0 { 2613 core0 { 2614 cpu = <&cpu0_0>; 2615 }; 2616 2617 core1 { 2618 cpu = <&cpu0_1>; 2619 }; 2620 }; 2621 2622 cluster1 { 2623 core0 { 2624 cpu = <&cpu1_0>; 2625 }; 2626 2627 core1 { 2628 cpu = <&cpu1_1>; 2629 }; 2630 }; 2631 2632 cluster2 { 2633 core0 { 2634 cpu = <&cpu2_0>; 2635 }; 2636 2637 core1 { 2638 cpu = <&cpu2_1>; 2639 }; 2640 }; 2641 2642 cluster3 { 2643 core0 { 2644 cpu = <&cpu3_0>; 2645 }; 2646 2647 core1 { 2648 cpu = <&cpu3_1>; 2649 }; 2650 }; 2651 }; 2652 2653 l2c_0: l2-cache0 { 2654 cache-size = <2097152>; 2655 cache-line-size = <64>; 2656 cache-sets = <2048>; 2657 next-level-cache = <&l3c>; 2658 }; 2659 2660 l2c_1: l2-cache1 { 2661 cache-size = <2097152>; 2662 cache-line-size = <64>; 2663 cache-sets = <2048>; 2664 next-level-cache = <&l3c>; 2665 }; 2666 2667 l2c_2: l2-cache2 { 2668 cache-size = <2097152>; 2669 cache-line-size = <64>; 2670 cache-sets = <2048>; 2671 next-level-cache = <&l3c>; 2672 }; 2673 2674 l2c_3: l2-cache3 { 2675 cache-size = <2097152>; 2676 cache-line-size = <64>; 2677 cache-sets = <2048>; 2678 next-level-cache = <&l3c>; 2679 }; 2680 2681 l3c: l3-cache { 2682 cache-size = <4194304>; 2683 cache-line-size = <64>; 2684 cache-sets = <4096>; 2685 }; 2686 }; 2687 2688 pmu { 2689 compatible = "arm,armv8-pmuv3"; 2690 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2691 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2692 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2693 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 2694 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 2695 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 2696 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 2697 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 2698 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 2699 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 2700 }; 2701 2702 psci { 2703 compatible = "arm,psci-1.0"; 2704 status = "okay"; 2705 method = "smc"; 2706 }; 2707 2708 sound { 2709 status = "disabled"; 2710 2711 clocks = <&bpmp TEGRA194_CLK_PLLA>, 2712 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2713 clock-names = "pll_a", "plla_out0"; 2714 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 2715 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 2716 <&bpmp TEGRA194_CLK_AUD_MCLK>; 2717 assigned-clock-parents = <0>, 2718 <&bpmp TEGRA194_CLK_PLLA>, 2719 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2720 /* 2721 * PLLA supports dynamic ramp. Below initial rate is chosen 2722 * for this to work and oscillate between base rates required 2723 * for 8x and 11.025x sample rate streams. 2724 */ 2725 assigned-clock-rates = <258000000>; 2726 2727 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 2728 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 2729 interconnect-names = "dma-mem", "write"; 2730 iommus = <&smmu TEGRA194_SID_APE>; 2731 }; 2732 2733 tcu: tcu { 2734 compatible = "nvidia,tegra194-tcu"; 2735 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2736 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2737 mbox-names = "rx", "tx"; 2738 }; 2739 2740 thermal-zones { 2741 cpu { 2742 thermal-sensors = <&{/bpmp/thermal} 2743 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2744 status = "disabled"; 2745 }; 2746 2747 gpu { 2748 thermal-sensors = <&{/bpmp/thermal} 2749 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2750 status = "disabled"; 2751 }; 2752 2753 aux { 2754 thermal-sensors = <&{/bpmp/thermal} 2755 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2756 status = "disabled"; 2757 }; 2758 2759 pllx { 2760 thermal-sensors = <&{/bpmp/thermal} 2761 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2762 status = "disabled"; 2763 }; 2764 2765 ao { 2766 thermal-sensors = <&{/bpmp/thermal} 2767 TEGRA194_BPMP_THERMAL_ZONE_AO>; 2768 status = "disabled"; 2769 }; 2770 2771 tj { 2772 thermal-sensors = <&{/bpmp/thermal} 2773 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2774 status = "disabled"; 2775 }; 2776 }; 2777 2778 timer { 2779 compatible = "arm,armv8-timer"; 2780 interrupts = <GIC_PPI 13 2781 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2782 <GIC_PPI 14 2783 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2784 <GIC_PPI 11 2785 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2786 <GIC_PPI 10 2787 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2788 interrupt-parent = <&gic>; 2789 always-on; 2790 }; 2791}; 2792