15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6ff21087eSPrathamesh Shete#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 83db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 9dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 10686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 125425fb15SMikko Perttunen 135425fb15SMikko Perttunen/ { 145425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 155425fb15SMikko Perttunen interrupt-parent = <&gic>; 165425fb15SMikko Perttunen #address-cells = <2>; 175425fb15SMikko Perttunen #size-cells = <2>; 185425fb15SMikko Perttunen 195425fb15SMikko Perttunen /* control backbone */ 208b3aee8fSThierry Reding bus@0 { 215425fb15SMikko Perttunen compatible = "simple-bus"; 225425fb15SMikko Perttunen #address-cells = <1>; 235425fb15SMikko Perttunen #size-cells = <1>; 245425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 255425fb15SMikko Perttunen 2609903c5eSJC Kuo misc@100000 { 2709903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2809903c5eSJC Kuo reg = <0x00100000 0xf000>, 2909903c5eSJC Kuo <0x0010f000 0x1000>; 3009903c5eSJC Kuo }; 3109903c5eSJC Kuo 32f69ce393SMikko Perttunen gpio: gpio@2200000 { 33f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 34f69ce393SMikko Perttunen reg-names = "security", "gpio"; 35f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 36f69ce393SMikko Perttunen <0x2210000 0x10000>; 37f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 380a85cf28Spshete <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 390a85cf28Spshete <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 400a85cf28Spshete <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 410a85cf28Spshete <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 420a85cf28Spshete <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 430a85cf28Spshete <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 440a85cf28Spshete <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 460a85cf28Spshete <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 470a85cf28Spshete <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 480a85cf28Spshete <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 490a85cf28Spshete <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 500a85cf28Spshete <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 510a85cf28Spshete <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 520a85cf28Spshete <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 540a85cf28Spshete <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 550a85cf28Spshete <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 560a85cf28Spshete <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 570a85cf28Spshete <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 580a85cf28Spshete <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 590a85cf28Spshete <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 600a85cf28Spshete <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 620a85cf28Spshete <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 630a85cf28Spshete <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 640a85cf28Spshete <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 650a85cf28Spshete <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 660a85cf28Spshete <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 670a85cf28Spshete <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 680a85cf28Spshete <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 700a85cf28Spshete <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 710a85cf28Spshete <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 720a85cf28Spshete <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 730a85cf28Spshete <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 740a85cf28Spshete <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 750a85cf28Spshete <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 760a85cf28Spshete <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 770a85cf28Spshete <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 780a85cf28Spshete <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 790a85cf28Spshete <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 800a85cf28Spshete <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 810a85cf28Spshete <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 820a85cf28Spshete <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 830a85cf28Spshete <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 840a85cf28Spshete <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85f69ce393SMikko Perttunen #interrupt-cells = <2>; 86f69ce393SMikko Perttunen interrupt-controller; 87f69ce393SMikko Perttunen #gpio-cells = <2>; 88f69ce393SMikko Perttunen gpio-controller; 89f69ce393SMikko Perttunen }; 90f69ce393SMikko Perttunen 91f89b58ceSMikko Perttunen ethernet@2490000 { 9219dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 9319dc772aSThierry Reding "nvidia,tegra186-eqos", 94f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 95f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 96f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 97f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 98f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 99f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 100f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 101f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 102f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 103f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 104f89b58ceSMikko Perttunen reset-names = "eqos"; 105d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 106d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 107d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 108c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_EQOS>; 109f89b58ceSMikko Perttunen status = "disabled"; 110f89b58ceSMikko Perttunen 111f89b58ceSMikko Perttunen snps,write-requests = <1>; 112f89b58ceSMikko Perttunen snps,read-requests = <3>; 113f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 114f89b58ceSMikko Perttunen snps,txpbl = <16>; 115f89b58ceSMikko Perttunen snps,rxpbl = <8>; 116f89b58ceSMikko Perttunen }; 117f89b58ceSMikko Perttunen 1181aaa7698SThierry Reding aconnect@2900000 { 1195d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 1205d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1215d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 1225d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 1235d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1245d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 1255d2249ddSSameer Pujar #address-cells = <1>; 1265d2249ddSSameer Pujar #size-cells = <1>; 1275d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 1285d2249ddSSameer Pujar status = "disabled"; 1295d2249ddSSameer Pujar 130177208f7SSameer Pujar adma: dma-controller@2930000 { 1315d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 1325d2249ddSSameer Pujar "nvidia,tegra186-adma"; 1335d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 1345d2249ddSSameer Pujar interrupt-parent = <&agic>; 1355d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1365d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1375d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1385d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1395d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1405d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1415d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1425d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1435d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1445d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1455d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1465d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1475d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1485d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1495d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1505d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1515d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1525d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1535d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1545d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1555d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1565d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1575d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1585d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1595d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1605d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1615d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1625d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1635d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1645d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1655d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1665d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1675d2249ddSSameer Pujar #dma-cells = <1>; 1685d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 1695d2249ddSSameer Pujar clock-names = "d_audio"; 1705d2249ddSSameer Pujar status = "disabled"; 1715d2249ddSSameer Pujar }; 1725d2249ddSSameer Pujar 1735d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1745d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 1755d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1765d2249ddSSameer Pujar #interrupt-cells = <3>; 1775d2249ddSSameer Pujar interrupt-controller; 1785d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1795d2249ddSSameer Pujar <0x02a42000 0x2000>; 1805d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1815d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 1825d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 1835d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 1845d2249ddSSameer Pujar clock-names = "clk"; 1855d2249ddSSameer Pujar status = "disabled"; 1865d2249ddSSameer Pujar }; 187177208f7SSameer Pujar 188177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 189177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 190177208f7SSameer Pujar "nvidia,tegra186-ahub"; 191177208f7SSameer Pujar reg = <0x02900800 0x800>; 192177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 193177208f7SSameer Pujar clock-names = "ahub"; 194177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 195177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 196177208f7SSameer Pujar #address-cells = <1>; 197177208f7SSameer Pujar #size-cells = <1>; 198177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 199177208f7SSameer Pujar status = "disabled"; 200177208f7SSameer Pujar 201177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 202177208f7SSameer Pujar compatible = "nvidia,tegra194-admaif", 203177208f7SSameer Pujar "nvidia,tegra186-admaif"; 204177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 205177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 206177208f7SSameer Pujar <&adma 2>, <&adma 2>, 207177208f7SSameer Pujar <&adma 3>, <&adma 3>, 208177208f7SSameer Pujar <&adma 4>, <&adma 4>, 209177208f7SSameer Pujar <&adma 5>, <&adma 5>, 210177208f7SSameer Pujar <&adma 6>, <&adma 6>, 211177208f7SSameer Pujar <&adma 7>, <&adma 7>, 212177208f7SSameer Pujar <&adma 8>, <&adma 8>, 213177208f7SSameer Pujar <&adma 9>, <&adma 9>, 214177208f7SSameer Pujar <&adma 10>, <&adma 10>, 215177208f7SSameer Pujar <&adma 11>, <&adma 11>, 216177208f7SSameer Pujar <&adma 12>, <&adma 12>, 217177208f7SSameer Pujar <&adma 13>, <&adma 13>, 218177208f7SSameer Pujar <&adma 14>, <&adma 14>, 219177208f7SSameer Pujar <&adma 15>, <&adma 15>, 220177208f7SSameer Pujar <&adma 16>, <&adma 16>, 221177208f7SSameer Pujar <&adma 17>, <&adma 17>, 222177208f7SSameer Pujar <&adma 18>, <&adma 18>, 223177208f7SSameer Pujar <&adma 19>, <&adma 19>, 224177208f7SSameer Pujar <&adma 20>, <&adma 20>; 225177208f7SSameer Pujar dma-names = "rx1", "tx1", 226177208f7SSameer Pujar "rx2", "tx2", 227177208f7SSameer Pujar "rx3", "tx3", 228177208f7SSameer Pujar "rx4", "tx4", 229177208f7SSameer Pujar "rx5", "tx5", 230177208f7SSameer Pujar "rx6", "tx6", 231177208f7SSameer Pujar "rx7", "tx7", 232177208f7SSameer Pujar "rx8", "tx8", 233177208f7SSameer Pujar "rx9", "tx9", 234177208f7SSameer Pujar "rx10", "tx10", 235177208f7SSameer Pujar "rx11", "tx11", 236177208f7SSameer Pujar "rx12", "tx12", 237177208f7SSameer Pujar "rx13", "tx13", 238177208f7SSameer Pujar "rx14", "tx14", 239177208f7SSameer Pujar "rx15", "tx15", 240177208f7SSameer Pujar "rx16", "tx16", 241177208f7SSameer Pujar "rx17", "tx17", 242177208f7SSameer Pujar "rx18", "tx18", 243177208f7SSameer Pujar "rx19", "tx19", 244177208f7SSameer Pujar "rx20", "tx20"; 245177208f7SSameer Pujar status = "disabled"; 246177208f7SSameer Pujar }; 247177208f7SSameer Pujar 248177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 249177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 250177208f7SSameer Pujar "nvidia,tegra210-i2s"; 251177208f7SSameer Pujar reg = <0x2901000 0x100>; 252177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 253177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 254177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 255177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 256177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 257177208f7SSameer Pujar assigned-clock-rates = <1536000>; 258177208f7SSameer Pujar sound-name-prefix = "I2S1"; 259177208f7SSameer Pujar status = "disabled"; 260177208f7SSameer Pujar }; 261177208f7SSameer Pujar 262177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 263177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 264177208f7SSameer Pujar "nvidia,tegra210-i2s"; 265177208f7SSameer Pujar reg = <0x2901100 0x100>; 266177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 267177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 268177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 269177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 270177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 271177208f7SSameer Pujar assigned-clock-rates = <1536000>; 272177208f7SSameer Pujar sound-name-prefix = "I2S2"; 273177208f7SSameer Pujar status = "disabled"; 274177208f7SSameer Pujar }; 275177208f7SSameer Pujar 276177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 277177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 278177208f7SSameer Pujar "nvidia,tegra210-i2s"; 279177208f7SSameer Pujar reg = <0x2901200 0x100>; 280177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 281177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 282177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 283177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 284177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 285177208f7SSameer Pujar assigned-clock-rates = <1536000>; 286177208f7SSameer Pujar sound-name-prefix = "I2S3"; 287177208f7SSameer Pujar status = "disabled"; 288177208f7SSameer Pujar }; 289177208f7SSameer Pujar 290177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 291177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 292177208f7SSameer Pujar "nvidia,tegra210-i2s"; 293177208f7SSameer Pujar reg = <0x2901300 0x100>; 294177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 295177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 296177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 297177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 298177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 299177208f7SSameer Pujar assigned-clock-rates = <1536000>; 300177208f7SSameer Pujar sound-name-prefix = "I2S4"; 301177208f7SSameer Pujar status = "disabled"; 302177208f7SSameer Pujar }; 303177208f7SSameer Pujar 304177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 305177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 306177208f7SSameer Pujar "nvidia,tegra210-i2s"; 307177208f7SSameer Pujar reg = <0x2901400 0x100>; 308177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 309177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 310177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 311177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 312177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 313177208f7SSameer Pujar assigned-clock-rates = <1536000>; 314177208f7SSameer Pujar sound-name-prefix = "I2S5"; 315177208f7SSameer Pujar status = "disabled"; 316177208f7SSameer Pujar }; 317177208f7SSameer Pujar 318177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 319177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 320177208f7SSameer Pujar "nvidia,tegra210-i2s"; 321177208f7SSameer Pujar reg = <0x2901500 0x100>; 322177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 323177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 324177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 325177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 326177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 327177208f7SSameer Pujar assigned-clock-rates = <1536000>; 328177208f7SSameer Pujar sound-name-prefix = "I2S6"; 329177208f7SSameer Pujar status = "disabled"; 330177208f7SSameer Pujar }; 331177208f7SSameer Pujar 332177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 333177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 334177208f7SSameer Pujar "nvidia,tegra210-dmic"; 335177208f7SSameer Pujar reg = <0x2904000 0x100>; 336177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 337177208f7SSameer Pujar clock-names = "dmic"; 338177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 339177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 340177208f7SSameer Pujar assigned-clock-rates = <3072000>; 341177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 342177208f7SSameer Pujar status = "disabled"; 343177208f7SSameer Pujar }; 344177208f7SSameer Pujar 345177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 346177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 347177208f7SSameer Pujar "nvidia,tegra210-dmic"; 348177208f7SSameer Pujar reg = <0x2904100 0x100>; 349177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 350177208f7SSameer Pujar clock-names = "dmic"; 351177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 352177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 353177208f7SSameer Pujar assigned-clock-rates = <3072000>; 354177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 355177208f7SSameer Pujar status = "disabled"; 356177208f7SSameer Pujar }; 357177208f7SSameer Pujar 358177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 359177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 360177208f7SSameer Pujar "nvidia,tegra210-dmic"; 361177208f7SSameer Pujar reg = <0x2904200 0x100>; 362177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 363177208f7SSameer Pujar clock-names = "dmic"; 364177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 365177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 366177208f7SSameer Pujar assigned-clock-rates = <3072000>; 367177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 368177208f7SSameer Pujar status = "disabled"; 369177208f7SSameer Pujar }; 370177208f7SSameer Pujar 371177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 372177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 373177208f7SSameer Pujar "nvidia,tegra210-dmic"; 374177208f7SSameer Pujar reg = <0x2904300 0x100>; 375177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 376177208f7SSameer Pujar clock-names = "dmic"; 377177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 378177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 379177208f7SSameer Pujar assigned-clock-rates = <3072000>; 380177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 381177208f7SSameer Pujar status = "disabled"; 382177208f7SSameer Pujar }; 383177208f7SSameer Pujar 384177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 385177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 386177208f7SSameer Pujar "nvidia,tegra186-dspk"; 387177208f7SSameer Pujar reg = <0x2905000 0x100>; 388177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 389177208f7SSameer Pujar clock-names = "dspk"; 390177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 391177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 392177208f7SSameer Pujar assigned-clock-rates = <12288000>; 393177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 394177208f7SSameer Pujar status = "disabled"; 395177208f7SSameer Pujar }; 396177208f7SSameer Pujar 397177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 398177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 399177208f7SSameer Pujar "nvidia,tegra186-dspk"; 400177208f7SSameer Pujar reg = <0x2905100 0x100>; 401177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 402177208f7SSameer Pujar clock-names = "dspk"; 403177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 404177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 405177208f7SSameer Pujar assigned-clock-rates = <12288000>; 406177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 407177208f7SSameer Pujar status = "disabled"; 408177208f7SSameer Pujar }; 409848f3290SSameer Pujar 410848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 411848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 412848f3290SSameer Pujar "nvidia,tegra210-sfc"; 413848f3290SSameer Pujar reg = <0x2902000 0x200>; 414848f3290SSameer Pujar sound-name-prefix = "SFC1"; 415848f3290SSameer Pujar status = "disabled"; 416848f3290SSameer Pujar }; 417848f3290SSameer Pujar 418848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 419848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 420848f3290SSameer Pujar "nvidia,tegra210-sfc"; 421848f3290SSameer Pujar reg = <0x2902200 0x200>; 422848f3290SSameer Pujar sound-name-prefix = "SFC2"; 423848f3290SSameer Pujar status = "disabled"; 424848f3290SSameer Pujar }; 425848f3290SSameer Pujar 426848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 427848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 428848f3290SSameer Pujar "nvidia,tegra210-sfc"; 429848f3290SSameer Pujar reg = <0x2902400 0x200>; 430848f3290SSameer Pujar sound-name-prefix = "SFC3"; 431848f3290SSameer Pujar status = "disabled"; 432848f3290SSameer Pujar }; 433848f3290SSameer Pujar 434848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 435848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 436848f3290SSameer Pujar "nvidia,tegra210-sfc"; 437848f3290SSameer Pujar reg = <0x2902600 0x200>; 438848f3290SSameer Pujar sound-name-prefix = "SFC4"; 439848f3290SSameer Pujar status = "disabled"; 440848f3290SSameer Pujar }; 441848f3290SSameer Pujar 442848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 443848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 444848f3290SSameer Pujar "nvidia,tegra210-mvc"; 445848f3290SSameer Pujar reg = <0x290a000 0x200>; 446848f3290SSameer Pujar sound-name-prefix = "MVC1"; 447848f3290SSameer Pujar status = "disabled"; 448848f3290SSameer Pujar }; 449848f3290SSameer Pujar 450848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 451848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 452848f3290SSameer Pujar "nvidia,tegra210-mvc"; 453848f3290SSameer Pujar reg = <0x290a200 0x200>; 454848f3290SSameer Pujar sound-name-prefix = "MVC2"; 455848f3290SSameer Pujar status = "disabled"; 456848f3290SSameer Pujar }; 457848f3290SSameer Pujar 458848f3290SSameer Pujar tegra_amx1: amx@2903000 { 459848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 460848f3290SSameer Pujar reg = <0x2903000 0x100>; 461848f3290SSameer Pujar sound-name-prefix = "AMX1"; 462848f3290SSameer Pujar status = "disabled"; 463848f3290SSameer Pujar }; 464848f3290SSameer Pujar 465848f3290SSameer Pujar tegra_amx2: amx@2903100 { 466848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 467848f3290SSameer Pujar reg = <0x2903100 0x100>; 468848f3290SSameer Pujar sound-name-prefix = "AMX2"; 469848f3290SSameer Pujar status = "disabled"; 470848f3290SSameer Pujar }; 471848f3290SSameer Pujar 472848f3290SSameer Pujar tegra_amx3: amx@2903200 { 473848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 474848f3290SSameer Pujar reg = <0x2903200 0x100>; 475848f3290SSameer Pujar sound-name-prefix = "AMX3"; 476848f3290SSameer Pujar status = "disabled"; 477848f3290SSameer Pujar }; 478848f3290SSameer Pujar 479848f3290SSameer Pujar tegra_amx4: amx@2903300 { 480848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 481848f3290SSameer Pujar reg = <0x2903300 0x100>; 482848f3290SSameer Pujar sound-name-prefix = "AMX4"; 483848f3290SSameer Pujar status = "disabled"; 484848f3290SSameer Pujar }; 485848f3290SSameer Pujar 486848f3290SSameer Pujar tegra_adx1: adx@2903800 { 487848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 488848f3290SSameer Pujar "nvidia,tegra210-adx"; 489848f3290SSameer Pujar reg = <0x2903800 0x100>; 490848f3290SSameer Pujar sound-name-prefix = "ADX1"; 491848f3290SSameer Pujar status = "disabled"; 492848f3290SSameer Pujar }; 493848f3290SSameer Pujar 494848f3290SSameer Pujar tegra_adx2: adx@2903900 { 495848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 496848f3290SSameer Pujar "nvidia,tegra210-adx"; 497848f3290SSameer Pujar reg = <0x2903900 0x100>; 498848f3290SSameer Pujar sound-name-prefix = "ADX2"; 499848f3290SSameer Pujar status = "disabled"; 500848f3290SSameer Pujar }; 501848f3290SSameer Pujar 502848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 503848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 504848f3290SSameer Pujar "nvidia,tegra210-adx"; 505848f3290SSameer Pujar reg = <0x2903a00 0x100>; 506848f3290SSameer Pujar sound-name-prefix = "ADX3"; 507848f3290SSameer Pujar status = "disabled"; 508848f3290SSameer Pujar }; 509848f3290SSameer Pujar 510848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 511848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 512848f3290SSameer Pujar "nvidia,tegra210-adx"; 513848f3290SSameer Pujar reg = <0x2903b00 0x100>; 514848f3290SSameer Pujar sound-name-prefix = "ADX4"; 515848f3290SSameer Pujar status = "disabled"; 516848f3290SSameer Pujar }; 517848f3290SSameer Pujar 518848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 519848f3290SSameer Pujar compatible = "nvidia,tegra194-amixer", 520848f3290SSameer Pujar "nvidia,tegra210-amixer"; 521848f3290SSameer Pujar reg = <0x290bb00 0x800>; 522848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 523848f3290SSameer Pujar status = "disabled"; 524848f3290SSameer Pujar }; 525177208f7SSameer Pujar }; 5265d2249ddSSameer Pujar }; 5275d2249ddSSameer Pujar 528dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 529dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 530644c569dSThierry Reding reg = <0x2430000 0x17000>, 531644c569dSThierry Reding <0xc300000 0x4000>; 532dbb72e2cSVidya Sagar 533dbb72e2cSVidya Sagar status = "okay"; 534dbb72e2cSVidya Sagar 535dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 536dbb72e2cSVidya Sagar pex_rst { 537dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 538dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 539dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 540dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 5416b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 542dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 543dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 544dbb72e2cSVidya Sagar }; 545dbb72e2cSVidya Sagar }; 546dbb72e2cSVidya Sagar 547dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 548dbb72e2cSVidya Sagar clkreq { 549dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 550dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 551dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 552dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 5536b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 554dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 555dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 556dbb72e2cSVidya Sagar }; 557dbb72e2cSVidya Sagar }; 558dbb72e2cSVidya Sagar }; 559dbb72e2cSVidya Sagar 560be9b887fSThierry Reding mc: memory-controller@2c00000 { 561be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 562be9b887fSThierry Reding reg = <0x02c00000 0x100000>, 563be9b887fSThierry Reding <0x02b80000 0x040000>, 564be9b887fSThierry Reding <0x01700000 0x100000>; 5658613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 566d5237c7cSThierry Reding #interconnect-cells = <1>; 567be9b887fSThierry Reding status = "disabled"; 568be9b887fSThierry Reding 569be9b887fSThierry Reding #address-cells = <2>; 570be9b887fSThierry Reding #size-cells = <2>; 571be9b887fSThierry Reding 572be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 573be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 574be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 575be9b887fSThierry Reding 576be9b887fSThierry Reding /* 577be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 578be9b887fSThierry Reding * controller selects the XBAR format used when memory 579be9b887fSThierry Reding * is accessed. This is used to transparently access 580be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 581be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 582be9b887fSThierry Reding * 583be9b887fSThierry Reding * As a consequence, the operating system must ensure 584be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 585be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 586be9b887fSThierry Reding * devices require access to the XBAR switch, their 587be9b887fSThierry Reding * drivers must set this bit explicitly. 588be9b887fSThierry Reding * 589be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 590be9b887fSThierry Reding */ 591be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 592be9b887fSThierry Reding 593be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 594be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 595be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 596be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 597be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 598be9b887fSThierry Reding clock-names = "emc"; 599be9b887fSThierry Reding 600d5237c7cSThierry Reding #interconnect-cells = <0>; 601d5237c7cSThierry Reding 602be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 603be9b887fSThierry Reding }; 604be9b887fSThierry Reding }; 605be9b887fSThierry Reding 6065425fb15SMikko Perttunen uarta: serial@3100000 { 6075425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6085425fb15SMikko Perttunen reg = <0x03100000 0x40>; 6095425fb15SMikko Perttunen reg-shift = <2>; 6105425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 6115425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 6125425fb15SMikko Perttunen clock-names = "serial"; 6135425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 6145425fb15SMikko Perttunen reset-names = "serial"; 6155425fb15SMikko Perttunen status = "disabled"; 6165425fb15SMikko Perttunen }; 6175425fb15SMikko Perttunen 6185425fb15SMikko Perttunen uartb: serial@3110000 { 6195425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6205425fb15SMikko Perttunen reg = <0x03110000 0x40>; 6215425fb15SMikko Perttunen reg-shift = <2>; 6225425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 6235425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 6245425fb15SMikko Perttunen clock-names = "serial"; 6255425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 6265425fb15SMikko Perttunen reset-names = "serial"; 6275425fb15SMikko Perttunen status = "disabled"; 6285425fb15SMikko Perttunen }; 6295425fb15SMikko Perttunen 6305425fb15SMikko Perttunen uartd: serial@3130000 { 6315425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6325425fb15SMikko Perttunen reg = <0x03130000 0x40>; 6335425fb15SMikko Perttunen reg-shift = <2>; 6345425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 6355425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 6365425fb15SMikko Perttunen clock-names = "serial"; 6375425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 6385425fb15SMikko Perttunen reset-names = "serial"; 6395425fb15SMikko Perttunen status = "disabled"; 6405425fb15SMikko Perttunen }; 6415425fb15SMikko Perttunen 6425425fb15SMikko Perttunen uarte: serial@3140000 { 6435425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6445425fb15SMikko Perttunen reg = <0x03140000 0x40>; 6455425fb15SMikko Perttunen reg-shift = <2>; 6465425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 6475425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 6485425fb15SMikko Perttunen clock-names = "serial"; 6495425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 6505425fb15SMikko Perttunen reset-names = "serial"; 6515425fb15SMikko Perttunen status = "disabled"; 6525425fb15SMikko Perttunen }; 6535425fb15SMikko Perttunen 6545425fb15SMikko Perttunen uartf: serial@3150000 { 6555425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6565425fb15SMikko Perttunen reg = <0x03150000 0x40>; 6575425fb15SMikko Perttunen reg-shift = <2>; 6585425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 6595425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 6605425fb15SMikko Perttunen clock-names = "serial"; 6615425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 6625425fb15SMikko Perttunen reset-names = "serial"; 6635425fb15SMikko Perttunen status = "disabled"; 6645425fb15SMikko Perttunen }; 6655425fb15SMikko Perttunen 6665425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 667d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 6685425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 6695425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 6705425fb15SMikko Perttunen #address-cells = <1>; 6715425fb15SMikko Perttunen #size-cells = <0>; 6725425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 6735425fb15SMikko Perttunen clock-names = "div-clk"; 6745425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 6755425fb15SMikko Perttunen reset-names = "i2c"; 6765425fb15SMikko Perttunen status = "disabled"; 6775425fb15SMikko Perttunen }; 6785425fb15SMikko Perttunen 6795425fb15SMikko Perttunen uarth: serial@3170000 { 6805425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6815425fb15SMikko Perttunen reg = <0x03170000 0x40>; 6825425fb15SMikko Perttunen reg-shift = <2>; 6835425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 6845425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 6855425fb15SMikko Perttunen clock-names = "serial"; 6865425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 6875425fb15SMikko Perttunen reset-names = "serial"; 6885425fb15SMikko Perttunen status = "disabled"; 6895425fb15SMikko Perttunen }; 6905425fb15SMikko Perttunen 6915425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 692d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 6935425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 6945425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 6955425fb15SMikko Perttunen #address-cells = <1>; 6965425fb15SMikko Perttunen #size-cells = <0>; 6975425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 6985425fb15SMikko Perttunen clock-names = "div-clk"; 6995425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 7005425fb15SMikko Perttunen reset-names = "i2c"; 7015425fb15SMikko Perttunen status = "disabled"; 7025425fb15SMikko Perttunen }; 7035425fb15SMikko Perttunen 7045425fb15SMikko Perttunen /* shares pads with dpaux1 */ 7055425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 706d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7075425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 7085425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 7095425fb15SMikko Perttunen #address-cells = <1>; 7105425fb15SMikko Perttunen #size-cells = <0>; 7115425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 7125425fb15SMikko Perttunen clock-names = "div-clk"; 7135425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 7145425fb15SMikko Perttunen reset-names = "i2c"; 715a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 716a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 717a4131561SThierry Reding pinctrl-names = "default", "idle"; 7185425fb15SMikko Perttunen status = "disabled"; 7195425fb15SMikko Perttunen }; 7205425fb15SMikko Perttunen 7215425fb15SMikko Perttunen /* shares pads with dpaux0 */ 7225425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 723d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7245425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 7255425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 7265425fb15SMikko Perttunen #address-cells = <1>; 7275425fb15SMikko Perttunen #size-cells = <0>; 7285425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 7295425fb15SMikko Perttunen clock-names = "div-clk"; 7305425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 7315425fb15SMikko Perttunen reset-names = "i2c"; 732a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 733a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 734a4131561SThierry Reding pinctrl-names = "default", "idle"; 7355425fb15SMikko Perttunen status = "disabled"; 7365425fb15SMikko Perttunen }; 7375425fb15SMikko Perttunen 738a4131561SThierry Reding /* shares pads with dpaux2 */ 739a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 740d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7415425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 7425425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 7435425fb15SMikko Perttunen #address-cells = <1>; 7445425fb15SMikko Perttunen #size-cells = <0>; 7455425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 7465425fb15SMikko Perttunen clock-names = "div-clk"; 7475425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 7485425fb15SMikko Perttunen reset-names = "i2c"; 749a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 750a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 751a4131561SThierry Reding pinctrl-names = "default", "idle"; 7525425fb15SMikko Perttunen status = "disabled"; 7535425fb15SMikko Perttunen }; 7545425fb15SMikko Perttunen 755a4131561SThierry Reding /* shares pads with dpaux3 */ 756a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 757d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7585425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 7595425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 7605425fb15SMikko Perttunen #address-cells = <1>; 7615425fb15SMikko Perttunen #size-cells = <0>; 7625425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 7635425fb15SMikko Perttunen clock-names = "div-clk"; 7645425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 7655425fb15SMikko Perttunen reset-names = "i2c"; 766a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 767a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 768a4131561SThierry Reding pinctrl-names = "default", "idle"; 7695425fb15SMikko Perttunen status = "disabled"; 7705425fb15SMikko Perttunen }; 7715425fb15SMikko Perttunen 77296ded827SSowjanya Komatineni spi@3270000 { 77396ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 77496ded827SSowjanya Komatineni reg = <0x3270000 0x1000>; 77596ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 77696ded827SSowjanya Komatineni #address-cells = <1>; 77796ded827SSowjanya Komatineni #size-cells = <0>; 77896ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 77996ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 78096ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 78196ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 78296ded827SSowjanya Komatineni reset-names = "qspi"; 78396ded827SSowjanya Komatineni status = "disabled"; 78496ded827SSowjanya Komatineni }; 78596ded827SSowjanya Komatineni 78696ded827SSowjanya Komatineni spi@3300000 { 78796ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 78896ded827SSowjanya Komatineni reg = <0x3300000 0x1000>; 78996ded827SSowjanya Komatineni interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 79096ded827SSowjanya Komatineni #address-cells = <1>; 79196ded827SSowjanya Komatineni #size-cells = <0>; 79296ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI1>, 79396ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI1_PM>; 79496ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 79596ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI1>; 79696ded827SSowjanya Komatineni reset-names = "qspi"; 79796ded827SSowjanya Komatineni status = "disabled"; 79896ded827SSowjanya Komatineni }; 79996ded827SSowjanya Komatineni 8006a574ec7SThierry Reding pwm1: pwm@3280000 { 8016a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8026a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8036a574ec7SThierry Reding reg = <0x3280000 0x10000>; 8046a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 8056a574ec7SThierry Reding clock-names = "pwm"; 8066a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 8076a574ec7SThierry Reding reset-names = "pwm"; 8086a574ec7SThierry Reding status = "disabled"; 8096a574ec7SThierry Reding #pwm-cells = <2>; 8106a574ec7SThierry Reding }; 8116a574ec7SThierry Reding 8126a574ec7SThierry Reding pwm2: pwm@3290000 { 8136a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8146a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8156a574ec7SThierry Reding reg = <0x3290000 0x10000>; 8166a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 8176a574ec7SThierry Reding clock-names = "pwm"; 8186a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 8196a574ec7SThierry Reding reset-names = "pwm"; 8206a574ec7SThierry Reding status = "disabled"; 8216a574ec7SThierry Reding #pwm-cells = <2>; 8226a574ec7SThierry Reding }; 8236a574ec7SThierry Reding 8246a574ec7SThierry Reding pwm3: pwm@32a0000 { 8256a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8266a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8276a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 8286a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 8296a574ec7SThierry Reding clock-names = "pwm"; 8306a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 8316a574ec7SThierry Reding reset-names = "pwm"; 8326a574ec7SThierry Reding status = "disabled"; 8336a574ec7SThierry Reding #pwm-cells = <2>; 8346a574ec7SThierry Reding }; 8356a574ec7SThierry Reding 8366a574ec7SThierry Reding pwm5: pwm@32c0000 { 8376a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8386a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8396a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 8406a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 8416a574ec7SThierry Reding clock-names = "pwm"; 8426a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 8436a574ec7SThierry Reding reset-names = "pwm"; 8446a574ec7SThierry Reding status = "disabled"; 8456a574ec7SThierry Reding #pwm-cells = <2>; 8466a574ec7SThierry Reding }; 8476a574ec7SThierry Reding 8486a574ec7SThierry Reding pwm6: pwm@32d0000 { 8496a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8506a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8516a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 8526a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 8536a574ec7SThierry Reding clock-names = "pwm"; 8546a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 8556a574ec7SThierry Reding reset-names = "pwm"; 8566a574ec7SThierry Reding status = "disabled"; 8576a574ec7SThierry Reding #pwm-cells = <2>; 8586a574ec7SThierry Reding }; 8596a574ec7SThierry Reding 8606a574ec7SThierry Reding pwm7: pwm@32e0000 { 8616a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8626a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8636a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 8646a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 8656a574ec7SThierry Reding clock-names = "pwm"; 8666a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 8676a574ec7SThierry Reding reset-names = "pwm"; 8686a574ec7SThierry Reding status = "disabled"; 8696a574ec7SThierry Reding #pwm-cells = <2>; 8706a574ec7SThierry Reding }; 8716a574ec7SThierry Reding 8726a574ec7SThierry Reding pwm8: pwm@32f0000 { 8736a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8746a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8756a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 8766a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 8776a574ec7SThierry Reding clock-names = "pwm"; 8786a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 8796a574ec7SThierry Reding reset-names = "pwm"; 8806a574ec7SThierry Reding status = "disabled"; 8816a574ec7SThierry Reding #pwm-cells = <2>; 8826a574ec7SThierry Reding }; 8836a574ec7SThierry Reding 88467bb17f6SThierry Reding sdmmc1: mmc@3400000 { 8852c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 8865425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 8875425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 888c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 889c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 890c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8915425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 8925425fb15SMikko Perttunen reset-names = "sdhci"; 893d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 894d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 895d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 896c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC1>; 897ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 898ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 899ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 9004e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 9014e0f1229SSowjanya Komatineni <0x07>; 9024e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 9034e0f1229SSowjanya Komatineni <0x07>; 9044e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 9054e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 9064e0f1229SSowjanya Komatineni <0x07>; 9074e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 9084e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 9094e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 9104e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 911ff21087eSPrathamesh Shete sd-uhs-sdr25; 912ff21087eSPrathamesh Shete sd-uhs-sdr50; 913ff21087eSPrathamesh Shete sd-uhs-ddr50; 914ff21087eSPrathamesh Shete sd-uhs-sdr104; 9155425fb15SMikko Perttunen status = "disabled"; 9165425fb15SMikko Perttunen }; 9175425fb15SMikko Perttunen 91867bb17f6SThierry Reding sdmmc3: mmc@3440000 { 9192c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 9205425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 9215425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 922c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 923c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 924c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 9255425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 9265425fb15SMikko Perttunen reset-names = "sdhci"; 927d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 928d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 929d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 930c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC3>; 931ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 932ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc3_3v3>; 933ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc3_1v8>; 9344e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 9354e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 9364e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 9374e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 9384e0f1229SSowjanya Komatineni <0x07>; 9394e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 9404e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 9414e0f1229SSowjanya Komatineni <0x07>; 9424e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 9434e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 9444e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 9454e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 946ff21087eSPrathamesh Shete sd-uhs-sdr25; 947ff21087eSPrathamesh Shete sd-uhs-sdr50; 948ff21087eSPrathamesh Shete sd-uhs-ddr50; 949ff21087eSPrathamesh Shete sd-uhs-sdr104; 9505425fb15SMikko Perttunen status = "disabled"; 9515425fb15SMikko Perttunen }; 9525425fb15SMikko Perttunen 95367bb17f6SThierry Reding sdmmc4: mmc@3460000 { 9542c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 9555425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 9565425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 957c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 958c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 959c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 960351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 961351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 962351648d0SSowjanya Komatineni assigned-clock-parents = 963351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 9645425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 9655425fb15SMikko Perttunen reset-names = "sdhci"; 966d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 967d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 968d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 969c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC4>; 9704e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 9714e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 9724e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 9734e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 9744e0f1229SSowjanya Komatineni <0x0a>; 9754e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 9764e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 9774e0f1229SSowjanya Komatineni <0x0a>; 9784e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 9794e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 9804e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 981dfd3cb6fSSowjanya Komatineni supports-cqe; 9825425fb15SMikko Perttunen status = "disabled"; 9835425fb15SMikko Perttunen }; 9845425fb15SMikko Perttunen 9854878cc0cSSameer Pujar hda@3510000 { 9864878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 9874878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 9884878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 9894878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 99048f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 99148f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 99248f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 9934878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 99448f6e195SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>, 99548f6e195SSameer Pujar <&bpmp TEGRA194_RESET_HDA2CODEC_2X>; 99648f6e195SSameer Pujar reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 9974878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 998d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 999d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1000d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1001c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HDA>; 10024878cc0cSSameer Pujar status = "disabled"; 10034878cc0cSSameer Pujar }; 10044878cc0cSSameer Pujar 1005fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 1006fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 1007fab7a039SJC Kuo reg = <0x03520000 0x1000>, 1008fab7a039SJC Kuo <0x03540000 0x1000>; 1009fab7a039SJC Kuo reg-names = "padctl", "ao"; 10106450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1011fab7a039SJC Kuo 1012fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1013fab7a039SJC Kuo reset-names = "padctl"; 1014fab7a039SJC Kuo 1015fab7a039SJC Kuo status = "disabled"; 1016fab7a039SJC Kuo 1017fab7a039SJC Kuo pads { 1018fab7a039SJC Kuo usb2 { 1019fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1020fab7a039SJC Kuo clock-names = "trk"; 1021fab7a039SJC Kuo 1022fab7a039SJC Kuo lanes { 1023fab7a039SJC Kuo usb2-0 { 1024fab7a039SJC Kuo nvidia,function = "xusb"; 1025fab7a039SJC Kuo status = "disabled"; 1026fab7a039SJC Kuo #phy-cells = <0>; 1027fab7a039SJC Kuo }; 1028fab7a039SJC Kuo 1029fab7a039SJC Kuo usb2-1 { 1030fab7a039SJC Kuo nvidia,function = "xusb"; 1031fab7a039SJC Kuo status = "disabled"; 1032fab7a039SJC Kuo #phy-cells = <0>; 1033fab7a039SJC Kuo }; 1034fab7a039SJC Kuo 1035fab7a039SJC Kuo usb2-2 { 1036fab7a039SJC Kuo nvidia,function = "xusb"; 1037fab7a039SJC Kuo status = "disabled"; 1038fab7a039SJC Kuo #phy-cells = <0>; 1039fab7a039SJC Kuo }; 1040fab7a039SJC Kuo 1041fab7a039SJC Kuo usb2-3 { 1042fab7a039SJC Kuo nvidia,function = "xusb"; 1043fab7a039SJC Kuo status = "disabled"; 1044fab7a039SJC Kuo #phy-cells = <0>; 1045fab7a039SJC Kuo }; 1046fab7a039SJC Kuo }; 1047fab7a039SJC Kuo }; 1048fab7a039SJC Kuo 1049fab7a039SJC Kuo usb3 { 1050fab7a039SJC Kuo lanes { 1051fab7a039SJC Kuo usb3-0 { 1052fab7a039SJC Kuo nvidia,function = "xusb"; 1053fab7a039SJC Kuo status = "disabled"; 1054fab7a039SJC Kuo #phy-cells = <0>; 1055fab7a039SJC Kuo }; 1056fab7a039SJC Kuo 1057fab7a039SJC Kuo usb3-1 { 1058fab7a039SJC Kuo nvidia,function = "xusb"; 1059fab7a039SJC Kuo status = "disabled"; 1060fab7a039SJC Kuo #phy-cells = <0>; 1061fab7a039SJC Kuo }; 1062fab7a039SJC Kuo 1063fab7a039SJC Kuo usb3-2 { 1064fab7a039SJC Kuo nvidia,function = "xusb"; 1065fab7a039SJC Kuo status = "disabled"; 1066fab7a039SJC Kuo #phy-cells = <0>; 1067fab7a039SJC Kuo }; 1068fab7a039SJC Kuo 1069fab7a039SJC Kuo usb3-3 { 1070fab7a039SJC Kuo nvidia,function = "xusb"; 1071fab7a039SJC Kuo status = "disabled"; 1072fab7a039SJC Kuo #phy-cells = <0>; 1073fab7a039SJC Kuo }; 1074fab7a039SJC Kuo }; 1075fab7a039SJC Kuo }; 1076fab7a039SJC Kuo }; 1077fab7a039SJC Kuo 1078fab7a039SJC Kuo ports { 1079fab7a039SJC Kuo usb2-0 { 1080fab7a039SJC Kuo status = "disabled"; 1081fab7a039SJC Kuo }; 1082fab7a039SJC Kuo 1083fab7a039SJC Kuo usb2-1 { 1084fab7a039SJC Kuo status = "disabled"; 1085fab7a039SJC Kuo }; 1086fab7a039SJC Kuo 1087fab7a039SJC Kuo usb2-2 { 1088fab7a039SJC Kuo status = "disabled"; 1089fab7a039SJC Kuo }; 1090fab7a039SJC Kuo 1091fab7a039SJC Kuo usb2-3 { 1092fab7a039SJC Kuo status = "disabled"; 1093fab7a039SJC Kuo }; 1094fab7a039SJC Kuo 1095fab7a039SJC Kuo usb3-0 { 1096fab7a039SJC Kuo status = "disabled"; 1097fab7a039SJC Kuo }; 1098fab7a039SJC Kuo 1099fab7a039SJC Kuo usb3-1 { 1100fab7a039SJC Kuo status = "disabled"; 1101fab7a039SJC Kuo }; 1102fab7a039SJC Kuo 1103fab7a039SJC Kuo usb3-2 { 1104fab7a039SJC Kuo status = "disabled"; 1105fab7a039SJC Kuo }; 1106fab7a039SJC Kuo 1107fab7a039SJC Kuo usb3-3 { 1108fab7a039SJC Kuo status = "disabled"; 1109fab7a039SJC Kuo }; 1110fab7a039SJC Kuo }; 1111fab7a039SJC Kuo }; 1112fab7a039SJC Kuo 1113bc8788b2SNagarjuna Kristam usb@3550000 { 1114bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 1115bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 1116bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 1117bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 1118bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1119bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1120bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1121bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 1122bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 1123bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1124c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1125c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1126c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1127c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1128bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1129bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1130bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 1131bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 1132bc8788b2SNagarjuna Kristam status = "disabled"; 1133bc8788b2SNagarjuna Kristam }; 1134bc8788b2SNagarjuna Kristam 1135fab7a039SJC Kuo usb@3610000 { 1136fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 1137fab7a039SJC Kuo reg = <0x03610000 0x40000>, 1138fab7a039SJC Kuo <0x03600000 0x10000>; 1139fab7a039SJC Kuo reg-names = "hcd", "fpci"; 1140fab7a039SJC Kuo 1141fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1142a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1143fab7a039SJC Kuo 1144fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1145fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1146fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1147fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 1148fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1149fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 1150fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 1151fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1152fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 1153fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 1154fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1155fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 1156fab7a039SJC Kuo "pll_e"; 1157c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1158c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1159c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1160c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1161fab7a039SJC Kuo 1162fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1163fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1164fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 1165fab7a039SJC Kuo 1166fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 1167fab7a039SJC Kuo status = "disabled"; 1168fab7a039SJC Kuo }; 1169fab7a039SJC Kuo 117009903c5eSJC Kuo fuse@3820000 { 117109903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 117209903c5eSJC Kuo reg = <0x03820000 0x10000>; 117309903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 117409903c5eSJC Kuo clock-names = "fuse"; 117509903c5eSJC Kuo }; 117609903c5eSJC Kuo 11775425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 11785425fb15SMikko Perttunen compatible = "arm,gic-400"; 11795425fb15SMikko Perttunen #interrupt-cells = <3>; 11805425fb15SMikko Perttunen interrupt-controller; 11815425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 11825425fb15SMikko Perttunen <0x03882000 0x2000>, 11835425fb15SMikko Perttunen <0x03884000 0x2000>, 11845425fb15SMikko Perttunen <0x03886000 0x2000>; 11855425fb15SMikko Perttunen interrupts = <GIC_PPI 9 11865425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 11875425fb15SMikko Perttunen interrupt-parent = <&gic>; 11885425fb15SMikko Perttunen }; 11895425fb15SMikko Perttunen 1190badb80beSThierry Reding cec@3960000 { 1191badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 1192badb80beSThierry Reding reg = <0x03960000 0x10000>; 1193badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1194badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1195badb80beSThierry Reding clock-names = "cec"; 1196badb80beSThierry Reding status = "disabled"; 1197badb80beSThierry Reding }; 1198badb80beSThierry Reding 11995425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1200a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 12015425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 1202a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1203a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1204a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1205a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1206a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1207a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1208a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1209a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1210a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1211a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1212a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1213a38570c2SMikko Perttunen "shared7"; 1214a38570c2SMikko Perttunen #mbox-cells = <2>; 1215a38570c2SMikko Perttunen }; 1216a38570c2SMikko Perttunen 12172602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 12182602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12192602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 12202602c32fSVidya Sagar reg-names = "ctl"; 12212602c32fSVidya Sagar 12222602c32fSVidya Sagar #phy-cells = <0>; 12232602c32fSVidya Sagar }; 12242602c32fSVidya Sagar 12252602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 12262602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12272602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 12282602c32fSVidya Sagar reg-names = "ctl"; 12292602c32fSVidya Sagar 12302602c32fSVidya Sagar #phy-cells = <0>; 12312602c32fSVidya Sagar }; 12322602c32fSVidya Sagar 12332602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 12342602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12352602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 12362602c32fSVidya Sagar reg-names = "ctl"; 12372602c32fSVidya Sagar 12382602c32fSVidya Sagar #phy-cells = <0>; 12392602c32fSVidya Sagar }; 12402602c32fSVidya Sagar 12412602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 12422602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12432602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 12442602c32fSVidya Sagar reg-names = "ctl"; 12452602c32fSVidya Sagar 12462602c32fSVidya Sagar #phy-cells = <0>; 12472602c32fSVidya Sagar }; 12482602c32fSVidya Sagar 12492602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 12502602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12512602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 12522602c32fSVidya Sagar reg-names = "ctl"; 12532602c32fSVidya Sagar 12542602c32fSVidya Sagar #phy-cells = <0>; 12552602c32fSVidya Sagar }; 12562602c32fSVidya Sagar 12572602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 12582602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12592602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 12602602c32fSVidya Sagar reg-names = "ctl"; 12612602c32fSVidya Sagar 12622602c32fSVidya Sagar #phy-cells = <0>; 12632602c32fSVidya Sagar }; 12642602c32fSVidya Sagar 12652602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 12662602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12672602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 12682602c32fSVidya Sagar reg-names = "ctl"; 12692602c32fSVidya Sagar 12702602c32fSVidya Sagar #phy-cells = <0>; 12712602c32fSVidya Sagar }; 12722602c32fSVidya Sagar 12732602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 12742602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12752602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 12762602c32fSVidya Sagar reg-names = "ctl"; 12772602c32fSVidya Sagar 12782602c32fSVidya Sagar #phy-cells = <0>; 12792602c32fSVidya Sagar }; 12802602c32fSVidya Sagar 12812602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 12822602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12832602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 12842602c32fSVidya Sagar reg-names = "ctl"; 12852602c32fSVidya Sagar 12862602c32fSVidya Sagar #phy-cells = <0>; 12872602c32fSVidya Sagar }; 12882602c32fSVidya Sagar 12892602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 12902602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12912602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 12922602c32fSVidya Sagar reg-names = "ctl"; 12932602c32fSVidya Sagar 12942602c32fSVidya Sagar #phy-cells = <0>; 12952602c32fSVidya Sagar }; 12962602c32fSVidya Sagar 12972602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 12982602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12992602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 13002602c32fSVidya Sagar reg-names = "ctl"; 13012602c32fSVidya Sagar 13022602c32fSVidya Sagar #phy-cells = <0>; 13032602c32fSVidya Sagar }; 13042602c32fSVidya Sagar 13052602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 13062602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13072602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 13082602c32fSVidya Sagar reg-names = "ctl"; 13092602c32fSVidya Sagar 13102602c32fSVidya Sagar #phy-cells = <0>; 13112602c32fSVidya Sagar }; 13122602c32fSVidya Sagar 13132602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 13142602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13152602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 13162602c32fSVidya Sagar reg-names = "ctl"; 13172602c32fSVidya Sagar 13182602c32fSVidya Sagar #phy-cells = <0>; 13192602c32fSVidya Sagar }; 13202602c32fSVidya Sagar 13212602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 13222602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13232602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 13242602c32fSVidya Sagar reg-names = "ctl"; 13252602c32fSVidya Sagar 13262602c32fSVidya Sagar #phy-cells = <0>; 13272602c32fSVidya Sagar }; 13282602c32fSVidya Sagar 13292602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 13302602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13312602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 13322602c32fSVidya Sagar reg-names = "ctl"; 13332602c32fSVidya Sagar 13342602c32fSVidya Sagar #phy-cells = <0>; 13352602c32fSVidya Sagar }; 13362602c32fSVidya Sagar 13372602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 13382602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13392602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 13402602c32fSVidya Sagar reg-names = "ctl"; 13412602c32fSVidya Sagar 13422602c32fSVidya Sagar #phy-cells = <0>; 13432602c32fSVidya Sagar }; 13442602c32fSVidya Sagar 13452602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 13462602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13472602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 13482602c32fSVidya Sagar reg-names = "ctl"; 13492602c32fSVidya Sagar 13502602c32fSVidya Sagar #phy-cells = <0>; 13512602c32fSVidya Sagar }; 13522602c32fSVidya Sagar 13532602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 13542602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13552602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 13562602c32fSVidya Sagar reg-names = "ctl"; 13572602c32fSVidya Sagar 13582602c32fSVidya Sagar #phy-cells = <0>; 13592602c32fSVidya Sagar }; 13602602c32fSVidya Sagar 13612602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 13622602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13632602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 13642602c32fSVidya Sagar reg-names = "ctl"; 13652602c32fSVidya Sagar 13662602c32fSVidya Sagar #phy-cells = <0>; 13672602c32fSVidya Sagar }; 13682602c32fSVidya Sagar 13692602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 13702602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13712602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 13722602c32fSVidya Sagar reg-names = "ctl"; 13732602c32fSVidya Sagar 13742602c32fSVidya Sagar #phy-cells = <0>; 13752602c32fSVidya Sagar }; 13762602c32fSVidya Sagar 1377a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1378a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 13791741e187SDipen Patel reg = <0x0c150000 0x90000>; 1380a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1381a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1382a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1383a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1384a38570c2SMikko Perttunen /* 1385a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1386a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1387a38570c2SMikko Perttunen */ 1388a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 13895425fb15SMikko Perttunen #mbox-cells = <2>; 13905425fb15SMikko Perttunen }; 13915425fb15SMikko Perttunen 13925425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1393d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 13945425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 13955425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 13965425fb15SMikko Perttunen #address-cells = <1>; 13975425fb15SMikko Perttunen #size-cells = <0>; 13985425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 13995425fb15SMikko Perttunen clock-names = "div-clk"; 14005425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 14015425fb15SMikko Perttunen reset-names = "i2c"; 14025425fb15SMikko Perttunen status = "disabled"; 14035425fb15SMikko Perttunen }; 14045425fb15SMikko Perttunen 14055425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1406d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 14075425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 14085425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 14095425fb15SMikko Perttunen #address-cells = <1>; 14105425fb15SMikko Perttunen #size-cells = <0>; 14115425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 14125425fb15SMikko Perttunen clock-names = "div-clk"; 14135425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 14145425fb15SMikko Perttunen reset-names = "i2c"; 14155425fb15SMikko Perttunen status = "disabled"; 14165425fb15SMikko Perttunen }; 14175425fb15SMikko Perttunen 14185425fb15SMikko Perttunen uartc: serial@c280000 { 14195425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 14205425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 14215425fb15SMikko Perttunen reg-shift = <2>; 14225425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 14235425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 14245425fb15SMikko Perttunen clock-names = "serial"; 14255425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 14265425fb15SMikko Perttunen reset-names = "serial"; 14275425fb15SMikko Perttunen status = "disabled"; 14285425fb15SMikko Perttunen }; 14295425fb15SMikko Perttunen 14305425fb15SMikko Perttunen uartg: serial@c290000 { 14315425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 14325425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 14335425fb15SMikko Perttunen reg-shift = <2>; 14345425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 14355425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 14365425fb15SMikko Perttunen clock-names = "serial"; 14375425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 14385425fb15SMikko Perttunen reset-names = "serial"; 14395425fb15SMikko Perttunen status = "disabled"; 14405425fb15SMikko Perttunen }; 14415425fb15SMikko Perttunen 144237e5a31dSThierry Reding rtc: rtc@c2a0000 { 144337e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 144437e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 144537e5a31dSThierry Reding interrupt-parent = <&pmc>; 144637e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 144737e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 144837e5a31dSThierry Reding clock-names = "rtc"; 144937e5a31dSThierry Reding status = "disabled"; 145037e5a31dSThierry Reding }; 145137e5a31dSThierry Reding 14524d286331SThierry Reding gpio_aon: gpio@c2f0000 { 14534d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 14544d286331SThierry Reding reg-names = "security", "gpio"; 14554d286331SThierry Reding reg = <0xc2f0000 0x1000>, 14564d286331SThierry Reding <0xc2f1000 0x1000>; 14570a85cf28Spshete interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 14580a85cf28Spshete <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 14590a85cf28Spshete <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 14600a85cf28Spshete <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 14614d286331SThierry Reding gpio-controller; 14624d286331SThierry Reding #gpio-cells = <2>; 14634d286331SThierry Reding interrupt-controller; 14644d286331SThierry Reding #interrupt-cells = <2>; 14654d286331SThierry Reding }; 14664d286331SThierry Reding 14676a574ec7SThierry Reding pwm4: pwm@c340000 { 14686a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 14696a574ec7SThierry Reding "nvidia,tegra186-pwm"; 14706a574ec7SThierry Reding reg = <0xc340000 0x10000>; 14716a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 14726a574ec7SThierry Reding clock-names = "pwm"; 14736a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 14746a574ec7SThierry Reding reset-names = "pwm"; 14756a574ec7SThierry Reding status = "disabled"; 14766a574ec7SThierry Reding #pwm-cells = <2>; 14776a574ec7SThierry Reding }; 14786a574ec7SThierry Reding 147938ecf1e5SThierry Reding pmc: pmc@c360000 { 14805425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 14815425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 14825425fb15SMikko Perttunen <0x0c370000 0x10000>, 14835425fb15SMikko Perttunen <0x0c380000 0x10000>, 14845425fb15SMikko Perttunen <0x0c390000 0x10000>, 14855425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 14865425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 148738ecf1e5SThierry Reding 148838ecf1e5SThierry Reding #interrupt-cells = <2>; 148938ecf1e5SThierry Reding interrupt-controller; 1490ff21087eSPrathamesh Shete sdmmc1_3v3: sdmmc1-3v3 { 1491ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1492ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1493ff21087eSPrathamesh Shete }; 1494ff21087eSPrathamesh Shete 1495ff21087eSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1496ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1497ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1498ff21087eSPrathamesh Shete }; 1499ff21087eSPrathamesh Shete sdmmc3_3v3: sdmmc3-3v3 { 1500ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1501ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1502ff21087eSPrathamesh Shete }; 1503ff21087eSPrathamesh Shete 1504ff21087eSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1505ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1506ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1507ff21087eSPrathamesh Shete }; 1508ff21087eSPrathamesh Shete 15095425fb15SMikko Perttunen }; 15103db6d3baSThierry Reding 1511*e762232fSJon Hunter iommu@10000000 { 1512*e762232fSJon Hunter compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1513*e762232fSJon Hunter reg = <0x10000000 0x800000>; 1514*e762232fSJon Hunter interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1515*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1516*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1517*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1518*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1519*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1520*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1521*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1522*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1523*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1524*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1525*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1526*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1527*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1528*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1529*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1530*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1531*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1532*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1533*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1534*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1535*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1536*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1537*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1538*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1539*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1540*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1541*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1542*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1543*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1544*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1545*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1546*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1547*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1548*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1549*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1550*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1551*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1552*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1553*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1554*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1555*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1556*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1557*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1558*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1559*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1560*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1561*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1562*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1563*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1564*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1565*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1566*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1567*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1568*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1569*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1570*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1571*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1572*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1573*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1574*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1575*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1576*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1577*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1578*e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1579*e762232fSJon Hunter stream-match-mask = <0x7f80>; 1580*e762232fSJon Hunter #global-interrupts = <1>; 1581*e762232fSJon Hunter #iommu-cells = <1>; 1582*e762232fSJon Hunter 1583*e762232fSJon Hunter nvidia,memory-controller = <&mc>; 1584*e762232fSJon Hunter status = "okay"; 1585*e762232fSJon Hunter }; 1586*e762232fSJon Hunter 1587c7289b1cSThierry Reding smmu: iommu@12000000 { 1588c7289b1cSThierry Reding compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1589c7289b1cSThierry Reding reg = <0x12000000 0x800000>, 1590c7289b1cSThierry Reding <0x11000000 0x800000>; 1591c7289b1cSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1592c7289b1cSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1593c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1594c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1595c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1596c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1597c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1598c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1599c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1600c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1601c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1602c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1603c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1604c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1605c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1606c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1607c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1608c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1609c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1610c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1611c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1612c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1613c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1614c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1615c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1616c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1617c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1618c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1619c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1620c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1621c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1622c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1623c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1624c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1625c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1626c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1627c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1628c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1629c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1630c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1631c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1632c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1633c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1634c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1635c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1636c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1637c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1638c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1639c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1640c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1641c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1642c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1643c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1644c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1645c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1646c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1647c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1648c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1649c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1650c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1651c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1652c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1653c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1654c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1655c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1656c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1657c7289b1cSThierry Reding stream-match-mask = <0x7f80>; 1658c7289b1cSThierry Reding #global-interrupts = <2>; 1659c7289b1cSThierry Reding #iommu-cells = <1>; 1660c7289b1cSThierry Reding 1661c7289b1cSThierry Reding nvidia,memory-controller = <&mc>; 1662c7289b1cSThierry Reding status = "okay"; 1663c7289b1cSThierry Reding }; 1664c7289b1cSThierry Reding 16653db6d3baSThierry Reding host1x@13e00000 { 1666ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 16673db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 16683db6d3baSThierry Reding <0x13e10000 0x10000>; 16693db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 16703db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 16713db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1672052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 16733db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 16743db6d3baSThierry Reding clock-names = "host1x"; 16753db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 16763db6d3baSThierry Reding reset-names = "host1x"; 16773db6d3baSThierry Reding 16783db6d3baSThierry Reding #address-cells = <1>; 16793db6d3baSThierry Reding #size-cells = <1>; 16803db6d3baSThierry Reding 16813db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 1682d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1683d5237c7cSThierry Reding interconnect-names = "dma-mem"; 1684c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HOST1X>; 16853db6d3baSThierry Reding 168678a05873SMikko Perttunen nvdec@15140000 { 168778a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 168878a05873SMikko Perttunen reg = <0x15140000 0x00040000>; 168978a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 169078a05873SMikko Perttunen clock-names = "nvdec"; 169178a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC1>; 169278a05873SMikko Perttunen reset-names = "nvdec"; 169378a05873SMikko Perttunen 169478a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 169578a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 169678a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 169778a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 169878a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 169978a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC1>; 170078a05873SMikko Perttunen dma-coherent; 170178a05873SMikko Perttunen 170278a05873SMikko Perttunen nvidia,host1x-class = <0xf5>; 170378a05873SMikko Perttunen }; 170478a05873SMikko Perttunen 17053db6d3baSThierry Reding display-hub@15200000 { 1706aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1707611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 17083db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 17093db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 17103db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 17113db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 17123db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 17133db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 17143db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 17153db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 17163db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 17173db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 17183db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 17193db6d3baSThierry Reding clock-names = "disp", "hub"; 17203db6d3baSThierry Reding status = "disabled"; 17213db6d3baSThierry Reding 17223db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 17233db6d3baSThierry Reding 17243db6d3baSThierry Reding #address-cells = <1>; 17253db6d3baSThierry Reding #size-cells = <1>; 17263db6d3baSThierry Reding 17273db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 17283db6d3baSThierry Reding 17293db6d3baSThierry Reding display@15200000 { 17303db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 17313db6d3baSThierry Reding reg = <0x15200000 0x10000>; 17323db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 17333db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 17343db6d3baSThierry Reding clock-names = "dc"; 17353db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 17363db6d3baSThierry Reding reset-names = "dc"; 17373db6d3baSThierry Reding 17383db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1739d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1740d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1741d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 17423db6d3baSThierry Reding 17433db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 17443db6d3baSThierry Reding nvidia,head = <0>; 17453db6d3baSThierry Reding }; 17463db6d3baSThierry Reding 17473db6d3baSThierry Reding display@15210000 { 17483db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 17493db6d3baSThierry Reding reg = <0x15210000 0x10000>; 17503db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 17513db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 17523db6d3baSThierry Reding clock-names = "dc"; 17533db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 17543db6d3baSThierry Reding reset-names = "dc"; 17553db6d3baSThierry Reding 17563db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1757d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1758d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1759d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 17603db6d3baSThierry Reding 17613db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 17623db6d3baSThierry Reding nvidia,head = <1>; 17633db6d3baSThierry Reding }; 17643db6d3baSThierry Reding 17653db6d3baSThierry Reding display@15220000 { 17663db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 17673db6d3baSThierry Reding reg = <0x15220000 0x10000>; 17683db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 17693db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 17703db6d3baSThierry Reding clock-names = "dc"; 17713db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 17723db6d3baSThierry Reding reset-names = "dc"; 17733db6d3baSThierry Reding 17743db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1775d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1776d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1777d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 17783db6d3baSThierry Reding 17793db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 17803db6d3baSThierry Reding nvidia,head = <2>; 17813db6d3baSThierry Reding }; 17823db6d3baSThierry Reding 17833db6d3baSThierry Reding display@15230000 { 17843db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 17853db6d3baSThierry Reding reg = <0x15230000 0x10000>; 17863db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 17873db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 17883db6d3baSThierry Reding clock-names = "dc"; 17893db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 17903db6d3baSThierry Reding reset-names = "dc"; 17913db6d3baSThierry Reding 17923db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1793d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1794d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1795d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 17963db6d3baSThierry Reding 17973db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 17983db6d3baSThierry Reding nvidia,head = <3>; 17993db6d3baSThierry Reding }; 18003db6d3baSThierry Reding }; 18013db6d3baSThierry Reding 18028d424ec2SThierry Reding vic@15340000 { 18038d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 18048d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 18058d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 18068d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 18078d424ec2SThierry Reding clock-names = "vic"; 18088d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 18098d424ec2SThierry Reding reset-names = "vic"; 18108d424ec2SThierry Reding 18118d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1812d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1813d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1814d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1815c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_VIC>; 18168d424ec2SThierry Reding }; 18178d424ec2SThierry Reding 1818f7eb2785SJon Hunter nvjpg@15380000 { 1819f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvjpg"; 1820f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 1821f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1822f7eb2785SJon Hunter clock-names = "nvjpg"; 1823f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVJPG>; 1824f7eb2785SJon Hunter reset-names = "nvjpg"; 1825f7eb2785SJon Hunter 1826f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1827f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1828f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1829f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1830f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVJPG>; 1831f7eb2785SJon Hunter dma-coherent; 1832f7eb2785SJon Hunter }; 1833f7eb2785SJon Hunter 183478a05873SMikko Perttunen nvdec@15480000 { 183578a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 183678a05873SMikko Perttunen reg = <0x15480000 0x00040000>; 183778a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC>; 183878a05873SMikko Perttunen clock-names = "nvdec"; 183978a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC>; 184078a05873SMikko Perttunen reset-names = "nvdec"; 184178a05873SMikko Perttunen 184278a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 184378a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 184478a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 184578a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 184678a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 184778a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC>; 184878a05873SMikko Perttunen dma-coherent; 184978a05873SMikko Perttunen 185078a05873SMikko Perttunen nvidia,host1x-class = <0xf0>; 185178a05873SMikko Perttunen }; 185278a05873SMikko Perttunen 1853f7eb2785SJon Hunter nvenc@154c0000 { 1854f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 1855f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 1856f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC>; 1857f7eb2785SJon Hunter clock-names = "nvenc"; 1858f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC>; 1859f7eb2785SJon Hunter reset-names = "nvenc"; 1860f7eb2785SJon Hunter 1861f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 1862f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 1863f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 1864f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 1865f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 1866f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC>; 1867f7eb2785SJon Hunter dma-coherent; 1868f7eb2785SJon Hunter 1869f7eb2785SJon Hunter nvidia,host1x-class = <0x21>; 1870f7eb2785SJon Hunter }; 1871f7eb2785SJon Hunter 18723db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 18733db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 18743db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 18753db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 18763db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 18773db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 18783db6d3baSThierry Reding clock-names = "dpaux", "parent"; 18793db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 18803db6d3baSThierry Reding reset-names = "dpaux"; 18813db6d3baSThierry Reding status = "disabled"; 18823db6d3baSThierry Reding 18833db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 18843db6d3baSThierry Reding 18853db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 18863db6d3baSThierry Reding groups = "dpaux-io"; 18873db6d3baSThierry Reding function = "aux"; 18883db6d3baSThierry Reding }; 18893db6d3baSThierry Reding 18903db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 18913db6d3baSThierry Reding groups = "dpaux-io"; 18923db6d3baSThierry Reding function = "i2c"; 18933db6d3baSThierry Reding }; 18943db6d3baSThierry Reding 18953db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 18963db6d3baSThierry Reding groups = "dpaux-io"; 18973db6d3baSThierry Reding function = "off"; 18983db6d3baSThierry Reding }; 18993db6d3baSThierry Reding 19003db6d3baSThierry Reding i2c-bus { 19013db6d3baSThierry Reding #address-cells = <1>; 19023db6d3baSThierry Reding #size-cells = <0>; 19033db6d3baSThierry Reding }; 19043db6d3baSThierry Reding }; 19053db6d3baSThierry Reding 19063db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 19073db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 19083db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 19093db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 19103db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 19113db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 19123db6d3baSThierry Reding clock-names = "dpaux", "parent"; 19133db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 19143db6d3baSThierry Reding reset-names = "dpaux"; 19153db6d3baSThierry Reding status = "disabled"; 19163db6d3baSThierry Reding 19173db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19183db6d3baSThierry Reding 19193db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 19203db6d3baSThierry Reding groups = "dpaux-io"; 19213db6d3baSThierry Reding function = "aux"; 19223db6d3baSThierry Reding }; 19233db6d3baSThierry Reding 19243db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 19253db6d3baSThierry Reding groups = "dpaux-io"; 19263db6d3baSThierry Reding function = "i2c"; 19273db6d3baSThierry Reding }; 19283db6d3baSThierry Reding 19293db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 19303db6d3baSThierry Reding groups = "dpaux-io"; 19313db6d3baSThierry Reding function = "off"; 19323db6d3baSThierry Reding }; 19333db6d3baSThierry Reding 19343db6d3baSThierry Reding i2c-bus { 19353db6d3baSThierry Reding #address-cells = <1>; 19363db6d3baSThierry Reding #size-cells = <0>; 19373db6d3baSThierry Reding }; 19383db6d3baSThierry Reding }; 19393db6d3baSThierry Reding 19403db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 19413db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 19423db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 19433db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 19443db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 19453db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 19463db6d3baSThierry Reding clock-names = "dpaux", "parent"; 19473db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 19483db6d3baSThierry Reding reset-names = "dpaux"; 19493db6d3baSThierry Reding status = "disabled"; 19503db6d3baSThierry Reding 19513db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19523db6d3baSThierry Reding 19533db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 19543db6d3baSThierry Reding groups = "dpaux-io"; 19553db6d3baSThierry Reding function = "aux"; 19563db6d3baSThierry Reding }; 19573db6d3baSThierry Reding 19583db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 19593db6d3baSThierry Reding groups = "dpaux-io"; 19603db6d3baSThierry Reding function = "i2c"; 19613db6d3baSThierry Reding }; 19623db6d3baSThierry Reding 19633db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 19643db6d3baSThierry Reding groups = "dpaux-io"; 19653db6d3baSThierry Reding function = "off"; 19663db6d3baSThierry Reding }; 19673db6d3baSThierry Reding 19683db6d3baSThierry Reding i2c-bus { 19693db6d3baSThierry Reding #address-cells = <1>; 19703db6d3baSThierry Reding #size-cells = <0>; 19713db6d3baSThierry Reding }; 19723db6d3baSThierry Reding }; 19733db6d3baSThierry Reding 19743db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 19753db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 19763db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 19773db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 19783db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 19793db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 19803db6d3baSThierry Reding clock-names = "dpaux", "parent"; 19813db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 19823db6d3baSThierry Reding reset-names = "dpaux"; 19833db6d3baSThierry Reding status = "disabled"; 19843db6d3baSThierry Reding 19853db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19863db6d3baSThierry Reding 19873db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 19883db6d3baSThierry Reding groups = "dpaux-io"; 19893db6d3baSThierry Reding function = "aux"; 19903db6d3baSThierry Reding }; 19913db6d3baSThierry Reding 19923db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 19933db6d3baSThierry Reding groups = "dpaux-io"; 19943db6d3baSThierry Reding function = "i2c"; 19953db6d3baSThierry Reding }; 19963db6d3baSThierry Reding 19973db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 19983db6d3baSThierry Reding groups = "dpaux-io"; 19993db6d3baSThierry Reding function = "off"; 20003db6d3baSThierry Reding }; 20013db6d3baSThierry Reding 20023db6d3baSThierry Reding i2c-bus { 20033db6d3baSThierry Reding #address-cells = <1>; 20043db6d3baSThierry Reding #size-cells = <0>; 20053db6d3baSThierry Reding }; 20063db6d3baSThierry Reding }; 20073db6d3baSThierry Reding 2008f7eb2785SJon Hunter nvenc@15a80000 { 2009f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 2010f7eb2785SJon Hunter reg = <0x15a80000 0x00040000>; 2011f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2012f7eb2785SJon Hunter clock-names = "nvenc"; 2013f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC1>; 2014f7eb2785SJon Hunter reset-names = "nvenc"; 2015f7eb2785SJon Hunter 2016f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2017f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2018f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2019f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2020f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2021f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC1>; 2022f7eb2785SJon Hunter dma-coherent; 2023f7eb2785SJon Hunter 2024f7eb2785SJon Hunter nvidia,host1x-class = <0x22>; 2025f7eb2785SJon Hunter }; 2026f7eb2785SJon Hunter 20273db6d3baSThierry Reding sor0: sor@15b00000 { 20283db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 20293db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 20303db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 20313db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 20323db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 20333db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 20343db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 20353db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 20363db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 20373db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 20383db6d3baSThierry Reding "pad"; 20393db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 20403db6d3baSThierry Reding reset-names = "sor"; 20413db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 20423db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 20433db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 20443db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 20453db6d3baSThierry Reding status = "disabled"; 20463db6d3baSThierry Reding 20473db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 20483db6d3baSThierry Reding nvidia,interface = <0>; 20493db6d3baSThierry Reding }; 20503db6d3baSThierry Reding 20513db6d3baSThierry Reding sor1: sor@15b40000 { 20523db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 2053939e7430SThierry Reding reg = <0x15b40000 0x40000>; 20543db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 20553db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 20563db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 20573db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 20583db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 20593db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 20603db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 20613db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 20623db6d3baSThierry Reding "pad"; 20633db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 20643db6d3baSThierry Reding reset-names = "sor"; 20653db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 20663db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 20673db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 20683db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 20693db6d3baSThierry Reding status = "disabled"; 20703db6d3baSThierry Reding 20713db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 20723db6d3baSThierry Reding nvidia,interface = <1>; 20733db6d3baSThierry Reding }; 20743db6d3baSThierry Reding 20753db6d3baSThierry Reding sor2: sor@15b80000 { 20763db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 20773db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 20783db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 20793db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 20803db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 20813db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 20823db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 20833db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 20843db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 20853db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 20863db6d3baSThierry Reding "pad"; 20873db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 20883db6d3baSThierry Reding reset-names = "sor"; 20893db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 20903db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 20913db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 20923db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 20933db6d3baSThierry Reding status = "disabled"; 20943db6d3baSThierry Reding 20953db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 20963db6d3baSThierry Reding nvidia,interface = <2>; 20973db6d3baSThierry Reding }; 20983db6d3baSThierry Reding 20993db6d3baSThierry Reding sor3: sor@15bc0000 { 21003db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 21013db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 21023db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 21033db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 21043db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 21053db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 21063db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 21073db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 21083db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 21093db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 21103db6d3baSThierry Reding "pad"; 21113db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 21123db6d3baSThierry Reding reset-names = "sor"; 21133db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 21143db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 21153db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 21163db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 21173db6d3baSThierry Reding status = "disabled"; 21183db6d3baSThierry Reding 21193db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21203db6d3baSThierry Reding nvidia,interface = <3>; 21213db6d3baSThierry Reding }; 21223db6d3baSThierry Reding }; 21230f134e39SThierry Reding 21240f134e39SThierry Reding gpu@17000000 { 21250f134e39SThierry Reding compatible = "nvidia,gv11b"; 2126818ae79aSThierry Reding reg = <0x17000000 0x1000000>, 2127818ae79aSThierry Reding <0x18000000 0x1000000>; 21280f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 21290f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 21300f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 21310f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 21320f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 21330f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 21340f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 21350f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 21360f134e39SThierry Reding reset-names = "gpu"; 21370f134e39SThierry Reding dma-coherent; 21380f134e39SThierry Reding 21390f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 21400f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 21410f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 21420f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 21430f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 21440f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 21450f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 21460f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 21470f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 21480f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 21490f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 21500f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 21510f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 21520f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 21530f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 21540f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 21550f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 21560f134e39SThierry Reding }; 21575425fb15SMikko Perttunen }; 21585425fb15SMikko Perttunen 21592602c32fSVidya Sagar pcie@14100000 { 2160f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 21612602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2162644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2163644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2164644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2165644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 21662602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 21672602c32fSVidya Sagar 21682602c32fSVidya Sagar status = "disabled"; 21692602c32fSVidya Sagar 21702602c32fSVidya Sagar #address-cells = <3>; 21712602c32fSVidya Sagar #size-cells = <2>; 21722602c32fSVidya Sagar device_type = "pci"; 21732602c32fSVidya Sagar num-lanes = <1>; 21742602c32fSVidya Sagar num-viewport = <8>; 21752602c32fSVidya Sagar linux,pci-domain = <1>; 21762602c32fSVidya Sagar 21772602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 21782602c32fSVidya Sagar clock-names = "core"; 21792602c32fSVidya Sagar 21802602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 21812602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 21822602c32fSVidya Sagar reset-names = "apb", "core"; 21832602c32fSVidya Sagar 21842602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 21852602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 21862602c32fSVidya Sagar interrupt-names = "intr", "msi"; 21872602c32fSVidya Sagar 21882602c32fSVidya Sagar #interrupt-cells = <1>; 21892602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 21902602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 21912602c32fSVidya Sagar 21922602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 21932602c32fSVidya Sagar 21942602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 21952602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 21962602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 21972602c32fSVidya Sagar 21982602c32fSVidya Sagar bus-range = <0x0 0xff>; 2199d5237c7cSThierry Reding 22008a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 22018a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 22028a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2203d5237c7cSThierry Reding 2204d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2205d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2206ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2207ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE1>; 2208ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2209ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2210ba02920cSVidya Sagar dma-coherent; 22112602c32fSVidya Sagar }; 22122602c32fSVidya Sagar 22132602c32fSVidya Sagar pcie@14120000 { 2214f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 22152602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2216644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2217644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2218644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2219644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 22202602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 22212602c32fSVidya Sagar 22222602c32fSVidya Sagar status = "disabled"; 22232602c32fSVidya Sagar 22242602c32fSVidya Sagar #address-cells = <3>; 22252602c32fSVidya Sagar #size-cells = <2>; 22262602c32fSVidya Sagar device_type = "pci"; 22272602c32fSVidya Sagar num-lanes = <1>; 22282602c32fSVidya Sagar num-viewport = <8>; 22292602c32fSVidya Sagar linux,pci-domain = <2>; 22302602c32fSVidya Sagar 22312602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 22322602c32fSVidya Sagar clock-names = "core"; 22332602c32fSVidya Sagar 22342602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 22352602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 22362602c32fSVidya Sagar reset-names = "apb", "core"; 22372602c32fSVidya Sagar 22382602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22392602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 22402602c32fSVidya Sagar interrupt-names = "intr", "msi"; 22412602c32fSVidya Sagar 22422602c32fSVidya Sagar #interrupt-cells = <1>; 22432602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 22442602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 22452602c32fSVidya Sagar 22462602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 22472602c32fSVidya Sagar 22482602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 22492602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 22502602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 22512602c32fSVidya Sagar 22522602c32fSVidya Sagar bus-range = <0x0 0xff>; 2253d5237c7cSThierry Reding 22548a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 22558a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 22568a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2257d5237c7cSThierry Reding 2258d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2259d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2260ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2261ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE2>; 2262ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2263ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2264ba02920cSVidya Sagar dma-coherent; 22652602c32fSVidya Sagar }; 22662602c32fSVidya Sagar 22672602c32fSVidya Sagar pcie@14140000 { 2268f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 22692602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2270644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2271644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2272644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2273644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 22742602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 22752602c32fSVidya Sagar 22762602c32fSVidya Sagar status = "disabled"; 22772602c32fSVidya Sagar 22782602c32fSVidya Sagar #address-cells = <3>; 22792602c32fSVidya Sagar #size-cells = <2>; 22802602c32fSVidya Sagar device_type = "pci"; 22812602c32fSVidya Sagar num-lanes = <1>; 22822602c32fSVidya Sagar num-viewport = <8>; 22832602c32fSVidya Sagar linux,pci-domain = <3>; 22842602c32fSVidya Sagar 22852602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 22862602c32fSVidya Sagar clock-names = "core"; 22872602c32fSVidya Sagar 22882602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 22892602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 22902602c32fSVidya Sagar reset-names = "apb", "core"; 22912602c32fSVidya Sagar 22922602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22932602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 22942602c32fSVidya Sagar interrupt-names = "intr", "msi"; 22952602c32fSVidya Sagar 22962602c32fSVidya Sagar #interrupt-cells = <1>; 22972602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 22982602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 22992602c32fSVidya Sagar 23002602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 23012602c32fSVidya Sagar 23022602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 23032602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 23042602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 23052602c32fSVidya Sagar 23062602c32fSVidya Sagar bus-range = <0x0 0xff>; 2307d5237c7cSThierry Reding 23088a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 23098a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 23108a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2311d5237c7cSThierry Reding 2312d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2313d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2314ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2315ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE3>; 2316ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2317ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2318ba02920cSVidya Sagar dma-coherent; 23192602c32fSVidya Sagar }; 23202602c32fSVidya Sagar 23212602c32fSVidya Sagar pcie@14160000 { 2322f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 23232602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2324644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2325644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2326644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2327644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 23282602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 23292602c32fSVidya Sagar 23302602c32fSVidya Sagar status = "disabled"; 23312602c32fSVidya Sagar 23322602c32fSVidya Sagar #address-cells = <3>; 23332602c32fSVidya Sagar #size-cells = <2>; 23342602c32fSVidya Sagar device_type = "pci"; 23352602c32fSVidya Sagar num-lanes = <4>; 23362602c32fSVidya Sagar num-viewport = <8>; 23372602c32fSVidya Sagar linux,pci-domain = <4>; 23382602c32fSVidya Sagar 23392602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 23402602c32fSVidya Sagar clock-names = "core"; 23412602c32fSVidya Sagar 23422602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 23432602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 23442602c32fSVidya Sagar reset-names = "apb", "core"; 23452602c32fSVidya Sagar 23462602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 23472602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 23482602c32fSVidya Sagar interrupt-names = "intr", "msi"; 23492602c32fSVidya Sagar 23502602c32fSVidya Sagar #interrupt-cells = <1>; 23512602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 23522602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 23532602c32fSVidya Sagar 23542602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 23552602c32fSVidya Sagar 23562602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 23572602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 23582602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 23592602c32fSVidya Sagar 23602602c32fSVidya Sagar bus-range = <0x0 0xff>; 2361d5237c7cSThierry Reding 23628a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 23638a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 23648a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2365d5237c7cSThierry Reding 2366d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2367d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2368ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2369ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE4>; 2370ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2371ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2372ba02920cSVidya Sagar dma-coherent; 23732602c32fSVidya Sagar }; 23742602c32fSVidya Sagar 23752602c32fSVidya Sagar pcie@14180000 { 2376f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 23772602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2378644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2379644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2380644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2381644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 23822602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 23832602c32fSVidya Sagar 23842602c32fSVidya Sagar status = "disabled"; 23852602c32fSVidya Sagar 23862602c32fSVidya Sagar #address-cells = <3>; 23872602c32fSVidya Sagar #size-cells = <2>; 23882602c32fSVidya Sagar device_type = "pci"; 23892602c32fSVidya Sagar num-lanes = <8>; 23902602c32fSVidya Sagar num-viewport = <8>; 23912602c32fSVidya Sagar linux,pci-domain = <0>; 23922602c32fSVidya Sagar 23932602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 23942602c32fSVidya Sagar clock-names = "core"; 23952602c32fSVidya Sagar 23962602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 23972602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 23982602c32fSVidya Sagar reset-names = "apb", "core"; 23992602c32fSVidya Sagar 24002602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24012602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24022602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24032602c32fSVidya Sagar 24042602c32fSVidya Sagar #interrupt-cells = <1>; 24052602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24062602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 24072602c32fSVidya Sagar 24082602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 24092602c32fSVidya Sagar 24102602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24112602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24122602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24132602c32fSVidya Sagar 24142602c32fSVidya Sagar bus-range = <0x0 0xff>; 2415d5237c7cSThierry Reding 24168a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 24178a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 24188a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2419d5237c7cSThierry Reding 2420d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2421d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2422ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2423ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE0>; 2424ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2425ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2426ba02920cSVidya Sagar dma-coherent; 24272602c32fSVidya Sagar }; 24282602c32fSVidya Sagar 24292602c32fSVidya Sagar pcie@141a0000 { 2430f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24312602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2432644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2433644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2434644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2435644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24362602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24372602c32fSVidya Sagar 24382602c32fSVidya Sagar status = "disabled"; 24392602c32fSVidya Sagar 24402602c32fSVidya Sagar #address-cells = <3>; 24412602c32fSVidya Sagar #size-cells = <2>; 24422602c32fSVidya Sagar device_type = "pci"; 24432602c32fSVidya Sagar num-lanes = <8>; 24442602c32fSVidya Sagar num-viewport = <8>; 24452602c32fSVidya Sagar linux,pci-domain = <5>; 24462602c32fSVidya Sagar 2447dbb72e2cSVidya Sagar pinctrl-names = "default"; 2448dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2449dbb72e2cSVidya Sagar 24502602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 24512602c32fSVidya Sagar <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 24522602c32fSVidya Sagar clock-names = "core", "core_m"; 24532602c32fSVidya Sagar 24542602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 24552602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 24562602c32fSVidya Sagar reset-names = "apb", "core"; 24572602c32fSVidya Sagar 24582602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24592602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24602602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24612602c32fSVidya Sagar 24622602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 24632602c32fSVidya Sagar 24642602c32fSVidya Sagar #interrupt-cells = <1>; 24652602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24662602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 24672602c32fSVidya Sagar 24682602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24692602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24702602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24712602c32fSVidya Sagar 24722602c32fSVidya Sagar bus-range = <0x0 0xff>; 2473d5237c7cSThierry Reding 24748a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 24758a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 24768a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2477d5237c7cSThierry Reding 2478d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2479d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2480ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2481ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE5>; 2482ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2483ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2484ba02920cSVidya Sagar dma-coherent; 24852602c32fSVidya Sagar }; 24862602c32fSVidya Sagar 2487b9e2404cSMauro Carvalho Chehab pcie-ep@14160000 { 2488bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 24890c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2490644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2491644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2492644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2493644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 24940c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 24950c988b73SVidya Sagar 24960c988b73SVidya Sagar status = "disabled"; 24970c988b73SVidya Sagar 24980c988b73SVidya Sagar num-lanes = <4>; 24990c988b73SVidya Sagar num-ib-windows = <2>; 25000c988b73SVidya Sagar num-ob-windows = <8>; 25010c988b73SVidya Sagar 25020c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 25030c988b73SVidya Sagar clock-names = "core"; 25040c988b73SVidya Sagar 25050c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 25060c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 25070c988b73SVidya Sagar reset-names = "apb", "core"; 25080c988b73SVidya Sagar 25090c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 25100c988b73SVidya Sagar interrupt-names = "intr"; 25110c988b73SVidya Sagar 25120c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 25130c988b73SVidya Sagar 25140c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 25150c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25160c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2517ba02920cSVidya Sagar 2518ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2519ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2520ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2521ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE4>; 2522ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2523ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2524ba02920cSVidya Sagar dma-coherent; 25250c988b73SVidya Sagar }; 25260c988b73SVidya Sagar 2527b9e2404cSMauro Carvalho Chehab pcie-ep@14180000 { 2528bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 25290c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2530644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2531644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2532644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2533644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 25340c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 25350c988b73SVidya Sagar 25360c988b73SVidya Sagar status = "disabled"; 25370c988b73SVidya Sagar 25380c988b73SVidya Sagar num-lanes = <8>; 25390c988b73SVidya Sagar num-ib-windows = <2>; 25400c988b73SVidya Sagar num-ob-windows = <8>; 25410c988b73SVidya Sagar 25420c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 25430c988b73SVidya Sagar clock-names = "core"; 25440c988b73SVidya Sagar 25450c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 25460c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 25470c988b73SVidya Sagar reset-names = "apb", "core"; 25480c988b73SVidya Sagar 25490c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 25500c988b73SVidya Sagar interrupt-names = "intr"; 25510c988b73SVidya Sagar 25520c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 25530c988b73SVidya Sagar 25540c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 25550c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25560c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2557ba02920cSVidya Sagar 2558ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2559ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2560ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2561ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE0>; 2562ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2563ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2564ba02920cSVidya Sagar dma-coherent; 25650c988b73SVidya Sagar }; 25660c988b73SVidya Sagar 2567b9e2404cSMauro Carvalho Chehab pcie-ep@141a0000 { 2568bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 25690c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2570644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2571644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2572644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2573644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 25740c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 25750c988b73SVidya Sagar 25760c988b73SVidya Sagar status = "disabled"; 25770c988b73SVidya Sagar 25780c988b73SVidya Sagar num-lanes = <8>; 25790c988b73SVidya Sagar num-ib-windows = <2>; 25800c988b73SVidya Sagar num-ob-windows = <8>; 25810c988b73SVidya Sagar 25820c988b73SVidya Sagar pinctrl-names = "default"; 25830c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 25840c988b73SVidya Sagar 25850c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 25860c988b73SVidya Sagar clock-names = "core"; 25870c988b73SVidya Sagar 25880c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 25890c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 25900c988b73SVidya Sagar reset-names = "apb", "core"; 25910c988b73SVidya Sagar 25920c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 25930c988b73SVidya Sagar interrupt-names = "intr"; 25940c988b73SVidya Sagar 25950c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 25960c988b73SVidya Sagar 25970c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 25980c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25990c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2600ba02920cSVidya Sagar 2601ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2602ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2603ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2604ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE5>; 2605ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2606ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2607ba02920cSVidya Sagar dma-coherent; 26080c988b73SVidya Sagar }; 26090c988b73SVidya Sagar 2610e867fe41SThierry Reding sram@40000000 { 26115425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 26125425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 26135425fb15SMikko Perttunen #address-cells = <1>; 26145425fb15SMikko Perttunen #size-cells = <1>; 26155425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 26165425fb15SMikko Perttunen 2617e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 26185425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 26195425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 26205425fb15SMikko Perttunen pool; 26215425fb15SMikko Perttunen }; 26225425fb15SMikko Perttunen 2623e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 26245425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 26255425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 26265425fb15SMikko Perttunen pool; 26275425fb15SMikko Perttunen }; 26285425fb15SMikko Perttunen }; 26295425fb15SMikko Perttunen 26305425fb15SMikko Perttunen bpmp: bpmp { 26315425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 26325425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 26335425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 26347fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 26355425fb15SMikko Perttunen #clock-cells = <1>; 26365425fb15SMikko Perttunen #reset-cells = <1>; 26375425fb15SMikko Perttunen #power-domain-cells = <1>; 2638d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2639d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2640d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2641d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2642d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 2643c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_BPMP>; 26445425fb15SMikko Perttunen 26455425fb15SMikko Perttunen bpmp_i2c: i2c { 26465425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 26475425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 26485425fb15SMikko Perttunen #address-cells = <1>; 26495425fb15SMikko Perttunen #size-cells = <0>; 26505425fb15SMikko Perttunen }; 26515425fb15SMikko Perttunen 26525425fb15SMikko Perttunen bpmp_thermal: thermal { 26535425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 26545425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 26555425fb15SMikko Perttunen }; 26565425fb15SMikko Perttunen }; 26575425fb15SMikko Perttunen 26587780a034SMikko Perttunen cpus { 2659d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2660d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 26617780a034SMikko Perttunen #address-cells = <1>; 26627780a034SMikko Perttunen #size-cells = <0>; 26637780a034SMikko Perttunen 2664b45d322cSThierry Reding cpu0_0: cpu@0 { 266531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 26667780a034SMikko Perttunen device_type = "cpu"; 2667b45d322cSThierry Reding reg = <0x000>; 26687780a034SMikko Perttunen enable-method = "psci"; 2669b45d322cSThierry Reding i-cache-size = <131072>; 2670b45d322cSThierry Reding i-cache-line-size = <64>; 2671b45d322cSThierry Reding i-cache-sets = <512>; 2672b45d322cSThierry Reding d-cache-size = <65536>; 2673b45d322cSThierry Reding d-cache-line-size = <64>; 2674b45d322cSThierry Reding d-cache-sets = <256>; 2675b45d322cSThierry Reding next-level-cache = <&l2c_0>; 26767780a034SMikko Perttunen }; 26777780a034SMikko Perttunen 2678b45d322cSThierry Reding cpu0_1: cpu@1 { 267931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 26807780a034SMikko Perttunen device_type = "cpu"; 2681b45d322cSThierry Reding reg = <0x001>; 26827780a034SMikko Perttunen enable-method = "psci"; 2683b45d322cSThierry Reding i-cache-size = <131072>; 2684b45d322cSThierry Reding i-cache-line-size = <64>; 2685b45d322cSThierry Reding i-cache-sets = <512>; 2686b45d322cSThierry Reding d-cache-size = <65536>; 2687b45d322cSThierry Reding d-cache-line-size = <64>; 2688b45d322cSThierry Reding d-cache-sets = <256>; 2689b45d322cSThierry Reding next-level-cache = <&l2c_0>; 26907780a034SMikko Perttunen }; 26917780a034SMikko Perttunen 2692b45d322cSThierry Reding cpu1_0: cpu@100 { 269331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 26947780a034SMikko Perttunen device_type = "cpu"; 26957780a034SMikko Perttunen reg = <0x100>; 26967780a034SMikko Perttunen enable-method = "psci"; 2697b45d322cSThierry Reding i-cache-size = <131072>; 2698b45d322cSThierry Reding i-cache-line-size = <64>; 2699b45d322cSThierry Reding i-cache-sets = <512>; 2700b45d322cSThierry Reding d-cache-size = <65536>; 2701b45d322cSThierry Reding d-cache-line-size = <64>; 2702b45d322cSThierry Reding d-cache-sets = <256>; 2703b45d322cSThierry Reding next-level-cache = <&l2c_1>; 27047780a034SMikko Perttunen }; 27057780a034SMikko Perttunen 2706b45d322cSThierry Reding cpu1_1: cpu@101 { 270731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27087780a034SMikko Perttunen device_type = "cpu"; 27097780a034SMikko Perttunen reg = <0x101>; 27107780a034SMikko Perttunen enable-method = "psci"; 2711b45d322cSThierry Reding i-cache-size = <131072>; 2712b45d322cSThierry Reding i-cache-line-size = <64>; 2713b45d322cSThierry Reding i-cache-sets = <512>; 2714b45d322cSThierry Reding d-cache-size = <65536>; 2715b45d322cSThierry Reding d-cache-line-size = <64>; 2716b45d322cSThierry Reding d-cache-sets = <256>; 2717b45d322cSThierry Reding next-level-cache = <&l2c_1>; 27187780a034SMikko Perttunen }; 27197780a034SMikko Perttunen 2720b45d322cSThierry Reding cpu2_0: cpu@200 { 272131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27227780a034SMikko Perttunen device_type = "cpu"; 27237780a034SMikko Perttunen reg = <0x200>; 27247780a034SMikko Perttunen enable-method = "psci"; 2725b45d322cSThierry Reding i-cache-size = <131072>; 2726b45d322cSThierry Reding i-cache-line-size = <64>; 2727b45d322cSThierry Reding i-cache-sets = <512>; 2728b45d322cSThierry Reding d-cache-size = <65536>; 2729b45d322cSThierry Reding d-cache-line-size = <64>; 2730b45d322cSThierry Reding d-cache-sets = <256>; 2731b45d322cSThierry Reding next-level-cache = <&l2c_2>; 27327780a034SMikko Perttunen }; 27337780a034SMikko Perttunen 2734b45d322cSThierry Reding cpu2_1: cpu@201 { 273531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27367780a034SMikko Perttunen device_type = "cpu"; 27377780a034SMikko Perttunen reg = <0x201>; 27387780a034SMikko Perttunen enable-method = "psci"; 2739b45d322cSThierry Reding i-cache-size = <131072>; 2740b45d322cSThierry Reding i-cache-line-size = <64>; 2741b45d322cSThierry Reding i-cache-sets = <512>; 2742b45d322cSThierry Reding d-cache-size = <65536>; 2743b45d322cSThierry Reding d-cache-line-size = <64>; 2744b45d322cSThierry Reding d-cache-sets = <256>; 2745b45d322cSThierry Reding next-level-cache = <&l2c_2>; 27467780a034SMikko Perttunen }; 27477780a034SMikko Perttunen 2748b45d322cSThierry Reding cpu3_0: cpu@300 { 274931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27507780a034SMikko Perttunen device_type = "cpu"; 2751b45d322cSThierry Reding reg = <0x300>; 27527780a034SMikko Perttunen enable-method = "psci"; 2753b45d322cSThierry Reding i-cache-size = <131072>; 2754b45d322cSThierry Reding i-cache-line-size = <64>; 2755b45d322cSThierry Reding i-cache-sets = <512>; 2756b45d322cSThierry Reding d-cache-size = <65536>; 2757b45d322cSThierry Reding d-cache-line-size = <64>; 2758b45d322cSThierry Reding d-cache-sets = <256>; 2759b45d322cSThierry Reding next-level-cache = <&l2c_3>; 27607780a034SMikko Perttunen }; 27617780a034SMikko Perttunen 2762b45d322cSThierry Reding cpu3_1: cpu@301 { 276331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27647780a034SMikko Perttunen device_type = "cpu"; 2765b45d322cSThierry Reding reg = <0x301>; 27667780a034SMikko Perttunen enable-method = "psci"; 2767b45d322cSThierry Reding i-cache-size = <131072>; 2768b45d322cSThierry Reding i-cache-line-size = <64>; 2769b45d322cSThierry Reding i-cache-sets = <512>; 2770b45d322cSThierry Reding d-cache-size = <65536>; 2771b45d322cSThierry Reding d-cache-line-size = <64>; 2772b45d322cSThierry Reding d-cache-sets = <256>; 2773b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2774b45d322cSThierry Reding }; 2775b45d322cSThierry Reding 2776b45d322cSThierry Reding cpu-map { 2777b45d322cSThierry Reding cluster0 { 2778b45d322cSThierry Reding core0 { 2779b45d322cSThierry Reding cpu = <&cpu0_0>; 2780b45d322cSThierry Reding }; 2781b45d322cSThierry Reding 2782b45d322cSThierry Reding core1 { 2783b45d322cSThierry Reding cpu = <&cpu0_1>; 2784b45d322cSThierry Reding }; 2785b45d322cSThierry Reding }; 2786b45d322cSThierry Reding 2787b45d322cSThierry Reding cluster1 { 2788b45d322cSThierry Reding core0 { 2789b45d322cSThierry Reding cpu = <&cpu1_0>; 2790b45d322cSThierry Reding }; 2791b45d322cSThierry Reding 2792b45d322cSThierry Reding core1 { 2793b45d322cSThierry Reding cpu = <&cpu1_1>; 2794b45d322cSThierry Reding }; 2795b45d322cSThierry Reding }; 2796b45d322cSThierry Reding 2797b45d322cSThierry Reding cluster2 { 2798b45d322cSThierry Reding core0 { 2799b45d322cSThierry Reding cpu = <&cpu2_0>; 2800b45d322cSThierry Reding }; 2801b45d322cSThierry Reding 2802b45d322cSThierry Reding core1 { 2803b45d322cSThierry Reding cpu = <&cpu2_1>; 2804b45d322cSThierry Reding }; 2805b45d322cSThierry Reding }; 2806b45d322cSThierry Reding 2807b45d322cSThierry Reding cluster3 { 2808b45d322cSThierry Reding core0 { 2809b45d322cSThierry Reding cpu = <&cpu3_0>; 2810b45d322cSThierry Reding }; 2811b45d322cSThierry Reding 2812b45d322cSThierry Reding core1 { 2813b45d322cSThierry Reding cpu = <&cpu3_1>; 2814b45d322cSThierry Reding }; 2815b45d322cSThierry Reding }; 2816b45d322cSThierry Reding }; 2817b45d322cSThierry Reding 2818b45d322cSThierry Reding l2c_0: l2-cache0 { 2819b45d322cSThierry Reding cache-size = <2097152>; 2820b45d322cSThierry Reding cache-line-size = <64>; 2821b45d322cSThierry Reding cache-sets = <2048>; 2822b45d322cSThierry Reding next-level-cache = <&l3c>; 2823b45d322cSThierry Reding }; 2824b45d322cSThierry Reding 2825b45d322cSThierry Reding l2c_1: l2-cache1 { 2826b45d322cSThierry Reding cache-size = <2097152>; 2827b45d322cSThierry Reding cache-line-size = <64>; 2828b45d322cSThierry Reding cache-sets = <2048>; 2829b45d322cSThierry Reding next-level-cache = <&l3c>; 2830b45d322cSThierry Reding }; 2831b45d322cSThierry Reding 2832b45d322cSThierry Reding l2c_2: l2-cache2 { 2833b45d322cSThierry Reding cache-size = <2097152>; 2834b45d322cSThierry Reding cache-line-size = <64>; 2835b45d322cSThierry Reding cache-sets = <2048>; 2836b45d322cSThierry Reding next-level-cache = <&l3c>; 2837b45d322cSThierry Reding }; 2838b45d322cSThierry Reding 2839b45d322cSThierry Reding l2c_3: l2-cache3 { 2840b45d322cSThierry Reding cache-size = <2097152>; 2841b45d322cSThierry Reding cache-line-size = <64>; 2842b45d322cSThierry Reding cache-sets = <2048>; 2843b45d322cSThierry Reding next-level-cache = <&l3c>; 2844b45d322cSThierry Reding }; 2845b45d322cSThierry Reding 2846b45d322cSThierry Reding l3c: l3-cache { 2847b45d322cSThierry Reding cache-size = <4194304>; 2848b45d322cSThierry Reding cache-line-size = <64>; 2849b45d322cSThierry Reding cache-sets = <4096>; 28507780a034SMikko Perttunen }; 28517780a034SMikko Perttunen }; 28527780a034SMikko Perttunen 28539e79e58fSJon Hunter pmu { 28549e79e58fSJon Hunter compatible = "arm,armv8-pmuv3"; 28559e79e58fSJon Hunter interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 28569e79e58fSJon Hunter <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 28579e79e58fSJon Hunter <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 28589e79e58fSJon Hunter <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 28599e79e58fSJon Hunter <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 28609e79e58fSJon Hunter <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 28619e79e58fSJon Hunter <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 28629e79e58fSJon Hunter <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 28639e79e58fSJon Hunter interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 28649e79e58fSJon Hunter &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 28659e79e58fSJon Hunter }; 28669e79e58fSJon Hunter 28677780a034SMikko Perttunen psci { 28687780a034SMikko Perttunen compatible = "arm,psci-1.0"; 28697780a034SMikko Perttunen status = "okay"; 28707780a034SMikko Perttunen method = "smc"; 28717780a034SMikko Perttunen }; 28727780a034SMikko Perttunen 28735b4f6323SSameer Pujar sound { 28745b4f6323SSameer Pujar status = "disabled"; 28755b4f6323SSameer Pujar 28765b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 28775b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 28785b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 28795b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 28805b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 28815b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 28825b4f6323SSameer Pujar assigned-clock-parents = <0>, 28835b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 28845b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 28855b4f6323SSameer Pujar /* 28865b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 28875b4f6323SSameer Pujar * for this to work and oscillate between base rates required 28885b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 28895b4f6323SSameer Pujar */ 28905b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 289134e0fc34SThierry Reding 289234e0fc34SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 289334e0fc34SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 289434e0fc34SThierry Reding interconnect-names = "dma-mem", "write"; 289534e0fc34SThierry Reding iommus = <&smmu TEGRA194_SID_APE>; 28965b4f6323SSameer Pujar }; 28975b4f6323SSameer Pujar 2898a38570c2SMikko Perttunen tcu: tcu { 2899a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 2900a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2901a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2902a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 2903a38570c2SMikko Perttunen }; 2904a38570c2SMikko Perttunen 2905686ba009SThierry Reding thermal-zones { 2906686ba009SThierry Reding cpu { 2907686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2908686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2909686ba009SThierry Reding status = "disabled"; 2910686ba009SThierry Reding }; 2911686ba009SThierry Reding 2912686ba009SThierry Reding gpu { 2913686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2914686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2915686ba009SThierry Reding status = "disabled"; 2916686ba009SThierry Reding }; 2917686ba009SThierry Reding 2918686ba009SThierry Reding aux { 2919686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2920686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2921686ba009SThierry Reding status = "disabled"; 2922686ba009SThierry Reding }; 2923686ba009SThierry Reding 2924686ba009SThierry Reding pllx { 2925686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2926686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2927686ba009SThierry Reding status = "disabled"; 2928686ba009SThierry Reding }; 2929686ba009SThierry Reding 2930686ba009SThierry Reding ao { 2931686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2932686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AO>; 2933686ba009SThierry Reding status = "disabled"; 2934686ba009SThierry Reding }; 2935686ba009SThierry Reding 2936686ba009SThierry Reding tj { 2937686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2938686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2939686ba009SThierry Reding status = "disabled"; 2940686ba009SThierry Reding }; 2941686ba009SThierry Reding }; 2942686ba009SThierry Reding 29435425fb15SMikko Perttunen timer { 29445425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 29455425fb15SMikko Perttunen interrupts = <GIC_PPI 13 29465425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 29475425fb15SMikko Perttunen <GIC_PPI 14 29485425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 29495425fb15SMikko Perttunen <GIC_PPI 11 29505425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 29515425fb15SMikko Perttunen <GIC_PPI 10 29525425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 29535425fb15SMikko Perttunen interrupt-parent = <&gic>; 2954b30be673SThierry Reding always-on; 29555425fb15SMikko Perttunen }; 29565425fb15SMikko Perttunen}; 2957