15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6ff21087eSPrathamesh Shete#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 83db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 9dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 10686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 125425fb15SMikko Perttunen 135425fb15SMikko Perttunen/ { 145425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 155425fb15SMikko Perttunen interrupt-parent = <&gic>; 165425fb15SMikko Perttunen #address-cells = <2>; 175425fb15SMikko Perttunen #size-cells = <2>; 185425fb15SMikko Perttunen 195425fb15SMikko Perttunen /* control backbone */ 208b3aee8fSThierry Reding bus@0 { 215425fb15SMikko Perttunen compatible = "simple-bus"; 225425fb15SMikko Perttunen #address-cells = <1>; 235425fb15SMikko Perttunen #size-cells = <1>; 245425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 255425fb15SMikko Perttunen 26a47e173eSSumit Gupta apbmisc: misc@100000 { 2709903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2809903c5eSJC Kuo reg = <0x00100000 0xf000>, 2909903c5eSJC Kuo <0x0010f000 0x1000>; 3009903c5eSJC Kuo }; 3109903c5eSJC Kuo 32f69ce393SMikko Perttunen gpio: gpio@2200000 { 33f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 34f69ce393SMikko Perttunen reg-names = "security", "gpio"; 35f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 36f69ce393SMikko Perttunen <0x2210000 0x10000>; 37f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 380a85cf28Spshete <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 390a85cf28Spshete <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 400a85cf28Spshete <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 410a85cf28Spshete <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 420a85cf28Spshete <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 430a85cf28Spshete <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 440a85cf28Spshete <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 460a85cf28Spshete <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 470a85cf28Spshete <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 480a85cf28Spshete <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 490a85cf28Spshete <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 500a85cf28Spshete <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 510a85cf28Spshete <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 520a85cf28Spshete <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 540a85cf28Spshete <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 550a85cf28Spshete <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 560a85cf28Spshete <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 570a85cf28Spshete <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 580a85cf28Spshete <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 590a85cf28Spshete <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 600a85cf28Spshete <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 620a85cf28Spshete <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 630a85cf28Spshete <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 640a85cf28Spshete <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 650a85cf28Spshete <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 660a85cf28Spshete <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 670a85cf28Spshete <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 680a85cf28Spshete <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 700a85cf28Spshete <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 710a85cf28Spshete <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 720a85cf28Spshete <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 730a85cf28Spshete <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 740a85cf28Spshete <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 750a85cf28Spshete <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 760a85cf28Spshete <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 770a85cf28Spshete <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 780a85cf28Spshete <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 790a85cf28Spshete <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 800a85cf28Spshete <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 810a85cf28Spshete <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 820a85cf28Spshete <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 830a85cf28Spshete <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 840a85cf28Spshete <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85f69ce393SMikko Perttunen #interrupt-cells = <2>; 86f69ce393SMikko Perttunen interrupt-controller; 87f69ce393SMikko Perttunen #gpio-cells = <2>; 88f69ce393SMikko Perttunen gpio-controller; 89f69ce393SMikko Perttunen }; 90f69ce393SMikko Perttunen 91a47e173eSSumit Gupta cbb-noc@2300000 { 92a47e173eSSumit Gupta compatible = "nvidia,tegra194-cbb-noc"; 93a47e173eSSumit Gupta reg = <0x02300000 0x1000>; 94a47e173eSSumit Gupta interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 95a47e173eSSumit Gupta <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 96a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 97a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 98a47e173eSSumit Gupta status = "okay"; 99a47e173eSSumit Gupta }; 100a47e173eSSumit Gupta 101a47e173eSSumit Gupta axi2apb: axi2apb@2390000 { 102a47e173eSSumit Gupta compatible = "nvidia,tegra194-axi2apb"; 103a47e173eSSumit Gupta reg = <0x2390000 0x1000>, 104a47e173eSSumit Gupta <0x23a0000 0x1000>, 105a47e173eSSumit Gupta <0x23b0000 0x1000>, 106a47e173eSSumit Gupta <0x23c0000 0x1000>, 107a47e173eSSumit Gupta <0x23d0000 0x1000>, 108a47e173eSSumit Gupta <0x23e0000 0x1000>; 109a47e173eSSumit Gupta status = "okay"; 110a47e173eSSumit Gupta }; 111a47e173eSSumit Gupta 112f89b58ceSMikko Perttunen ethernet@2490000 { 11319dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 11419dc772aSThierry Reding "nvidia,tegra186-eqos", 115f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 116f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 117f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 118f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 119f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 120f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 121f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 122f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 123f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 124f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 125f89b58ceSMikko Perttunen reset-names = "eqos"; 126d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 127d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 128d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 129c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_EQOS>; 130f89b58ceSMikko Perttunen status = "disabled"; 131f89b58ceSMikko Perttunen 132f89b58ceSMikko Perttunen snps,write-requests = <1>; 133f89b58ceSMikko Perttunen snps,read-requests = <3>; 134f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 135f89b58ceSMikko Perttunen snps,txpbl = <16>; 136f89b58ceSMikko Perttunen snps,rxpbl = <8>; 137f89b58ceSMikko Perttunen }; 138f89b58ceSMikko Perttunen 139835553b3SAkhil R gpcdma: dma-controller@2600000 { 140835553b3SAkhil R compatible = "nvidia,tegra194-gpcdma", 141835553b3SAkhil R "nvidia,tegra186-gpcdma"; 142835553b3SAkhil R reg = <0x2600000 0x210000>; 143835553b3SAkhil R resets = <&bpmp TEGRA194_RESET_GPCDMA>; 144835553b3SAkhil R reset-names = "gpcdma"; 145835553b3SAkhil R interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 146835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 147835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 148835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 149835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 150835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 151835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 152835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 153835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 154835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 155835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 156835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 157835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 158835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 159835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 160835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 161835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 162835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 163835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 164835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 165835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 166835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 167835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 168835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 169835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 170835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 171835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 172835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 173835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 174835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 175835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 176835553b3SAkhil R #dma-cells = <1>; 177835553b3SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 178835553b3SAkhil R dma-coherent; 179835553b3SAkhil R status = "okay"; 180835553b3SAkhil R }; 181835553b3SAkhil R 1821aaa7698SThierry Reding aconnect@2900000 { 1835d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 1845d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1855d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 1865d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 1875d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1885d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 1895d2249ddSSameer Pujar #address-cells = <1>; 1905d2249ddSSameer Pujar #size-cells = <1>; 1915d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 1925d2249ddSSameer Pujar status = "disabled"; 1935d2249ddSSameer Pujar 194177208f7SSameer Pujar adma: dma-controller@2930000 { 1955d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 1965d2249ddSSameer Pujar "nvidia,tegra186-adma"; 1975d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 1985d2249ddSSameer Pujar interrupt-parent = <&agic>; 1995d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 2005d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 2015d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 2025d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2035d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2045d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 2055d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 2065d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2075d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2085d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 2095d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 2105d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 2115d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 2125d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 2135d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 2145d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 2155d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 2165d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 2175d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 2185d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 2195d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 2205d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 2215d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 2225d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 2235d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 2245d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 2255d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 2265d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 2275d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 2285d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 2295d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 2305d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2315d2249ddSSameer Pujar #dma-cells = <1>; 2325d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 2335d2249ddSSameer Pujar clock-names = "d_audio"; 2345d2249ddSSameer Pujar status = "disabled"; 2355d2249ddSSameer Pujar }; 2365d2249ddSSameer Pujar 2375d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 2385d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 2395d2249ddSSameer Pujar "nvidia,tegra210-agic"; 2405d2249ddSSameer Pujar #interrupt-cells = <3>; 2415d2249ddSSameer Pujar interrupt-controller; 2425d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 2435d2249ddSSameer Pujar <0x02a42000 0x2000>; 2445d2249ddSSameer Pujar interrupts = <GIC_SPI 145 2455d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 2465d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 2475d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 2485d2249ddSSameer Pujar clock-names = "clk"; 2495d2249ddSSameer Pujar status = "disabled"; 2505d2249ddSSameer Pujar }; 251177208f7SSameer Pujar 252177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 253177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 254177208f7SSameer Pujar "nvidia,tegra186-ahub"; 255177208f7SSameer Pujar reg = <0x02900800 0x800>; 256177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 257177208f7SSameer Pujar clock-names = "ahub"; 258177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 259177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 260177208f7SSameer Pujar #address-cells = <1>; 261177208f7SSameer Pujar #size-cells = <1>; 262177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 263177208f7SSameer Pujar status = "disabled"; 264177208f7SSameer Pujar 265177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 266177208f7SSameer Pujar compatible = "nvidia,tegra194-admaif", 267177208f7SSameer Pujar "nvidia,tegra186-admaif"; 268177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 269177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 270177208f7SSameer Pujar <&adma 2>, <&adma 2>, 271177208f7SSameer Pujar <&adma 3>, <&adma 3>, 272177208f7SSameer Pujar <&adma 4>, <&adma 4>, 273177208f7SSameer Pujar <&adma 5>, <&adma 5>, 274177208f7SSameer Pujar <&adma 6>, <&adma 6>, 275177208f7SSameer Pujar <&adma 7>, <&adma 7>, 276177208f7SSameer Pujar <&adma 8>, <&adma 8>, 277177208f7SSameer Pujar <&adma 9>, <&adma 9>, 278177208f7SSameer Pujar <&adma 10>, <&adma 10>, 279177208f7SSameer Pujar <&adma 11>, <&adma 11>, 280177208f7SSameer Pujar <&adma 12>, <&adma 12>, 281177208f7SSameer Pujar <&adma 13>, <&adma 13>, 282177208f7SSameer Pujar <&adma 14>, <&adma 14>, 283177208f7SSameer Pujar <&adma 15>, <&adma 15>, 284177208f7SSameer Pujar <&adma 16>, <&adma 16>, 285177208f7SSameer Pujar <&adma 17>, <&adma 17>, 286177208f7SSameer Pujar <&adma 18>, <&adma 18>, 287177208f7SSameer Pujar <&adma 19>, <&adma 19>, 288177208f7SSameer Pujar <&adma 20>, <&adma 20>; 289177208f7SSameer Pujar dma-names = "rx1", "tx1", 290177208f7SSameer Pujar "rx2", "tx2", 291177208f7SSameer Pujar "rx3", "tx3", 292177208f7SSameer Pujar "rx4", "tx4", 293177208f7SSameer Pujar "rx5", "tx5", 294177208f7SSameer Pujar "rx6", "tx6", 295177208f7SSameer Pujar "rx7", "tx7", 296177208f7SSameer Pujar "rx8", "tx8", 297177208f7SSameer Pujar "rx9", "tx9", 298177208f7SSameer Pujar "rx10", "tx10", 299177208f7SSameer Pujar "rx11", "tx11", 300177208f7SSameer Pujar "rx12", "tx12", 301177208f7SSameer Pujar "rx13", "tx13", 302177208f7SSameer Pujar "rx14", "tx14", 303177208f7SSameer Pujar "rx15", "tx15", 304177208f7SSameer Pujar "rx16", "tx16", 305177208f7SSameer Pujar "rx17", "tx17", 306177208f7SSameer Pujar "rx18", "tx18", 307177208f7SSameer Pujar "rx19", "tx19", 308177208f7SSameer Pujar "rx20", "tx20"; 309177208f7SSameer Pujar status = "disabled"; 310cd0c2edfSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 311cd0c2edfSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 312cd0c2edfSThierry Reding interconnect-names = "dma-mem", "write"; 313cd0c2edfSThierry Reding iommus = <&smmu TEGRA194_SID_APE>; 314177208f7SSameer Pujar }; 315177208f7SSameer Pujar 316177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 317177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 318177208f7SSameer Pujar "nvidia,tegra210-i2s"; 319177208f7SSameer Pujar reg = <0x2901000 0x100>; 320177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 321177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 322177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 323177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 324177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 325177208f7SSameer Pujar assigned-clock-rates = <1536000>; 326177208f7SSameer Pujar sound-name-prefix = "I2S1"; 327177208f7SSameer Pujar status = "disabled"; 328177208f7SSameer Pujar }; 329177208f7SSameer Pujar 330177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 331177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 332177208f7SSameer Pujar "nvidia,tegra210-i2s"; 333177208f7SSameer Pujar reg = <0x2901100 0x100>; 334177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 335177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 336177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 337177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 338177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 339177208f7SSameer Pujar assigned-clock-rates = <1536000>; 340177208f7SSameer Pujar sound-name-prefix = "I2S2"; 341177208f7SSameer Pujar status = "disabled"; 342177208f7SSameer Pujar }; 343177208f7SSameer Pujar 344177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 345177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 346177208f7SSameer Pujar "nvidia,tegra210-i2s"; 347177208f7SSameer Pujar reg = <0x2901200 0x100>; 348177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 349177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 350177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 351177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 352177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 353177208f7SSameer Pujar assigned-clock-rates = <1536000>; 354177208f7SSameer Pujar sound-name-prefix = "I2S3"; 355177208f7SSameer Pujar status = "disabled"; 356177208f7SSameer Pujar }; 357177208f7SSameer Pujar 358177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 359177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 360177208f7SSameer Pujar "nvidia,tegra210-i2s"; 361177208f7SSameer Pujar reg = <0x2901300 0x100>; 362177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 363177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 364177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 365177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 366177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 367177208f7SSameer Pujar assigned-clock-rates = <1536000>; 368177208f7SSameer Pujar sound-name-prefix = "I2S4"; 369177208f7SSameer Pujar status = "disabled"; 370177208f7SSameer Pujar }; 371177208f7SSameer Pujar 372177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 373177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 374177208f7SSameer Pujar "nvidia,tegra210-i2s"; 375177208f7SSameer Pujar reg = <0x2901400 0x100>; 376177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 377177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 378177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 379177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 380177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 381177208f7SSameer Pujar assigned-clock-rates = <1536000>; 382177208f7SSameer Pujar sound-name-prefix = "I2S5"; 383177208f7SSameer Pujar status = "disabled"; 384177208f7SSameer Pujar }; 385177208f7SSameer Pujar 386177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 387177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 388177208f7SSameer Pujar "nvidia,tegra210-i2s"; 389177208f7SSameer Pujar reg = <0x2901500 0x100>; 390177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 391177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 392177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 393177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 394177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 395177208f7SSameer Pujar assigned-clock-rates = <1536000>; 396177208f7SSameer Pujar sound-name-prefix = "I2S6"; 397177208f7SSameer Pujar status = "disabled"; 398177208f7SSameer Pujar }; 399177208f7SSameer Pujar 400177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 401177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 402177208f7SSameer Pujar "nvidia,tegra210-dmic"; 403177208f7SSameer Pujar reg = <0x2904000 0x100>; 404177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 405177208f7SSameer Pujar clock-names = "dmic"; 406177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 407177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 408177208f7SSameer Pujar assigned-clock-rates = <3072000>; 409177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 410177208f7SSameer Pujar status = "disabled"; 411177208f7SSameer Pujar }; 412177208f7SSameer Pujar 413177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 414177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 415177208f7SSameer Pujar "nvidia,tegra210-dmic"; 416177208f7SSameer Pujar reg = <0x2904100 0x100>; 417177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 418177208f7SSameer Pujar clock-names = "dmic"; 419177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 420177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 421177208f7SSameer Pujar assigned-clock-rates = <3072000>; 422177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 423177208f7SSameer Pujar status = "disabled"; 424177208f7SSameer Pujar }; 425177208f7SSameer Pujar 426177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 427177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 428177208f7SSameer Pujar "nvidia,tegra210-dmic"; 429177208f7SSameer Pujar reg = <0x2904200 0x100>; 430177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 431177208f7SSameer Pujar clock-names = "dmic"; 432177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 433177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 434177208f7SSameer Pujar assigned-clock-rates = <3072000>; 435177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 436177208f7SSameer Pujar status = "disabled"; 437177208f7SSameer Pujar }; 438177208f7SSameer Pujar 439177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 440177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 441177208f7SSameer Pujar "nvidia,tegra210-dmic"; 442177208f7SSameer Pujar reg = <0x2904300 0x100>; 443177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 444177208f7SSameer Pujar clock-names = "dmic"; 445177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 446177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 447177208f7SSameer Pujar assigned-clock-rates = <3072000>; 448177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 449177208f7SSameer Pujar status = "disabled"; 450177208f7SSameer Pujar }; 451177208f7SSameer Pujar 452177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 453177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 454177208f7SSameer Pujar "nvidia,tegra186-dspk"; 455177208f7SSameer Pujar reg = <0x2905000 0x100>; 456177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 457177208f7SSameer Pujar clock-names = "dspk"; 458177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 459177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 460177208f7SSameer Pujar assigned-clock-rates = <12288000>; 461177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 462177208f7SSameer Pujar status = "disabled"; 463177208f7SSameer Pujar }; 464177208f7SSameer Pujar 465177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 466177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 467177208f7SSameer Pujar "nvidia,tegra186-dspk"; 468177208f7SSameer Pujar reg = <0x2905100 0x100>; 469177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 470177208f7SSameer Pujar clock-names = "dspk"; 471177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 472177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 473177208f7SSameer Pujar assigned-clock-rates = <12288000>; 474177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 475177208f7SSameer Pujar status = "disabled"; 476177208f7SSameer Pujar }; 477848f3290SSameer Pujar 478848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 479848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 480848f3290SSameer Pujar "nvidia,tegra210-sfc"; 481848f3290SSameer Pujar reg = <0x2902000 0x200>; 482848f3290SSameer Pujar sound-name-prefix = "SFC1"; 483848f3290SSameer Pujar status = "disabled"; 484848f3290SSameer Pujar }; 485848f3290SSameer Pujar 486848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 487848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 488848f3290SSameer Pujar "nvidia,tegra210-sfc"; 489848f3290SSameer Pujar reg = <0x2902200 0x200>; 490848f3290SSameer Pujar sound-name-prefix = "SFC2"; 491848f3290SSameer Pujar status = "disabled"; 492848f3290SSameer Pujar }; 493848f3290SSameer Pujar 494848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 495848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 496848f3290SSameer Pujar "nvidia,tegra210-sfc"; 497848f3290SSameer Pujar reg = <0x2902400 0x200>; 498848f3290SSameer Pujar sound-name-prefix = "SFC3"; 499848f3290SSameer Pujar status = "disabled"; 500848f3290SSameer Pujar }; 501848f3290SSameer Pujar 502848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 503848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 504848f3290SSameer Pujar "nvidia,tegra210-sfc"; 505848f3290SSameer Pujar reg = <0x2902600 0x200>; 506848f3290SSameer Pujar sound-name-prefix = "SFC4"; 507848f3290SSameer Pujar status = "disabled"; 508848f3290SSameer Pujar }; 509848f3290SSameer Pujar 510848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 511848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 512848f3290SSameer Pujar "nvidia,tegra210-mvc"; 513848f3290SSameer Pujar reg = <0x290a000 0x200>; 514848f3290SSameer Pujar sound-name-prefix = "MVC1"; 515848f3290SSameer Pujar status = "disabled"; 516848f3290SSameer Pujar }; 517848f3290SSameer Pujar 518848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 519848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 520848f3290SSameer Pujar "nvidia,tegra210-mvc"; 521848f3290SSameer Pujar reg = <0x290a200 0x200>; 522848f3290SSameer Pujar sound-name-prefix = "MVC2"; 523848f3290SSameer Pujar status = "disabled"; 524848f3290SSameer Pujar }; 525848f3290SSameer Pujar 526848f3290SSameer Pujar tegra_amx1: amx@2903000 { 527848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 528848f3290SSameer Pujar reg = <0x2903000 0x100>; 529848f3290SSameer Pujar sound-name-prefix = "AMX1"; 530848f3290SSameer Pujar status = "disabled"; 531848f3290SSameer Pujar }; 532848f3290SSameer Pujar 533848f3290SSameer Pujar tegra_amx2: amx@2903100 { 534848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 535848f3290SSameer Pujar reg = <0x2903100 0x100>; 536848f3290SSameer Pujar sound-name-prefix = "AMX2"; 537848f3290SSameer Pujar status = "disabled"; 538848f3290SSameer Pujar }; 539848f3290SSameer Pujar 540848f3290SSameer Pujar tegra_amx3: amx@2903200 { 541848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 542848f3290SSameer Pujar reg = <0x2903200 0x100>; 543848f3290SSameer Pujar sound-name-prefix = "AMX3"; 544848f3290SSameer Pujar status = "disabled"; 545848f3290SSameer Pujar }; 546848f3290SSameer Pujar 547848f3290SSameer Pujar tegra_amx4: amx@2903300 { 548848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 549848f3290SSameer Pujar reg = <0x2903300 0x100>; 550848f3290SSameer Pujar sound-name-prefix = "AMX4"; 551848f3290SSameer Pujar status = "disabled"; 552848f3290SSameer Pujar }; 553848f3290SSameer Pujar 554848f3290SSameer Pujar tegra_adx1: adx@2903800 { 555848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 556848f3290SSameer Pujar "nvidia,tegra210-adx"; 557848f3290SSameer Pujar reg = <0x2903800 0x100>; 558848f3290SSameer Pujar sound-name-prefix = "ADX1"; 559848f3290SSameer Pujar status = "disabled"; 560848f3290SSameer Pujar }; 561848f3290SSameer Pujar 562848f3290SSameer Pujar tegra_adx2: adx@2903900 { 563848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 564848f3290SSameer Pujar "nvidia,tegra210-adx"; 565848f3290SSameer Pujar reg = <0x2903900 0x100>; 566848f3290SSameer Pujar sound-name-prefix = "ADX2"; 567848f3290SSameer Pujar status = "disabled"; 568848f3290SSameer Pujar }; 569848f3290SSameer Pujar 570848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 571848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 572848f3290SSameer Pujar "nvidia,tegra210-adx"; 573848f3290SSameer Pujar reg = <0x2903a00 0x100>; 574848f3290SSameer Pujar sound-name-prefix = "ADX3"; 575848f3290SSameer Pujar status = "disabled"; 576848f3290SSameer Pujar }; 577848f3290SSameer Pujar 578848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 579848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 580848f3290SSameer Pujar "nvidia,tegra210-adx"; 581848f3290SSameer Pujar reg = <0x2903b00 0x100>; 582848f3290SSameer Pujar sound-name-prefix = "ADX4"; 583848f3290SSameer Pujar status = "disabled"; 584848f3290SSameer Pujar }; 585848f3290SSameer Pujar 5864b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 5874b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-ope", 5884b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 5894b6a1b7cSSameer Pujar reg = <0x2908000 0x100>; 5904b6a1b7cSSameer Pujar #address-cells = <1>; 5914b6a1b7cSSameer Pujar #size-cells = <1>; 5924b6a1b7cSSameer Pujar ranges; 5934b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 5944b6a1b7cSSameer Pujar status = "disabled"; 5954b6a1b7cSSameer Pujar 5964b6a1b7cSSameer Pujar equalizer@2908100 { 5974b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-peq", 5984b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 5994b6a1b7cSSameer Pujar reg = <0x2908100 0x100>; 6004b6a1b7cSSameer Pujar }; 6014b6a1b7cSSameer Pujar 6024b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 6034b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-mbdrc", 6044b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 6054b6a1b7cSSameer Pujar reg = <0x2908200 0x200>; 6064b6a1b7cSSameer Pujar }; 6074b6a1b7cSSameer Pujar }; 6084b6a1b7cSSameer Pujar 609848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 610848f3290SSameer Pujar compatible = "nvidia,tegra194-amixer", 611848f3290SSameer Pujar "nvidia,tegra210-amixer"; 612848f3290SSameer Pujar reg = <0x290bb00 0x800>; 613848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 614848f3290SSameer Pujar status = "disabled"; 615848f3290SSameer Pujar }; 61647a08153SSameer Pujar 61747a08153SSameer Pujar tegra_asrc: asrc@2910000 { 61847a08153SSameer Pujar compatible = "nvidia,tegra194-asrc", 61947a08153SSameer Pujar "nvidia,tegra186-asrc"; 62047a08153SSameer Pujar reg = <0x2910000 0x2000>; 62147a08153SSameer Pujar sound-name-prefix = "ASRC1"; 62247a08153SSameer Pujar status = "disabled"; 62347a08153SSameer Pujar }; 624177208f7SSameer Pujar }; 6255d2249ddSSameer Pujar }; 6265d2249ddSSameer Pujar 627dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 628dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 629644c569dSThierry Reding reg = <0x2430000 0x17000>, 630644c569dSThierry Reding <0xc300000 0x4000>; 631dbb72e2cSVidya Sagar 632dbb72e2cSVidya Sagar status = "okay"; 633dbb72e2cSVidya Sagar 634dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 635dbb72e2cSVidya Sagar pex_rst { 636dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 637dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 638dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6396b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 640dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 641dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 642dbb72e2cSVidya Sagar }; 643dbb72e2cSVidya Sagar }; 644dbb72e2cSVidya Sagar 645dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 646dbb72e2cSVidya Sagar clkreq { 647dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 648dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 649dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 6506b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 651dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 652dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 653dbb72e2cSVidya Sagar }; 654dbb72e2cSVidya Sagar }; 655dbb72e2cSVidya Sagar }; 656dbb72e2cSVidya Sagar 657be9b887fSThierry Reding mc: memory-controller@2c00000 { 658be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 659000b99e5SAshish Mhetre reg = <0x02c00000 0x10000>, /* MC-SID */ 660000b99e5SAshish Mhetre <0x02c10000 0x10000>, /* MC Broadcast*/ 661000b99e5SAshish Mhetre <0x02c20000 0x10000>, /* MC0 */ 662000b99e5SAshish Mhetre <0x02c30000 0x10000>, /* MC1 */ 663000b99e5SAshish Mhetre <0x02c40000 0x10000>, /* MC2 */ 664000b99e5SAshish Mhetre <0x02c50000 0x10000>, /* MC3 */ 665000b99e5SAshish Mhetre <0x02b80000 0x10000>, /* MC4 */ 666000b99e5SAshish Mhetre <0x02b90000 0x10000>, /* MC5 */ 667000b99e5SAshish Mhetre <0x02ba0000 0x10000>, /* MC6 */ 668000b99e5SAshish Mhetre <0x02bb0000 0x10000>, /* MC7 */ 669000b99e5SAshish Mhetre <0x01700000 0x10000>, /* MC8 */ 670000b99e5SAshish Mhetre <0x01710000 0x10000>, /* MC9 */ 671000b99e5SAshish Mhetre <0x01720000 0x10000>, /* MC10 */ 672000b99e5SAshish Mhetre <0x01730000 0x10000>, /* MC11 */ 673000b99e5SAshish Mhetre <0x01740000 0x10000>, /* MC12 */ 674000b99e5SAshish Mhetre <0x01750000 0x10000>, /* MC13 */ 675000b99e5SAshish Mhetre <0x01760000 0x10000>, /* MC14 */ 676000b99e5SAshish Mhetre <0x01770000 0x10000>; /* MC15 */ 677000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 678000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 679000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 6808613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 681d5237c7cSThierry Reding #interconnect-cells = <1>; 682be9b887fSThierry Reding status = "disabled"; 683be9b887fSThierry Reding 684be9b887fSThierry Reding #address-cells = <2>; 685be9b887fSThierry Reding #size-cells = <2>; 686be9b887fSThierry Reding 687be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 688be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 689be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 690be9b887fSThierry Reding 691be9b887fSThierry Reding /* 692be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 693be9b887fSThierry Reding * controller selects the XBAR format used when memory 694be9b887fSThierry Reding * is accessed. This is used to transparently access 695be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 696be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 697be9b887fSThierry Reding * 698be9b887fSThierry Reding * As a consequence, the operating system must ensure 699be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 700be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 701be9b887fSThierry Reding * devices require access to the XBAR switch, their 702be9b887fSThierry Reding * drivers must set this bit explicitly. 703be9b887fSThierry Reding * 704be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 705be9b887fSThierry Reding */ 706be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 707be9b887fSThierry Reding 708be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 709be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 710be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 711be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 712cc939667SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 713be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 714be9b887fSThierry Reding clock-names = "emc"; 715be9b887fSThierry Reding 716d5237c7cSThierry Reding #interconnect-cells = <0>; 717d5237c7cSThierry Reding 718be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 719be9b887fSThierry Reding }; 720be9b887fSThierry Reding }; 721be9b887fSThierry Reding 7225aa9083eSThierry Reding timer@3010000 { 7235aa9083eSThierry Reding compatible = "nvidia,tegra186-timer"; 7245aa9083eSThierry Reding reg = <0x03010000 0x000e0000>; 7255aa9083eSThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 7265aa9083eSThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 7275aa9083eSThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 7285aa9083eSThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7295aa9083eSThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7305aa9083eSThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 7315aa9083eSThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 7325aa9083eSThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 7335aa9083eSThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 7345aa9083eSThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 7355aa9083eSThierry Reding status = "okay"; 7365aa9083eSThierry Reding }; 7375aa9083eSThierry Reding 7385425fb15SMikko Perttunen uarta: serial@3100000 { 7395425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7405425fb15SMikko Perttunen reg = <0x03100000 0x40>; 7415425fb15SMikko Perttunen reg-shift = <2>; 7425425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 7435425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 7445425fb15SMikko Perttunen clock-names = "serial"; 7455425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 7465425fb15SMikko Perttunen reset-names = "serial"; 7475425fb15SMikko Perttunen status = "disabled"; 7485425fb15SMikko Perttunen }; 7495425fb15SMikko Perttunen 7505425fb15SMikko Perttunen uartb: serial@3110000 { 7515425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7525425fb15SMikko Perttunen reg = <0x03110000 0x40>; 7535425fb15SMikko Perttunen reg-shift = <2>; 7545425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 7555425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 7565425fb15SMikko Perttunen clock-names = "serial"; 7575425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 7585425fb15SMikko Perttunen reset-names = "serial"; 7595425fb15SMikko Perttunen status = "disabled"; 7605425fb15SMikko Perttunen }; 7615425fb15SMikko Perttunen 7625425fb15SMikko Perttunen uartd: serial@3130000 { 7635425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7645425fb15SMikko Perttunen reg = <0x03130000 0x40>; 7655425fb15SMikko Perttunen reg-shift = <2>; 7665425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 7675425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 7685425fb15SMikko Perttunen clock-names = "serial"; 7695425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 7705425fb15SMikko Perttunen reset-names = "serial"; 7715425fb15SMikko Perttunen status = "disabled"; 7725425fb15SMikko Perttunen }; 7735425fb15SMikko Perttunen 7745425fb15SMikko Perttunen uarte: serial@3140000 { 7755425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7765425fb15SMikko Perttunen reg = <0x03140000 0x40>; 7775425fb15SMikko Perttunen reg-shift = <2>; 7785425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 7795425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 7805425fb15SMikko Perttunen clock-names = "serial"; 7815425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 7825425fb15SMikko Perttunen reset-names = "serial"; 7835425fb15SMikko Perttunen status = "disabled"; 7845425fb15SMikko Perttunen }; 7855425fb15SMikko Perttunen 7865425fb15SMikko Perttunen uartf: serial@3150000 { 7875425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7885425fb15SMikko Perttunen reg = <0x03150000 0x40>; 7895425fb15SMikko Perttunen reg-shift = <2>; 7905425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 7915425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 7925425fb15SMikko Perttunen clock-names = "serial"; 7935425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 7945425fb15SMikko Perttunen reset-names = "serial"; 7955425fb15SMikko Perttunen status = "disabled"; 7965425fb15SMikko Perttunen }; 7975425fb15SMikko Perttunen 7985425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 799d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8005425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 8015425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 8025425fb15SMikko Perttunen #address-cells = <1>; 8035425fb15SMikko Perttunen #size-cells = <0>; 8045425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 8055425fb15SMikko Perttunen clock-names = "div-clk"; 8065425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 8075425fb15SMikko Perttunen reset-names = "i2c"; 8088e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8098e442805SAkhil R dma-coherent; 8108e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 8118e442805SAkhil R dma-names = "rx", "tx"; 8125425fb15SMikko Perttunen status = "disabled"; 8135425fb15SMikko Perttunen }; 8145425fb15SMikko Perttunen 8155425fb15SMikko Perttunen uarth: serial@3170000 { 8165425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 8175425fb15SMikko Perttunen reg = <0x03170000 0x40>; 8185425fb15SMikko Perttunen reg-shift = <2>; 8195425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 8205425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 8215425fb15SMikko Perttunen clock-names = "serial"; 8225425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 8235425fb15SMikko Perttunen reset-names = "serial"; 8245425fb15SMikko Perttunen status = "disabled"; 8255425fb15SMikko Perttunen }; 8265425fb15SMikko Perttunen 8275425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 828d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8295425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 8305425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 8315425fb15SMikko Perttunen #address-cells = <1>; 8325425fb15SMikko Perttunen #size-cells = <0>; 8335425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 8345425fb15SMikko Perttunen clock-names = "div-clk"; 8355425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 8365425fb15SMikko Perttunen reset-names = "i2c"; 8378e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8388e442805SAkhil R dma-coherent; 8398e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 8408e442805SAkhil R dma-names = "rx", "tx"; 8415425fb15SMikko Perttunen status = "disabled"; 8425425fb15SMikko Perttunen }; 8435425fb15SMikko Perttunen 8445425fb15SMikko Perttunen /* shares pads with dpaux1 */ 8455425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 846d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8475425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 8485425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 8495425fb15SMikko Perttunen #address-cells = <1>; 8505425fb15SMikko Perttunen #size-cells = <0>; 8515425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 8525425fb15SMikko Perttunen clock-names = "div-clk"; 8535425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 8545425fb15SMikko Perttunen reset-names = "i2c"; 855a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 856a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 857a4131561SThierry Reding pinctrl-names = "default", "idle"; 8588e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8598e442805SAkhil R dma-coherent; 8608e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 8618e442805SAkhil R dma-names = "rx", "tx"; 8625425fb15SMikko Perttunen status = "disabled"; 8635425fb15SMikko Perttunen }; 8645425fb15SMikko Perttunen 8655425fb15SMikko Perttunen /* shares pads with dpaux0 */ 8665425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 867d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8685425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 8695425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 8705425fb15SMikko Perttunen #address-cells = <1>; 8715425fb15SMikko Perttunen #size-cells = <0>; 8725425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 8735425fb15SMikko Perttunen clock-names = "div-clk"; 8745425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 8755425fb15SMikko Perttunen reset-names = "i2c"; 876a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 877a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 878a4131561SThierry Reding pinctrl-names = "default", "idle"; 8798e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8808e442805SAkhil R dma-coherent; 8818e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 8828e442805SAkhil R dma-names = "rx", "tx"; 8835425fb15SMikko Perttunen status = "disabled"; 8845425fb15SMikko Perttunen }; 8855425fb15SMikko Perttunen 886a4131561SThierry Reding /* shares pads with dpaux2 */ 887a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 888d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8895425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 8905425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 8915425fb15SMikko Perttunen #address-cells = <1>; 8925425fb15SMikko Perttunen #size-cells = <0>; 8935425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 8945425fb15SMikko Perttunen clock-names = "div-clk"; 8955425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 8965425fb15SMikko Perttunen reset-names = "i2c"; 897a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 898a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 899a4131561SThierry Reding pinctrl-names = "default", "idle"; 9008e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 9018e442805SAkhil R dma-coherent; 9028e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 9038e442805SAkhil R dma-names = "rx", "tx"; 9045425fb15SMikko Perttunen status = "disabled"; 9055425fb15SMikko Perttunen }; 9065425fb15SMikko Perttunen 907a4131561SThierry Reding /* shares pads with dpaux3 */ 908a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 909d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 9105425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 9115425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 9125425fb15SMikko Perttunen #address-cells = <1>; 9135425fb15SMikko Perttunen #size-cells = <0>; 9145425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 9155425fb15SMikko Perttunen clock-names = "div-clk"; 9165425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 9175425fb15SMikko Perttunen reset-names = "i2c"; 918a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 919a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 920a4131561SThierry Reding pinctrl-names = "default", "idle"; 9218e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 9228e442805SAkhil R dma-coherent; 9238e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 9248e442805SAkhil R dma-names = "rx", "tx"; 9255425fb15SMikko Perttunen status = "disabled"; 9265425fb15SMikko Perttunen }; 9275425fb15SMikko Perttunen 92896ded827SSowjanya Komatineni spi@3270000 { 92996ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 93096ded827SSowjanya Komatineni reg = <0x3270000 0x1000>; 93196ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 93296ded827SSowjanya Komatineni #address-cells = <1>; 93396ded827SSowjanya Komatineni #size-cells = <0>; 93496ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 93596ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 93696ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 93796ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 93896ded827SSowjanya Komatineni reset-names = "qspi"; 93996ded827SSowjanya Komatineni status = "disabled"; 94096ded827SSowjanya Komatineni }; 94196ded827SSowjanya Komatineni 94296ded827SSowjanya Komatineni spi@3300000 { 94396ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 94496ded827SSowjanya Komatineni reg = <0x3300000 0x1000>; 94596ded827SSowjanya Komatineni interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 94696ded827SSowjanya Komatineni #address-cells = <1>; 94796ded827SSowjanya Komatineni #size-cells = <0>; 94896ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI1>, 94996ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI1_PM>; 95096ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 95196ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI1>; 95296ded827SSowjanya Komatineni reset-names = "qspi"; 95396ded827SSowjanya Komatineni status = "disabled"; 95496ded827SSowjanya Komatineni }; 95596ded827SSowjanya Komatineni 9566a574ec7SThierry Reding pwm1: pwm@3280000 { 9576a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9586a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9596a574ec7SThierry Reding reg = <0x3280000 0x10000>; 9606a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 9616a574ec7SThierry Reding clock-names = "pwm"; 9626a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 9636a574ec7SThierry Reding reset-names = "pwm"; 9646a574ec7SThierry Reding status = "disabled"; 9656a574ec7SThierry Reding #pwm-cells = <2>; 9666a574ec7SThierry Reding }; 9676a574ec7SThierry Reding 9686a574ec7SThierry Reding pwm2: pwm@3290000 { 9696a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9706a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9716a574ec7SThierry Reding reg = <0x3290000 0x10000>; 9726a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 9736a574ec7SThierry Reding clock-names = "pwm"; 9746a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 9756a574ec7SThierry Reding reset-names = "pwm"; 9766a574ec7SThierry Reding status = "disabled"; 9776a574ec7SThierry Reding #pwm-cells = <2>; 9786a574ec7SThierry Reding }; 9796a574ec7SThierry Reding 9806a574ec7SThierry Reding pwm3: pwm@32a0000 { 9816a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9826a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9836a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 9846a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 9856a574ec7SThierry Reding clock-names = "pwm"; 9866a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 9876a574ec7SThierry Reding reset-names = "pwm"; 9886a574ec7SThierry Reding status = "disabled"; 9896a574ec7SThierry Reding #pwm-cells = <2>; 9906a574ec7SThierry Reding }; 9916a574ec7SThierry Reding 9926a574ec7SThierry Reding pwm5: pwm@32c0000 { 9936a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9946a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9956a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 9966a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 9976a574ec7SThierry Reding clock-names = "pwm"; 9986a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 9996a574ec7SThierry Reding reset-names = "pwm"; 10006a574ec7SThierry Reding status = "disabled"; 10016a574ec7SThierry Reding #pwm-cells = <2>; 10026a574ec7SThierry Reding }; 10036a574ec7SThierry Reding 10046a574ec7SThierry Reding pwm6: pwm@32d0000 { 10056a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10066a574ec7SThierry Reding "nvidia,tegra186-pwm"; 10076a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 10086a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 10096a574ec7SThierry Reding clock-names = "pwm"; 10106a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 10116a574ec7SThierry Reding reset-names = "pwm"; 10126a574ec7SThierry Reding status = "disabled"; 10136a574ec7SThierry Reding #pwm-cells = <2>; 10146a574ec7SThierry Reding }; 10156a574ec7SThierry Reding 10166a574ec7SThierry Reding pwm7: pwm@32e0000 { 10176a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10186a574ec7SThierry Reding "nvidia,tegra186-pwm"; 10196a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 10206a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 10216a574ec7SThierry Reding clock-names = "pwm"; 10226a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 10236a574ec7SThierry Reding reset-names = "pwm"; 10246a574ec7SThierry Reding status = "disabled"; 10256a574ec7SThierry Reding #pwm-cells = <2>; 10266a574ec7SThierry Reding }; 10276a574ec7SThierry Reding 10286a574ec7SThierry Reding pwm8: pwm@32f0000 { 10296a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10306a574ec7SThierry Reding "nvidia,tegra186-pwm"; 10316a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 10326a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 10336a574ec7SThierry Reding clock-names = "pwm"; 10346a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 10356a574ec7SThierry Reding reset-names = "pwm"; 10366a574ec7SThierry Reding status = "disabled"; 10376a574ec7SThierry Reding #pwm-cells = <2>; 10386a574ec7SThierry Reding }; 10396a574ec7SThierry Reding 104067bb17f6SThierry Reding sdmmc1: mmc@3400000 { 10412c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 10425425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 10435425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1044c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1045c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1046c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 10477ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 10487ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 10497ac853baSAniruddha Rao assigned-clock-parents = 10507ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 10517ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 10525425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 10535425fb15SMikko Perttunen reset-names = "sdhci"; 1054d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1055d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1056d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1057c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC1>; 1058ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1059ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 1060ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 10614e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 10624e0f1229SSowjanya Komatineni <0x07>; 10634e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10644e0f1229SSowjanya Komatineni <0x07>; 10654e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 10664e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 10674e0f1229SSowjanya Komatineni <0x07>; 10684e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 10694e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 10704e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 10714e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1072ff21087eSPrathamesh Shete sd-uhs-sdr25; 1073ff21087eSPrathamesh Shete sd-uhs-sdr50; 1074ff21087eSPrathamesh Shete sd-uhs-ddr50; 1075ff21087eSPrathamesh Shete sd-uhs-sdr104; 10765425fb15SMikko Perttunen status = "disabled"; 10775425fb15SMikko Perttunen }; 10785425fb15SMikko Perttunen 107967bb17f6SThierry Reding sdmmc3: mmc@3440000 { 10802c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 10815425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 10825425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1083c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1084c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1085c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 10867ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 10877ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 10887ac853baSAniruddha Rao assigned-clock-parents = 10897ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 10907ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 10915425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 10925425fb15SMikko Perttunen reset-names = "sdhci"; 1093d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1094d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1095d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1096c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC3>; 1097ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1098ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc3_3v3>; 1099ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc3_1v8>; 11004e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 11014e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 11024e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 11034e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 11044e0f1229SSowjanya Komatineni <0x07>; 11054e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 11064e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 11074e0f1229SSowjanya Komatineni <0x07>; 11084e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 11094e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 11104e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 11114e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1112ff21087eSPrathamesh Shete sd-uhs-sdr25; 1113ff21087eSPrathamesh Shete sd-uhs-sdr50; 1114ff21087eSPrathamesh Shete sd-uhs-ddr50; 1115ff21087eSPrathamesh Shete sd-uhs-sdr104; 11165425fb15SMikko Perttunen status = "disabled"; 11175425fb15SMikko Perttunen }; 11185425fb15SMikko Perttunen 111967bb17f6SThierry Reding sdmmc4: mmc@3460000 { 11202c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 11215425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 11225425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1123c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1124c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1125c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1126351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1127351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 1128351648d0SSowjanya Komatineni assigned-clock-parents = 1129351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 11305425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 11315425fb15SMikko Perttunen reset-names = "sdhci"; 1132d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1133d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1134d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1135c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC4>; 11364e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 11374e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 11384e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 11394e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 11404e0f1229SSowjanya Komatineni <0x0a>; 11414e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 11424e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 11434e0f1229SSowjanya Komatineni <0x0a>; 11444e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 11454e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 11464e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 1147c2fee443SPrathamesh Shete cap-mmc-highspeed; 1148c2fee443SPrathamesh Shete mmc-ddr-1_8v; 1149c2fee443SPrathamesh Shete mmc-hs200-1_8v; 1150c2fee443SPrathamesh Shete mmc-hs400-1_8v; 1151c2fee443SPrathamesh Shete mmc-hs400-enhanced-strobe; 1152dfd3cb6fSSowjanya Komatineni supports-cqe; 11535425fb15SMikko Perttunen status = "disabled"; 11545425fb15SMikko Perttunen }; 11555425fb15SMikko Perttunen 11564878cc0cSSameer Pujar hda@3510000 { 11574878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 11584878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 11594878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 11604878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 116148f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 116248f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 116348f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 11644878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 1165146b3a77SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1166146b3a77SSameer Pujar reset-names = "hda", "hda2hdmi"; 11674878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1168d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1169d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1170d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1171c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HDA>; 11724878cc0cSSameer Pujar status = "disabled"; 11734878cc0cSSameer Pujar }; 11744878cc0cSSameer Pujar 1175fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 1176fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 1177fab7a039SJC Kuo reg = <0x03520000 0x1000>, 1178fab7a039SJC Kuo <0x03540000 0x1000>; 1179fab7a039SJC Kuo reg-names = "padctl", "ao"; 11806450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1181fab7a039SJC Kuo 1182fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1183fab7a039SJC Kuo reset-names = "padctl"; 1184fab7a039SJC Kuo 1185fab7a039SJC Kuo status = "disabled"; 1186fab7a039SJC Kuo 1187fab7a039SJC Kuo pads { 1188fab7a039SJC Kuo usb2 { 1189fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1190fab7a039SJC Kuo clock-names = "trk"; 1191fab7a039SJC Kuo 1192fab7a039SJC Kuo lanes { 1193fab7a039SJC Kuo usb2-0 { 1194fab7a039SJC Kuo nvidia,function = "xusb"; 1195fab7a039SJC Kuo status = "disabled"; 1196fab7a039SJC Kuo #phy-cells = <0>; 1197fab7a039SJC Kuo }; 1198fab7a039SJC Kuo 1199fab7a039SJC Kuo usb2-1 { 1200fab7a039SJC Kuo nvidia,function = "xusb"; 1201fab7a039SJC Kuo status = "disabled"; 1202fab7a039SJC Kuo #phy-cells = <0>; 1203fab7a039SJC Kuo }; 1204fab7a039SJC Kuo 1205fab7a039SJC Kuo usb2-2 { 1206fab7a039SJC Kuo nvidia,function = "xusb"; 1207fab7a039SJC Kuo status = "disabled"; 1208fab7a039SJC Kuo #phy-cells = <0>; 1209fab7a039SJC Kuo }; 1210fab7a039SJC Kuo 1211fab7a039SJC Kuo usb2-3 { 1212fab7a039SJC Kuo nvidia,function = "xusb"; 1213fab7a039SJC Kuo status = "disabled"; 1214fab7a039SJC Kuo #phy-cells = <0>; 1215fab7a039SJC Kuo }; 1216fab7a039SJC Kuo }; 1217fab7a039SJC Kuo }; 1218fab7a039SJC Kuo 1219fab7a039SJC Kuo usb3 { 1220fab7a039SJC Kuo lanes { 1221fab7a039SJC Kuo usb3-0 { 1222fab7a039SJC Kuo nvidia,function = "xusb"; 1223fab7a039SJC Kuo status = "disabled"; 1224fab7a039SJC Kuo #phy-cells = <0>; 1225fab7a039SJC Kuo }; 1226fab7a039SJC Kuo 1227fab7a039SJC Kuo usb3-1 { 1228fab7a039SJC Kuo nvidia,function = "xusb"; 1229fab7a039SJC Kuo status = "disabled"; 1230fab7a039SJC Kuo #phy-cells = <0>; 1231fab7a039SJC Kuo }; 1232fab7a039SJC Kuo 1233fab7a039SJC Kuo usb3-2 { 1234fab7a039SJC Kuo nvidia,function = "xusb"; 1235fab7a039SJC Kuo status = "disabled"; 1236fab7a039SJC Kuo #phy-cells = <0>; 1237fab7a039SJC Kuo }; 1238fab7a039SJC Kuo 1239fab7a039SJC Kuo usb3-3 { 1240fab7a039SJC Kuo nvidia,function = "xusb"; 1241fab7a039SJC Kuo status = "disabled"; 1242fab7a039SJC Kuo #phy-cells = <0>; 1243fab7a039SJC Kuo }; 1244fab7a039SJC Kuo }; 1245fab7a039SJC Kuo }; 1246fab7a039SJC Kuo }; 1247fab7a039SJC Kuo 1248fab7a039SJC Kuo ports { 1249fab7a039SJC Kuo usb2-0 { 1250fab7a039SJC Kuo status = "disabled"; 1251fab7a039SJC Kuo }; 1252fab7a039SJC Kuo 1253fab7a039SJC Kuo usb2-1 { 1254fab7a039SJC Kuo status = "disabled"; 1255fab7a039SJC Kuo }; 1256fab7a039SJC Kuo 1257fab7a039SJC Kuo usb2-2 { 1258fab7a039SJC Kuo status = "disabled"; 1259fab7a039SJC Kuo }; 1260fab7a039SJC Kuo 1261fab7a039SJC Kuo usb2-3 { 1262fab7a039SJC Kuo status = "disabled"; 1263fab7a039SJC Kuo }; 1264fab7a039SJC Kuo 1265fab7a039SJC Kuo usb3-0 { 1266fab7a039SJC Kuo status = "disabled"; 1267fab7a039SJC Kuo }; 1268fab7a039SJC Kuo 1269fab7a039SJC Kuo usb3-1 { 1270fab7a039SJC Kuo status = "disabled"; 1271fab7a039SJC Kuo }; 1272fab7a039SJC Kuo 1273fab7a039SJC Kuo usb3-2 { 1274fab7a039SJC Kuo status = "disabled"; 1275fab7a039SJC Kuo }; 1276fab7a039SJC Kuo 1277fab7a039SJC Kuo usb3-3 { 1278fab7a039SJC Kuo status = "disabled"; 1279fab7a039SJC Kuo }; 1280fab7a039SJC Kuo }; 1281fab7a039SJC Kuo }; 1282fab7a039SJC Kuo 1283bc8788b2SNagarjuna Kristam usb@3550000 { 1284bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 1285bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 1286bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 1287bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 1288bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1289bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1290bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1291bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 1292bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 1293bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1294c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1295c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1296c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1297c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1298bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1299bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1300bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 1301bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 1302bc8788b2SNagarjuna Kristam status = "disabled"; 1303bc8788b2SNagarjuna Kristam }; 1304bc8788b2SNagarjuna Kristam 1305fab7a039SJC Kuo usb@3610000 { 1306fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 1307fab7a039SJC Kuo reg = <0x03610000 0x40000>, 1308fab7a039SJC Kuo <0x03600000 0x10000>; 1309fab7a039SJC Kuo reg-names = "hcd", "fpci"; 1310fab7a039SJC Kuo 1311fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1312a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1313fab7a039SJC Kuo 1314fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1315fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1316fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1317fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 1318fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1319fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 1320fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 1321fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1322fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 1323fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 1324fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1325fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 1326fab7a039SJC Kuo "pll_e"; 1327c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1328c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1329c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1330c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1331fab7a039SJC Kuo 1332fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1333fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1334fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 1335fab7a039SJC Kuo 1336fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 1337fab7a039SJC Kuo status = "disabled"; 1338fab7a039SJC Kuo }; 1339fab7a039SJC Kuo 134009903c5eSJC Kuo fuse@3820000 { 134109903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 134209903c5eSJC Kuo reg = <0x03820000 0x10000>; 134309903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 134409903c5eSJC Kuo clock-names = "fuse"; 134509903c5eSJC Kuo }; 134609903c5eSJC Kuo 13475425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 13485425fb15SMikko Perttunen compatible = "arm,gic-400"; 13495425fb15SMikko Perttunen #interrupt-cells = <3>; 13505425fb15SMikko Perttunen interrupt-controller; 13515425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 13525425fb15SMikko Perttunen <0x03882000 0x2000>, 13535425fb15SMikko Perttunen <0x03884000 0x2000>, 13545425fb15SMikko Perttunen <0x03886000 0x2000>; 13555425fb15SMikko Perttunen interrupts = <GIC_PPI 9 13565425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 13575425fb15SMikko Perttunen interrupt-parent = <&gic>; 13585425fb15SMikko Perttunen }; 13595425fb15SMikko Perttunen 1360badb80beSThierry Reding cec@3960000 { 1361badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 1362badb80beSThierry Reding reg = <0x03960000 0x10000>; 1363badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1364badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1365badb80beSThierry Reding clock-names = "cec"; 1366badb80beSThierry Reding status = "disabled"; 1367badb80beSThierry Reding }; 1368badb80beSThierry Reding 13695425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1370cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 13715425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 1372a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1373a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1374a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1375a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1376a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1377a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1378a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1379a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1380a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1381a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1382a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1383a38570c2SMikko Perttunen "shared7"; 1384a38570c2SMikko Perttunen #mbox-cells = <2>; 1385a38570c2SMikko Perttunen }; 1386a38570c2SMikko Perttunen 13872602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 13882602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13892602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 13902602c32fSVidya Sagar reg-names = "ctl"; 13912602c32fSVidya Sagar 13922602c32fSVidya Sagar #phy-cells = <0>; 13932602c32fSVidya Sagar }; 13942602c32fSVidya Sagar 13952602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 13962602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13972602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 13982602c32fSVidya Sagar reg-names = "ctl"; 13992602c32fSVidya Sagar 14002602c32fSVidya Sagar #phy-cells = <0>; 14012602c32fSVidya Sagar }; 14022602c32fSVidya Sagar 14032602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 14042602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14052602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 14062602c32fSVidya Sagar reg-names = "ctl"; 14072602c32fSVidya Sagar 14082602c32fSVidya Sagar #phy-cells = <0>; 14092602c32fSVidya Sagar }; 14102602c32fSVidya Sagar 14112602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 14122602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14132602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 14142602c32fSVidya Sagar reg-names = "ctl"; 14152602c32fSVidya Sagar 14162602c32fSVidya Sagar #phy-cells = <0>; 14172602c32fSVidya Sagar }; 14182602c32fSVidya Sagar 14192602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 14202602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14212602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 14222602c32fSVidya Sagar reg-names = "ctl"; 14232602c32fSVidya Sagar 14242602c32fSVidya Sagar #phy-cells = <0>; 14252602c32fSVidya Sagar }; 14262602c32fSVidya Sagar 14272602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 14282602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14292602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 14302602c32fSVidya Sagar reg-names = "ctl"; 14312602c32fSVidya Sagar 14322602c32fSVidya Sagar #phy-cells = <0>; 14332602c32fSVidya Sagar }; 14342602c32fSVidya Sagar 14352602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 14362602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14372602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 14382602c32fSVidya Sagar reg-names = "ctl"; 14392602c32fSVidya Sagar 14402602c32fSVidya Sagar #phy-cells = <0>; 14412602c32fSVidya Sagar }; 14422602c32fSVidya Sagar 14432602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 14442602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14452602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 14462602c32fSVidya Sagar reg-names = "ctl"; 14472602c32fSVidya Sagar 14482602c32fSVidya Sagar #phy-cells = <0>; 14492602c32fSVidya Sagar }; 14502602c32fSVidya Sagar 14512602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 14522602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14532602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 14542602c32fSVidya Sagar reg-names = "ctl"; 14552602c32fSVidya Sagar 14562602c32fSVidya Sagar #phy-cells = <0>; 14572602c32fSVidya Sagar }; 14582602c32fSVidya Sagar 14592602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 14602602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14612602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 14622602c32fSVidya Sagar reg-names = "ctl"; 14632602c32fSVidya Sagar 14642602c32fSVidya Sagar #phy-cells = <0>; 14652602c32fSVidya Sagar }; 14662602c32fSVidya Sagar 14672602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 14682602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14692602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 14702602c32fSVidya Sagar reg-names = "ctl"; 14712602c32fSVidya Sagar 14722602c32fSVidya Sagar #phy-cells = <0>; 14732602c32fSVidya Sagar }; 14742602c32fSVidya Sagar 14752602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 14762602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14772602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 14782602c32fSVidya Sagar reg-names = "ctl"; 14792602c32fSVidya Sagar 14802602c32fSVidya Sagar #phy-cells = <0>; 14812602c32fSVidya Sagar }; 14822602c32fSVidya Sagar 14832602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 14842602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14852602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 14862602c32fSVidya Sagar reg-names = "ctl"; 14872602c32fSVidya Sagar 14882602c32fSVidya Sagar #phy-cells = <0>; 14892602c32fSVidya Sagar }; 14902602c32fSVidya Sagar 14912602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 14922602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14932602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 14942602c32fSVidya Sagar reg-names = "ctl"; 14952602c32fSVidya Sagar 14962602c32fSVidya Sagar #phy-cells = <0>; 14972602c32fSVidya Sagar }; 14982602c32fSVidya Sagar 14992602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 15002602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15012602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 15022602c32fSVidya Sagar reg-names = "ctl"; 15032602c32fSVidya Sagar 15042602c32fSVidya Sagar #phy-cells = <0>; 15052602c32fSVidya Sagar }; 15062602c32fSVidya Sagar 15072602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 15082602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15092602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 15102602c32fSVidya Sagar reg-names = "ctl"; 15112602c32fSVidya Sagar 15122602c32fSVidya Sagar #phy-cells = <0>; 15132602c32fSVidya Sagar }; 15142602c32fSVidya Sagar 15152602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 15162602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15172602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 15182602c32fSVidya Sagar reg-names = "ctl"; 15192602c32fSVidya Sagar 15202602c32fSVidya Sagar #phy-cells = <0>; 15212602c32fSVidya Sagar }; 15222602c32fSVidya Sagar 15232602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 15242602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15252602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 15262602c32fSVidya Sagar reg-names = "ctl"; 15272602c32fSVidya Sagar 15282602c32fSVidya Sagar #phy-cells = <0>; 15292602c32fSVidya Sagar }; 15302602c32fSVidya Sagar 15312602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 15322602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15332602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 15342602c32fSVidya Sagar reg-names = "ctl"; 15352602c32fSVidya Sagar 15362602c32fSVidya Sagar #phy-cells = <0>; 15372602c32fSVidya Sagar }; 15382602c32fSVidya Sagar 15392602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 15402602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15412602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 15422602c32fSVidya Sagar reg-names = "ctl"; 15432602c32fSVidya Sagar 15442602c32fSVidya Sagar #phy-cells = <0>; 15452602c32fSVidya Sagar }; 15462602c32fSVidya Sagar 1547a47e173eSSumit Gupta sce-noc@b600000 { 1548a47e173eSSumit Gupta compatible = "nvidia,tegra194-sce-noc"; 1549a47e173eSSumit Gupta reg = <0xb600000 0x1000>; 1550a47e173eSSumit Gupta interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1551a47e173eSSumit Gupta <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1552a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1553a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1554a47e173eSSumit Gupta status = "okay"; 1555a47e173eSSumit Gupta }; 1556a47e173eSSumit Gupta 1557a47e173eSSumit Gupta rce-noc@be00000 { 1558a47e173eSSumit Gupta compatible = "nvidia,tegra194-rce-noc"; 1559a47e173eSSumit Gupta reg = <0xbe00000 0x1000>; 1560a47e173eSSumit Gupta interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1561a47e173eSSumit Gupta <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1562a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1563a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1564a47e173eSSumit Gupta status = "okay"; 1565a47e173eSSumit Gupta }; 1566a47e173eSSumit Gupta 1567a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1568cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 15691741e187SDipen Patel reg = <0x0c150000 0x90000>; 1570a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1571a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1572a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1573a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1574a38570c2SMikko Perttunen /* 1575a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1576a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1577a38570c2SMikko Perttunen */ 1578a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 15795425fb15SMikko Perttunen #mbox-cells = <2>; 15805425fb15SMikko Perttunen }; 15815425fb15SMikko Perttunen 15825425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1583d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 15845425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 15855425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 15865425fb15SMikko Perttunen #address-cells = <1>; 15875425fb15SMikko Perttunen #size-cells = <0>; 15885425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 15895425fb15SMikko Perttunen clock-names = "div-clk"; 15905425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 15915425fb15SMikko Perttunen reset-names = "i2c"; 15928e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 15938e442805SAkhil R dma-coherent; 15948e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 15958e442805SAkhil R dma-names = "rx", "tx"; 15965425fb15SMikko Perttunen status = "disabled"; 15975425fb15SMikko Perttunen }; 15985425fb15SMikko Perttunen 15995425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1600d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 16015425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 16025425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 16035425fb15SMikko Perttunen #address-cells = <1>; 16045425fb15SMikko Perttunen #size-cells = <0>; 16055425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 16065425fb15SMikko Perttunen clock-names = "div-clk"; 16075425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 16085425fb15SMikko Perttunen reset-names = "i2c"; 16098e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 16108e442805SAkhil R dma-coherent; 16118e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 16128e442805SAkhil R dma-names = "rx", "tx"; 16135425fb15SMikko Perttunen status = "disabled"; 16145425fb15SMikko Perttunen }; 16155425fb15SMikko Perttunen 16165425fb15SMikko Perttunen uartc: serial@c280000 { 16175425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 16185425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 16195425fb15SMikko Perttunen reg-shift = <2>; 16205425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 16215425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 16225425fb15SMikko Perttunen clock-names = "serial"; 16235425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 16245425fb15SMikko Perttunen reset-names = "serial"; 16255425fb15SMikko Perttunen status = "disabled"; 16265425fb15SMikko Perttunen }; 16275425fb15SMikko Perttunen 16285425fb15SMikko Perttunen uartg: serial@c290000 { 16295425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 16305425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 16315425fb15SMikko Perttunen reg-shift = <2>; 16325425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 16335425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 16345425fb15SMikko Perttunen clock-names = "serial"; 16355425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 16365425fb15SMikko Perttunen reset-names = "serial"; 16375425fb15SMikko Perttunen status = "disabled"; 16385425fb15SMikko Perttunen }; 16395425fb15SMikko Perttunen 164037e5a31dSThierry Reding rtc: rtc@c2a0000 { 164137e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 164237e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 164337e5a31dSThierry Reding interrupt-parent = <&pmc>; 164437e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 164537e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 164637e5a31dSThierry Reding clock-names = "rtc"; 164737e5a31dSThierry Reding status = "disabled"; 164837e5a31dSThierry Reding }; 164937e5a31dSThierry Reding 16504d286331SThierry Reding gpio_aon: gpio@c2f0000 { 16514d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 16524d286331SThierry Reding reg-names = "security", "gpio"; 16534d286331SThierry Reding reg = <0xc2f0000 0x1000>, 16544d286331SThierry Reding <0xc2f1000 0x1000>; 16550a85cf28Spshete interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 16560a85cf28Spshete <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 16570a85cf28Spshete <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 16580a85cf28Spshete <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 16594d286331SThierry Reding gpio-controller; 16604d286331SThierry Reding #gpio-cells = <2>; 16614d286331SThierry Reding interrupt-controller; 16624d286331SThierry Reding #interrupt-cells = <2>; 16634d286331SThierry Reding }; 16644d286331SThierry Reding 16656a574ec7SThierry Reding pwm4: pwm@c340000 { 16666a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 16676a574ec7SThierry Reding "nvidia,tegra186-pwm"; 16686a574ec7SThierry Reding reg = <0xc340000 0x10000>; 16696a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 16706a574ec7SThierry Reding clock-names = "pwm"; 16716a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 16726a574ec7SThierry Reding reset-names = "pwm"; 16736a574ec7SThierry Reding status = "disabled"; 16746a574ec7SThierry Reding #pwm-cells = <2>; 16756a574ec7SThierry Reding }; 16766a574ec7SThierry Reding 167738ecf1e5SThierry Reding pmc: pmc@c360000 { 16785425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 16795425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 16805425fb15SMikko Perttunen <0x0c370000 0x10000>, 16815425fb15SMikko Perttunen <0x0c380000 0x10000>, 16825425fb15SMikko Perttunen <0x0c390000 0x10000>, 16835425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 16845425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 168538ecf1e5SThierry Reding 168638ecf1e5SThierry Reding #interrupt-cells = <2>; 168738ecf1e5SThierry Reding interrupt-controller; 1688ff21087eSPrathamesh Shete sdmmc1_3v3: sdmmc1-3v3 { 1689ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1690ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1691ff21087eSPrathamesh Shete }; 1692ff21087eSPrathamesh Shete 1693ff21087eSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1694ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1695ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1696ff21087eSPrathamesh Shete }; 1697ff21087eSPrathamesh Shete sdmmc3_3v3: sdmmc3-3v3 { 1698ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1699ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1700ff21087eSPrathamesh Shete }; 1701ff21087eSPrathamesh Shete 1702ff21087eSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1703ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1704ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1705ff21087eSPrathamesh Shete }; 1706ff21087eSPrathamesh Shete 17075425fb15SMikko Perttunen }; 17083db6d3baSThierry Reding 1709a47e173eSSumit Gupta aon-noc@c600000 { 1710a47e173eSSumit Gupta compatible = "nvidia,tegra194-aon-noc"; 1711a47e173eSSumit Gupta reg = <0xc600000 0x1000>; 1712a47e173eSSumit Gupta interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1713a47e173eSSumit Gupta <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1714a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1715a47e173eSSumit Gupta status = "okay"; 1716a47e173eSSumit Gupta }; 1717a47e173eSSumit Gupta 1718a47e173eSSumit Gupta bpmp-noc@d600000 { 1719a47e173eSSumit Gupta compatible = "nvidia,tegra194-bpmp-noc"; 1720a47e173eSSumit Gupta reg = <0xd600000 0x1000>; 1721a47e173eSSumit Gupta interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1722a47e173eSSumit Gupta <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1723a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1724a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1725a47e173eSSumit Gupta status = "okay"; 1726a47e173eSSumit Gupta }; 1727a47e173eSSumit Gupta 1728e762232fSJon Hunter iommu@10000000 { 1729e762232fSJon Hunter compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1730e762232fSJon Hunter reg = <0x10000000 0x800000>; 1731e762232fSJon Hunter interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1732e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1733e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1734e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1735e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1736e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1737e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1738e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1739e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1740e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1741e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1742e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1743e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1744e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1745e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1746e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1747e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1748e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1749e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1750e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1796e762232fSJon Hunter stream-match-mask = <0x7f80>; 1797e762232fSJon Hunter #global-interrupts = <1>; 1798e762232fSJon Hunter #iommu-cells = <1>; 1799e762232fSJon Hunter 1800e762232fSJon Hunter nvidia,memory-controller = <&mc>; 1801ebea268eSJon Hunter status = "disabled"; 1802e762232fSJon Hunter }; 1803e762232fSJon Hunter 1804c7289b1cSThierry Reding smmu: iommu@12000000 { 1805c7289b1cSThierry Reding compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1806c7289b1cSThierry Reding reg = <0x12000000 0x800000>, 1807c7289b1cSThierry Reding <0x11000000 0x800000>; 1808c7289b1cSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1809c7289b1cSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1810c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1811c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1812c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1813c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1814c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1815c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1816c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1817c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1818c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1819c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1820c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1821c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1822c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1823c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1824c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1825c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1826c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1827c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1828c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1829c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1874c7289b1cSThierry Reding stream-match-mask = <0x7f80>; 1875c7289b1cSThierry Reding #global-interrupts = <2>; 1876c7289b1cSThierry Reding #iommu-cells = <1>; 1877c7289b1cSThierry Reding 1878c7289b1cSThierry Reding nvidia,memory-controller = <&mc>; 1879c7289b1cSThierry Reding status = "okay"; 1880c7289b1cSThierry Reding }; 1881c7289b1cSThierry Reding 18823db6d3baSThierry Reding host1x@13e00000 { 1883ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 18843db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 18853db6d3baSThierry Reding <0x13e10000 0x10000>; 18863db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 18873db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 18883db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1889052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 18903db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 18913db6d3baSThierry Reding clock-names = "host1x"; 18923db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 18933db6d3baSThierry Reding reset-names = "host1x"; 18943db6d3baSThierry Reding 18953db6d3baSThierry Reding #address-cells = <1>; 18963db6d3baSThierry Reding #size-cells = <1>; 18973db6d3baSThierry Reding 1898*e25770feSMikko Perttunen ranges = <0x14800000 0x14800000 0x02800000>; 1899d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1900d5237c7cSThierry Reding interconnect-names = "dma-mem"; 1901c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HOST1X>; 19023db6d3baSThierry Reding 1903e30cf101SMikko Perttunen /* Context isolation domains */ 1904b0c1a994SThierry Reding iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1905b0c1a994SThierry Reding <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1906b0c1a994SThierry Reding <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1907b0c1a994SThierry Reding <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1908b0c1a994SThierry Reding <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1909b0c1a994SThierry Reding <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1910b0c1a994SThierry Reding <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1911b0c1a994SThierry Reding <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1912e30cf101SMikko Perttunen 191378a05873SMikko Perttunen nvdec@15140000 { 191478a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 191578a05873SMikko Perttunen reg = <0x15140000 0x00040000>; 191678a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 191778a05873SMikko Perttunen clock-names = "nvdec"; 191878a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC1>; 191978a05873SMikko Perttunen reset-names = "nvdec"; 192078a05873SMikko Perttunen 192178a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 192278a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 192378a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 192478a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 192578a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 192678a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC1>; 192778a05873SMikko Perttunen dma-coherent; 192878a05873SMikko Perttunen 192978a05873SMikko Perttunen nvidia,host1x-class = <0xf5>; 193078a05873SMikko Perttunen }; 193178a05873SMikko Perttunen 19323db6d3baSThierry Reding display-hub@15200000 { 1933aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1934611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 19353db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 19363db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 19373db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 19383db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 19393db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 19403db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 19413db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 19423db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 19433db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 19443db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 19453db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 19463db6d3baSThierry Reding clock-names = "disp", "hub"; 19473db6d3baSThierry Reding status = "disabled"; 19483db6d3baSThierry Reding 19493db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19503db6d3baSThierry Reding 19513db6d3baSThierry Reding #address-cells = <1>; 19523db6d3baSThierry Reding #size-cells = <1>; 19533db6d3baSThierry Reding 19543db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 19553db6d3baSThierry Reding 19563db6d3baSThierry Reding display@15200000 { 19573db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19583db6d3baSThierry Reding reg = <0x15200000 0x10000>; 19593db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 19603db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 19613db6d3baSThierry Reding clock-names = "dc"; 19623db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 19633db6d3baSThierry Reding reset-names = "dc"; 19643db6d3baSThierry Reding 19653db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1966d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1967d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1968d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 19693db6d3baSThierry Reding 19703db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 19713db6d3baSThierry Reding nvidia,head = <0>; 19723db6d3baSThierry Reding }; 19733db6d3baSThierry Reding 19743db6d3baSThierry Reding display@15210000 { 19753db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19763db6d3baSThierry Reding reg = <0x15210000 0x10000>; 19773db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 19783db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 19793db6d3baSThierry Reding clock-names = "dc"; 19803db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 19813db6d3baSThierry Reding reset-names = "dc"; 19823db6d3baSThierry Reding 19833db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1984d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1985d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1986d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 19873db6d3baSThierry Reding 19883db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 19893db6d3baSThierry Reding nvidia,head = <1>; 19903db6d3baSThierry Reding }; 19913db6d3baSThierry Reding 19923db6d3baSThierry Reding display@15220000 { 19933db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19943db6d3baSThierry Reding reg = <0x15220000 0x10000>; 19953db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 19963db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 19973db6d3baSThierry Reding clock-names = "dc"; 19983db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 19993db6d3baSThierry Reding reset-names = "dc"; 20003db6d3baSThierry Reding 20013db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2002d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2003d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2004d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20053db6d3baSThierry Reding 20063db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20073db6d3baSThierry Reding nvidia,head = <2>; 20083db6d3baSThierry Reding }; 20093db6d3baSThierry Reding 20103db6d3baSThierry Reding display@15230000 { 20113db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 20123db6d3baSThierry Reding reg = <0x15230000 0x10000>; 20133db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 20143db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 20153db6d3baSThierry Reding clock-names = "dc"; 20163db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 20173db6d3baSThierry Reding reset-names = "dc"; 20183db6d3baSThierry Reding 20193db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2020d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2021d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2022d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20233db6d3baSThierry Reding 20243db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20253db6d3baSThierry Reding nvidia,head = <3>; 20263db6d3baSThierry Reding }; 20273db6d3baSThierry Reding }; 20283db6d3baSThierry Reding 20298d424ec2SThierry Reding vic@15340000 { 20308d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 20318d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 20328d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 20338d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 20348d424ec2SThierry Reding clock-names = "vic"; 20358d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 20368d424ec2SThierry Reding reset-names = "vic"; 20378d424ec2SThierry Reding 20388d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2039d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2040d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2041d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 2042c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_VIC>; 2043a52280c8SJon Hunter dma-coherent; 20448d424ec2SThierry Reding }; 20458d424ec2SThierry Reding 2046f7eb2785SJon Hunter nvjpg@15380000 { 2047f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvjpg"; 2048f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 2049f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2050f7eb2785SJon Hunter clock-names = "nvjpg"; 2051f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVJPG>; 2052f7eb2785SJon Hunter reset-names = "nvjpg"; 2053f7eb2785SJon Hunter 2054f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2055f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2056f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2057f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 2058f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVJPG>; 2059f7eb2785SJon Hunter dma-coherent; 2060f7eb2785SJon Hunter }; 2061f7eb2785SJon Hunter 206278a05873SMikko Perttunen nvdec@15480000 { 206378a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 206478a05873SMikko Perttunen reg = <0x15480000 0x00040000>; 206578a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC>; 206678a05873SMikko Perttunen clock-names = "nvdec"; 206778a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC>; 206878a05873SMikko Perttunen reset-names = "nvdec"; 206978a05873SMikko Perttunen 207078a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 207178a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 207278a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 207378a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 207478a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 207578a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC>; 207678a05873SMikko Perttunen dma-coherent; 207778a05873SMikko Perttunen 207878a05873SMikko Perttunen nvidia,host1x-class = <0xf0>; 207978a05873SMikko Perttunen }; 208078a05873SMikko Perttunen 2081f7eb2785SJon Hunter nvenc@154c0000 { 2082f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 2083f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 2084f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC>; 2085f7eb2785SJon Hunter clock-names = "nvenc"; 2086f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC>; 2087f7eb2785SJon Hunter reset-names = "nvenc"; 2088f7eb2785SJon Hunter 2089f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2090f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2091f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2092f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2093f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2094f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC>; 2095f7eb2785SJon Hunter dma-coherent; 2096f7eb2785SJon Hunter 2097f7eb2785SJon Hunter nvidia,host1x-class = <0x21>; 2098f7eb2785SJon Hunter }; 2099f7eb2785SJon Hunter 21003db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 21013db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21023db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 21033db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 21043db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 21053db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21063db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21073db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 21083db6d3baSThierry Reding reset-names = "dpaux"; 21093db6d3baSThierry Reding status = "disabled"; 21103db6d3baSThierry Reding 21113db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21123db6d3baSThierry Reding 21133db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 21143db6d3baSThierry Reding groups = "dpaux-io"; 21153db6d3baSThierry Reding function = "aux"; 21163db6d3baSThierry Reding }; 21173db6d3baSThierry Reding 21183db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 21193db6d3baSThierry Reding groups = "dpaux-io"; 21203db6d3baSThierry Reding function = "i2c"; 21213db6d3baSThierry Reding }; 21223db6d3baSThierry Reding 21233db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 21243db6d3baSThierry Reding groups = "dpaux-io"; 21253db6d3baSThierry Reding function = "off"; 21263db6d3baSThierry Reding }; 21273db6d3baSThierry Reding 21283db6d3baSThierry Reding i2c-bus { 21293db6d3baSThierry Reding #address-cells = <1>; 21303db6d3baSThierry Reding #size-cells = <0>; 21313db6d3baSThierry Reding }; 21323db6d3baSThierry Reding }; 21333db6d3baSThierry Reding 21343db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 21353db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21363db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 21373db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 21383db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 21393db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21403db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21413db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 21423db6d3baSThierry Reding reset-names = "dpaux"; 21433db6d3baSThierry Reding status = "disabled"; 21443db6d3baSThierry Reding 21453db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21463db6d3baSThierry Reding 21473db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 21483db6d3baSThierry Reding groups = "dpaux-io"; 21493db6d3baSThierry Reding function = "aux"; 21503db6d3baSThierry Reding }; 21513db6d3baSThierry Reding 21523db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 21533db6d3baSThierry Reding groups = "dpaux-io"; 21543db6d3baSThierry Reding function = "i2c"; 21553db6d3baSThierry Reding }; 21563db6d3baSThierry Reding 21573db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 21583db6d3baSThierry Reding groups = "dpaux-io"; 21593db6d3baSThierry Reding function = "off"; 21603db6d3baSThierry Reding }; 21613db6d3baSThierry Reding 21623db6d3baSThierry Reding i2c-bus { 21633db6d3baSThierry Reding #address-cells = <1>; 21643db6d3baSThierry Reding #size-cells = <0>; 21653db6d3baSThierry Reding }; 21663db6d3baSThierry Reding }; 21673db6d3baSThierry Reding 21683db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 21693db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21703db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 21713db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 21723db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 21733db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21743db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21753db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 21763db6d3baSThierry Reding reset-names = "dpaux"; 21773db6d3baSThierry Reding status = "disabled"; 21783db6d3baSThierry Reding 21793db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21803db6d3baSThierry Reding 21813db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 21823db6d3baSThierry Reding groups = "dpaux-io"; 21833db6d3baSThierry Reding function = "aux"; 21843db6d3baSThierry Reding }; 21853db6d3baSThierry Reding 21863db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 21873db6d3baSThierry Reding groups = "dpaux-io"; 21883db6d3baSThierry Reding function = "i2c"; 21893db6d3baSThierry Reding }; 21903db6d3baSThierry Reding 21913db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 21923db6d3baSThierry Reding groups = "dpaux-io"; 21933db6d3baSThierry Reding function = "off"; 21943db6d3baSThierry Reding }; 21953db6d3baSThierry Reding 21963db6d3baSThierry Reding i2c-bus { 21973db6d3baSThierry Reding #address-cells = <1>; 21983db6d3baSThierry Reding #size-cells = <0>; 21993db6d3baSThierry Reding }; 22003db6d3baSThierry Reding }; 22013db6d3baSThierry Reding 22023db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 22033db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 22043db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 22053db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 22063db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 22073db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 22083db6d3baSThierry Reding clock-names = "dpaux", "parent"; 22093db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 22103db6d3baSThierry Reding reset-names = "dpaux"; 22113db6d3baSThierry Reding status = "disabled"; 22123db6d3baSThierry Reding 22133db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22143db6d3baSThierry Reding 22153db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 22163db6d3baSThierry Reding groups = "dpaux-io"; 22173db6d3baSThierry Reding function = "aux"; 22183db6d3baSThierry Reding }; 22193db6d3baSThierry Reding 22203db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 22213db6d3baSThierry Reding groups = "dpaux-io"; 22223db6d3baSThierry Reding function = "i2c"; 22233db6d3baSThierry Reding }; 22243db6d3baSThierry Reding 22253db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 22263db6d3baSThierry Reding groups = "dpaux-io"; 22273db6d3baSThierry Reding function = "off"; 22283db6d3baSThierry Reding }; 22293db6d3baSThierry Reding 22303db6d3baSThierry Reding i2c-bus { 22313db6d3baSThierry Reding #address-cells = <1>; 22323db6d3baSThierry Reding #size-cells = <0>; 22333db6d3baSThierry Reding }; 22343db6d3baSThierry Reding }; 22353db6d3baSThierry Reding 2236f7eb2785SJon Hunter nvenc@15a80000 { 2237f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 2238f7eb2785SJon Hunter reg = <0x15a80000 0x00040000>; 2239f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2240f7eb2785SJon Hunter clock-names = "nvenc"; 2241f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC1>; 2242f7eb2785SJon Hunter reset-names = "nvenc"; 2243f7eb2785SJon Hunter 2244f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2245f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2246f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2247f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2248f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2249f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC1>; 2250f7eb2785SJon Hunter dma-coherent; 2251f7eb2785SJon Hunter 2252f7eb2785SJon Hunter nvidia,host1x-class = <0x22>; 2253f7eb2785SJon Hunter }; 2254f7eb2785SJon Hunter 22553db6d3baSThierry Reding sor0: sor@15b00000 { 22563db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 22573db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 22583db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 22593db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 22603db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 22613db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 22623db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 22633db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 22643db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 22653db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 22663db6d3baSThierry Reding "pad"; 22673db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 22683db6d3baSThierry Reding reset-names = "sor"; 22693db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 22703db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 22713db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 22723db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 22733db6d3baSThierry Reding status = "disabled"; 22743db6d3baSThierry Reding 22753db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22763db6d3baSThierry Reding nvidia,interface = <0>; 22773db6d3baSThierry Reding }; 22783db6d3baSThierry Reding 22793db6d3baSThierry Reding sor1: sor@15b40000 { 22803db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 2281939e7430SThierry Reding reg = <0x15b40000 0x40000>; 22823db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 22833db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 22843db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 22853db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 22863db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 22873db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 22883db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 22893db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 22903db6d3baSThierry Reding "pad"; 22913db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 22923db6d3baSThierry Reding reset-names = "sor"; 22933db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 22943db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 22953db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 22963db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 22973db6d3baSThierry Reding status = "disabled"; 22983db6d3baSThierry Reding 22993db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23003db6d3baSThierry Reding nvidia,interface = <1>; 23013db6d3baSThierry Reding }; 23023db6d3baSThierry Reding 23033db6d3baSThierry Reding sor2: sor@15b80000 { 23043db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 23053db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 23063db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 23073db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 23083db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 23093db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 23103db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23113db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23123db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 23133db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23143db6d3baSThierry Reding "pad"; 23153db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 23163db6d3baSThierry Reding reset-names = "sor"; 23173db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 23183db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 23193db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 23203db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23213db6d3baSThierry Reding status = "disabled"; 23223db6d3baSThierry Reding 23233db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23243db6d3baSThierry Reding nvidia,interface = <2>; 23253db6d3baSThierry Reding }; 23263db6d3baSThierry Reding 23273db6d3baSThierry Reding sor3: sor@15bc0000 { 23283db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 23293db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 23303db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 23313db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 23323db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 23333db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 23343db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23353db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23363db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 23373db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23383db6d3baSThierry Reding "pad"; 23393db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 23403db6d3baSThierry Reding reset-names = "sor"; 23413db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 23423db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 23433db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 23443db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23453db6d3baSThierry Reding status = "disabled"; 23463db6d3baSThierry Reding 23473db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23483db6d3baSThierry Reding nvidia,interface = <3>; 23493db6d3baSThierry Reding }; 23503db6d3baSThierry Reding }; 23510f134e39SThierry Reding 23520f134e39SThierry Reding gpu@17000000 { 23530f134e39SThierry Reding compatible = "nvidia,gv11b"; 2354818ae79aSThierry Reding reg = <0x17000000 0x1000000>, 2355818ae79aSThierry Reding <0x18000000 0x1000000>; 23560f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 23570f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 23580f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 23590f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 23600f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 23610f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 23620f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 23630f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 23640f134e39SThierry Reding reset-names = "gpu"; 23650f134e39SThierry Reding dma-coherent; 23660f134e39SThierry Reding 23670f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 23680f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 23690f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 23700f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 23710f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 23720f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 23730f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 23740f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 23750f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 23760f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 23770f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 23780f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 23790f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 23800f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 23810f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 23820f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 23830f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 23840f134e39SThierry Reding }; 23855425fb15SMikko Perttunen }; 23865425fb15SMikko Perttunen 23872602c32fSVidya Sagar pcie@14100000 { 2388f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 23892602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2390644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2391644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2392644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2393644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 23942602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 23952602c32fSVidya Sagar 23962602c32fSVidya Sagar status = "disabled"; 23972602c32fSVidya Sagar 23982602c32fSVidya Sagar #address-cells = <3>; 23992602c32fSVidya Sagar #size-cells = <2>; 24002602c32fSVidya Sagar device_type = "pci"; 24012602c32fSVidya Sagar num-lanes = <1>; 24022602c32fSVidya Sagar linux,pci-domain = <1>; 24032602c32fSVidya Sagar 24042602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 24052602c32fSVidya Sagar clock-names = "core"; 24062602c32fSVidya Sagar 24072602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 24082602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 24092602c32fSVidya Sagar reset-names = "apb", "core"; 24102602c32fSVidya Sagar 24112602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24122602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24132602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24142602c32fSVidya Sagar 24152602c32fSVidya Sagar #interrupt-cells = <1>; 24162602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24172602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 24182602c32fSVidya Sagar 24192602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 24202602c32fSVidya Sagar 24212602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24222602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24232602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24242602c32fSVidya Sagar 24252602c32fSVidya Sagar bus-range = <0x0 0xff>; 2426d5237c7cSThierry Reding 24278a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 24288a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 24298a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2430d5237c7cSThierry Reding 2431d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2432d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2433ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2434ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2435ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2436ba02920cSVidya Sagar dma-coherent; 24372602c32fSVidya Sagar }; 24382602c32fSVidya Sagar 24392602c32fSVidya Sagar pcie@14120000 { 2440f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24412602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2442644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2443644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2444644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2445644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24462602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24472602c32fSVidya Sagar 24482602c32fSVidya Sagar status = "disabled"; 24492602c32fSVidya Sagar 24502602c32fSVidya Sagar #address-cells = <3>; 24512602c32fSVidya Sagar #size-cells = <2>; 24522602c32fSVidya Sagar device_type = "pci"; 24532602c32fSVidya Sagar num-lanes = <1>; 24542602c32fSVidya Sagar linux,pci-domain = <2>; 24552602c32fSVidya Sagar 24562602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 24572602c32fSVidya Sagar clock-names = "core"; 24582602c32fSVidya Sagar 24592602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 24602602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 24612602c32fSVidya Sagar reset-names = "apb", "core"; 24622602c32fSVidya Sagar 24632602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24642602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24652602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24662602c32fSVidya Sagar 24672602c32fSVidya Sagar #interrupt-cells = <1>; 24682602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24692602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 24702602c32fSVidya Sagar 24712602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 24722602c32fSVidya Sagar 24732602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24742602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24752602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24762602c32fSVidya Sagar 24772602c32fSVidya Sagar bus-range = <0x0 0xff>; 2478d5237c7cSThierry Reding 24798a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 24808a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 24818a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2482d5237c7cSThierry Reding 2483d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2484d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2485ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2486ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2487ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2488ba02920cSVidya Sagar dma-coherent; 24892602c32fSVidya Sagar }; 24902602c32fSVidya Sagar 24912602c32fSVidya Sagar pcie@14140000 { 2492f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24932602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2494644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2495644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2496644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2497644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24982602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24992602c32fSVidya Sagar 25002602c32fSVidya Sagar status = "disabled"; 25012602c32fSVidya Sagar 25022602c32fSVidya Sagar #address-cells = <3>; 25032602c32fSVidya Sagar #size-cells = <2>; 25042602c32fSVidya Sagar device_type = "pci"; 25052602c32fSVidya Sagar num-lanes = <1>; 25062602c32fSVidya Sagar linux,pci-domain = <3>; 25072602c32fSVidya Sagar 25082602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 25092602c32fSVidya Sagar clock-names = "core"; 25102602c32fSVidya Sagar 25112602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 25122602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 25132602c32fSVidya Sagar reset-names = "apb", "core"; 25142602c32fSVidya Sagar 25152602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25162602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 25172602c32fSVidya Sagar interrupt-names = "intr", "msi"; 25182602c32fSVidya Sagar 25192602c32fSVidya Sagar #interrupt-cells = <1>; 25202602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 25212602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 25222602c32fSVidya Sagar 25232602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 25242602c32fSVidya Sagar 25252602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 25262602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25272602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 25282602c32fSVidya Sagar 25292602c32fSVidya Sagar bus-range = <0x0 0xff>; 2530d5237c7cSThierry Reding 25318a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 25328a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 25338a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2534d5237c7cSThierry Reding 2535d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2536d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2537ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2538ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2539ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2540ba02920cSVidya Sagar dma-coherent; 25412602c32fSVidya Sagar }; 25422602c32fSVidya Sagar 25432602c32fSVidya Sagar pcie@14160000 { 2544f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 25452602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2546644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2547644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2548644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2549644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 25502602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 25512602c32fSVidya Sagar 25522602c32fSVidya Sagar status = "disabled"; 25532602c32fSVidya Sagar 25542602c32fSVidya Sagar #address-cells = <3>; 25552602c32fSVidya Sagar #size-cells = <2>; 25562602c32fSVidya Sagar device_type = "pci"; 25572602c32fSVidya Sagar num-lanes = <4>; 25582602c32fSVidya Sagar linux,pci-domain = <4>; 25592602c32fSVidya Sagar 25602602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 25612602c32fSVidya Sagar clock-names = "core"; 25622602c32fSVidya Sagar 25632602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 25642602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 25652602c32fSVidya Sagar reset-names = "apb", "core"; 25662602c32fSVidya Sagar 25672602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25682602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 25692602c32fSVidya Sagar interrupt-names = "intr", "msi"; 25702602c32fSVidya Sagar 25712602c32fSVidya Sagar #interrupt-cells = <1>; 25722602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 25732602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 25742602c32fSVidya Sagar 25752602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 25762602c32fSVidya Sagar 25772602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 25782602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25792602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 25802602c32fSVidya Sagar 25812602c32fSVidya Sagar bus-range = <0x0 0xff>; 2582d5237c7cSThierry Reding 25838a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 25848a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 25858a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2586d5237c7cSThierry Reding 2587d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2588d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2589ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2590ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2591ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2592ba02920cSVidya Sagar dma-coherent; 25932602c32fSVidya Sagar }; 25942602c32fSVidya Sagar 25952602c32fSVidya Sagar pcie@14180000 { 2596f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 25972602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2598644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2599644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2600644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2601644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 26022602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 26032602c32fSVidya Sagar 26042602c32fSVidya Sagar status = "disabled"; 26052602c32fSVidya Sagar 26062602c32fSVidya Sagar #address-cells = <3>; 26072602c32fSVidya Sagar #size-cells = <2>; 26082602c32fSVidya Sagar device_type = "pci"; 26092602c32fSVidya Sagar num-lanes = <8>; 26102602c32fSVidya Sagar linux,pci-domain = <0>; 26112602c32fSVidya Sagar 26122602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 26132602c32fSVidya Sagar clock-names = "core"; 26142602c32fSVidya Sagar 26152602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 26162602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 26172602c32fSVidya Sagar reset-names = "apb", "core"; 26182602c32fSVidya Sagar 26192602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26202602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26212602c32fSVidya Sagar interrupt-names = "intr", "msi"; 26222602c32fSVidya Sagar 26232602c32fSVidya Sagar #interrupt-cells = <1>; 26242602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 26252602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 26262602c32fSVidya Sagar 26272602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 26282602c32fSVidya Sagar 26292602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 26302602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 26312602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 26322602c32fSVidya Sagar 26332602c32fSVidya Sagar bus-range = <0x0 0xff>; 2634d5237c7cSThierry Reding 26358a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 26368a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 26378a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2638d5237c7cSThierry Reding 2639d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2640d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2641ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2642ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2643ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2644ba02920cSVidya Sagar dma-coherent; 26452602c32fSVidya Sagar }; 26462602c32fSVidya Sagar 26472602c32fSVidya Sagar pcie@141a0000 { 2648f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 26492602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2650644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2651644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2652644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2653644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 26542602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 26552602c32fSVidya Sagar 26562602c32fSVidya Sagar status = "disabled"; 26572602c32fSVidya Sagar 26582602c32fSVidya Sagar #address-cells = <3>; 26592602c32fSVidya Sagar #size-cells = <2>; 26602602c32fSVidya Sagar device_type = "pci"; 26612602c32fSVidya Sagar num-lanes = <8>; 26622602c32fSVidya Sagar linux,pci-domain = <5>; 26632602c32fSVidya Sagar 2664dbb72e2cSVidya Sagar pinctrl-names = "default"; 2665dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2666dbb72e2cSVidya Sagar 2667c453cc9eSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2668c453cc9eSThierry Reding clock-names = "core"; 26692602c32fSVidya Sagar 26702602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 26712602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 26722602c32fSVidya Sagar reset-names = "apb", "core"; 26732602c32fSVidya Sagar 26742602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26752602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26762602c32fSVidya Sagar interrupt-names = "intr", "msi"; 26772602c32fSVidya Sagar 26782602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 26792602c32fSVidya Sagar 26802602c32fSVidya Sagar #interrupt-cells = <1>; 26812602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 26822602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 26832602c32fSVidya Sagar 26842602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 26852602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 26862602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 26872602c32fSVidya Sagar 26882602c32fSVidya Sagar bus-range = <0x0 0xff>; 2689d5237c7cSThierry Reding 26908a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 26918a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 26928a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2693d5237c7cSThierry Reding 2694d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2695d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2696ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2697ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2698ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2699ba02920cSVidya Sagar dma-coherent; 27002602c32fSVidya Sagar }; 27012602c32fSVidya Sagar 2702b9e2404cSMauro Carvalho Chehab pcie-ep@14160000 { 2703bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 27040c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2705644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2706644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2707644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2708644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 27090c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 27100c988b73SVidya Sagar 27110c988b73SVidya Sagar status = "disabled"; 27120c988b73SVidya Sagar 27130c988b73SVidya Sagar num-lanes = <4>; 27140c988b73SVidya Sagar num-ib-windows = <2>; 27150c988b73SVidya Sagar num-ob-windows = <8>; 27160c988b73SVidya Sagar 27170c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 27180c988b73SVidya Sagar clock-names = "core"; 27190c988b73SVidya Sagar 27200c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 27210c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 27220c988b73SVidya Sagar reset-names = "apb", "core"; 27230c988b73SVidya Sagar 27240c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 27250c988b73SVidya Sagar interrupt-names = "intr"; 27260c988b73SVidya Sagar 27270c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 27280c988b73SVidya Sagar 27290c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 27300c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27310c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2732ba02920cSVidya Sagar 2733ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2734ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2735ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2736ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2737ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2738ba02920cSVidya Sagar dma-coherent; 27390c988b73SVidya Sagar }; 27400c988b73SVidya Sagar 2741b9e2404cSMauro Carvalho Chehab pcie-ep@14180000 { 2742bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 27430c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2744644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2745644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2746644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2747644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 27480c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 27490c988b73SVidya Sagar 27500c988b73SVidya Sagar status = "disabled"; 27510c988b73SVidya Sagar 27520c988b73SVidya Sagar num-lanes = <8>; 27530c988b73SVidya Sagar num-ib-windows = <2>; 27540c988b73SVidya Sagar num-ob-windows = <8>; 27550c988b73SVidya Sagar 27560c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 27570c988b73SVidya Sagar clock-names = "core"; 27580c988b73SVidya Sagar 27590c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 27600c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 27610c988b73SVidya Sagar reset-names = "apb", "core"; 27620c988b73SVidya Sagar 27630c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 27640c988b73SVidya Sagar interrupt-names = "intr"; 27650c988b73SVidya Sagar 27660c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 27670c988b73SVidya Sagar 27680c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 27690c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27700c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2771ba02920cSVidya Sagar 2772ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2773ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2774ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2775ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2776ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2777ba02920cSVidya Sagar dma-coherent; 27780c988b73SVidya Sagar }; 27790c988b73SVidya Sagar 2780b9e2404cSMauro Carvalho Chehab pcie-ep@141a0000 { 2781bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 27820c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2783644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2784644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2785644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2786644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 27870c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 27880c988b73SVidya Sagar 27890c988b73SVidya Sagar status = "disabled"; 27900c988b73SVidya Sagar 27910c988b73SVidya Sagar num-lanes = <8>; 27920c988b73SVidya Sagar num-ib-windows = <2>; 27930c988b73SVidya Sagar num-ob-windows = <8>; 27940c988b73SVidya Sagar 27950c988b73SVidya Sagar pinctrl-names = "default"; 27960c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 27970c988b73SVidya Sagar 27980c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 27990c988b73SVidya Sagar clock-names = "core"; 28000c988b73SVidya Sagar 28010c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 28020c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 28030c988b73SVidya Sagar reset-names = "apb", "core"; 28040c988b73SVidya Sagar 28050c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 28060c988b73SVidya Sagar interrupt-names = "intr"; 28070c988b73SVidya Sagar 28080c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 28090c988b73SVidya Sagar 28100c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 28110c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 28120c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2813ba02920cSVidya Sagar 2814ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2815ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2816ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2817ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2818ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2819ba02920cSVidya Sagar dma-coherent; 28200c988b73SVidya Sagar }; 28210c988b73SVidya Sagar 2822e867fe41SThierry Reding sram@40000000 { 28235425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 28245425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 28255425fb15SMikko Perttunen #address-cells = <1>; 28265425fb15SMikko Perttunen #size-cells = <1>; 28275425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 282861192a9dSMikko Perttunen no-memory-wc; 28295425fb15SMikko Perttunen 2830e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 28315425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 28325425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 28335425fb15SMikko Perttunen pool; 28345425fb15SMikko Perttunen }; 28355425fb15SMikko Perttunen 2836e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 28375425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 28385425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 28395425fb15SMikko Perttunen pool; 28405425fb15SMikko Perttunen }; 28415425fb15SMikko Perttunen }; 28425425fb15SMikko Perttunen 28435425fb15SMikko Perttunen bpmp: bpmp { 28445425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 28455425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 28465425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 28477fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 28485425fb15SMikko Perttunen #clock-cells = <1>; 28495425fb15SMikko Perttunen #reset-cells = <1>; 28505425fb15SMikko Perttunen #power-domain-cells = <1>; 2851d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2852d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2853d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2854d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2855d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 2856c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_BPMP>; 28575425fb15SMikko Perttunen 28585425fb15SMikko Perttunen bpmp_i2c: i2c { 28595425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 28605425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 28615425fb15SMikko Perttunen #address-cells = <1>; 28625425fb15SMikko Perttunen #size-cells = <0>; 28635425fb15SMikko Perttunen }; 28645425fb15SMikko Perttunen 28655425fb15SMikko Perttunen bpmp_thermal: thermal { 28665425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 28675425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 28685425fb15SMikko Perttunen }; 28695425fb15SMikko Perttunen }; 28705425fb15SMikko Perttunen 28717780a034SMikko Perttunen cpus { 2872d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2873d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 28747780a034SMikko Perttunen #address-cells = <1>; 28757780a034SMikko Perttunen #size-cells = <0>; 28767780a034SMikko Perttunen 2877b45d322cSThierry Reding cpu0_0: cpu@0 { 287831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 28797780a034SMikko Perttunen device_type = "cpu"; 2880b45d322cSThierry Reding reg = <0x000>; 28817780a034SMikko Perttunen enable-method = "psci"; 2882b45d322cSThierry Reding i-cache-size = <131072>; 2883b45d322cSThierry Reding i-cache-line-size = <64>; 2884b45d322cSThierry Reding i-cache-sets = <512>; 2885b45d322cSThierry Reding d-cache-size = <65536>; 2886b45d322cSThierry Reding d-cache-line-size = <64>; 2887b45d322cSThierry Reding d-cache-sets = <256>; 2888b45d322cSThierry Reding next-level-cache = <&l2c_0>; 28897780a034SMikko Perttunen }; 28907780a034SMikko Perttunen 2891b45d322cSThierry Reding cpu0_1: cpu@1 { 289231af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 28937780a034SMikko Perttunen device_type = "cpu"; 2894b45d322cSThierry Reding reg = <0x001>; 28957780a034SMikko Perttunen enable-method = "psci"; 2896b45d322cSThierry Reding i-cache-size = <131072>; 2897b45d322cSThierry Reding i-cache-line-size = <64>; 2898b45d322cSThierry Reding i-cache-sets = <512>; 2899b45d322cSThierry Reding d-cache-size = <65536>; 2900b45d322cSThierry Reding d-cache-line-size = <64>; 2901b45d322cSThierry Reding d-cache-sets = <256>; 2902b45d322cSThierry Reding next-level-cache = <&l2c_0>; 29037780a034SMikko Perttunen }; 29047780a034SMikko Perttunen 2905b45d322cSThierry Reding cpu1_0: cpu@100 { 290631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29077780a034SMikko Perttunen device_type = "cpu"; 29087780a034SMikko Perttunen reg = <0x100>; 29097780a034SMikko Perttunen enable-method = "psci"; 2910b45d322cSThierry Reding i-cache-size = <131072>; 2911b45d322cSThierry Reding i-cache-line-size = <64>; 2912b45d322cSThierry Reding i-cache-sets = <512>; 2913b45d322cSThierry Reding d-cache-size = <65536>; 2914b45d322cSThierry Reding d-cache-line-size = <64>; 2915b45d322cSThierry Reding d-cache-sets = <256>; 2916b45d322cSThierry Reding next-level-cache = <&l2c_1>; 29177780a034SMikko Perttunen }; 29187780a034SMikko Perttunen 2919b45d322cSThierry Reding cpu1_1: cpu@101 { 292031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29217780a034SMikko Perttunen device_type = "cpu"; 29227780a034SMikko Perttunen reg = <0x101>; 29237780a034SMikko Perttunen enable-method = "psci"; 2924b45d322cSThierry Reding i-cache-size = <131072>; 2925b45d322cSThierry Reding i-cache-line-size = <64>; 2926b45d322cSThierry Reding i-cache-sets = <512>; 2927b45d322cSThierry Reding d-cache-size = <65536>; 2928b45d322cSThierry Reding d-cache-line-size = <64>; 2929b45d322cSThierry Reding d-cache-sets = <256>; 2930b45d322cSThierry Reding next-level-cache = <&l2c_1>; 29317780a034SMikko Perttunen }; 29327780a034SMikko Perttunen 2933b45d322cSThierry Reding cpu2_0: cpu@200 { 293431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29357780a034SMikko Perttunen device_type = "cpu"; 29367780a034SMikko Perttunen reg = <0x200>; 29377780a034SMikko Perttunen enable-method = "psci"; 2938b45d322cSThierry Reding i-cache-size = <131072>; 2939b45d322cSThierry Reding i-cache-line-size = <64>; 2940b45d322cSThierry Reding i-cache-sets = <512>; 2941b45d322cSThierry Reding d-cache-size = <65536>; 2942b45d322cSThierry Reding d-cache-line-size = <64>; 2943b45d322cSThierry Reding d-cache-sets = <256>; 2944b45d322cSThierry Reding next-level-cache = <&l2c_2>; 29457780a034SMikko Perttunen }; 29467780a034SMikko Perttunen 2947b45d322cSThierry Reding cpu2_1: cpu@201 { 294831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29497780a034SMikko Perttunen device_type = "cpu"; 29507780a034SMikko Perttunen reg = <0x201>; 29517780a034SMikko Perttunen enable-method = "psci"; 2952b45d322cSThierry Reding i-cache-size = <131072>; 2953b45d322cSThierry Reding i-cache-line-size = <64>; 2954b45d322cSThierry Reding i-cache-sets = <512>; 2955b45d322cSThierry Reding d-cache-size = <65536>; 2956b45d322cSThierry Reding d-cache-line-size = <64>; 2957b45d322cSThierry Reding d-cache-sets = <256>; 2958b45d322cSThierry Reding next-level-cache = <&l2c_2>; 29597780a034SMikko Perttunen }; 29607780a034SMikko Perttunen 2961b45d322cSThierry Reding cpu3_0: cpu@300 { 296231af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29637780a034SMikko Perttunen device_type = "cpu"; 2964b45d322cSThierry Reding reg = <0x300>; 29657780a034SMikko Perttunen enable-method = "psci"; 2966b45d322cSThierry Reding i-cache-size = <131072>; 2967b45d322cSThierry Reding i-cache-line-size = <64>; 2968b45d322cSThierry Reding i-cache-sets = <512>; 2969b45d322cSThierry Reding d-cache-size = <65536>; 2970b45d322cSThierry Reding d-cache-line-size = <64>; 2971b45d322cSThierry Reding d-cache-sets = <256>; 2972b45d322cSThierry Reding next-level-cache = <&l2c_3>; 29737780a034SMikko Perttunen }; 29747780a034SMikko Perttunen 2975b45d322cSThierry Reding cpu3_1: cpu@301 { 297631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29777780a034SMikko Perttunen device_type = "cpu"; 2978b45d322cSThierry Reding reg = <0x301>; 29797780a034SMikko Perttunen enable-method = "psci"; 2980b45d322cSThierry Reding i-cache-size = <131072>; 2981b45d322cSThierry Reding i-cache-line-size = <64>; 2982b45d322cSThierry Reding i-cache-sets = <512>; 2983b45d322cSThierry Reding d-cache-size = <65536>; 2984b45d322cSThierry Reding d-cache-line-size = <64>; 2985b45d322cSThierry Reding d-cache-sets = <256>; 2986b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2987b45d322cSThierry Reding }; 2988b45d322cSThierry Reding 2989b45d322cSThierry Reding cpu-map { 2990b45d322cSThierry Reding cluster0 { 2991b45d322cSThierry Reding core0 { 2992b45d322cSThierry Reding cpu = <&cpu0_0>; 2993b45d322cSThierry Reding }; 2994b45d322cSThierry Reding 2995b45d322cSThierry Reding core1 { 2996b45d322cSThierry Reding cpu = <&cpu0_1>; 2997b45d322cSThierry Reding }; 2998b45d322cSThierry Reding }; 2999b45d322cSThierry Reding 3000b45d322cSThierry Reding cluster1 { 3001b45d322cSThierry Reding core0 { 3002b45d322cSThierry Reding cpu = <&cpu1_0>; 3003b45d322cSThierry Reding }; 3004b45d322cSThierry Reding 3005b45d322cSThierry Reding core1 { 3006b45d322cSThierry Reding cpu = <&cpu1_1>; 3007b45d322cSThierry Reding }; 3008b45d322cSThierry Reding }; 3009b45d322cSThierry Reding 3010b45d322cSThierry Reding cluster2 { 3011b45d322cSThierry Reding core0 { 3012b45d322cSThierry Reding cpu = <&cpu2_0>; 3013b45d322cSThierry Reding }; 3014b45d322cSThierry Reding 3015b45d322cSThierry Reding core1 { 3016b45d322cSThierry Reding cpu = <&cpu2_1>; 3017b45d322cSThierry Reding }; 3018b45d322cSThierry Reding }; 3019b45d322cSThierry Reding 3020b45d322cSThierry Reding cluster3 { 3021b45d322cSThierry Reding core0 { 3022b45d322cSThierry Reding cpu = <&cpu3_0>; 3023b45d322cSThierry Reding }; 3024b45d322cSThierry Reding 3025b45d322cSThierry Reding core1 { 3026b45d322cSThierry Reding cpu = <&cpu3_1>; 3027b45d322cSThierry Reding }; 3028b45d322cSThierry Reding }; 3029b45d322cSThierry Reding }; 3030b45d322cSThierry Reding 3031b45d322cSThierry Reding l2c_0: l2-cache0 { 3032b45d322cSThierry Reding cache-size = <2097152>; 3033b45d322cSThierry Reding cache-line-size = <64>; 3034b45d322cSThierry Reding cache-sets = <2048>; 3035b45d322cSThierry Reding next-level-cache = <&l3c>; 3036b45d322cSThierry Reding }; 3037b45d322cSThierry Reding 3038b45d322cSThierry Reding l2c_1: l2-cache1 { 3039b45d322cSThierry Reding cache-size = <2097152>; 3040b45d322cSThierry Reding cache-line-size = <64>; 3041b45d322cSThierry Reding cache-sets = <2048>; 3042b45d322cSThierry Reding next-level-cache = <&l3c>; 3043b45d322cSThierry Reding }; 3044b45d322cSThierry Reding 3045b45d322cSThierry Reding l2c_2: l2-cache2 { 3046b45d322cSThierry Reding cache-size = <2097152>; 3047b45d322cSThierry Reding cache-line-size = <64>; 3048b45d322cSThierry Reding cache-sets = <2048>; 3049b45d322cSThierry Reding next-level-cache = <&l3c>; 3050b45d322cSThierry Reding }; 3051b45d322cSThierry Reding 3052b45d322cSThierry Reding l2c_3: l2-cache3 { 3053b45d322cSThierry Reding cache-size = <2097152>; 3054b45d322cSThierry Reding cache-line-size = <64>; 3055b45d322cSThierry Reding cache-sets = <2048>; 3056b45d322cSThierry Reding next-level-cache = <&l3c>; 3057b45d322cSThierry Reding }; 3058b45d322cSThierry Reding 3059b45d322cSThierry Reding l3c: l3-cache { 3060b45d322cSThierry Reding cache-size = <4194304>; 3061b45d322cSThierry Reding cache-line-size = <64>; 3062b45d322cSThierry Reding cache-sets = <4096>; 30637780a034SMikko Perttunen }; 30647780a034SMikko Perttunen }; 30657780a034SMikko Perttunen 30669e79e58fSJon Hunter pmu { 3067f0a48120SThierry Reding compatible = "nvidia,carmel-pmu"; 30689e79e58fSJon Hunter interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 30699e79e58fSJon Hunter <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 30709e79e58fSJon Hunter <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 30719e79e58fSJon Hunter <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 30729e79e58fSJon Hunter <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 30739e79e58fSJon Hunter <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 30749e79e58fSJon Hunter <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 30759e79e58fSJon Hunter <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 30769e79e58fSJon Hunter interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 30779e79e58fSJon Hunter &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 30789e79e58fSJon Hunter }; 30799e79e58fSJon Hunter 30807780a034SMikko Perttunen psci { 30817780a034SMikko Perttunen compatible = "arm,psci-1.0"; 30827780a034SMikko Perttunen status = "okay"; 30837780a034SMikko Perttunen method = "smc"; 30847780a034SMikko Perttunen }; 30857780a034SMikko Perttunen 30865b4f6323SSameer Pujar sound { 30875b4f6323SSameer Pujar status = "disabled"; 30885b4f6323SSameer Pujar 30895b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 30905b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 30915b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 30925b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 30935b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 30945b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 30955b4f6323SSameer Pujar assigned-clock-parents = <0>, 30965b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 30975b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 30985b4f6323SSameer Pujar /* 30995b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 31005b4f6323SSameer Pujar * for this to work and oscillate between base rates required 31015b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 31025b4f6323SSameer Pujar */ 31035b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 31045b4f6323SSameer Pujar }; 31055b4f6323SSameer Pujar 310699d9bde5SThierry Reding tcu: serial { 3107a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 3108a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3109a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3110a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 3111a38570c2SMikko Perttunen }; 3112a38570c2SMikko Perttunen 3113686ba009SThierry Reding thermal-zones { 3114fe57ff53SThierry Reding cpu-thermal { 3115fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3116686ba009SThierry Reding status = "disabled"; 3117686ba009SThierry Reding }; 3118686ba009SThierry Reding 3119fe57ff53SThierry Reding gpu-thermal { 3120fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3121686ba009SThierry Reding status = "disabled"; 3122686ba009SThierry Reding }; 3123686ba009SThierry Reding 3124fe57ff53SThierry Reding aux-thermal { 3125fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3126686ba009SThierry Reding status = "disabled"; 3127686ba009SThierry Reding }; 3128686ba009SThierry Reding 3129fe57ff53SThierry Reding pllx-thermal { 3130fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3131686ba009SThierry Reding status = "disabled"; 3132686ba009SThierry Reding }; 3133686ba009SThierry Reding 3134fe57ff53SThierry Reding ao-thermal { 3135fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3136686ba009SThierry Reding status = "disabled"; 3137686ba009SThierry Reding }; 3138686ba009SThierry Reding 3139fe57ff53SThierry Reding tj-thermal { 3140fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3141686ba009SThierry Reding status = "disabled"; 3142686ba009SThierry Reding }; 3143686ba009SThierry Reding }; 3144686ba009SThierry Reding 31455425fb15SMikko Perttunen timer { 31465425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 31475425fb15SMikko Perttunen interrupts = <GIC_PPI 13 31485425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31495425fb15SMikko Perttunen <GIC_PPI 14 31505425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31515425fb15SMikko Perttunen <GIC_PPI 11 31525425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31535425fb15SMikko Perttunen <GIC_PPI 10 31545425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 31555425fb15SMikko Perttunen interrupt-parent = <&gic>; 3156b30be673SThierry Reding always-on; 31575425fb15SMikko Perttunen }; 31585425fb15SMikko Perttunen}; 3159