15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 73db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 8dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 9686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 115425fb15SMikko Perttunen 125425fb15SMikko Perttunen/ { 135425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 145425fb15SMikko Perttunen interrupt-parent = <&gic>; 155425fb15SMikko Perttunen #address-cells = <2>; 165425fb15SMikko Perttunen #size-cells = <2>; 175425fb15SMikko Perttunen 185425fb15SMikko Perttunen /* control backbone */ 198b3aee8fSThierry Reding bus@0 { 205425fb15SMikko Perttunen compatible = "simple-bus"; 215425fb15SMikko Perttunen #address-cells = <1>; 225425fb15SMikko Perttunen #size-cells = <1>; 235425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 245425fb15SMikko Perttunen 2509903c5eSJC Kuo misc@100000 { 2609903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2709903c5eSJC Kuo reg = <0x00100000 0xf000>, 2809903c5eSJC Kuo <0x0010f000 0x1000>; 2909903c5eSJC Kuo }; 3009903c5eSJC Kuo 31f69ce393SMikko Perttunen gpio: gpio@2200000 { 32f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 33f69ce393SMikko Perttunen reg-names = "security", "gpio"; 34f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 35f69ce393SMikko Perttunen <0x2210000 0x10000>; 36f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41f69ce393SMikko Perttunen <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42f69ce393SMikko Perttunen #interrupt-cells = <2>; 43f69ce393SMikko Perttunen interrupt-controller; 44f69ce393SMikko Perttunen #gpio-cells = <2>; 45f69ce393SMikko Perttunen gpio-controller; 46f69ce393SMikko Perttunen }; 47f69ce393SMikko Perttunen 48f89b58ceSMikko Perttunen ethernet@2490000 { 4919dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 5019dc772aSThierry Reding "nvidia,tegra186-eqos", 51f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 52f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 53f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 56f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 57f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 58f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 61f89b58ceSMikko Perttunen reset-names = "eqos"; 62d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 63d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 64d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 65f89b58ceSMikko Perttunen status = "disabled"; 66f89b58ceSMikko Perttunen 67f89b58ceSMikko Perttunen snps,write-requests = <1>; 68f89b58ceSMikko Perttunen snps,read-requests = <3>; 69f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 70f89b58ceSMikko Perttunen snps,txpbl = <16>; 71f89b58ceSMikko Perttunen snps,rxpbl = <8>; 72f89b58ceSMikko Perttunen }; 73f89b58ceSMikko Perttunen 741aaa7698SThierry Reding aconnect@2900000 { 755d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 765d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 775d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 785d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 795d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 805d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 815d2249ddSSameer Pujar #address-cells = <1>; 825d2249ddSSameer Pujar #size-cells = <1>; 835d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 845d2249ddSSameer Pujar status = "disabled"; 855d2249ddSSameer Pujar 865d2249ddSSameer Pujar dma-controller@2930000 { 875d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 885d2249ddSSameer Pujar "nvidia,tegra186-adma"; 895d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 905d2249ddSSameer Pujar interrupt-parent = <&agic>; 915d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 925d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1135d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1145d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1155d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1165d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1175d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1185d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1195d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1205d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1215d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1225d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1235d2249ddSSameer Pujar #dma-cells = <1>; 1245d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 1255d2249ddSSameer Pujar clock-names = "d_audio"; 1265d2249ddSSameer Pujar status = "disabled"; 1275d2249ddSSameer Pujar }; 1285d2249ddSSameer Pujar 1295d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1305d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 1315d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1325d2249ddSSameer Pujar #interrupt-cells = <3>; 1335d2249ddSSameer Pujar interrupt-controller; 1345d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1355d2249ddSSameer Pujar <0x02a42000 0x2000>; 1365d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1375d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 1385d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 1395d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 1405d2249ddSSameer Pujar clock-names = "clk"; 1415d2249ddSSameer Pujar status = "disabled"; 1425d2249ddSSameer Pujar }; 1435d2249ddSSameer Pujar }; 1445d2249ddSSameer Pujar 145dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 146dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 147644c569dSThierry Reding reg = <0x2430000 0x17000>, 148644c569dSThierry Reding <0xc300000 0x4000>; 149dbb72e2cSVidya Sagar 150dbb72e2cSVidya Sagar status = "okay"; 151dbb72e2cSVidya Sagar 152dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 153dbb72e2cSVidya Sagar pex_rst { 154dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 155dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 156dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 157dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 158dbb72e2cSVidya Sagar nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 159dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 160dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 161dbb72e2cSVidya Sagar }; 162dbb72e2cSVidya Sagar }; 163dbb72e2cSVidya Sagar 164dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 165dbb72e2cSVidya Sagar clkreq { 166dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 167dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 168dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 169dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 170dbb72e2cSVidya Sagar nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 171dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 172dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 173dbb72e2cSVidya Sagar }; 174dbb72e2cSVidya Sagar }; 175dbb72e2cSVidya Sagar }; 176dbb72e2cSVidya Sagar 177be9b887fSThierry Reding mc: memory-controller@2c00000 { 178be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 179be9b887fSThierry Reding reg = <0x02c00000 0x100000>, 180be9b887fSThierry Reding <0x02b80000 0x040000>, 181be9b887fSThierry Reding <0x01700000 0x100000>; 1828613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 183d5237c7cSThierry Reding #interconnect-cells = <1>; 184be9b887fSThierry Reding status = "disabled"; 185be9b887fSThierry Reding 186be9b887fSThierry Reding #address-cells = <2>; 187be9b887fSThierry Reding #size-cells = <2>; 188be9b887fSThierry Reding 189be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 190be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 191be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 192be9b887fSThierry Reding 193be9b887fSThierry Reding /* 194be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 195be9b887fSThierry Reding * controller selects the XBAR format used when memory 196be9b887fSThierry Reding * is accessed. This is used to transparently access 197be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 198be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 199be9b887fSThierry Reding * 200be9b887fSThierry Reding * As a consequence, the operating system must ensure 201be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 202be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 203be9b887fSThierry Reding * devices require access to the XBAR switch, their 204be9b887fSThierry Reding * drivers must set this bit explicitly. 205be9b887fSThierry Reding * 206be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 207be9b887fSThierry Reding */ 208be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 209be9b887fSThierry Reding 210be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 211be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 212be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 213be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 214be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 215be9b887fSThierry Reding clock-names = "emc"; 216be9b887fSThierry Reding 217d5237c7cSThierry Reding #interconnect-cells = <0>; 218d5237c7cSThierry Reding 219be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 220be9b887fSThierry Reding }; 221be9b887fSThierry Reding }; 222be9b887fSThierry Reding 2235425fb15SMikko Perttunen uarta: serial@3100000 { 2245425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2255425fb15SMikko Perttunen reg = <0x03100000 0x40>; 2265425fb15SMikko Perttunen reg-shift = <2>; 2275425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2285425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 2295425fb15SMikko Perttunen clock-names = "serial"; 2305425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 2315425fb15SMikko Perttunen reset-names = "serial"; 2325425fb15SMikko Perttunen status = "disabled"; 2335425fb15SMikko Perttunen }; 2345425fb15SMikko Perttunen 2355425fb15SMikko Perttunen uartb: serial@3110000 { 2365425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2375425fb15SMikko Perttunen reg = <0x03110000 0x40>; 2385425fb15SMikko Perttunen reg-shift = <2>; 2395425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 2405425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 2415425fb15SMikko Perttunen clock-names = "serial"; 2425425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 2435425fb15SMikko Perttunen reset-names = "serial"; 2445425fb15SMikko Perttunen status = "disabled"; 2455425fb15SMikko Perttunen }; 2465425fb15SMikko Perttunen 2475425fb15SMikko Perttunen uartd: serial@3130000 { 2485425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2495425fb15SMikko Perttunen reg = <0x03130000 0x40>; 2505425fb15SMikko Perttunen reg-shift = <2>; 2515425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 2525425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 2535425fb15SMikko Perttunen clock-names = "serial"; 2545425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 2555425fb15SMikko Perttunen reset-names = "serial"; 2565425fb15SMikko Perttunen status = "disabled"; 2575425fb15SMikko Perttunen }; 2585425fb15SMikko Perttunen 2595425fb15SMikko Perttunen uarte: serial@3140000 { 2605425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2615425fb15SMikko Perttunen reg = <0x03140000 0x40>; 2625425fb15SMikko Perttunen reg-shift = <2>; 2635425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2645425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 2655425fb15SMikko Perttunen clock-names = "serial"; 2665425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 2675425fb15SMikko Perttunen reset-names = "serial"; 2685425fb15SMikko Perttunen status = "disabled"; 2695425fb15SMikko Perttunen }; 2705425fb15SMikko Perttunen 2715425fb15SMikko Perttunen uartf: serial@3150000 { 2725425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2735425fb15SMikko Perttunen reg = <0x03150000 0x40>; 2745425fb15SMikko Perttunen reg-shift = <2>; 2755425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 2765425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 2775425fb15SMikko Perttunen clock-names = "serial"; 2785425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 2795425fb15SMikko Perttunen reset-names = "serial"; 2805425fb15SMikko Perttunen status = "disabled"; 2815425fb15SMikko Perttunen }; 2825425fb15SMikko Perttunen 2835425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 284d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2855425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 2865425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2875425fb15SMikko Perttunen #address-cells = <1>; 2885425fb15SMikko Perttunen #size-cells = <0>; 2895425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 2905425fb15SMikko Perttunen clock-names = "div-clk"; 2915425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 2925425fb15SMikko Perttunen reset-names = "i2c"; 2935425fb15SMikko Perttunen status = "disabled"; 2945425fb15SMikko Perttunen }; 2955425fb15SMikko Perttunen 2965425fb15SMikko Perttunen uarth: serial@3170000 { 2975425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2985425fb15SMikko Perttunen reg = <0x03170000 0x40>; 2995425fb15SMikko Perttunen reg-shift = <2>; 3005425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 3015425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 3025425fb15SMikko Perttunen clock-names = "serial"; 3035425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 3045425fb15SMikko Perttunen reset-names = "serial"; 3055425fb15SMikko Perttunen status = "disabled"; 3065425fb15SMikko Perttunen }; 3075425fb15SMikko Perttunen 3085425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 309d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3105425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 3115425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 3125425fb15SMikko Perttunen #address-cells = <1>; 3135425fb15SMikko Perttunen #size-cells = <0>; 3145425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 3155425fb15SMikko Perttunen clock-names = "div-clk"; 3165425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 3175425fb15SMikko Perttunen reset-names = "i2c"; 3185425fb15SMikko Perttunen status = "disabled"; 3195425fb15SMikko Perttunen }; 3205425fb15SMikko Perttunen 3215425fb15SMikko Perttunen /* shares pads with dpaux1 */ 3225425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 323d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3245425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 3255425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 3265425fb15SMikko Perttunen #address-cells = <1>; 3275425fb15SMikko Perttunen #size-cells = <0>; 3285425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 3295425fb15SMikko Perttunen clock-names = "div-clk"; 3305425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 3315425fb15SMikko Perttunen reset-names = "i2c"; 3325425fb15SMikko Perttunen status = "disabled"; 3335425fb15SMikko Perttunen }; 3345425fb15SMikko Perttunen 3355425fb15SMikko Perttunen /* shares pads with dpaux0 */ 3365425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 337d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3385425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 3395425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3405425fb15SMikko Perttunen #address-cells = <1>; 3415425fb15SMikko Perttunen #size-cells = <0>; 3425425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 3435425fb15SMikko Perttunen clock-names = "div-clk"; 3445425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 3455425fb15SMikko Perttunen reset-names = "i2c"; 3465425fb15SMikko Perttunen status = "disabled"; 3475425fb15SMikko Perttunen }; 3485425fb15SMikko Perttunen 3495425fb15SMikko Perttunen gen7_i2c: i2c@31c0000 { 350d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3515425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 3525425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 3535425fb15SMikko Perttunen #address-cells = <1>; 3545425fb15SMikko Perttunen #size-cells = <0>; 3555425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 3565425fb15SMikko Perttunen clock-names = "div-clk"; 3575425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 3585425fb15SMikko Perttunen reset-names = "i2c"; 3595425fb15SMikko Perttunen status = "disabled"; 3605425fb15SMikko Perttunen }; 3615425fb15SMikko Perttunen 3625425fb15SMikko Perttunen gen9_i2c: i2c@31e0000 { 363d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3645425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 3655425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3665425fb15SMikko Perttunen #address-cells = <1>; 3675425fb15SMikko Perttunen #size-cells = <0>; 3685425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 3695425fb15SMikko Perttunen clock-names = "div-clk"; 3705425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 3715425fb15SMikko Perttunen reset-names = "i2c"; 3725425fb15SMikko Perttunen status = "disabled"; 3735425fb15SMikko Perttunen }; 3745425fb15SMikko Perttunen 3756a574ec7SThierry Reding pwm1: pwm@3280000 { 3766a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3776a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3786a574ec7SThierry Reding reg = <0x3280000 0x10000>; 3796a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 3806a574ec7SThierry Reding clock-names = "pwm"; 3816a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 3826a574ec7SThierry Reding reset-names = "pwm"; 3836a574ec7SThierry Reding status = "disabled"; 3846a574ec7SThierry Reding #pwm-cells = <2>; 3856a574ec7SThierry Reding }; 3866a574ec7SThierry Reding 3876a574ec7SThierry Reding pwm2: pwm@3290000 { 3886a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3896a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3906a574ec7SThierry Reding reg = <0x3290000 0x10000>; 3916a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 3926a574ec7SThierry Reding clock-names = "pwm"; 3936a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 3946a574ec7SThierry Reding reset-names = "pwm"; 3956a574ec7SThierry Reding status = "disabled"; 3966a574ec7SThierry Reding #pwm-cells = <2>; 3976a574ec7SThierry Reding }; 3986a574ec7SThierry Reding 3996a574ec7SThierry Reding pwm3: pwm@32a0000 { 4006a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4016a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4026a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 4036a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 4046a574ec7SThierry Reding clock-names = "pwm"; 4056a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 4066a574ec7SThierry Reding reset-names = "pwm"; 4076a574ec7SThierry Reding status = "disabled"; 4086a574ec7SThierry Reding #pwm-cells = <2>; 4096a574ec7SThierry Reding }; 4106a574ec7SThierry Reding 4116a574ec7SThierry Reding pwm5: pwm@32c0000 { 4126a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4136a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4146a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 4156a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 4166a574ec7SThierry Reding clock-names = "pwm"; 4176a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 4186a574ec7SThierry Reding reset-names = "pwm"; 4196a574ec7SThierry Reding status = "disabled"; 4206a574ec7SThierry Reding #pwm-cells = <2>; 4216a574ec7SThierry Reding }; 4226a574ec7SThierry Reding 4236a574ec7SThierry Reding pwm6: pwm@32d0000 { 4246a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4256a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4266a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 4276a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 4286a574ec7SThierry Reding clock-names = "pwm"; 4296a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 4306a574ec7SThierry Reding reset-names = "pwm"; 4316a574ec7SThierry Reding status = "disabled"; 4326a574ec7SThierry Reding #pwm-cells = <2>; 4336a574ec7SThierry Reding }; 4346a574ec7SThierry Reding 4356a574ec7SThierry Reding pwm7: pwm@32e0000 { 4366a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4376a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4386a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 4396a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 4406a574ec7SThierry Reding clock-names = "pwm"; 4416a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 4426a574ec7SThierry Reding reset-names = "pwm"; 4436a574ec7SThierry Reding status = "disabled"; 4446a574ec7SThierry Reding #pwm-cells = <2>; 4456a574ec7SThierry Reding }; 4466a574ec7SThierry Reding 4476a574ec7SThierry Reding pwm8: pwm@32f0000 { 4486a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4496a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4506a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 4516a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 4526a574ec7SThierry Reding clock-names = "pwm"; 4536a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 4546a574ec7SThierry Reding reset-names = "pwm"; 4556a574ec7SThierry Reding status = "disabled"; 4566a574ec7SThierry Reding #pwm-cells = <2>; 4576a574ec7SThierry Reding }; 4586a574ec7SThierry Reding 45967bb17f6SThierry Reding sdmmc1: mmc@3400000 { 4602c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 4615425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 4625425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 463c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 464c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 465c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 4665425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 4675425fb15SMikko Perttunen reset-names = "sdhci"; 468d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 469d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 470d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 4714e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 4724e0f1229SSowjanya Komatineni <0x07>; 4734e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 4744e0f1229SSowjanya Komatineni <0x07>; 4754e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 4764e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 4774e0f1229SSowjanya Komatineni <0x07>; 4784e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 4794e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 4804e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 4814e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 4825425fb15SMikko Perttunen status = "disabled"; 4835425fb15SMikko Perttunen }; 4845425fb15SMikko Perttunen 48567bb17f6SThierry Reding sdmmc3: mmc@3440000 { 4862c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 4875425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 4885425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 489c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 490c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 491c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 4925425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 4935425fb15SMikko Perttunen reset-names = "sdhci"; 494d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 495d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 496d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 4974e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 4984e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 4994e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 5004e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 5014e0f1229SSowjanya Komatineni <0x07>; 5024e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 5034e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 5044e0f1229SSowjanya Komatineni <0x07>; 5054e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 5064e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 5074e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 5084e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 5095425fb15SMikko Perttunen status = "disabled"; 5105425fb15SMikko Perttunen }; 5115425fb15SMikko Perttunen 51267bb17f6SThierry Reding sdmmc4: mmc@3460000 { 5132c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 5145425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 5155425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 516c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 517c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 518c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 519351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 520351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 521351648d0SSowjanya Komatineni assigned-clock-parents = 522351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 5235425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 5245425fb15SMikko Perttunen reset-names = "sdhci"; 525d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 526d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 527d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 5284e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 5294e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 5304e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 5314e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 5324e0f1229SSowjanya Komatineni <0x0a>; 5334e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 5344e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 5354e0f1229SSowjanya Komatineni <0x0a>; 5364e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 5374e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 5384e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 539dfd3cb6fSSowjanya Komatineni supports-cqe; 5405425fb15SMikko Perttunen status = "disabled"; 5415425fb15SMikko Perttunen }; 5425425fb15SMikko Perttunen 5434878cc0cSSameer Pujar hda@3510000 { 5444878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 5454878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 5464878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 5474878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 5484878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 5494878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 5504878cc0cSSameer Pujar clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 5514878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 5524878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 5534878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 5544878cc0cSSameer Pujar reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 5554878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 556d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 557d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 558d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 5594878cc0cSSameer Pujar status = "disabled"; 5604878cc0cSSameer Pujar }; 5614878cc0cSSameer Pujar 562fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 563fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 564fab7a039SJC Kuo reg = <0x03520000 0x1000>, 565fab7a039SJC Kuo <0x03540000 0x1000>; 566fab7a039SJC Kuo reg-names = "padctl", "ao"; 567fab7a039SJC Kuo 568fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 569fab7a039SJC Kuo reset-names = "padctl"; 570fab7a039SJC Kuo 571fab7a039SJC Kuo status = "disabled"; 572fab7a039SJC Kuo 573fab7a039SJC Kuo pads { 574fab7a039SJC Kuo usb2 { 575fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 576fab7a039SJC Kuo clock-names = "trk"; 577fab7a039SJC Kuo 578fab7a039SJC Kuo lanes { 579fab7a039SJC Kuo usb2-0 { 580fab7a039SJC Kuo nvidia,function = "xusb"; 581fab7a039SJC Kuo status = "disabled"; 582fab7a039SJC Kuo #phy-cells = <0>; 583fab7a039SJC Kuo }; 584fab7a039SJC Kuo 585fab7a039SJC Kuo usb2-1 { 586fab7a039SJC Kuo nvidia,function = "xusb"; 587fab7a039SJC Kuo status = "disabled"; 588fab7a039SJC Kuo #phy-cells = <0>; 589fab7a039SJC Kuo }; 590fab7a039SJC Kuo 591fab7a039SJC Kuo usb2-2 { 592fab7a039SJC Kuo nvidia,function = "xusb"; 593fab7a039SJC Kuo status = "disabled"; 594fab7a039SJC Kuo #phy-cells = <0>; 595fab7a039SJC Kuo }; 596fab7a039SJC Kuo 597fab7a039SJC Kuo usb2-3 { 598fab7a039SJC Kuo nvidia,function = "xusb"; 599fab7a039SJC Kuo status = "disabled"; 600fab7a039SJC Kuo #phy-cells = <0>; 601fab7a039SJC Kuo }; 602fab7a039SJC Kuo }; 603fab7a039SJC Kuo }; 604fab7a039SJC Kuo 605fab7a039SJC Kuo usb3 { 606fab7a039SJC Kuo lanes { 607fab7a039SJC Kuo usb3-0 { 608fab7a039SJC Kuo nvidia,function = "xusb"; 609fab7a039SJC Kuo status = "disabled"; 610fab7a039SJC Kuo #phy-cells = <0>; 611fab7a039SJC Kuo }; 612fab7a039SJC Kuo 613fab7a039SJC Kuo usb3-1 { 614fab7a039SJC Kuo nvidia,function = "xusb"; 615fab7a039SJC Kuo status = "disabled"; 616fab7a039SJC Kuo #phy-cells = <0>; 617fab7a039SJC Kuo }; 618fab7a039SJC Kuo 619fab7a039SJC Kuo usb3-2 { 620fab7a039SJC Kuo nvidia,function = "xusb"; 621fab7a039SJC Kuo status = "disabled"; 622fab7a039SJC Kuo #phy-cells = <0>; 623fab7a039SJC Kuo }; 624fab7a039SJC Kuo 625fab7a039SJC Kuo usb3-3 { 626fab7a039SJC Kuo nvidia,function = "xusb"; 627fab7a039SJC Kuo status = "disabled"; 628fab7a039SJC Kuo #phy-cells = <0>; 629fab7a039SJC Kuo }; 630fab7a039SJC Kuo }; 631fab7a039SJC Kuo }; 632fab7a039SJC Kuo }; 633fab7a039SJC Kuo 634fab7a039SJC Kuo ports { 635fab7a039SJC Kuo usb2-0 { 636fab7a039SJC Kuo status = "disabled"; 637fab7a039SJC Kuo }; 638fab7a039SJC Kuo 639fab7a039SJC Kuo usb2-1 { 640fab7a039SJC Kuo status = "disabled"; 641fab7a039SJC Kuo }; 642fab7a039SJC Kuo 643fab7a039SJC Kuo usb2-2 { 644fab7a039SJC Kuo status = "disabled"; 645fab7a039SJC Kuo }; 646fab7a039SJC Kuo 647fab7a039SJC Kuo usb2-3 { 648fab7a039SJC Kuo status = "disabled"; 649fab7a039SJC Kuo }; 650fab7a039SJC Kuo 651fab7a039SJC Kuo usb3-0 { 652fab7a039SJC Kuo status = "disabled"; 653fab7a039SJC Kuo }; 654fab7a039SJC Kuo 655fab7a039SJC Kuo usb3-1 { 656fab7a039SJC Kuo status = "disabled"; 657fab7a039SJC Kuo }; 658fab7a039SJC Kuo 659fab7a039SJC Kuo usb3-2 { 660fab7a039SJC Kuo status = "disabled"; 661fab7a039SJC Kuo }; 662fab7a039SJC Kuo 663fab7a039SJC Kuo usb3-3 { 664fab7a039SJC Kuo status = "disabled"; 665fab7a039SJC Kuo }; 666fab7a039SJC Kuo }; 667fab7a039SJC Kuo }; 668fab7a039SJC Kuo 669bc8788b2SNagarjuna Kristam usb@3550000 { 670bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 671bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 672bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 673bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 674bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 675bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 676bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 677bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 678bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 679bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 680bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 681bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 682bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 683bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 684bc8788b2SNagarjuna Kristam status = "disabled"; 685bc8788b2SNagarjuna Kristam }; 686bc8788b2SNagarjuna Kristam 687fab7a039SJC Kuo usb@3610000 { 688fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 689fab7a039SJC Kuo reg = <0x03610000 0x40000>, 690fab7a039SJC Kuo <0x03600000 0x10000>; 691fab7a039SJC Kuo reg-names = "hcd", "fpci"; 692fab7a039SJC Kuo 693fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 694a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 695fab7a039SJC Kuo 696fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 697fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 698fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 699fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 700fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 701fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 702fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 703fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 704fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 705fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 706fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 707fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 708fab7a039SJC Kuo "pll_e"; 709fab7a039SJC Kuo 710fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 711fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 712fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 713fab7a039SJC Kuo 714fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 715fab7a039SJC Kuo status = "disabled"; 716fab7a039SJC Kuo }; 717fab7a039SJC Kuo 71809903c5eSJC Kuo fuse@3820000 { 71909903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 72009903c5eSJC Kuo reg = <0x03820000 0x10000>; 72109903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 72209903c5eSJC Kuo clock-names = "fuse"; 72309903c5eSJC Kuo }; 72409903c5eSJC Kuo 7255425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 7265425fb15SMikko Perttunen compatible = "arm,gic-400"; 7275425fb15SMikko Perttunen #interrupt-cells = <3>; 7285425fb15SMikko Perttunen interrupt-controller; 7295425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 7305425fb15SMikko Perttunen <0x03882000 0x2000>, 7315425fb15SMikko Perttunen <0x03884000 0x2000>, 7325425fb15SMikko Perttunen <0x03886000 0x2000>; 7335425fb15SMikko Perttunen interrupts = <GIC_PPI 9 7345425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 7355425fb15SMikko Perttunen interrupt-parent = <&gic>; 7365425fb15SMikko Perttunen }; 7375425fb15SMikko Perttunen 738badb80beSThierry Reding cec@3960000 { 739badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 740badb80beSThierry Reding reg = <0x03960000 0x10000>; 741badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 742badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 743badb80beSThierry Reding clock-names = "cec"; 744badb80beSThierry Reding status = "disabled"; 745badb80beSThierry Reding }; 746badb80beSThierry Reding 7475425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 748a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 7495425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 750a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 751a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 752a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 753a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 754a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 755a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 756a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 757a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 758a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 759a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 760a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 761a38570c2SMikko Perttunen "shared7"; 762a38570c2SMikko Perttunen #mbox-cells = <2>; 763a38570c2SMikko Perttunen }; 764a38570c2SMikko Perttunen 7652602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 7662602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7672602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 7682602c32fSVidya Sagar reg-names = "ctl"; 7692602c32fSVidya Sagar 7702602c32fSVidya Sagar #phy-cells = <0>; 7712602c32fSVidya Sagar }; 7722602c32fSVidya Sagar 7732602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 7742602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7752602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 7762602c32fSVidya Sagar reg-names = "ctl"; 7772602c32fSVidya Sagar 7782602c32fSVidya Sagar #phy-cells = <0>; 7792602c32fSVidya Sagar }; 7802602c32fSVidya Sagar 7812602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 7822602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7832602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 7842602c32fSVidya Sagar reg-names = "ctl"; 7852602c32fSVidya Sagar 7862602c32fSVidya Sagar #phy-cells = <0>; 7872602c32fSVidya Sagar }; 7882602c32fSVidya Sagar 7892602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 7902602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7912602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 7922602c32fSVidya Sagar reg-names = "ctl"; 7932602c32fSVidya Sagar 7942602c32fSVidya Sagar #phy-cells = <0>; 7952602c32fSVidya Sagar }; 7962602c32fSVidya Sagar 7972602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 7982602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7992602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 8002602c32fSVidya Sagar reg-names = "ctl"; 8012602c32fSVidya Sagar 8022602c32fSVidya Sagar #phy-cells = <0>; 8032602c32fSVidya Sagar }; 8042602c32fSVidya Sagar 8052602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 8062602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8072602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 8082602c32fSVidya Sagar reg-names = "ctl"; 8092602c32fSVidya Sagar 8102602c32fSVidya Sagar #phy-cells = <0>; 8112602c32fSVidya Sagar }; 8122602c32fSVidya Sagar 8132602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 8142602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8152602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 8162602c32fSVidya Sagar reg-names = "ctl"; 8172602c32fSVidya Sagar 8182602c32fSVidya Sagar #phy-cells = <0>; 8192602c32fSVidya Sagar }; 8202602c32fSVidya Sagar 8212602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 8222602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8232602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 8242602c32fSVidya Sagar reg-names = "ctl"; 8252602c32fSVidya Sagar 8262602c32fSVidya Sagar #phy-cells = <0>; 8272602c32fSVidya Sagar }; 8282602c32fSVidya Sagar 8292602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 8302602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8312602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 8322602c32fSVidya Sagar reg-names = "ctl"; 8332602c32fSVidya Sagar 8342602c32fSVidya Sagar #phy-cells = <0>; 8352602c32fSVidya Sagar }; 8362602c32fSVidya Sagar 8372602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 8382602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8392602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 8402602c32fSVidya Sagar reg-names = "ctl"; 8412602c32fSVidya Sagar 8422602c32fSVidya Sagar #phy-cells = <0>; 8432602c32fSVidya Sagar }; 8442602c32fSVidya Sagar 8452602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 8462602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8472602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 8482602c32fSVidya Sagar reg-names = "ctl"; 8492602c32fSVidya Sagar 8502602c32fSVidya Sagar #phy-cells = <0>; 8512602c32fSVidya Sagar }; 8522602c32fSVidya Sagar 8532602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 8542602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8552602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 8562602c32fSVidya Sagar reg-names = "ctl"; 8572602c32fSVidya Sagar 8582602c32fSVidya Sagar #phy-cells = <0>; 8592602c32fSVidya Sagar }; 8602602c32fSVidya Sagar 8612602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 8622602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8632602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 8642602c32fSVidya Sagar reg-names = "ctl"; 8652602c32fSVidya Sagar 8662602c32fSVidya Sagar #phy-cells = <0>; 8672602c32fSVidya Sagar }; 8682602c32fSVidya Sagar 8692602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 8702602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8712602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 8722602c32fSVidya Sagar reg-names = "ctl"; 8732602c32fSVidya Sagar 8742602c32fSVidya Sagar #phy-cells = <0>; 8752602c32fSVidya Sagar }; 8762602c32fSVidya Sagar 8772602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 8782602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8792602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 8802602c32fSVidya Sagar reg-names = "ctl"; 8812602c32fSVidya Sagar 8822602c32fSVidya Sagar #phy-cells = <0>; 8832602c32fSVidya Sagar }; 8842602c32fSVidya Sagar 8852602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 8862602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8872602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 8882602c32fSVidya Sagar reg-names = "ctl"; 8892602c32fSVidya Sagar 8902602c32fSVidya Sagar #phy-cells = <0>; 8912602c32fSVidya Sagar }; 8922602c32fSVidya Sagar 8932602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 8942602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8952602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 8962602c32fSVidya Sagar reg-names = "ctl"; 8972602c32fSVidya Sagar 8982602c32fSVidya Sagar #phy-cells = <0>; 8992602c32fSVidya Sagar }; 9002602c32fSVidya Sagar 9012602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 9022602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 9032602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 9042602c32fSVidya Sagar reg-names = "ctl"; 9052602c32fSVidya Sagar 9062602c32fSVidya Sagar #phy-cells = <0>; 9072602c32fSVidya Sagar }; 9082602c32fSVidya Sagar 9092602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 9102602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 9112602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 9122602c32fSVidya Sagar reg-names = "ctl"; 9132602c32fSVidya Sagar 9142602c32fSVidya Sagar #phy-cells = <0>; 9152602c32fSVidya Sagar }; 9162602c32fSVidya Sagar 9172602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 9182602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 9192602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 9202602c32fSVidya Sagar reg-names = "ctl"; 9212602c32fSVidya Sagar 9222602c32fSVidya Sagar #phy-cells = <0>; 9232602c32fSVidya Sagar }; 9242602c32fSVidya Sagar 925a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 926a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 927a38570c2SMikko Perttunen reg = <0x0c150000 0xa0000>; 928a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 929a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 930a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 931a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 932a38570c2SMikko Perttunen /* 933a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 934a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 935a38570c2SMikko Perttunen */ 936a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 9375425fb15SMikko Perttunen #mbox-cells = <2>; 9385425fb15SMikko Perttunen }; 9395425fb15SMikko Perttunen 9405425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 941d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 9425425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 9435425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 9445425fb15SMikko Perttunen #address-cells = <1>; 9455425fb15SMikko Perttunen #size-cells = <0>; 9465425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 9475425fb15SMikko Perttunen clock-names = "div-clk"; 9485425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 9495425fb15SMikko Perttunen reset-names = "i2c"; 9505425fb15SMikko Perttunen status = "disabled"; 9515425fb15SMikko Perttunen }; 9525425fb15SMikko Perttunen 9535425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 954d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 9555425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 9565425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 9575425fb15SMikko Perttunen #address-cells = <1>; 9585425fb15SMikko Perttunen #size-cells = <0>; 9595425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 9605425fb15SMikko Perttunen clock-names = "div-clk"; 9615425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 9625425fb15SMikko Perttunen reset-names = "i2c"; 9635425fb15SMikko Perttunen status = "disabled"; 9645425fb15SMikko Perttunen }; 9655425fb15SMikko Perttunen 9665425fb15SMikko Perttunen uartc: serial@c280000 { 9675425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 9685425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 9695425fb15SMikko Perttunen reg-shift = <2>; 9705425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 9715425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 9725425fb15SMikko Perttunen clock-names = "serial"; 9735425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 9745425fb15SMikko Perttunen reset-names = "serial"; 9755425fb15SMikko Perttunen status = "disabled"; 9765425fb15SMikko Perttunen }; 9775425fb15SMikko Perttunen 9785425fb15SMikko Perttunen uartg: serial@c290000 { 9795425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 9805425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 9815425fb15SMikko Perttunen reg-shift = <2>; 9825425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 9835425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 9845425fb15SMikko Perttunen clock-names = "serial"; 9855425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 9865425fb15SMikko Perttunen reset-names = "serial"; 9875425fb15SMikko Perttunen status = "disabled"; 9885425fb15SMikko Perttunen }; 9895425fb15SMikko Perttunen 99037e5a31dSThierry Reding rtc: rtc@c2a0000 { 99137e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 99237e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 99337e5a31dSThierry Reding interrupt-parent = <&pmc>; 99437e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 99537e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 99637e5a31dSThierry Reding clock-names = "rtc"; 99737e5a31dSThierry Reding status = "disabled"; 99837e5a31dSThierry Reding }; 99937e5a31dSThierry Reding 10004d286331SThierry Reding gpio_aon: gpio@c2f0000 { 10014d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 10024d286331SThierry Reding reg-names = "security", "gpio"; 10034d286331SThierry Reding reg = <0xc2f0000 0x1000>, 10044d286331SThierry Reding <0xc2f1000 0x1000>; 100575b5608aSThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 10064d286331SThierry Reding gpio-controller; 10074d286331SThierry Reding #gpio-cells = <2>; 10084d286331SThierry Reding interrupt-controller; 10094d286331SThierry Reding #interrupt-cells = <2>; 10104d286331SThierry Reding }; 10114d286331SThierry Reding 10126a574ec7SThierry Reding pwm4: pwm@c340000 { 10136a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10146a574ec7SThierry Reding "nvidia,tegra186-pwm"; 10156a574ec7SThierry Reding reg = <0xc340000 0x10000>; 10166a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 10176a574ec7SThierry Reding clock-names = "pwm"; 10186a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 10196a574ec7SThierry Reding reset-names = "pwm"; 10206a574ec7SThierry Reding status = "disabled"; 10216a574ec7SThierry Reding #pwm-cells = <2>; 10226a574ec7SThierry Reding }; 10236a574ec7SThierry Reding 102438ecf1e5SThierry Reding pmc: pmc@c360000 { 10255425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 10265425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 10275425fb15SMikko Perttunen <0x0c370000 0x10000>, 10285425fb15SMikko Perttunen <0x0c380000 0x10000>, 10295425fb15SMikko Perttunen <0x0c390000 0x10000>, 10305425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 10315425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 103238ecf1e5SThierry Reding 103338ecf1e5SThierry Reding #interrupt-cells = <2>; 103438ecf1e5SThierry Reding interrupt-controller; 10355425fb15SMikko Perttunen }; 10363db6d3baSThierry Reding 10373db6d3baSThierry Reding host1x@13e00000 { 1038ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 10393db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 10403db6d3baSThierry Reding <0x13e10000 0x10000>; 10413db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 10423db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 10433db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1044052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 10453db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 10463db6d3baSThierry Reding clock-names = "host1x"; 10473db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 10483db6d3baSThierry Reding reset-names = "host1x"; 10493db6d3baSThierry Reding 10503db6d3baSThierry Reding #address-cells = <1>; 10513db6d3baSThierry Reding #size-cells = <1>; 10523db6d3baSThierry Reding 10533db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 1054d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1055d5237c7cSThierry Reding interconnect-names = "dma-mem"; 10563db6d3baSThierry Reding 10573db6d3baSThierry Reding display-hub@15200000 { 1058aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1059611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 10603db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 10613db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 10623db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 10633db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 10643db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 10653db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 10663db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 10673db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 10683db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 10693db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 10703db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 10713db6d3baSThierry Reding clock-names = "disp", "hub"; 10723db6d3baSThierry Reding status = "disabled"; 10733db6d3baSThierry Reding 10743db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 10753db6d3baSThierry Reding 10763db6d3baSThierry Reding #address-cells = <1>; 10773db6d3baSThierry Reding #size-cells = <1>; 10783db6d3baSThierry Reding 10793db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 10803db6d3baSThierry Reding 10813db6d3baSThierry Reding display@15200000 { 10823db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 10833db6d3baSThierry Reding reg = <0x15200000 0x10000>; 10843db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 10853db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 10863db6d3baSThierry Reding clock-names = "dc"; 10873db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 10883db6d3baSThierry Reding reset-names = "dc"; 10893db6d3baSThierry Reding 10903db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1091d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1092d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1093d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 10943db6d3baSThierry Reding 10953db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 10963db6d3baSThierry Reding nvidia,head = <0>; 10973db6d3baSThierry Reding }; 10983db6d3baSThierry Reding 10993db6d3baSThierry Reding display@15210000 { 11003db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 11013db6d3baSThierry Reding reg = <0x15210000 0x10000>; 11023db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 11033db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 11043db6d3baSThierry Reding clock-names = "dc"; 11053db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 11063db6d3baSThierry Reding reset-names = "dc"; 11073db6d3baSThierry Reding 11083db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1109d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1110d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1111d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 11123db6d3baSThierry Reding 11133db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 11143db6d3baSThierry Reding nvidia,head = <1>; 11153db6d3baSThierry Reding }; 11163db6d3baSThierry Reding 11173db6d3baSThierry Reding display@15220000 { 11183db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 11193db6d3baSThierry Reding reg = <0x15220000 0x10000>; 11203db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 11213db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 11223db6d3baSThierry Reding clock-names = "dc"; 11233db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 11243db6d3baSThierry Reding reset-names = "dc"; 11253db6d3baSThierry Reding 11263db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1127d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1128d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1129d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 11303db6d3baSThierry Reding 11313db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 11323db6d3baSThierry Reding nvidia,head = <2>; 11333db6d3baSThierry Reding }; 11343db6d3baSThierry Reding 11353db6d3baSThierry Reding display@15230000 { 11363db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 11373db6d3baSThierry Reding reg = <0x15230000 0x10000>; 11383db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 11393db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 11403db6d3baSThierry Reding clock-names = "dc"; 11413db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 11423db6d3baSThierry Reding reset-names = "dc"; 11433db6d3baSThierry Reding 11443db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1145d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1146d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1147d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 11483db6d3baSThierry Reding 11493db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 11503db6d3baSThierry Reding nvidia,head = <3>; 11513db6d3baSThierry Reding }; 11523db6d3baSThierry Reding }; 11533db6d3baSThierry Reding 11548d424ec2SThierry Reding vic@15340000 { 11558d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 11568d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 11578d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 11588d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 11598d424ec2SThierry Reding clock-names = "vic"; 11608d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 11618d424ec2SThierry Reding reset-names = "vic"; 11628d424ec2SThierry Reding 11638d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1164d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1165d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1166d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 11678d424ec2SThierry Reding }; 11688d424ec2SThierry Reding 11693db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 11703db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 11713db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 11723db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 11733db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 11743db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 11753db6d3baSThierry Reding clock-names = "dpaux", "parent"; 11763db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 11773db6d3baSThierry Reding reset-names = "dpaux"; 11783db6d3baSThierry Reding status = "disabled"; 11793db6d3baSThierry Reding 11803db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 11813db6d3baSThierry Reding 11823db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 11833db6d3baSThierry Reding groups = "dpaux-io"; 11843db6d3baSThierry Reding function = "aux"; 11853db6d3baSThierry Reding }; 11863db6d3baSThierry Reding 11873db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 11883db6d3baSThierry Reding groups = "dpaux-io"; 11893db6d3baSThierry Reding function = "i2c"; 11903db6d3baSThierry Reding }; 11913db6d3baSThierry Reding 11923db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 11933db6d3baSThierry Reding groups = "dpaux-io"; 11943db6d3baSThierry Reding function = "off"; 11953db6d3baSThierry Reding }; 11963db6d3baSThierry Reding 11973db6d3baSThierry Reding i2c-bus { 11983db6d3baSThierry Reding #address-cells = <1>; 11993db6d3baSThierry Reding #size-cells = <0>; 12003db6d3baSThierry Reding }; 12013db6d3baSThierry Reding }; 12023db6d3baSThierry Reding 12033db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 12043db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 12053db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 12063db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 12073db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 12083db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 12093db6d3baSThierry Reding clock-names = "dpaux", "parent"; 12103db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 12113db6d3baSThierry Reding reset-names = "dpaux"; 12123db6d3baSThierry Reding status = "disabled"; 12133db6d3baSThierry Reding 12143db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 12153db6d3baSThierry Reding 12163db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 12173db6d3baSThierry Reding groups = "dpaux-io"; 12183db6d3baSThierry Reding function = "aux"; 12193db6d3baSThierry Reding }; 12203db6d3baSThierry Reding 12213db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 12223db6d3baSThierry Reding groups = "dpaux-io"; 12233db6d3baSThierry Reding function = "i2c"; 12243db6d3baSThierry Reding }; 12253db6d3baSThierry Reding 12263db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 12273db6d3baSThierry Reding groups = "dpaux-io"; 12283db6d3baSThierry Reding function = "off"; 12293db6d3baSThierry Reding }; 12303db6d3baSThierry Reding 12313db6d3baSThierry Reding i2c-bus { 12323db6d3baSThierry Reding #address-cells = <1>; 12333db6d3baSThierry Reding #size-cells = <0>; 12343db6d3baSThierry Reding }; 12353db6d3baSThierry Reding }; 12363db6d3baSThierry Reding 12373db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 12383db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 12393db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 12403db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 12413db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 12423db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 12433db6d3baSThierry Reding clock-names = "dpaux", "parent"; 12443db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 12453db6d3baSThierry Reding reset-names = "dpaux"; 12463db6d3baSThierry Reding status = "disabled"; 12473db6d3baSThierry Reding 12483db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 12493db6d3baSThierry Reding 12503db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 12513db6d3baSThierry Reding groups = "dpaux-io"; 12523db6d3baSThierry Reding function = "aux"; 12533db6d3baSThierry Reding }; 12543db6d3baSThierry Reding 12553db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 12563db6d3baSThierry Reding groups = "dpaux-io"; 12573db6d3baSThierry Reding function = "i2c"; 12583db6d3baSThierry Reding }; 12593db6d3baSThierry Reding 12603db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 12613db6d3baSThierry Reding groups = "dpaux-io"; 12623db6d3baSThierry Reding function = "off"; 12633db6d3baSThierry Reding }; 12643db6d3baSThierry Reding 12653db6d3baSThierry Reding i2c-bus { 12663db6d3baSThierry Reding #address-cells = <1>; 12673db6d3baSThierry Reding #size-cells = <0>; 12683db6d3baSThierry Reding }; 12693db6d3baSThierry Reding }; 12703db6d3baSThierry Reding 12713db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 12723db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 12733db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 12743db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 12753db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 12763db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 12773db6d3baSThierry Reding clock-names = "dpaux", "parent"; 12783db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 12793db6d3baSThierry Reding reset-names = "dpaux"; 12803db6d3baSThierry Reding status = "disabled"; 12813db6d3baSThierry Reding 12823db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 12833db6d3baSThierry Reding 12843db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 12853db6d3baSThierry Reding groups = "dpaux-io"; 12863db6d3baSThierry Reding function = "aux"; 12873db6d3baSThierry Reding }; 12883db6d3baSThierry Reding 12893db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 12903db6d3baSThierry Reding groups = "dpaux-io"; 12913db6d3baSThierry Reding function = "i2c"; 12923db6d3baSThierry Reding }; 12933db6d3baSThierry Reding 12943db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 12953db6d3baSThierry Reding groups = "dpaux-io"; 12963db6d3baSThierry Reding function = "off"; 12973db6d3baSThierry Reding }; 12983db6d3baSThierry Reding 12993db6d3baSThierry Reding i2c-bus { 13003db6d3baSThierry Reding #address-cells = <1>; 13013db6d3baSThierry Reding #size-cells = <0>; 13023db6d3baSThierry Reding }; 13033db6d3baSThierry Reding }; 13043db6d3baSThierry Reding 13053db6d3baSThierry Reding sor0: sor@15b00000 { 13063db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 13073db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 13083db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 13093db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 13103db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 13113db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 13123db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 13133db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 13143db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 13153db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 13163db6d3baSThierry Reding "pad"; 13173db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 13183db6d3baSThierry Reding reset-names = "sor"; 13193db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 13203db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 13213db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 13223db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 13233db6d3baSThierry Reding status = "disabled"; 13243db6d3baSThierry Reding 13253db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 13263db6d3baSThierry Reding nvidia,interface = <0>; 13273db6d3baSThierry Reding }; 13283db6d3baSThierry Reding 13293db6d3baSThierry Reding sor1: sor@15b40000 { 13303db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 1331939e7430SThierry Reding reg = <0x15b40000 0x40000>; 13323db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 13333db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 13343db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 13353db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 13363db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 13373db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 13383db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 13393db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 13403db6d3baSThierry Reding "pad"; 13413db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 13423db6d3baSThierry Reding reset-names = "sor"; 13433db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 13443db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 13453db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 13463db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 13473db6d3baSThierry Reding status = "disabled"; 13483db6d3baSThierry Reding 13493db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 13503db6d3baSThierry Reding nvidia,interface = <1>; 13513db6d3baSThierry Reding }; 13523db6d3baSThierry Reding 13533db6d3baSThierry Reding sor2: sor@15b80000 { 13543db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 13553db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 13563db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 13573db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 13583db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 13593db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 13603db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 13613db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 13623db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 13633db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 13643db6d3baSThierry Reding "pad"; 13653db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 13663db6d3baSThierry Reding reset-names = "sor"; 13673db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 13683db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 13693db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 13703db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 13713db6d3baSThierry Reding status = "disabled"; 13723db6d3baSThierry Reding 13733db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 13743db6d3baSThierry Reding nvidia,interface = <2>; 13753db6d3baSThierry Reding }; 13763db6d3baSThierry Reding 13773db6d3baSThierry Reding sor3: sor@15bc0000 { 13783db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 13793db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 13803db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 13813db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 13823db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 13833db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 13843db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 13853db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 13863db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 13873db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 13883db6d3baSThierry Reding "pad"; 13893db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 13903db6d3baSThierry Reding reset-names = "sor"; 13913db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 13923db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 13933db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 13943db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 13953db6d3baSThierry Reding status = "disabled"; 13963db6d3baSThierry Reding 13973db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 13983db6d3baSThierry Reding nvidia,interface = <3>; 13993db6d3baSThierry Reding }; 14003db6d3baSThierry Reding }; 14010f134e39SThierry Reding 14020f134e39SThierry Reding gpu@17000000 { 14030f134e39SThierry Reding compatible = "nvidia,gv11b"; 14040f134e39SThierry Reding reg = <0x17000000 0x10000000>, 14050f134e39SThierry Reding <0x18000000 0x10000000>; 14060f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 14070f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 14080f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 14090f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 14100f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 14110f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 14120f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 14130f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 14140f134e39SThierry Reding reset-names = "gpu"; 14150f134e39SThierry Reding dma-coherent; 14160f134e39SThierry Reding 14170f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 14180f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 14190f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 14200f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 14210f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 14220f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 14230f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 14240f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 14250f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 14260f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 14270f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 14280f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 14290f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 14300f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 14310f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 14320f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 14330f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 14340f134e39SThierry Reding }; 14355425fb15SMikko Perttunen }; 14365425fb15SMikko Perttunen 14372602c32fSVidya Sagar pcie@14100000 { 1438f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 14392602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1440644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1441644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1442644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1443644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 14442602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 14452602c32fSVidya Sagar 14462602c32fSVidya Sagar status = "disabled"; 14472602c32fSVidya Sagar 14482602c32fSVidya Sagar #address-cells = <3>; 14492602c32fSVidya Sagar #size-cells = <2>; 14502602c32fSVidya Sagar device_type = "pci"; 14512602c32fSVidya Sagar num-lanes = <1>; 14522602c32fSVidya Sagar num-viewport = <8>; 14532602c32fSVidya Sagar linux,pci-domain = <1>; 14542602c32fSVidya Sagar 14552602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 14562602c32fSVidya Sagar clock-names = "core"; 14572602c32fSVidya Sagar 14582602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 14592602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 14602602c32fSVidya Sagar reset-names = "apb", "core"; 14612602c32fSVidya Sagar 14622602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 14632602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 14642602c32fSVidya Sagar interrupt-names = "intr", "msi"; 14652602c32fSVidya Sagar 14662602c32fSVidya Sagar #interrupt-cells = <1>; 14672602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 14682602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 14692602c32fSVidya Sagar 14702602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 14712602c32fSVidya Sagar 14722602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 14732602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 14742602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 14752602c32fSVidya Sagar 14762602c32fSVidya Sagar bus-range = <0x0 0xff>; 1477d5237c7cSThierry Reding 14788a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 14798a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 14808a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1481d5237c7cSThierry Reding 1482d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1483d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1484d5237c7cSThierry Reding interconnect-names = "read", "write"; 14852602c32fSVidya Sagar }; 14862602c32fSVidya Sagar 14872602c32fSVidya Sagar pcie@14120000 { 1488f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 14892602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1490644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1491644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1492644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1493644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 14942602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 14952602c32fSVidya Sagar 14962602c32fSVidya Sagar status = "disabled"; 14972602c32fSVidya Sagar 14982602c32fSVidya Sagar #address-cells = <3>; 14992602c32fSVidya Sagar #size-cells = <2>; 15002602c32fSVidya Sagar device_type = "pci"; 15012602c32fSVidya Sagar num-lanes = <1>; 15022602c32fSVidya Sagar num-viewport = <8>; 15032602c32fSVidya Sagar linux,pci-domain = <2>; 15042602c32fSVidya Sagar 15052602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 15062602c32fSVidya Sagar clock-names = "core"; 15072602c32fSVidya Sagar 15082602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 15092602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 15102602c32fSVidya Sagar reset-names = "apb", "core"; 15112602c32fSVidya Sagar 15122602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 15132602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 15142602c32fSVidya Sagar interrupt-names = "intr", "msi"; 15152602c32fSVidya Sagar 15162602c32fSVidya Sagar #interrupt-cells = <1>; 15172602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 15182602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 15192602c32fSVidya Sagar 15202602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 15212602c32fSVidya Sagar 15222602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 15232602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 15242602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 15252602c32fSVidya Sagar 15262602c32fSVidya Sagar bus-range = <0x0 0xff>; 1527d5237c7cSThierry Reding 15288a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 15298a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 15308a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1531d5237c7cSThierry Reding 1532d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1533d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1534d5237c7cSThierry Reding interconnect-names = "read", "write"; 15352602c32fSVidya Sagar }; 15362602c32fSVidya Sagar 15372602c32fSVidya Sagar pcie@14140000 { 1538f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 15392602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1540644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1541644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1542644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1543644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 15442602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 15452602c32fSVidya Sagar 15462602c32fSVidya Sagar status = "disabled"; 15472602c32fSVidya Sagar 15482602c32fSVidya Sagar #address-cells = <3>; 15492602c32fSVidya Sagar #size-cells = <2>; 15502602c32fSVidya Sagar device_type = "pci"; 15512602c32fSVidya Sagar num-lanes = <1>; 15522602c32fSVidya Sagar num-viewport = <8>; 15532602c32fSVidya Sagar linux,pci-domain = <3>; 15542602c32fSVidya Sagar 15552602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 15562602c32fSVidya Sagar clock-names = "core"; 15572602c32fSVidya Sagar 15582602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 15592602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 15602602c32fSVidya Sagar reset-names = "apb", "core"; 15612602c32fSVidya Sagar 15622602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 15632602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 15642602c32fSVidya Sagar interrupt-names = "intr", "msi"; 15652602c32fSVidya Sagar 15662602c32fSVidya Sagar #interrupt-cells = <1>; 15672602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 15682602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 15692602c32fSVidya Sagar 15702602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 15712602c32fSVidya Sagar 15722602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 15732602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 15742602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 15752602c32fSVidya Sagar 15762602c32fSVidya Sagar bus-range = <0x0 0xff>; 1577d5237c7cSThierry Reding 15788a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 15798a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 15808a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1581d5237c7cSThierry Reding 1582d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 1583d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 1584d5237c7cSThierry Reding interconnect-names = "read", "write"; 15852602c32fSVidya Sagar }; 15862602c32fSVidya Sagar 15872602c32fSVidya Sagar pcie@14160000 { 1588f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 15892602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1590644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1591644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 1592644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1593644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 15942602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 15952602c32fSVidya Sagar 15962602c32fSVidya Sagar status = "disabled"; 15972602c32fSVidya Sagar 15982602c32fSVidya Sagar #address-cells = <3>; 15992602c32fSVidya Sagar #size-cells = <2>; 16002602c32fSVidya Sagar device_type = "pci"; 16012602c32fSVidya Sagar num-lanes = <4>; 16022602c32fSVidya Sagar num-viewport = <8>; 16032602c32fSVidya Sagar linux,pci-domain = <4>; 16042602c32fSVidya Sagar 16052602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 16062602c32fSVidya Sagar clock-names = "core"; 16072602c32fSVidya Sagar 16082602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 16092602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 16102602c32fSVidya Sagar reset-names = "apb", "core"; 16112602c32fSVidya Sagar 16122602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 16132602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 16142602c32fSVidya Sagar interrupt-names = "intr", "msi"; 16152602c32fSVidya Sagar 16162602c32fSVidya Sagar #interrupt-cells = <1>; 16172602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 16182602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 16192602c32fSVidya Sagar 16202602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 16212602c32fSVidya Sagar 16222602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 16232602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 16242602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 16252602c32fSVidya Sagar 16262602c32fSVidya Sagar bus-range = <0x0 0xff>; 1627d5237c7cSThierry Reding 16288a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 16298a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 16308a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1631d5237c7cSThierry Reding 1632d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 1633d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 1634d5237c7cSThierry Reding interconnect-names = "read", "write"; 16352602c32fSVidya Sagar }; 16362602c32fSVidya Sagar 16372602c32fSVidya Sagar pcie@14180000 { 1638f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 16392602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1640644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1641644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 1642644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1643644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 16442602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 16452602c32fSVidya Sagar 16462602c32fSVidya Sagar status = "disabled"; 16472602c32fSVidya Sagar 16482602c32fSVidya Sagar #address-cells = <3>; 16492602c32fSVidya Sagar #size-cells = <2>; 16502602c32fSVidya Sagar device_type = "pci"; 16512602c32fSVidya Sagar num-lanes = <8>; 16522602c32fSVidya Sagar num-viewport = <8>; 16532602c32fSVidya Sagar linux,pci-domain = <0>; 16542602c32fSVidya Sagar 16552602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 16562602c32fSVidya Sagar clock-names = "core"; 16572602c32fSVidya Sagar 16582602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 16592602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 16602602c32fSVidya Sagar reset-names = "apb", "core"; 16612602c32fSVidya Sagar 16622602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 16632602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 16642602c32fSVidya Sagar interrupt-names = "intr", "msi"; 16652602c32fSVidya Sagar 16662602c32fSVidya Sagar #interrupt-cells = <1>; 16672602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 16682602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 16692602c32fSVidya Sagar 16702602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 16712602c32fSVidya Sagar 16722602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 16732602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 16742602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 16752602c32fSVidya Sagar 16762602c32fSVidya Sagar bus-range = <0x0 0xff>; 1677d5237c7cSThierry Reding 16788a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 16798a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 16808a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1681d5237c7cSThierry Reding 1682d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 1683d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 1684d5237c7cSThierry Reding interconnect-names = "read", "write"; 16852602c32fSVidya Sagar }; 16862602c32fSVidya Sagar 16872602c32fSVidya Sagar pcie@141a0000 { 1688f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 16892602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1690644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1691644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 1692644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1693644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 16942602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 16952602c32fSVidya Sagar 16962602c32fSVidya Sagar status = "disabled"; 16972602c32fSVidya Sagar 16982602c32fSVidya Sagar #address-cells = <3>; 16992602c32fSVidya Sagar #size-cells = <2>; 17002602c32fSVidya Sagar device_type = "pci"; 17012602c32fSVidya Sagar num-lanes = <8>; 17022602c32fSVidya Sagar num-viewport = <8>; 17032602c32fSVidya Sagar linux,pci-domain = <5>; 17042602c32fSVidya Sagar 1705dbb72e2cSVidya Sagar pinctrl-names = "default"; 1706dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1707dbb72e2cSVidya Sagar 17082602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 17092602c32fSVidya Sagar <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 17102602c32fSVidya Sagar clock-names = "core", "core_m"; 17112602c32fSVidya Sagar 17122602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 17132602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 17142602c32fSVidya Sagar reset-names = "apb", "core"; 17152602c32fSVidya Sagar 17162602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 17172602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 17182602c32fSVidya Sagar interrupt-names = "intr", "msi"; 17192602c32fSVidya Sagar 17202602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 17212602c32fSVidya Sagar 17222602c32fSVidya Sagar #interrupt-cells = <1>; 17232602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 17242602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 17252602c32fSVidya Sagar 17262602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 17272602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 17282602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 17292602c32fSVidya Sagar 17302602c32fSVidya Sagar bus-range = <0x0 0xff>; 1731d5237c7cSThierry Reding 17328a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 17338a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 17348a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1735d5237c7cSThierry Reding 1736d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 1737d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 1738d5237c7cSThierry Reding interconnect-names = "read", "write"; 17392602c32fSVidya Sagar }; 17402602c32fSVidya Sagar 17410c988b73SVidya Sagar pcie_ep@14160000 { 17420c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 17430c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1744644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1745644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1746644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1747644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 17480c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 17490c988b73SVidya Sagar 17500c988b73SVidya Sagar status = "disabled"; 17510c988b73SVidya Sagar 17520c988b73SVidya Sagar num-lanes = <4>; 17530c988b73SVidya Sagar num-ib-windows = <2>; 17540c988b73SVidya Sagar num-ob-windows = <8>; 17550c988b73SVidya Sagar 17560c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 17570c988b73SVidya Sagar clock-names = "core"; 17580c988b73SVidya Sagar 17590c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 17600c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 17610c988b73SVidya Sagar reset-names = "apb", "core"; 17620c988b73SVidya Sagar 17630c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 17640c988b73SVidya Sagar interrupt-names = "intr"; 17650c988b73SVidya Sagar 17660c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 17670c988b73SVidya Sagar 17680c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 17690c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 17700c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 17710c988b73SVidya Sagar }; 17720c988b73SVidya Sagar 17730c988b73SVidya Sagar pcie_ep@14180000 { 17740c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 17750c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1776644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1777644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1778644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1779644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 17800c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 17810c988b73SVidya Sagar 17820c988b73SVidya Sagar status = "disabled"; 17830c988b73SVidya Sagar 17840c988b73SVidya Sagar num-lanes = <8>; 17850c988b73SVidya Sagar num-ib-windows = <2>; 17860c988b73SVidya Sagar num-ob-windows = <8>; 17870c988b73SVidya Sagar 17880c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 17890c988b73SVidya Sagar clock-names = "core"; 17900c988b73SVidya Sagar 17910c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 17920c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 17930c988b73SVidya Sagar reset-names = "apb", "core"; 17940c988b73SVidya Sagar 17950c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 17960c988b73SVidya Sagar interrupt-names = "intr"; 17970c988b73SVidya Sagar 17980c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 17990c988b73SVidya Sagar 18000c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 18010c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 18020c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 18030c988b73SVidya Sagar }; 18040c988b73SVidya Sagar 18050c988b73SVidya Sagar pcie_ep@141a0000 { 18060c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 18070c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1808644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1809644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1810644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1811644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 18120c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 18130c988b73SVidya Sagar 18140c988b73SVidya Sagar status = "disabled"; 18150c988b73SVidya Sagar 18160c988b73SVidya Sagar num-lanes = <8>; 18170c988b73SVidya Sagar num-ib-windows = <2>; 18180c988b73SVidya Sagar num-ob-windows = <8>; 18190c988b73SVidya Sagar 18200c988b73SVidya Sagar pinctrl-names = "default"; 18210c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 18220c988b73SVidya Sagar 18230c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 18240c988b73SVidya Sagar clock-names = "core"; 18250c988b73SVidya Sagar 18260c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 18270c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 18280c988b73SVidya Sagar reset-names = "apb", "core"; 18290c988b73SVidya Sagar 18300c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 18310c988b73SVidya Sagar interrupt-names = "intr"; 18320c988b73SVidya Sagar 18330c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 18340c988b73SVidya Sagar 18350c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 18360c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 18370c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 18380c988b73SVidya Sagar }; 18390c988b73SVidya Sagar 1840e867fe41SThierry Reding sram@40000000 { 18415425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 18425425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 18435425fb15SMikko Perttunen #address-cells = <1>; 18445425fb15SMikko Perttunen #size-cells = <1>; 18455425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 18465425fb15SMikko Perttunen 1847e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 18485425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 18495425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 18505425fb15SMikko Perttunen pool; 18515425fb15SMikko Perttunen }; 18525425fb15SMikko Perttunen 1853e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 18545425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 18555425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 18565425fb15SMikko Perttunen pool; 18575425fb15SMikko Perttunen }; 18585425fb15SMikko Perttunen }; 18595425fb15SMikko Perttunen 18605425fb15SMikko Perttunen bpmp: bpmp { 18615425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 18625425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 18635425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 18645425fb15SMikko Perttunen shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 18655425fb15SMikko Perttunen #clock-cells = <1>; 18665425fb15SMikko Perttunen #reset-cells = <1>; 18675425fb15SMikko Perttunen #power-domain-cells = <1>; 1868d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 1869d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 1870d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 1871d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 1872d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 18735425fb15SMikko Perttunen 18745425fb15SMikko Perttunen bpmp_i2c: i2c { 18755425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 18765425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 18775425fb15SMikko Perttunen #address-cells = <1>; 18785425fb15SMikko Perttunen #size-cells = <0>; 18795425fb15SMikko Perttunen }; 18805425fb15SMikko Perttunen 18815425fb15SMikko Perttunen bpmp_thermal: thermal { 18825425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 18835425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 18845425fb15SMikko Perttunen }; 18855425fb15SMikko Perttunen }; 18865425fb15SMikko Perttunen 18877780a034SMikko Perttunen cpus { 1888d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 1889d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 18907780a034SMikko Perttunen #address-cells = <1>; 18917780a034SMikko Perttunen #size-cells = <0>; 18927780a034SMikko Perttunen 1893b45d322cSThierry Reding cpu0_0: cpu@0 { 189431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 18957780a034SMikko Perttunen device_type = "cpu"; 1896b45d322cSThierry Reding reg = <0x000>; 18977780a034SMikko Perttunen enable-method = "psci"; 1898b45d322cSThierry Reding i-cache-size = <131072>; 1899b45d322cSThierry Reding i-cache-line-size = <64>; 1900b45d322cSThierry Reding i-cache-sets = <512>; 1901b45d322cSThierry Reding d-cache-size = <65536>; 1902b45d322cSThierry Reding d-cache-line-size = <64>; 1903b45d322cSThierry Reding d-cache-sets = <256>; 1904b45d322cSThierry Reding next-level-cache = <&l2c_0>; 19057780a034SMikko Perttunen }; 19067780a034SMikko Perttunen 1907b45d322cSThierry Reding cpu0_1: cpu@1 { 190831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 19097780a034SMikko Perttunen device_type = "cpu"; 1910b45d322cSThierry Reding reg = <0x001>; 19117780a034SMikko Perttunen enable-method = "psci"; 1912b45d322cSThierry Reding i-cache-size = <131072>; 1913b45d322cSThierry Reding i-cache-line-size = <64>; 1914b45d322cSThierry Reding i-cache-sets = <512>; 1915b45d322cSThierry Reding d-cache-size = <65536>; 1916b45d322cSThierry Reding d-cache-line-size = <64>; 1917b45d322cSThierry Reding d-cache-sets = <256>; 1918b45d322cSThierry Reding next-level-cache = <&l2c_0>; 19197780a034SMikko Perttunen }; 19207780a034SMikko Perttunen 1921b45d322cSThierry Reding cpu1_0: cpu@100 { 192231af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 19237780a034SMikko Perttunen device_type = "cpu"; 19247780a034SMikko Perttunen reg = <0x100>; 19257780a034SMikko Perttunen enable-method = "psci"; 1926b45d322cSThierry Reding i-cache-size = <131072>; 1927b45d322cSThierry Reding i-cache-line-size = <64>; 1928b45d322cSThierry Reding i-cache-sets = <512>; 1929b45d322cSThierry Reding d-cache-size = <65536>; 1930b45d322cSThierry Reding d-cache-line-size = <64>; 1931b45d322cSThierry Reding d-cache-sets = <256>; 1932b45d322cSThierry Reding next-level-cache = <&l2c_1>; 19337780a034SMikko Perttunen }; 19347780a034SMikko Perttunen 1935b45d322cSThierry Reding cpu1_1: cpu@101 { 193631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 19377780a034SMikko Perttunen device_type = "cpu"; 19387780a034SMikko Perttunen reg = <0x101>; 19397780a034SMikko Perttunen enable-method = "psci"; 1940b45d322cSThierry Reding i-cache-size = <131072>; 1941b45d322cSThierry Reding i-cache-line-size = <64>; 1942b45d322cSThierry Reding i-cache-sets = <512>; 1943b45d322cSThierry Reding d-cache-size = <65536>; 1944b45d322cSThierry Reding d-cache-line-size = <64>; 1945b45d322cSThierry Reding d-cache-sets = <256>; 1946b45d322cSThierry Reding next-level-cache = <&l2c_1>; 19477780a034SMikko Perttunen }; 19487780a034SMikko Perttunen 1949b45d322cSThierry Reding cpu2_0: cpu@200 { 195031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 19517780a034SMikko Perttunen device_type = "cpu"; 19527780a034SMikko Perttunen reg = <0x200>; 19537780a034SMikko Perttunen enable-method = "psci"; 1954b45d322cSThierry Reding i-cache-size = <131072>; 1955b45d322cSThierry Reding i-cache-line-size = <64>; 1956b45d322cSThierry Reding i-cache-sets = <512>; 1957b45d322cSThierry Reding d-cache-size = <65536>; 1958b45d322cSThierry Reding d-cache-line-size = <64>; 1959b45d322cSThierry Reding d-cache-sets = <256>; 1960b45d322cSThierry Reding next-level-cache = <&l2c_2>; 19617780a034SMikko Perttunen }; 19627780a034SMikko Perttunen 1963b45d322cSThierry Reding cpu2_1: cpu@201 { 196431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 19657780a034SMikko Perttunen device_type = "cpu"; 19667780a034SMikko Perttunen reg = <0x201>; 19677780a034SMikko Perttunen enable-method = "psci"; 1968b45d322cSThierry Reding i-cache-size = <131072>; 1969b45d322cSThierry Reding i-cache-line-size = <64>; 1970b45d322cSThierry Reding i-cache-sets = <512>; 1971b45d322cSThierry Reding d-cache-size = <65536>; 1972b45d322cSThierry Reding d-cache-line-size = <64>; 1973b45d322cSThierry Reding d-cache-sets = <256>; 1974b45d322cSThierry Reding next-level-cache = <&l2c_2>; 19757780a034SMikko Perttunen }; 19767780a034SMikko Perttunen 1977b45d322cSThierry Reding cpu3_0: cpu@300 { 197831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 19797780a034SMikko Perttunen device_type = "cpu"; 1980b45d322cSThierry Reding reg = <0x300>; 19817780a034SMikko Perttunen enable-method = "psci"; 1982b45d322cSThierry Reding i-cache-size = <131072>; 1983b45d322cSThierry Reding i-cache-line-size = <64>; 1984b45d322cSThierry Reding i-cache-sets = <512>; 1985b45d322cSThierry Reding d-cache-size = <65536>; 1986b45d322cSThierry Reding d-cache-line-size = <64>; 1987b45d322cSThierry Reding d-cache-sets = <256>; 1988b45d322cSThierry Reding next-level-cache = <&l2c_3>; 19897780a034SMikko Perttunen }; 19907780a034SMikko Perttunen 1991b45d322cSThierry Reding cpu3_1: cpu@301 { 199231af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 19937780a034SMikko Perttunen device_type = "cpu"; 1994b45d322cSThierry Reding reg = <0x301>; 19957780a034SMikko Perttunen enable-method = "psci"; 1996b45d322cSThierry Reding i-cache-size = <131072>; 1997b45d322cSThierry Reding i-cache-line-size = <64>; 1998b45d322cSThierry Reding i-cache-sets = <512>; 1999b45d322cSThierry Reding d-cache-size = <65536>; 2000b45d322cSThierry Reding d-cache-line-size = <64>; 2001b45d322cSThierry Reding d-cache-sets = <256>; 2002b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2003b45d322cSThierry Reding }; 2004b45d322cSThierry Reding 2005b45d322cSThierry Reding cpu-map { 2006b45d322cSThierry Reding cluster0 { 2007b45d322cSThierry Reding core0 { 2008b45d322cSThierry Reding cpu = <&cpu0_0>; 2009b45d322cSThierry Reding }; 2010b45d322cSThierry Reding 2011b45d322cSThierry Reding core1 { 2012b45d322cSThierry Reding cpu = <&cpu0_1>; 2013b45d322cSThierry Reding }; 2014b45d322cSThierry Reding }; 2015b45d322cSThierry Reding 2016b45d322cSThierry Reding cluster1 { 2017b45d322cSThierry Reding core0 { 2018b45d322cSThierry Reding cpu = <&cpu1_0>; 2019b45d322cSThierry Reding }; 2020b45d322cSThierry Reding 2021b45d322cSThierry Reding core1 { 2022b45d322cSThierry Reding cpu = <&cpu1_1>; 2023b45d322cSThierry Reding }; 2024b45d322cSThierry Reding }; 2025b45d322cSThierry Reding 2026b45d322cSThierry Reding cluster2 { 2027b45d322cSThierry Reding core0 { 2028b45d322cSThierry Reding cpu = <&cpu2_0>; 2029b45d322cSThierry Reding }; 2030b45d322cSThierry Reding 2031b45d322cSThierry Reding core1 { 2032b45d322cSThierry Reding cpu = <&cpu2_1>; 2033b45d322cSThierry Reding }; 2034b45d322cSThierry Reding }; 2035b45d322cSThierry Reding 2036b45d322cSThierry Reding cluster3 { 2037b45d322cSThierry Reding core0 { 2038b45d322cSThierry Reding cpu = <&cpu3_0>; 2039b45d322cSThierry Reding }; 2040b45d322cSThierry Reding 2041b45d322cSThierry Reding core1 { 2042b45d322cSThierry Reding cpu = <&cpu3_1>; 2043b45d322cSThierry Reding }; 2044b45d322cSThierry Reding }; 2045b45d322cSThierry Reding }; 2046b45d322cSThierry Reding 2047b45d322cSThierry Reding l2c_0: l2-cache0 { 2048b45d322cSThierry Reding cache-size = <2097152>; 2049b45d322cSThierry Reding cache-line-size = <64>; 2050b45d322cSThierry Reding cache-sets = <2048>; 2051b45d322cSThierry Reding next-level-cache = <&l3c>; 2052b45d322cSThierry Reding }; 2053b45d322cSThierry Reding 2054b45d322cSThierry Reding l2c_1: l2-cache1 { 2055b45d322cSThierry Reding cache-size = <2097152>; 2056b45d322cSThierry Reding cache-line-size = <64>; 2057b45d322cSThierry Reding cache-sets = <2048>; 2058b45d322cSThierry Reding next-level-cache = <&l3c>; 2059b45d322cSThierry Reding }; 2060b45d322cSThierry Reding 2061b45d322cSThierry Reding l2c_2: l2-cache2 { 2062b45d322cSThierry Reding cache-size = <2097152>; 2063b45d322cSThierry Reding cache-line-size = <64>; 2064b45d322cSThierry Reding cache-sets = <2048>; 2065b45d322cSThierry Reding next-level-cache = <&l3c>; 2066b45d322cSThierry Reding }; 2067b45d322cSThierry Reding 2068b45d322cSThierry Reding l2c_3: l2-cache3 { 2069b45d322cSThierry Reding cache-size = <2097152>; 2070b45d322cSThierry Reding cache-line-size = <64>; 2071b45d322cSThierry Reding cache-sets = <2048>; 2072b45d322cSThierry Reding next-level-cache = <&l3c>; 2073b45d322cSThierry Reding }; 2074b45d322cSThierry Reding 2075b45d322cSThierry Reding l3c: l3-cache { 2076b45d322cSThierry Reding cache-size = <4194304>; 2077b45d322cSThierry Reding cache-line-size = <64>; 2078b45d322cSThierry Reding cache-sets = <4096>; 20797780a034SMikko Perttunen }; 20807780a034SMikko Perttunen }; 20817780a034SMikko Perttunen 20827780a034SMikko Perttunen psci { 20837780a034SMikko Perttunen compatible = "arm,psci-1.0"; 20847780a034SMikko Perttunen status = "okay"; 20857780a034SMikko Perttunen method = "smc"; 20867780a034SMikko Perttunen }; 20877780a034SMikko Perttunen 2088a38570c2SMikko Perttunen tcu: tcu { 2089a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 2090a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2091a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2092a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 2093a38570c2SMikko Perttunen }; 2094a38570c2SMikko Perttunen 2095686ba009SThierry Reding thermal-zones { 2096686ba009SThierry Reding cpu { 2097686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2098686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2099686ba009SThierry Reding status = "disabled"; 2100686ba009SThierry Reding }; 2101686ba009SThierry Reding 2102686ba009SThierry Reding gpu { 2103686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2104686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2105686ba009SThierry Reding status = "disabled"; 2106686ba009SThierry Reding }; 2107686ba009SThierry Reding 2108686ba009SThierry Reding aux { 2109686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2110686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2111686ba009SThierry Reding status = "disabled"; 2112686ba009SThierry Reding }; 2113686ba009SThierry Reding 2114686ba009SThierry Reding pllx { 2115686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2116686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2117686ba009SThierry Reding status = "disabled"; 2118686ba009SThierry Reding }; 2119686ba009SThierry Reding 2120686ba009SThierry Reding ao { 2121686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2122686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AO>; 2123686ba009SThierry Reding status = "disabled"; 2124686ba009SThierry Reding }; 2125686ba009SThierry Reding 2126686ba009SThierry Reding tj { 2127686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2128686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2129686ba009SThierry Reding status = "disabled"; 2130686ba009SThierry Reding }; 2131686ba009SThierry Reding }; 2132686ba009SThierry Reding 21335425fb15SMikko Perttunen timer { 21345425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 21355425fb15SMikko Perttunen interrupts = <GIC_PPI 13 21365425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 21375425fb15SMikko Perttunen <GIC_PPI 14 21385425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 21395425fb15SMikko Perttunen <GIC_PPI 11 21405425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 21415425fb15SMikko Perttunen <GIC_PPI 10 21425425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 21435425fb15SMikko Perttunen interrupt-parent = <&gic>; 2144b30be673SThierry Reding always-on; 21455425fb15SMikko Perttunen }; 21465425fb15SMikko Perttunen}; 2147